./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:15,420 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:15,448 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:15,503 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:15,504 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:15,506 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:15,509 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:15,513 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:15,515 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:15,518 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:15,519 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:15,520 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:15,535 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:15,537 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:15,538 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:15,541 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:15,542 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:15,543 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:15,544 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:15,548 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:15,550 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:15,551 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:15,552 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:15,552 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:15,556 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:15,556 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:15,556 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:15,557 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:15,558 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:15,558 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:15,558 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:15,559 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:15,560 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:15,561 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:15,562 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:15,562 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:15,563 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:15,563 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:15,563 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:15,563 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:15,564 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:15,565 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:15,590 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:15,590 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:15,590 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:15,591 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:15,592 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:15,592 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:15,592 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:15,592 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:15,592 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:15,592 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:15,593 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:15,593 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:15,593 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:15,593 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:15,594 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:15,595 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:15,595 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:15,595 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:15,595 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:15,595 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:15,595 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:15,595 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:15,596 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:15,596 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:15,596 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:15,597 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:15,597 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2021-12-15 17:20:15,807 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:15,830 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:15,832 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:15,833 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:15,833 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:15,834 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/bist_cell.cil.c [2021-12-15 17:20:15,878 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8c153120d/f654879e7de848239ae9148f33c8ed48/FLAG31d42fbc1 [2021-12-15 17:20:16,253 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:16,253 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2021-12-15 17:20:16,259 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8c153120d/f654879e7de848239ae9148f33c8ed48/FLAG31d42fbc1 [2021-12-15 17:20:16,269 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8c153120d/f654879e7de848239ae9148f33c8ed48 [2021-12-15 17:20:16,271 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:16,272 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:16,273 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:16,273 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:16,275 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:16,276 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,277 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@45adda53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16, skipping insertion in model container [2021-12-15 17:20:16,277 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,282 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:16,299 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:16,439 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c[639,652] [2021-12-15 17:20:16,478 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:16,491 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:16,499 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c[639,652] [2021-12-15 17:20:16,515 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:16,525 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:16,525 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16 WrapperNode [2021-12-15 17:20:16,525 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:16,526 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:16,526 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:16,526 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:16,531 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,536 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,555 INFO L137 Inliner]: procedures = 30, calls = 30, calls flagged for inlining = 25, calls inlined = 31, statements flattened = 344 [2021-12-15 17:20:16,556 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:16,556 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:16,556 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:16,557 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:16,561 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,562 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,563 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,564 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,567 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,571 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,572 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,574 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:16,575 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:16,575 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:16,575 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:16,576 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,581 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:16,589 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:16,610 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:16,616 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:16,663 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:16,663 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:16,663 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:16,664 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:16,715 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:16,716 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:16,919 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:16,925 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:16,925 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-12-15 17:20:16,927 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:16 BoogieIcfgContainer [2021-12-15 17:20:16,927 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:16,928 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:16,928 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:16,934 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:16,935 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:16,935 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:16" (1/3) ... [2021-12-15 17:20:16,936 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f9ab0c0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:16, skipping insertion in model container [2021-12-15 17:20:16,936 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:16,936 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (2/3) ... [2021-12-15 17:20:16,937 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f9ab0c0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:16, skipping insertion in model container [2021-12-15 17:20:16,937 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:16,937 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:16" (3/3) ... [2021-12-15 17:20:16,938 INFO L388 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2021-12-15 17:20:16,980 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:16,981 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:16,981 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:16,981 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:16,981 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:16,981 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:16,981 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:16,981 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:16,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,019 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,020 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,020 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:17,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,027 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,028 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,033 INFO L791 eck$LassoCheckResult]: Stem: 113#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 43#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 18#L490true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77#L212true assume !(1 == ~b0_req_up~0); 125#L212-2true assume !(1 == ~b1_req_up~0); 85#L219-1true assume !(1 == ~d0_req_up~0); 44#L226-1true assume !(1 == ~d1_req_up~0); 67#L233-1true assume !(1 == ~z_req_up~0); 108#L240-1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16#L255true assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 118#L255-2true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68#L321true assume !(0 == ~b0_ev~0); 84#L321-2true assume !(0 == ~b1_ev~0); 25#L326-1true assume !(0 == ~d0_ev~0); 28#L331-1true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 9#L336-1true assume !(0 == ~z_ev~0); 123#L341-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 119#L107true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 107#L129true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 58#L130true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 92#L390true assume !(0 != activate_threads_~tmp~1#1); 112#L390-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57#L354true assume !(1 == ~b0_ev~0); 40#L354-2true assume !(1 == ~b1_ev~0); 90#L359-1true assume !(1 == ~d0_ev~0); 42#L364-1true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 48#L369-1true assume !(1 == ~z_ev~0); 96#L374-1true assume { :end_inline_reset_delta_events } true; 35#L432-2true [2021-12-15 17:20:17,034 INFO L793 eck$LassoCheckResult]: Loop: 35#L432-2true assume !false; 71#L433true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 8#L295true assume !true; 49#L311true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86#L212-3true assume !(1 == ~b0_req_up~0); 109#L212-5true assume !(1 == ~b1_req_up~0); 89#L219-3true assume !(1 == ~d0_req_up~0); 5#L226-3true assume !(1 == ~d1_req_up~0); 38#L233-3true assume !(1 == ~z_req_up~0); 17#L240-3true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82#L321-3true assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 66#L321-5true assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 93#L326-3true assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 52#L331-3true assume !(0 == ~d1_ev~0); 12#L336-3true assume 0 == ~z_ev~0;~z_ev~0 := 1; 19#L341-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 115#L107-1true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 45#L129-1true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 122#L130-1true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 10#L390-3true assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 24#L390-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33#L354-3true assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 101#L354-5true assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 99#L359-3true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 83#L364-3true assume !(1 == ~d1_ev~0); 81#L369-3true assume 1 == ~z_ev~0;~z_ev~0 := 2; 50#L374-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 73#L268-1true assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 120#L275-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 41#L276-1true stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 14#L407true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117#L414true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105#L415true start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 74#L449true assume !(0 != start_simulation_~tmp~3#1); 35#L432-2true [2021-12-15 17:20:17,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,038 INFO L85 PathProgramCache]: Analyzing trace with hash -1345002148, now seen corresponding path program 1 times [2021-12-15 17:20:17,045 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,045 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744660425] [2021-12-15 17:20:17,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,046 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,212 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,213 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744660425] [2021-12-15 17:20:17,213 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744660425] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,214 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:17,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291973458] [2021-12-15 17:20:17,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,218 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,219 INFO L85 PathProgramCache]: Analyzing trace with hash 972845291, now seen corresponding path program 1 times [2021-12-15 17:20:17,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512234268] [2021-12-15 17:20:17,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,220 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512234268] [2021-12-15 17:20:17,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512234268] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,236 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,236 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:17,236 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957379699] [2021-12-15 17:20:17,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,237 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,238 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:17,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:17,261 INFO L87 Difference]: Start difference. First operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,284 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2021-12-15 17:20:17,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:17,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2021-12-15 17:20:17,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2021-12-15 17:20:17,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2021-12-15 17:20:17,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2021-12-15 17:20:17,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2021-12-15 17:20:17,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,298 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2021-12-15 17:20:17,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2021-12-15 17:20:17,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-12-15 17:20:17,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2021-12-15 17:20:17,320 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2021-12-15 17:20:17,320 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2021-12-15 17:20:17,320 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:17,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2021-12-15 17:20:17,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,324 INFO L791 eck$LassoCheckResult]: Stem: 372#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 282#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 283#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 345#L137 assume !(~b0_val~0 != ~b0_val_t~0); 346#L137-2 ~b0_req_up~0 := 0; 340#L145 assume { :end_inline_update_b0 } true; 341#L212-2 assume !(1 == ~b1_req_up~0); 363#L219-1 assume !(1 == ~d0_req_up~0); 264#L226-1 assume !(1 == ~d1_req_up~0); 322#L233-1 assume !(1 == ~z_req_up~0); 350#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 278#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 279#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 351#L321 assume !(0 == ~b0_ev~0); 352#L321-2 assume !(0 == ~b1_ev~0); 295#L326-1 assume !(0 == ~d0_ev~0); 296#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 267#L336-1 assume !(0 == ~z_ev~0); 268#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 374#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 288#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 335#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 336#L390 assume !(0 != activate_threads_~tmp~1#1); 365#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 334#L354 assume !(1 == ~b0_ev~0); 315#L354-2 assume !(1 == ~b1_ev~0); 316#L359-1 assume !(1 == ~d0_ev~0); 318#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 319#L369-1 assume !(1 == ~z_ev~0); 324#L374-1 assume { :end_inline_reset_delta_events } true; 307#L432-2 [2021-12-15 17:20:17,324 INFO L793 eck$LassoCheckResult]: Loop: 307#L432-2 assume !false; 308#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 265#L295 assume !false; 266#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 292#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 293#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 258#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 259#L290 assume !(0 != eval_~tmp___0~0#1); 325#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 326#L212-3 assume !(1 == ~b0_req_up~0); 354#L212-5 assume !(1 == ~b1_req_up~0); 310#L219-3 assume !(1 == ~d0_req_up~0); 260#L226-3 assume !(1 == ~d1_req_up~0); 261#L233-3 assume !(1 == ~z_req_up~0); 280#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 281#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 347#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 348#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 330#L331-3 assume !(0 == ~d1_ev~0); 274#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 275#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 284#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 300#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 323#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 269#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 270#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 304#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 368#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 362#L364-3 assume !(1 == ~d1_ev~0); 361#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 327#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 328#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 355#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 317#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 276#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 277#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 369#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 356#L449 assume !(0 != start_simulation_~tmp~3#1); 307#L432-2 [2021-12-15 17:20:17,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1840469421, now seen corresponding path program 1 times [2021-12-15 17:20:17,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474150987] [2021-12-15 17:20:17,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,361 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,361 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474150987] [2021-12-15 17:20:17,361 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474150987] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,361 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,361 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:17,361 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [57776543] [2021-12-15 17:20:17,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,362 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,363 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 1 times [2021-12-15 17:20:17,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079941502] [2021-12-15 17:20:17,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,400 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079941502] [2021-12-15 17:20:17,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079941502] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,401 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,401 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136639227] [2021-12-15 17:20:17,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,402 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,402 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:17,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:17,403 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,417 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2021-12-15 17:20:17,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:17,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2021-12-15 17:20:17,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2021-12-15 17:20:17,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2021-12-15 17:20:17,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2021-12-15 17:20:17,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2021-12-15 17:20:17,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,421 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2021-12-15 17:20:17,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2021-12-15 17:20:17,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-12-15 17:20:17,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2021-12-15 17:20:17,426 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2021-12-15 17:20:17,426 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2021-12-15 17:20:17,426 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:17,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2021-12-15 17:20:17,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,428 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,429 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,429 INFO L791 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 525#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 526#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 588#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 589#L137-2 ~b0_req_up~0 := 0; 583#L145 assume { :end_inline_update_b0 } true; 584#L212-2 assume !(1 == ~b1_req_up~0); 606#L219-1 assume !(1 == ~d0_req_up~0); 507#L226-1 assume !(1 == ~d1_req_up~0); 565#L233-1 assume !(1 == ~z_req_up~0); 593#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 522#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 594#L321 assume !(0 == ~b0_ev~0); 595#L321-2 assume !(0 == ~b1_ev~0); 538#L326-1 assume !(0 == ~d0_ev~0); 539#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 510#L336-1 assume !(0 == ~z_ev~0); 511#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 617#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 531#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 578#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 579#L390 assume !(0 != activate_threads_~tmp~1#1); 608#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 577#L354 assume !(1 == ~b0_ev~0); 558#L354-2 assume !(1 == ~b1_ev~0); 559#L359-1 assume !(1 == ~d0_ev~0); 561#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 562#L369-1 assume !(1 == ~z_ev~0); 567#L374-1 assume { :end_inline_reset_delta_events } true; 550#L432-2 [2021-12-15 17:20:17,429 INFO L793 eck$LassoCheckResult]: Loop: 550#L432-2 assume !false; 551#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 508#L295 assume !false; 509#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 535#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 536#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 501#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 502#L290 assume !(0 != eval_~tmp___0~0#1); 568#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 569#L212-3 assume !(1 == ~b0_req_up~0); 597#L212-5 assume !(1 == ~b1_req_up~0); 553#L219-3 assume !(1 == ~d0_req_up~0); 503#L226-3 assume !(1 == ~d1_req_up~0); 504#L233-3 assume !(1 == ~z_req_up~0); 523#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 524#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 590#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 591#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 573#L331-3 assume !(0 == ~d1_ev~0); 517#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 518#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 527#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 543#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 566#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 512#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 513#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 537#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 547#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 611#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 605#L364-3 assume !(1 == ~d1_ev~0); 604#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 570#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 571#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 598#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 560#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 519#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 612#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 599#L449 assume !(0 != start_simulation_~tmp~3#1); 550#L432-2 [2021-12-15 17:20:17,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,430 INFO L85 PathProgramCache]: Analyzing trace with hash 531269841, now seen corresponding path program 1 times [2021-12-15 17:20:17,430 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130957973] [2021-12-15 17:20:17,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,431 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130957973] [2021-12-15 17:20:17,489 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130957973] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,489 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,489 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:17,489 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929675753] [2021-12-15 17:20:17,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,490 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,490 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 2 times [2021-12-15 17:20:17,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44888056] [2021-12-15 17:20:17,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,491 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,523 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44888056] [2021-12-15 17:20:17,524 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [44888056] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,524 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,524 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,524 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1132778116] [2021-12-15 17:20:17,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,525 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,525 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:17,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:17,525 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,541 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2021-12-15 17:20:17,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:17,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2021-12-15 17:20:17,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2021-12-15 17:20:17,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2021-12-15 17:20:17,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2021-12-15 17:20:17,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2021-12-15 17:20:17,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,545 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2021-12-15 17:20:17,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2021-12-15 17:20:17,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-12-15 17:20:17,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2021-12-15 17:20:17,549 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2021-12-15 17:20:17,549 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2021-12-15 17:20:17,549 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:17,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2021-12-15 17:20:17,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,551 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,551 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,552 INFO L791 eck$LassoCheckResult]: Stem: 858#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 806#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 768#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 769#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 831#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 832#L137-2 ~b0_req_up~0 := 0; 826#L145 assume { :end_inline_update_b0 } true; 827#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 787#L152 assume !(~b1_val~0 != ~b1_val_t~0); 788#L152-2 ~b1_req_up~0 := 0; 850#L160 assume { :end_inline_update_b1 } true; 849#L219-1 assume !(1 == ~d0_req_up~0); 750#L226-1 assume !(1 == ~d1_req_up~0); 808#L233-1 assume !(1 == ~z_req_up~0); 836#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 764#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 765#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 837#L321 assume !(0 == ~b0_ev~0); 838#L321-2 assume !(0 == ~b1_ev~0); 781#L326-1 assume !(0 == ~d0_ev~0); 782#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 753#L336-1 assume !(0 == ~z_ev~0); 754#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 860#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 774#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 821#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 822#L390 assume !(0 != activate_threads_~tmp~1#1); 851#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 820#L354 assume !(1 == ~b0_ev~0); 801#L354-2 assume !(1 == ~b1_ev~0); 802#L359-1 assume !(1 == ~d0_ev~0); 804#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 805#L369-1 assume !(1 == ~z_ev~0); 810#L374-1 assume { :end_inline_reset_delta_events } true; 793#L432-2 [2021-12-15 17:20:17,552 INFO L793 eck$LassoCheckResult]: Loop: 793#L432-2 assume !false; 794#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 751#L295 assume !false; 752#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 778#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 779#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 744#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 745#L290 assume !(0 != eval_~tmp___0~0#1); 811#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 812#L212-3 assume !(1 == ~b0_req_up~0); 840#L212-5 assume !(1 == ~b1_req_up~0); 796#L219-3 assume !(1 == ~d0_req_up~0); 746#L226-3 assume !(1 == ~d1_req_up~0); 747#L233-3 assume !(1 == ~z_req_up~0); 766#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 767#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 833#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 834#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 816#L331-3 assume !(0 == ~d1_ev~0); 760#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 761#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 770#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 786#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 809#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 755#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 756#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 780#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 790#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 854#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 848#L364-3 assume !(1 == ~d1_ev~0); 847#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 813#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 814#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 841#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 803#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 762#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 763#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 855#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 842#L449 assume !(0 != start_simulation_~tmp~3#1); 793#L432-2 [2021-12-15 17:20:17,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1296388927, now seen corresponding path program 1 times [2021-12-15 17:20:17,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2062860066] [2021-12-15 17:20:17,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,612 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,612 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2062860066] [2021-12-15 17:20:17,612 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2062860066] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,612 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,613 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:17,613 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841650444] [2021-12-15 17:20:17,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,613 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,613 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 3 times [2021-12-15 17:20:17,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366682520] [2021-12-15 17:20:17,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,639 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [366682520] [2021-12-15 17:20:17,639 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [366682520] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,639 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,639 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,639 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137547251] [2021-12-15 17:20:17,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,639 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,640 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:17,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:17,640 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,663 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2021-12-15 17:20:17,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-15 17:20:17,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2021-12-15 17:20:17,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2021-12-15 17:20:17,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2021-12-15 17:20:17,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2021-12-15 17:20:17,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2021-12-15 17:20:17,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,666 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2021-12-15 17:20:17,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2021-12-15 17:20:17,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-12-15 17:20:17,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2021-12-15 17:20:17,669 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2021-12-15 17:20:17,669 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2021-12-15 17:20:17,669 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:17,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2021-12-15 17:20:17,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,670 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,670 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,671 INFO L791 eck$LassoCheckResult]: Stem: 1104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1014#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1015#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1077#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1078#L137-2 ~b0_req_up~0 := 0; 1072#L145 assume { :end_inline_update_b0 } true; 1073#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1033#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1034#L152-2 ~b1_req_up~0 := 0; 1096#L160 assume { :end_inline_update_b1 } true; 1095#L219-1 assume !(1 == ~d0_req_up~0); 996#L226-1 assume !(1 == ~d1_req_up~0); 1054#L233-1 assume !(1 == ~z_req_up~0); 1082#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1010#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1011#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1083#L321 assume !(0 == ~b0_ev~0); 1084#L321-2 assume !(0 == ~b1_ev~0); 1027#L326-1 assume !(0 == ~d0_ev~0); 1028#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 999#L336-1 assume !(0 == ~z_ev~0); 1000#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1106#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1020#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1067#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1068#L390 assume !(0 != activate_threads_~tmp~1#1); 1097#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1066#L354 assume !(1 == ~b0_ev~0); 1047#L354-2 assume !(1 == ~b1_ev~0); 1048#L359-1 assume !(1 == ~d0_ev~0); 1050#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1051#L369-1 assume !(1 == ~z_ev~0); 1056#L374-1 assume { :end_inline_reset_delta_events } true; 1039#L432-2 [2021-12-15 17:20:17,671 INFO L793 eck$LassoCheckResult]: Loop: 1039#L432-2 assume !false; 1040#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 997#L295 assume !false; 998#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1024#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1025#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 990#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 991#L290 assume !(0 != eval_~tmp___0~0#1); 1057#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1058#L212-3 assume !(1 == ~b0_req_up~0); 1086#L212-5 assume !(1 == ~b1_req_up~0); 1042#L219-3 assume !(1 == ~d0_req_up~0); 992#L226-3 assume !(1 == ~d1_req_up~0); 993#L233-3 assume !(1 == ~z_req_up~0); 1012#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1013#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1079#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1080#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1062#L331-3 assume !(0 == ~d1_ev~0); 1006#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1007#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1016#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1032#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1055#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1001#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1002#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1026#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1036#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1100#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1094#L364-3 assume !(1 == ~d1_ev~0); 1093#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1059#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1060#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1087#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1049#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1008#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1009#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1101#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1088#L449 assume !(0 != start_simulation_~tmp~3#1); 1039#L432-2 [2021-12-15 17:20:17,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,671 INFO L85 PathProgramCache]: Analyzing trace with hash 1234349313, now seen corresponding path program 1 times [2021-12-15 17:20:17,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747116490] [2021-12-15 17:20:17,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,672 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,690 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747116490] [2021-12-15 17:20:17,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747116490] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,691 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:17,691 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [713332761] [2021-12-15 17:20:17,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,691 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,691 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 4 times [2021-12-15 17:20:17,692 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,692 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109754046] [2021-12-15 17:20:17,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,692 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109754046] [2021-12-15 17:20:17,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109754046] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,714 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,714 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,714 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404999743] [2021-12-15 17:20:17,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,714 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,714 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:17,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:17,715 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,721 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2021-12-15 17:20:17,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:17,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2021-12-15 17:20:17,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2021-12-15 17:20:17,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2021-12-15 17:20:17,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2021-12-15 17:20:17,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2021-12-15 17:20:17,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,724 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2021-12-15 17:20:17,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2021-12-15 17:20:17,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-12-15 17:20:17,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2021-12-15 17:20:17,727 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2021-12-15 17:20:17,727 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2021-12-15 17:20:17,727 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:17,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2021-12-15 17:20:17,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,729 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,729 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,729 INFO L791 eck$LassoCheckResult]: Stem: 1347#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1257#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1258#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1320#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1321#L137-2 ~b0_req_up~0 := 0; 1315#L145 assume { :end_inline_update_b0 } true; 1316#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1276#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1277#L152-2 ~b1_req_up~0 := 0; 1339#L160 assume { :end_inline_update_b1 } true; 1338#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1260#L167 assume !(~d0_val~0 != ~d0_val_t~0); 1261#L167-2 ~d0_req_up~0 := 0; 1238#L175 assume { :end_inline_update_d0 } true; 1239#L226-1 assume !(1 == ~d1_req_up~0); 1297#L233-1 assume !(1 == ~z_req_up~0); 1325#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1253#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1254#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1326#L321 assume !(0 == ~b0_ev~0); 1327#L321-2 assume !(0 == ~b1_ev~0); 1270#L326-1 assume !(0 == ~d0_ev~0); 1271#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1242#L336-1 assume !(0 == ~z_ev~0); 1243#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1349#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1263#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1310#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1311#L390 assume !(0 != activate_threads_~tmp~1#1); 1340#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L354 assume !(1 == ~b0_ev~0); 1290#L354-2 assume !(1 == ~b1_ev~0); 1291#L359-1 assume !(1 == ~d0_ev~0); 1293#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1294#L369-1 assume !(1 == ~z_ev~0); 1299#L374-1 assume { :end_inline_reset_delta_events } true; 1282#L432-2 [2021-12-15 17:20:17,729 INFO L793 eck$LassoCheckResult]: Loop: 1282#L432-2 assume !false; 1283#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1240#L295 assume !false; 1241#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1267#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1268#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1233#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1234#L290 assume !(0 != eval_~tmp___0~0#1); 1300#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1301#L212-3 assume !(1 == ~b0_req_up~0); 1329#L212-5 assume !(1 == ~b1_req_up~0); 1285#L219-3 assume !(1 == ~d0_req_up~0); 1235#L226-3 assume !(1 == ~d1_req_up~0); 1236#L233-3 assume !(1 == ~z_req_up~0); 1255#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1256#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1322#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1323#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1305#L331-3 assume !(0 == ~d1_ev~0); 1249#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1250#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1259#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1275#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1298#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1244#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1245#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1269#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1279#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1343#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1337#L364-3 assume !(1 == ~d1_ev~0); 1336#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1302#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1303#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1330#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1292#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1251#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1252#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1344#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1331#L449 assume !(0 != start_simulation_~tmp~3#1); 1282#L432-2 [2021-12-15 17:20:17,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,729 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 1 times [2021-12-15 17:20:17,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805204866] [2021-12-15 17:20:17,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,754 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805204866] [2021-12-15 17:20:17,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1805204866] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,754 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,754 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:17,755 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321040629] [2021-12-15 17:20:17,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,755 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 5 times [2021-12-15 17:20:17,755 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116342445] [2021-12-15 17:20:17,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,779 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116342445] [2021-12-15 17:20:17,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116342445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,779 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,779 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,779 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303121538] [2021-12-15 17:20:17,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,780 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,780 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:17,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:17,780 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,808 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2021-12-15 17:20:17,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-15 17:20:17,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2021-12-15 17:20:17,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2021-12-15 17:20:17,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2021-12-15 17:20:17,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2021-12-15 17:20:17,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2021-12-15 17:20:17,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,811 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2021-12-15 17:20:17,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2021-12-15 17:20:17,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-12-15 17:20:17,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2021-12-15 17:20:17,814 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2021-12-15 17:20:17,814 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2021-12-15 17:20:17,814 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:17,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2021-12-15 17:20:17,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,815 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,815 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,815 INFO L791 eck$LassoCheckResult]: Stem: 1593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1503#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1504#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1566#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1567#L137-2 ~b0_req_up~0 := 0; 1561#L145 assume { :end_inline_update_b0 } true; 1562#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1522#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1523#L152-2 ~b1_req_up~0 := 0; 1585#L160 assume { :end_inline_update_b1 } true; 1584#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1506#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1507#L167-2 ~d0_req_up~0 := 0; 1484#L175 assume { :end_inline_update_d0 } true; 1485#L226-1 assume !(1 == ~d1_req_up~0); 1543#L233-1 assume !(1 == ~z_req_up~0); 1571#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1499#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1500#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1572#L321 assume !(0 == ~b0_ev~0); 1573#L321-2 assume !(0 == ~b1_ev~0); 1516#L326-1 assume !(0 == ~d0_ev~0); 1517#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1488#L336-1 assume !(0 == ~z_ev~0); 1489#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1595#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1509#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1556#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1557#L390 assume !(0 != activate_threads_~tmp~1#1); 1586#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1555#L354 assume !(1 == ~b0_ev~0); 1536#L354-2 assume !(1 == ~b1_ev~0); 1537#L359-1 assume !(1 == ~d0_ev~0); 1539#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1540#L369-1 assume !(1 == ~z_ev~0); 1545#L374-1 assume { :end_inline_reset_delta_events } true; 1528#L432-2 [2021-12-15 17:20:17,815 INFO L793 eck$LassoCheckResult]: Loop: 1528#L432-2 assume !false; 1529#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1486#L295 assume !false; 1487#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1513#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1514#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1479#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1480#L290 assume !(0 != eval_~tmp___0~0#1); 1546#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1547#L212-3 assume !(1 == ~b0_req_up~0); 1575#L212-5 assume !(1 == ~b1_req_up~0); 1531#L219-3 assume !(1 == ~d0_req_up~0); 1481#L226-3 assume !(1 == ~d1_req_up~0); 1482#L233-3 assume !(1 == ~z_req_up~0); 1501#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1568#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1569#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1551#L331-3 assume !(0 == ~d1_ev~0); 1495#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1496#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1505#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1521#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1544#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1490#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1491#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1515#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1525#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1589#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1583#L364-3 assume !(1 == ~d1_ev~0); 1582#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1548#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1549#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1576#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1538#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1497#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1498#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1590#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1577#L449 assume !(0 != start_simulation_~tmp~3#1); 1528#L432-2 [2021-12-15 17:20:17,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,816 INFO L85 PathProgramCache]: Analyzing trace with hash 2039338604, now seen corresponding path program 1 times [2021-12-15 17:20:17,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221963136] [2021-12-15 17:20:17,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,816 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,840 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,840 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221963136] [2021-12-15 17:20:17,840 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221963136] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,840 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,840 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:17,840 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310758874] [2021-12-15 17:20:17,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,840 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 6 times [2021-12-15 17:20:17,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802269903] [2021-12-15 17:20:17,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,861 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802269903] [2021-12-15 17:20:17,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802269903] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,863 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,863 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660082164] [2021-12-15 17:20:17,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,864 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,864 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:17,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:17,864 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,870 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2021-12-15 17:20:17,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:17,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2021-12-15 17:20:17,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2021-12-15 17:20:17,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2021-12-15 17:20:17,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2021-12-15 17:20:17,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2021-12-15 17:20:17,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,873 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2021-12-15 17:20:17,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2021-12-15 17:20:17,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-12-15 17:20:17,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2021-12-15 17:20:17,876 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2021-12-15 17:20:17,876 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2021-12-15 17:20:17,876 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:17,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2021-12-15 17:20:17,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-12-15 17:20:17,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,878 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,878 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,878 INFO L791 eck$LassoCheckResult]: Stem: 1836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1746#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1747#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1809#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1810#L137-2 ~b0_req_up~0 := 0; 1803#L145 assume { :end_inline_update_b0 } true; 1804#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1765#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1766#L152-2 ~b1_req_up~0 := 0; 1828#L160 assume { :end_inline_update_b1 } true; 1827#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1749#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1750#L167-2 ~d0_req_up~0 := 0; 1727#L175 assume { :end_inline_update_d0 } true; 1728#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 1785#L182 assume !(~d1_val~0 != ~d1_val_t~0); 1754#L182-2 ~d1_req_up~0 := 0; 1755#L190 assume { :end_inline_update_d1 } true; 1808#L233-1 assume !(1 == ~z_req_up~0); 1814#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1742#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1743#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815#L321 assume !(0 == ~b0_ev~0); 1816#L321-2 assume !(0 == ~b1_ev~0); 1759#L326-1 assume !(0 == ~d0_ev~0); 1760#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1731#L336-1 assume !(0 == ~z_ev~0); 1732#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1838#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1752#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1798#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1799#L390 assume !(0 != activate_threads_~tmp~1#1); 1829#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1797#L354 assume !(1 == ~b0_ev~0); 1779#L354-2 assume !(1 == ~b1_ev~0); 1780#L359-1 assume !(1 == ~d0_ev~0); 1782#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1783#L369-1 assume !(1 == ~z_ev~0); 1787#L374-1 assume { :end_inline_reset_delta_events } true; 1771#L432-2 [2021-12-15 17:20:17,878 INFO L793 eck$LassoCheckResult]: Loop: 1771#L432-2 assume !false; 1772#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1729#L295 assume !false; 1730#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1756#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1757#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1722#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1723#L290 assume !(0 != eval_~tmp___0~0#1); 1788#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1789#L212-3 assume !(1 == ~b0_req_up~0); 1818#L212-5 assume !(1 == ~b1_req_up~0); 1774#L219-3 assume !(1 == ~d0_req_up~0); 1724#L226-3 assume !(1 == ~d1_req_up~0); 1725#L233-3 assume !(1 == ~z_req_up~0); 1744#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1745#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1811#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1812#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1793#L331-3 assume !(0 == ~d1_ev~0); 1738#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1739#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1748#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1764#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1786#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1733#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1734#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1758#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1768#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1832#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1826#L364-3 assume !(1 == ~d1_ev~0); 1825#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1790#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1791#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1819#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1781#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1740#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1741#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1833#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1820#L449 assume !(0 != start_simulation_~tmp~3#1); 1771#L432-2 [2021-12-15 17:20:17,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,879 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 1 times [2021-12-15 17:20:17,879 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,879 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562725780] [2021-12-15 17:20:17,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,879 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,902 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562725780] [2021-12-15 17:20:17,902 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562725780] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,903 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,903 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:17,903 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574113371] [2021-12-15 17:20:17,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,904 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 7 times [2021-12-15 17:20:17,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,908 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485206069] [2021-12-15 17:20:17,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,910 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,968 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485206069] [2021-12-15 17:20:17,969 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485206069] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,971 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,971 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,971 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017188580] [2021-12-15 17:20:17,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,974 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,974 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:17,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:17,975 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:18,017 INFO L93 Difference]: Finished difference Result 151 states and 225 transitions. [2021-12-15 17:20:18,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:18,020 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 225 transitions. [2021-12-15 17:20:18,021 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2021-12-15 17:20:18,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 151 states and 225 transitions. [2021-12-15 17:20:18,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151 [2021-12-15 17:20:18,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151 [2021-12-15 17:20:18,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151 states and 225 transitions. [2021-12-15 17:20:18,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:18,023 INFO L681 BuchiCegarLoop]: Abstraction has 151 states and 225 transitions. [2021-12-15 17:20:18,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states and 225 transitions. [2021-12-15 17:20:18,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 120. [2021-12-15 17:20:18,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2021-12-15 17:20:18,031 INFO L704 BuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2021-12-15 17:20:18,032 INFO L587 BuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2021-12-15 17:20:18,032 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:18,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2021-12-15 17:20:18,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2021-12-15 17:20:18,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:18,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:18,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,034 INFO L791 eck$LassoCheckResult]: Stem: 2123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 2071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 2032#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2033#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 2096#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 2097#L137-2 ~b0_req_up~0 := 0; 2090#L145 assume { :end_inline_update_b0 } true; 2091#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 2052#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 2053#L152-2 ~b1_req_up~0 := 0; 2115#L160 assume { :end_inline_update_b1 } true; 2114#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 2035#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 2036#L167-2 ~d0_req_up~0 := 0; 2013#L175 assume { :end_inline_update_d0 } true; 2014#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 2072#L182 assume !(~d1_val~0 != ~d1_val_t~0); 2040#L182-2 ~d1_req_up~0 := 0; 2041#L190 assume { :end_inline_update_d1 } true; 2095#L233-1 assume !(1 == ~z_req_up~0); 2101#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2028#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 2029#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2102#L321 assume !(0 == ~b0_ev~0); 2103#L321-2 assume !(0 == ~b1_ev~0); 2046#L326-1 assume !(0 == ~d0_ev~0); 2047#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 2017#L336-1 assume !(0 == ~z_ev~0); 2018#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2125#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2038#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2085#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2086#L390 assume !(0 != activate_threads_~tmp~1#1); 2116#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2084#L354 assume !(1 == ~b0_ev~0); 2066#L354-2 assume !(1 == ~b1_ev~0); 2067#L359-1 assume !(1 == ~d0_ev~0); 2069#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2070#L369-1 assume !(1 == ~z_ev~0); 2074#L374-1 assume { :end_inline_reset_delta_events } true; 2058#L432-2 [2021-12-15 17:20:18,034 INFO L793 eck$LassoCheckResult]: Loop: 2058#L432-2 assume !false; 2059#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 2015#L295 assume !false; 2016#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2042#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 2044#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2127#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2126#L290 assume !(0 != eval_~tmp___0~0#1); 2075#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2076#L212-3 assume !(1 == ~b0_req_up~0); 2105#L212-5 assume !(1 == ~b1_req_up~0); 2061#L219-3 assume !(1 == ~d0_req_up~0); 2010#L226-3 assume !(1 == ~d1_req_up~0); 2011#L233-3 assume !(1 == ~z_req_up~0); 2030#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2031#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 2098#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 2099#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 2080#L331-3 assume !(0 == ~d1_ev~0); 2024#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 2025#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2034#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2051#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2073#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2019#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 2020#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2045#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 2055#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 2119#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2113#L364-3 assume !(1 == ~d1_ev~0); 2112#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 2077#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2078#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 2106#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2068#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 2026#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2027#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2120#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 2107#L449 assume !(0 != start_simulation_~tmp~3#1); 2058#L432-2 [2021-12-15 17:20:18,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,035 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 2 times [2021-12-15 17:20:18,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114151034] [2021-12-15 17:20:18,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:18,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:18,072 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:18,072 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114151034] [2021-12-15 17:20:18,072 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114151034] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:18,072 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:18,073 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:18,073 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396410168] [2021-12-15 17:20:18,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:18,073 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:18,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,074 INFO L85 PathProgramCache]: Analyzing trace with hash 356628037, now seen corresponding path program 1 times [2021-12-15 17:20:18,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137364445] [2021-12-15 17:20:18,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,082 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:18,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,104 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:18,411 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:818) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:18,414 INFO L158 Benchmark]: Toolchain (without parser) took 2141.87ms. Allocated memory is still 125.8MB. Free memory was 92.3MB in the beginning and 53.3MB in the end (delta: 39.0MB). Peak memory consumption was 39.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,414 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 75.5MB. Free memory was 48.7MB in the beginning and 48.7MB in the end (delta: 25.2kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:18,414 INFO L158 Benchmark]: CACSL2BoogieTranslator took 252.72ms. Allocated memory is still 125.8MB. Free memory was 92.3MB in the beginning and 100.5MB in the end (delta: -8.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,415 INFO L158 Benchmark]: Boogie Procedure Inliner took 29.90ms. Allocated memory is still 125.8MB. Free memory was 100.5MB in the beginning and 97.7MB in the end (delta: 2.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,415 INFO L158 Benchmark]: Boogie Preprocessor took 18.23ms. Allocated memory is still 125.8MB. Free memory was 97.7MB in the beginning and 96.3MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:18,415 INFO L158 Benchmark]: RCFGBuilder took 352.01ms. Allocated memory is still 125.8MB. Free memory was 96.3MB in the beginning and 78.1MB in the end (delta: 18.2MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,415 INFO L158 Benchmark]: BuchiAutomizer took 1485.26ms. Allocated memory is still 125.8MB. Free memory was 78.1MB in the beginning and 53.3MB in the end (delta: 24.8MB). Peak memory consumption was 27.4MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,417 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 75.5MB. Free memory was 48.7MB in the beginning and 48.7MB in the end (delta: 25.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 252.72ms. Allocated memory is still 125.8MB. Free memory was 92.3MB in the beginning and 100.5MB in the end (delta: -8.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 29.90ms. Allocated memory is still 125.8MB. Free memory was 100.5MB in the beginning and 97.7MB in the end (delta: 2.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 18.23ms. Allocated memory is still 125.8MB. Free memory was 97.7MB in the beginning and 96.3MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 352.01ms. Allocated memory is still 125.8MB. Free memory was 96.3MB in the beginning and 78.1MB in the end (delta: 18.2MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 1485.26ms. Allocated memory is still 125.8MB. Free memory was 78.1MB in the beginning and 53.3MB in the end (delta: 24.8MB). Peak memory consumption was 27.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:18,441 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable