./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu2.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:15,221 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:15,223 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:15,280 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:15,281 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:15,283 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:15,284 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:15,285 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:15,286 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:15,287 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:15,287 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:15,288 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:15,288 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:15,288 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:15,289 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:15,290 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:15,291 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:15,291 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:15,292 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:15,293 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:15,294 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:15,303 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:15,304 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:15,306 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:15,308 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:15,310 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:15,310 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:15,310 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:15,311 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:15,312 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:15,312 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:15,313 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:15,313 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:15,314 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:15,315 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:15,315 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:15,316 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:15,316 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:15,316 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:15,317 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:15,317 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:15,318 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:15,343 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:15,343 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:15,344 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:15,344 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:15,345 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:15,345 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:15,345 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:15,345 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:15,345 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:15,345 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:15,346 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:15,346 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:15,346 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:15,346 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:15,347 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:15,347 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:15,347 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:15,347 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:15,347 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:15,347 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:15,347 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:15,348 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:15,348 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:15,348 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:15,348 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:15,348 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:15,348 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:15,348 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:15,349 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:15,349 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:15,349 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:15,349 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:15,350 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:15,350 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2021-12-15 17:20:15,548 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:15,564 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:15,565 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:15,566 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:15,566 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:15,567 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu2.cil.c [2021-12-15 17:20:15,622 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f89b9bd3a/166e685af62b46b78b916cf8c2245dc1/FLAGe69b85088 [2021-12-15 17:20:15,989 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:15,989 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu2.cil.c [2021-12-15 17:20:15,995 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f89b9bd3a/166e685af62b46b78b916cf8c2245dc1/FLAGe69b85088 [2021-12-15 17:20:16,011 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f89b9bd3a/166e685af62b46b78b916cf8c2245dc1 [2021-12-15 17:20:16,013 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:16,015 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:16,017 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:16,017 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:16,020 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:16,020 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,021 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27ef4b9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16, skipping insertion in model container [2021-12-15 17:20:16,021 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,026 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:16,051 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:16,189 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu2.cil.c[636,649] [2021-12-15 17:20:16,253 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:16,261 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:16,276 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu2.cil.c[636,649] [2021-12-15 17:20:16,300 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:16,318 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:16,318 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16 WrapperNode [2021-12-15 17:20:16,318 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:16,319 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:16,319 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:16,320 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:16,324 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,343 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,380 INFO L137 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 45, statements flattened = 529 [2021-12-15 17:20:16,381 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:16,381 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:16,382 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:16,382 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:16,387 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,388 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,394 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,394 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,404 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,413 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,423 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,425 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:16,429 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:16,430 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:16,430 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:16,431 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (1/1) ... [2021-12-15 17:20:16,435 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:16,443 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:16,460 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:16,474 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:16,498 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:16,498 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:16,498 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:16,498 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:16,575 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:16,577 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:16,974 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:16,985 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:16,986 INFO L301 CfgBuilder]: Removed 5 assume(true) statements. [2021-12-15 17:20:16,988 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:16 BoogieIcfgContainer [2021-12-15 17:20:16,988 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:16,989 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:16,989 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:16,991 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:16,991 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:16,992 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:16" (1/3) ... [2021-12-15 17:20:16,992 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39f5db31 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:16, skipping insertion in model container [2021-12-15 17:20:16,992 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:16,992 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:16" (2/3) ... [2021-12-15 17:20:16,992 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39f5db31 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:16, skipping insertion in model container [2021-12-15 17:20:16,993 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:16,993 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:16" (3/3) ... [2021-12-15 17:20:16,993 INFO L388 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2021-12-15 17:20:17,025 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:17,026 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:17,026 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:17,026 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:17,026 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:17,026 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:17,026 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:17,026 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:17,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 153 [2021-12-15 17:20:17,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,084 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:17,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 153 [2021-12-15 17:20:17,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,098 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,098 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,103 INFO L791 eck$LassoCheckResult]: Stem: 176#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 70#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 98#L599true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63#L297true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 150#L304true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 144#L304-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 35#L309-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 92#L314-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36#L423true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10#L117true assume !(1 == ~P_1_pc~0); 42#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 87#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 171#L129true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 54#L477true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 131#L477-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 151#L185true assume 1 == ~P_2_pc~0; 102#L186true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 103#L196true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 118#L197true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 145#L485true assume !(0 != activate_threads_~tmp___0~1#1); 11#L485-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 44#L267true assume 1 == ~C_1_pc~0; 40#L268true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 50#L288true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 65#L289true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28#L493true assume !(0 != activate_threads_~tmp___1~1#1); 94#L493-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183#L431true assume { :end_inline_reset_delta_events } true; 82#L547-2true [2021-12-15 17:20:17,104 INFO L793 eck$LassoCheckResult]: Loop: 82#L547-2true assume !false; 99#L548true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 139#L396true assume !true; 95#L412true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60#L297-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100#L423-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 66#L117-6true assume !(1 == ~P_1_pc~0); 71#L117-8true is_P_1_triggered_~__retres1~0#1 := 0; 189#L128-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 23#L129-2true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 45#L477-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 105#L477-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 72#L185-6true assume 1 == ~P_2_pc~0; 15#L186-2true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 181#L196-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 161#L197-2true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 79#L485-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 180#L485-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 132#L267-6true assume 1 == ~C_1_pc~0; 153#L268-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 80#L288-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 25#L289-2true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 81#L493-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 58#L493-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9#L431-1true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 163#L327-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 165#L344-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 126#L345-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 166#L566true assume !(0 == start_simulation_~tmp~3#1); 76#L566-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 67#L327-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 122#L344-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 172#L345-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 143#L521true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74#L528true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138#L529true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 19#L579true assume !(0 != start_simulation_~tmp___0~2#1); 82#L547-2true [2021-12-15 17:20:17,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,110 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2021-12-15 17:20:17,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748251200] [2021-12-15 17:20:17,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,233 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748251200] [2021-12-15 17:20:17,234 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748251200] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,234 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,235 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:17,236 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583537017] [2021-12-15 17:20:17,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,239 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,239 INFO L85 PathProgramCache]: Analyzing trace with hash -224400385, now seen corresponding path program 1 times [2021-12-15 17:20:17,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694482296] [2021-12-15 17:20:17,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,269 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694482296] [2021-12-15 17:20:17,269 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694482296] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,269 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:17,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608789610] [2021-12-15 17:20:17,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,271 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,272 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:17,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:17,299 INFO L87 Difference]: Start difference. First operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,339 INFO L93 Difference]: Finished difference Result 186 states and 268 transitions. [2021-12-15 17:20:17,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:17,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 268 transitions. [2021-12-15 17:20:17,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2021-12-15 17:20:17,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 178 states and 260 transitions. [2021-12-15 17:20:17,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2021-12-15 17:20:17,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2021-12-15 17:20:17,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 260 transitions. [2021-12-15 17:20:17,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,360 INFO L681 BuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2021-12-15 17:20:17,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 260 transitions. [2021-12-15 17:20:17,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2021-12-15 17:20:17,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4606741573033708) internal successors, (260), 177 states have internal predecessors, (260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 260 transitions. [2021-12-15 17:20:17,392 INFO L704 BuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2021-12-15 17:20:17,392 INFO L587 BuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2021-12-15 17:20:17,392 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:17,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 260 transitions. [2021-12-15 17:20:17,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2021-12-15 17:20:17,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,396 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,396 INFO L791 eck$LassoCheckResult]: Stem: 562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 500#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 490#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 491#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 554#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 453#L309-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 454#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 455#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 401#L117 assume !(1 == ~P_1_pc~0); 402#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 464#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 521#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 479#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 480#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 549#L185 assume 1 == ~P_2_pc~0; 530#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 508#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 531#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 541#L485 assume !(0 != activate_threads_~tmp___0~1#1); 406#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 407#L267 assume 1 == ~C_1_pc~0; 460#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 461#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 478#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 444#L493 assume !(0 != activate_threads_~tmp___1~1#1); 445#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 524#L431 assume { :end_inline_reset_delta_events } true; 425#L547-2 [2021-12-15 17:20:17,400 INFO L793 eck$LassoCheckResult]: Loop: 425#L547-2 assume !false; 517#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 527#L396 assume !false; 522#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 456#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 418#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 482#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 542#L361 assume !(0 != eval_~tmp___2~0#1); 525#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 488#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 489#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 494#L117-6 assume 1 == ~P_1_pc~0; 496#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 501#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 433#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 434#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 465#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 502#L185-6 assume !(1 == ~P_2_pc~0); 416#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 415#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 560#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 513#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 514#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 550#L267-6 assume 1 == ~C_1_pc~0; 551#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 386#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 437#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 438#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 484#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 399#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 400#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 475#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 545#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 546#L566 assume !(0 == start_simulation_~tmp~3#1); 509#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 492#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 486#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 544#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 553#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 505#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 506#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 424#L579 assume !(0 != start_simulation_~tmp___0~2#1); 425#L547-2 [2021-12-15 17:20:17,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,402 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2021-12-15 17:20:17,402 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643935829] [2021-12-15 17:20:17,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,403 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643935829] [2021-12-15 17:20:17,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643935829] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,477 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,477 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:17,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096353870] [2021-12-15 17:20:17,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,477 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,479 INFO L85 PathProgramCache]: Analyzing trace with hash -1683132646, now seen corresponding path program 1 times [2021-12-15 17:20:17,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478177004] [2021-12-15 17:20:17,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,479 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [478177004] [2021-12-15 17:20:17,531 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [478177004] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,531 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,531 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005499590] [2021-12-15 17:20:17,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,531 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,532 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:17,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:17,532 INFO L87 Difference]: Start difference. First operand 178 states and 260 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,541 INFO L93 Difference]: Finished difference Result 178 states and 259 transitions. [2021-12-15 17:20:17,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:17,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 259 transitions. [2021-12-15 17:20:17,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2021-12-15 17:20:17,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 178 states and 259 transitions. [2021-12-15 17:20:17,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2021-12-15 17:20:17,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2021-12-15 17:20:17,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 259 transitions. [2021-12-15 17:20:17,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,545 INFO L681 BuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2021-12-15 17:20:17,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 259 transitions. [2021-12-15 17:20:17,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2021-12-15 17:20:17,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4550561797752808) internal successors, (259), 177 states have internal predecessors, (259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 259 transitions. [2021-12-15 17:20:17,549 INFO L704 BuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2021-12-15 17:20:17,549 INFO L587 BuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2021-12-15 17:20:17,549 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:17,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 259 transitions. [2021-12-15 17:20:17,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2021-12-15 17:20:17,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,551 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,551 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,551 INFO L791 eck$LassoCheckResult]: Stem: 927#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 865#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 856#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 919#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 817#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 818#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 819#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 766#L117 assume !(1 == ~P_1_pc~0); 767#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 829#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 885#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 844#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 845#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 914#L185 assume 1 == ~P_2_pc~0; 894#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 873#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 895#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 906#L485 assume !(0 != activate_threads_~tmp___0~1#1); 769#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 770#L267 assume 1 == ~C_1_pc~0; 825#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 826#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 838#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 809#L493 assume !(0 != activate_threads_~tmp___1~1#1); 810#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 889#L431 assume { :end_inline_reset_delta_events } true; 790#L547-2 [2021-12-15 17:20:17,551 INFO L793 eck$LassoCheckResult]: Loop: 790#L547-2 assume !false; 880#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 892#L396 assume !false; 887#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 821#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 783#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 847#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 907#L361 assume !(0 != eval_~tmp___2~0#1); 890#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 852#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 853#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 857#L117-6 assume !(1 == ~P_1_pc~0); 858#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 866#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 798#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 799#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 830#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 867#L185-6 assume 1 == ~P_2_pc~0; 779#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 780#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 925#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 878#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 879#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 915#L267-6 assume 1 == ~C_1_pc~0; 916#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 754#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 802#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 803#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 849#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 764#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 765#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 841#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 910#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 911#L566 assume !(0 == start_simulation_~tmp~3#1); 874#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 860#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 851#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 909#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 918#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 870#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 871#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 789#L579 assume !(0 != start_simulation_~tmp___0~2#1); 790#L547-2 [2021-12-15 17:20:17,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2021-12-15 17:20:17,552 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [638837340] [2021-12-15 17:20:17,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,552 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,606 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,606 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [638837340] [2021-12-15 17:20:17,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [638837340] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,606 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,606 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,607 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14780774] [2021-12-15 17:20:17,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,607 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1396999590, now seen corresponding path program 1 times [2021-12-15 17:20:17,608 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219925640] [2021-12-15 17:20:17,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,609 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,670 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219925640] [2021-12-15 17:20:17,670 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [219925640] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,670 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,671 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,671 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907372969] [2021-12-15 17:20:17,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,671 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,671 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:17,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:17,672 INFO L87 Difference]: Start difference. First operand 178 states and 259 transitions. cyclomatic complexity: 82 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,758 INFO L93 Difference]: Finished difference Result 480 states and 697 transitions. [2021-12-15 17:20:17,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:17,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 697 transitions. [2021-12-15 17:20:17,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 408 [2021-12-15 17:20:17,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 697 transitions. [2021-12-15 17:20:17,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2021-12-15 17:20:17,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2021-12-15 17:20:17,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 697 transitions. [2021-12-15 17:20:17,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,771 INFO L681 BuchiCegarLoop]: Abstraction has 480 states and 697 transitions. [2021-12-15 17:20:17,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 697 transitions. [2021-12-15 17:20:17,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 190. [2021-12-15 17:20:17,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190 states, 190 states have (on average 1.4263157894736842) internal successors, (271), 189 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 271 transitions. [2021-12-15 17:20:17,786 INFO L704 BuchiCegarLoop]: Abstraction has 190 states and 271 transitions. [2021-12-15 17:20:17,786 INFO L587 BuchiCegarLoop]: Abstraction has 190 states and 271 transitions. [2021-12-15 17:20:17,786 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:17,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190 states and 271 transitions. [2021-12-15 17:20:17,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2021-12-15 17:20:17,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,788 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,788 INFO L791 eck$LassoCheckResult]: Stem: 1611#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1539#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1529#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1530#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1599#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1491#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1492#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1493#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1439#L117 assume !(1 == ~P_1_pc~0); 1440#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1502#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1560#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1518#L477 assume !(0 != activate_threads_~tmp~1#1); 1519#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1591#L185 assume 1 == ~P_2_pc~0; 1570#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1547#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1571#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1583#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1444#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1445#L267 assume 1 == ~C_1_pc~0; 1498#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1499#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1517#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1482#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1483#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1565#L431 assume { :end_inline_reset_delta_events } true; 1463#L547-2 [2021-12-15 17:20:17,788 INFO L793 eck$LassoCheckResult]: Loop: 1463#L547-2 assume !false; 1556#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1567#L396 assume !false; 1561#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1494#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1456#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1521#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1581#L361 assume !(0 != eval_~tmp___2~0#1); 1564#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1526#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1527#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1531#L117-6 assume !(1 == ~P_1_pc~0); 1532#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 1540#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1612#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1503#L477-6 assume !(0 != activate_threads_~tmp~1#1); 1504#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1541#L185-6 assume 1 == ~P_2_pc~0; 1452#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1453#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1607#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1552#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1553#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1592#L267-6 assume 1 == ~C_1_pc~0; 1593#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1427#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1475#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1476#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1523#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1437#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1438#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1514#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1586#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1587#L566 assume !(0 == start_simulation_~tmp~3#1); 1548#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1534#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1525#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1584#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1598#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1544#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1545#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1462#L579 assume !(0 != start_simulation_~tmp___0~2#1); 1463#L547-2 [2021-12-15 17:20:17,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,789 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2021-12-15 17:20:17,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,791 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213709396] [2021-12-15 17:20:17,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,824 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213709396] [2021-12-15 17:20:17,824 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213709396] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,824 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,824 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:17,825 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394203381] [2021-12-15 17:20:17,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,825 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,825 INFO L85 PathProgramCache]: Analyzing trace with hash 526228444, now seen corresponding path program 1 times [2021-12-15 17:20:17,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651431049] [2021-12-15 17:20:17,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,855 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651431049] [2021-12-15 17:20:17,855 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651431049] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,855 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,855 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:17,855 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903400939] [2021-12-15 17:20:17,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,856 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:17,856 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:17,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:17,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:17,856 INFO L87 Difference]: Start difference. First operand 190 states and 271 transitions. cyclomatic complexity: 82 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:17,921 INFO L93 Difference]: Finished difference Result 475 states and 665 transitions. [2021-12-15 17:20:17,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:17,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 665 transitions. [2021-12-15 17:20:17,925 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 412 [2021-12-15 17:20:17,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 665 transitions. [2021-12-15 17:20:17,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2021-12-15 17:20:17,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2021-12-15 17:20:17,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 665 transitions. [2021-12-15 17:20:17,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:17,927 INFO L681 BuchiCegarLoop]: Abstraction has 475 states and 665 transitions. [2021-12-15 17:20:17,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 665 transitions. [2021-12-15 17:20:17,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 433. [2021-12-15 17:20:17,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 433 states have (on average 1.4087759815242493) internal successors, (610), 432 states have internal predecessors, (610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:17,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 610 transitions. [2021-12-15 17:20:17,933 INFO L704 BuchiCegarLoop]: Abstraction has 433 states and 610 transitions. [2021-12-15 17:20:17,933 INFO L587 BuchiCegarLoop]: Abstraction has 433 states and 610 transitions. [2021-12-15 17:20:17,933 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:17,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 610 transitions. [2021-12-15 17:20:17,935 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2021-12-15 17:20:17,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:17,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:17,936 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,936 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:17,936 INFO L791 eck$LassoCheckResult]: Stem: 2288#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2216#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2207#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2208#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2280#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2167#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2168#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2169#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2115#L117 assume !(1 == ~P_1_pc~0); 2116#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2179#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2238#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2195#L477 assume !(0 != activate_threads_~tmp~1#1); 2196#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2272#L185 assume !(1 == ~P_2_pc~0); 2224#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 2225#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2252#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2263#L485 assume !(0 != activate_threads_~tmp___0~1#1); 2117#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2118#L267 assume 1 == ~C_1_pc~0; 2175#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2176#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2190#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2156#L493 assume !(0 != activate_threads_~tmp___1~1#1); 2157#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2246#L431 assume { :end_inline_reset_delta_events } true; 2138#L547-2 [2021-12-15 17:20:17,936 INFO L793 eck$LassoCheckResult]: Loop: 2138#L547-2 assume !false; 2232#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2250#L396 assume !false; 2241#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2171#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2131#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2199#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2264#L361 assume !(0 != eval_~tmp___2~0#1); 2247#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2204#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2205#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2209#L117-6 assume !(1 == ~P_1_pc~0); 2210#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 2217#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2145#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2146#L477-6 assume !(0 != activate_threads_~tmp~1#1); 2180#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2218#L185-6 assume !(1 == ~P_2_pc~0); 2219#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 2249#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2286#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2230#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2231#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2273#L267-6 assume 1 == ~C_1_pc~0; 2274#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2105#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2151#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2152#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2201#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2113#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2114#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2193#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2268#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2269#L566 assume !(0 == start_simulation_~tmp~3#1); 2226#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2211#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2203#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2266#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2279#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2222#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2223#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2137#L579 assume !(0 != start_simulation_~tmp___0~2#1); 2138#L547-2 [2021-12-15 17:20:17,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,936 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2021-12-15 17:20:17,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050440910] [2021-12-15 17:20:17,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,937 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:17,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:17,979 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:17,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050440910] [2021-12-15 17:20:17,980 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050440910] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:17,980 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:17,980 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:17,980 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841298460] [2021-12-15 17:20:17,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:17,980 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:17,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:17,981 INFO L85 PathProgramCache]: Analyzing trace with hash -1531375587, now seen corresponding path program 1 times [2021-12-15 17:20:17,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:17,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154626644] [2021-12-15 17:20:17,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:17,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:17,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:18,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:18,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:18,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154626644] [2021-12-15 17:20:18,002 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154626644] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:18,002 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:18,002 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:18,002 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913959476] [2021-12-15 17:20:18,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:18,003 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:18,003 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:18,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:18,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:18,003 INFO L87 Difference]: Start difference. First operand 433 states and 610 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:18,076 INFO L93 Difference]: Finished difference Result 1179 states and 1624 transitions. [2021-12-15 17:20:18,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:18,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1179 states and 1624 transitions. [2021-12-15 17:20:18,083 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1099 [2021-12-15 17:20:18,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1179 states to 1179 states and 1624 transitions. [2021-12-15 17:20:18,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1179 [2021-12-15 17:20:18,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1179 [2021-12-15 17:20:18,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1179 states and 1624 transitions. [2021-12-15 17:20:18,097 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:18,097 INFO L681 BuchiCegarLoop]: Abstraction has 1179 states and 1624 transitions. [2021-12-15 17:20:18,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1179 states and 1624 transitions. [2021-12-15 17:20:18,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1179 to 1120. [2021-12-15 17:20:18,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1120 states, 1120 states have (on average 1.3857142857142857) internal successors, (1552), 1119 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1120 states to 1120 states and 1552 transitions. [2021-12-15 17:20:18,110 INFO L704 BuchiCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2021-12-15 17:20:18,110 INFO L587 BuchiCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2021-12-15 17:20:18,110 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:18,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1120 states and 1552 transitions. [2021-12-15 17:20:18,114 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1078 [2021-12-15 17:20:18,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:18,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:18,114 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,114 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,115 INFO L791 eck$LassoCheckResult]: Stem: 3932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3842#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3831#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3832#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3915#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3793#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3794#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3795#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3740#L117 assume !(1 == ~P_1_pc~0); 3741#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3802#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3863#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3818#L477 assume !(0 != activate_threads_~tmp~1#1); 3819#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3908#L185 assume !(1 == ~P_2_pc~0); 3850#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 3851#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3880#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3895#L485 assume !(0 != activate_threads_~tmp___0~1#1); 3742#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3743#L267 assume !(1 == ~C_1_pc~0); 3803#L267-2 assume 2 == ~C_1_pc~0; 3910#L278 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3812#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3813#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3781#L493 assume !(0 != activate_threads_~tmp___1~1#1); 3782#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3874#L431 assume { :end_inline_reset_delta_events } true; 3933#L547-2 [2021-12-15 17:20:18,123 INFO L793 eck$LassoCheckResult]: Loop: 3933#L547-2 assume !false; 4614#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4612#L396 assume !false; 4611#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4608#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4605#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4603#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4601#L361 assume !(0 != eval_~tmp___2~0#1); 3875#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3827#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3828#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3833#L117-6 assume !(1 == ~P_1_pc~0); 3834#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 3843#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3770#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3771#L477-6 assume !(0 != activate_threads_~tmp~1#1); 3804#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3844#L185-6 assume !(1 == ~P_2_pc~0); 3845#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 3877#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3927#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3856#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 3857#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3909#L267-6 assume !(1 == ~C_1_pc~0); 3883#L267-8 assume 2 == ~C_1_pc~0; 3729#L278-2 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3730#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3774#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3775#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 3824#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3738#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3739#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3815#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3928#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4642#L566 assume !(0 == start_simulation_~tmp~3#1); 4637#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4632#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4628#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4624#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4622#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4620#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4618#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4617#L579 assume !(0 != start_simulation_~tmp___0~2#1); 3933#L547-2 [2021-12-15 17:20:18,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,124 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2021-12-15 17:20:18,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,124 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469807720] [2021-12-15 17:20:18,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:18,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:18,155 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:18,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469807720] [2021-12-15 17:20:18,155 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469807720] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:18,155 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:18,155 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:18,155 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459165631] [2021-12-15 17:20:18,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:18,156 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:18,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,157 INFO L85 PathProgramCache]: Analyzing trace with hash 221061876, now seen corresponding path program 1 times [2021-12-15 17:20:18,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153393412] [2021-12-15 17:20:18,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,157 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:18,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:18,191 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:18,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153393412] [2021-12-15 17:20:18,194 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1153393412] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:18,194 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:18,194 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:18,194 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729698548] [2021-12-15 17:20:18,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:18,195 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:18,195 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:18,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:18,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:18,196 INFO L87 Difference]: Start difference. First operand 1120 states and 1552 transitions. cyclomatic complexity: 436 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:18,228 INFO L93 Difference]: Finished difference Result 1488 states and 2031 transitions. [2021-12-15 17:20:18,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:18,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2031 transitions. [2021-12-15 17:20:18,236 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1441 [2021-12-15 17:20:18,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2031 transitions. [2021-12-15 17:20:18,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2021-12-15 17:20:18,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2021-12-15 17:20:18,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2031 transitions. [2021-12-15 17:20:18,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:18,244 INFO L681 BuchiCegarLoop]: Abstraction has 1488 states and 2031 transitions. [2021-12-15 17:20:18,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2031 transitions. [2021-12-15 17:20:18,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1464. [2021-12-15 17:20:18,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.3668032786885247) internal successors, (2001), 1463 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2001 transitions. [2021-12-15 17:20:18,259 INFO L704 BuchiCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2021-12-15 17:20:18,259 INFO L587 BuchiCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2021-12-15 17:20:18,259 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:18,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2001 transitions. [2021-12-15 17:20:18,263 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1417 [2021-12-15 17:20:18,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:18,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:18,264 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,264 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,265 INFO L791 eck$LassoCheckResult]: Stem: 6559#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6462#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6447#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6448#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6540#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6408#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6409#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6410#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6357#L117 assume !(1 == ~P_1_pc~0); 6358#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 6417#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6487#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6435#L477 assume !(0 != activate_threads_~tmp~1#1); 6436#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6531#L185 assume !(1 == ~P_2_pc~0); 6470#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 6471#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6501#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6516#L485 assume !(0 != activate_threads_~tmp___0~1#1); 6359#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6360#L267 assume !(1 == ~C_1_pc~0); 6418#L267-2 assume !(2 == ~C_1_pc~0); 6500#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 6430#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6431#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6397#L493 assume !(0 != activate_threads_~tmp___1~1#1); 6398#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6496#L431 assume { :end_inline_reset_delta_events } true; 6560#L547-2 [2021-12-15 17:20:18,265 INFO L793 eck$LassoCheckResult]: Loop: 6560#L547-2 assume !false; 7640#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 7638#L396 assume !false; 7635#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7631#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7627#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7624#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7620#L361 assume !(0 != eval_~tmp___2~0#1); 6497#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6444#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6445#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6454#L117-6 assume !(1 == ~P_1_pc~0); 6455#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 6463#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6564#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6419#L477-6 assume !(0 != activate_threads_~tmp~1#1); 6420#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6464#L185-6 assume !(1 == ~P_2_pc~0); 6465#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 7764#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7762#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7761#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7750#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7749#L267-6 assume !(1 == ~C_1_pc~0); 7748#L267-8 assume !(2 == ~C_1_pc~0); 7746#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 7744#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7726#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6480#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 6441#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6355#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6356#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6433#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6524#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6525#L566 assume !(0 == start_simulation_~tmp~3#1); 6472#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6452#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6443#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6520#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7650#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7649#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7648#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7646#L579 assume !(0 != start_simulation_~tmp___0~2#1); 6560#L547-2 [2021-12-15 17:20:18,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,266 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2021-12-15 17:20:18,266 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272270040] [2021-12-15 17:20:18,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,266 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,274 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:18,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,300 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:18,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1212226549, now seen corresponding path program 1 times [2021-12-15 17:20:18,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61819945] [2021-12-15 17:20:18,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:18,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:18,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:18,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61819945] [2021-12-15 17:20:18,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [61819945] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:18,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:18,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:18,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6119879] [2021-12-15 17:20:18,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:18,325 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:18,325 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:18,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:18,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:18,325 INFO L87 Difference]: Start difference. First operand 1464 states and 2001 transitions. cyclomatic complexity: 541 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:18,376 INFO L93 Difference]: Finished difference Result 2589 states and 3511 transitions. [2021-12-15 17:20:18,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:18,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2589 states and 3511 transitions. [2021-12-15 17:20:18,389 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2524 [2021-12-15 17:20:18,398 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2589 states to 2589 states and 3511 transitions. [2021-12-15 17:20:18,398 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2589 [2021-12-15 17:20:18,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2589 [2021-12-15 17:20:18,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2589 states and 3511 transitions. [2021-12-15 17:20:18,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:18,401 INFO L681 BuchiCegarLoop]: Abstraction has 2589 states and 3511 transitions. [2021-12-15 17:20:18,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2589 states and 3511 transitions. [2021-12-15 17:20:18,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2589 to 1500. [2021-12-15 17:20:18,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1500 states, 1500 states have (on average 1.358) internal successors, (2037), 1499 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2037 transitions. [2021-12-15 17:20:18,418 INFO L704 BuchiCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2021-12-15 17:20:18,418 INFO L587 BuchiCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2021-12-15 17:20:18,419 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:18,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1500 states and 2037 transitions. [2021-12-15 17:20:18,423 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2021-12-15 17:20:18,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:18,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:18,423 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,423 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,424 INFO L791 eck$LassoCheckResult]: Stem: 10639#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10534#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10535#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10520#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10521#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10621#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10480#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10481#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10482#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10426#L117 assume !(1 == ~P_1_pc~0); 10427#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 10488#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10564#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10506#L477 assume !(0 != activate_threads_~tmp~1#1); 10507#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10613#L185 assume !(1 == ~P_2_pc~0); 10544#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 10545#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10583#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10604#L485 assume !(0 != activate_threads_~tmp___0~1#1); 10431#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10432#L267 assume !(1 == ~C_1_pc~0); 10491#L267-2 assume !(2 == ~C_1_pc~0); 10580#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 10504#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10505#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10467#L493 assume !(0 != activate_threads_~tmp___1~1#1); 10468#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10574#L431 assume { :end_inline_reset_delta_events } true; 10450#L547-2 [2021-12-15 17:20:18,425 INFO L793 eck$LassoCheckResult]: Loop: 10450#L547-2 assume !false; 10558#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10579#L396 assume !false; 10619#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11796#L327 assume !(0 == ~P_1_st~0); 11789#L331 assume !(0 == ~P_2_st~0); 11786#L335 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11784#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11783#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11583#L361 assume !(0 != eval_~tmp___2~0#1); 10572#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10573#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10577#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10578#L117-6 assume !(1 == ~P_1_pc~0); 10536#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 10537#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10456#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10457#L477-6 assume !(0 != activate_threads_~tmp~1#1); 10584#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10585#L185-6 assume !(1 == ~P_2_pc~0); 11909#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 10643#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10644#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10552#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10553#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10642#L267-6 assume !(1 == ~C_1_pc~0); 10588#L267-8 assume !(2 == ~C_1_pc~0); 10589#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 10551#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10460#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10461#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10513#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10514#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11906#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11839#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11838#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11836#L566 assume !(0 == start_simulation_~tmp~3#1); 11834#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10527#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10516#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10605#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10620#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10542#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10543#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10449#L579 assume !(0 != start_simulation_~tmp___0~2#1); 10450#L547-2 [2021-12-15 17:20:18,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,425 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2021-12-15 17:20:18,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228286002] [2021-12-15 17:20:18,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,440 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:18,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,455 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:18,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,456 INFO L85 PathProgramCache]: Analyzing trace with hash 1972558684, now seen corresponding path program 1 times [2021-12-15 17:20:18,456 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420671741] [2021-12-15 17:20:18,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,456 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:18,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:18,486 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:18,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420671741] [2021-12-15 17:20:18,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1420671741] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:18,487 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:18,487 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:18,487 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240733034] [2021-12-15 17:20:18,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:18,488 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:18,488 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:18,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:18,488 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:18,488 INFO L87 Difference]: Start difference. First operand 1500 states and 2037 transitions. cyclomatic complexity: 541 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:18,510 INFO L93 Difference]: Finished difference Result 2325 states and 3118 transitions. [2021-12-15 17:20:18,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:18,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2325 states and 3118 transitions. [2021-12-15 17:20:18,522 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2021-12-15 17:20:18,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2325 states to 2325 states and 3118 transitions. [2021-12-15 17:20:18,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2325 [2021-12-15 17:20:18,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2325 [2021-12-15 17:20:18,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2325 states and 3118 transitions. [2021-12-15 17:20:18,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:18,534 INFO L681 BuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2021-12-15 17:20:18,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states and 3118 transitions. [2021-12-15 17:20:18,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2325. [2021-12-15 17:20:18,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2325 states, 2325 states have (on average 1.3410752688172043) internal successors, (3118), 2324 states have internal predecessors, (3118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:18,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2325 states to 2325 states and 3118 transitions. [2021-12-15 17:20:18,559 INFO L704 BuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2021-12-15 17:20:18,559 INFO L587 BuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2021-12-15 17:20:18,559 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:18,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2325 states and 3118 transitions. [2021-12-15 17:20:18,565 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2021-12-15 17:20:18,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:18,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:18,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:18,567 INFO L791 eck$LassoCheckResult]: Stem: 14471#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14365#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14366#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14351#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14352#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14449#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14312#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14313#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14314#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14257#L117 assume !(1 == ~P_1_pc~0); 14258#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 14321#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14397#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14337#L477 assume !(0 != activate_threads_~tmp~1#1); 14338#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14440#L185 assume !(1 == ~P_2_pc~0); 14374#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 14375#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14411#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14429#L485 assume !(0 != activate_threads_~tmp___0~1#1); 14262#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14263#L267 assume !(1 == ~C_1_pc~0); 14323#L267-2 assume !(2 == ~C_1_pc~0); 14409#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 14335#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14336#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14298#L493 assume !(0 != activate_threads_~tmp___1~1#1); 14299#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14405#L431 assume { :end_inline_reset_delta_events } true; 14473#L547-2 assume !false; 16047#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 16045#L396 [2021-12-15 17:20:18,567 INFO L793 eck$LassoCheckResult]: Loop: 16045#L396 assume !false; 16044#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16043#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16041#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16040#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16038#L361 assume 0 != eval_~tmp___2~0#1; 16034#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16030#L370 assume !(0 != eval_~tmp~0#1); 16032#L366 assume !(0 == ~P_2_st~0); 16050#L381 assume !(0 == ~C_1_st~0); 16045#L396 [2021-12-15 17:20:18,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,568 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2021-12-15 17:20:18,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416494702] [2021-12-15 17:20:18,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,568 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,573 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:18,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,579 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:18,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,580 INFO L85 PathProgramCache]: Analyzing trace with hash -658300295, now seen corresponding path program 1 times [2021-12-15 17:20:18,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834151780] [2021-12-15 17:20:18,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,582 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:18,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:18,584 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:18,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:18,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1216570650, now seen corresponding path program 1 times [2021-12-15 17:20:18,585 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:18,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813237695] [2021-12-15 17:20:18,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:18,585 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:18,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:18,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:18,599 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:18,599 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813237695] [2021-12-15 17:20:18,599 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [813237695] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:18,599 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:18,599 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:18,599 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967665484] [2021-12-15 17:20:18,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:18,657 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:18,672 INFO L158 Benchmark]: Toolchain (without parser) took 2644.52ms. Allocated memory was 121.6MB in the beginning and 159.4MB in the end (delta: 37.7MB). Free memory was 87.2MB in the beginning and 81.5MB in the end (delta: 5.7MB). Peak memory consumption was 45.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,672 INFO L158 Benchmark]: CDTParser took 1.22ms. Allocated memory is still 73.4MB. Free memory is still 32.0MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:18,672 INFO L158 Benchmark]: CACSL2BoogieTranslator took 301.62ms. Allocated memory is still 121.6MB. Free memory was 87.0MB in the beginning and 93.9MB in the end (delta: -6.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,675 INFO L158 Benchmark]: Boogie Procedure Inliner took 61.60ms. Allocated memory is still 121.6MB. Free memory was 93.9MB in the beginning and 91.2MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,676 INFO L158 Benchmark]: Boogie Preprocessor took 47.39ms. Allocated memory is still 121.6MB. Free memory was 90.5MB in the beginning and 88.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,676 INFO L158 Benchmark]: RCFGBuilder took 558.76ms. Allocated memory is still 121.6MB. Free memory was 88.4MB in the beginning and 67.5MB in the end (delta: 21.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,676 INFO L158 Benchmark]: BuchiAutomizer took 1670.78ms. Allocated memory was 121.6MB in the beginning and 159.4MB in the end (delta: 37.7MB). Free memory was 66.8MB in the beginning and 81.5MB in the end (delta: -14.6MB). Peak memory consumption was 27.0MB. Max. memory is 16.1GB. [2021-12-15 17:20:18,682 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.22ms. Allocated memory is still 73.4MB. Free memory is still 32.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 301.62ms. Allocated memory is still 121.6MB. Free memory was 87.0MB in the beginning and 93.9MB in the end (delta: -6.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 61.60ms. Allocated memory is still 121.6MB. Free memory was 93.9MB in the beginning and 91.2MB in the end (delta: 2.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 47.39ms. Allocated memory is still 121.6MB. Free memory was 90.5MB in the beginning and 88.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 558.76ms. Allocated memory is still 121.6MB. Free memory was 88.4MB in the beginning and 67.5MB in the end (delta: 21.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 1670.78ms. Allocated memory was 121.6MB in the beginning and 159.4MB in the end (delta: 37.7MB). Free memory was 66.8MB in the beginning and 81.5MB in the end (delta: -14.6MB). Peak memory consumption was 27.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:18,711 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable