./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:19,343 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:19,345 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:19,379 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:19,379 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:19,381 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:19,384 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:19,386 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:19,390 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:19,391 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:19,392 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:19,393 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:19,394 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:19,397 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:19,398 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:19,400 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:19,403 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:19,408 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:19,409 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:19,411 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:19,417 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:19,418 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:19,419 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:19,420 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:19,422 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:19,425 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:19,426 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:19,427 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:19,427 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:19,428 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:19,428 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:19,429 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:19,429 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:19,431 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:19,432 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:19,432 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:19,433 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:19,434 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:19,434 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:19,435 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:19,435 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:19,436 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:19,470 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:19,473 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:19,473 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:19,473 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:19,474 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:19,474 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:19,475 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:19,475 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:19,475 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:19,475 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:19,476 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:19,476 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:19,476 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:19,476 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:19,477 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:19,477 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:19,477 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:19,477 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:19,477 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:19,477 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:19,478 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:19,478 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:19,478 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:19,478 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:19,478 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:19,478 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:19,479 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:19,479 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:19,479 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:19,479 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:19,479 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:19,480 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:19,480 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:19,480 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2021-12-15 17:20:19,707 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:19,723 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:19,725 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:19,726 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:19,727 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:19,728 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2021-12-15 17:20:19,801 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/88ccc08c5/900938e8dc0845119dabb273b0716422/FLAGb98806013 [2021-12-15 17:20:20,166 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:20,167 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2021-12-15 17:20:20,177 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/88ccc08c5/900938e8dc0845119dabb273b0716422/FLAGb98806013 [2021-12-15 17:20:20,570 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/88ccc08c5/900938e8dc0845119dabb273b0716422 [2021-12-15 17:20:20,571 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:20,572 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:20,575 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:20,575 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:20,577 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:20,578 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,579 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@63d2b4d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20, skipping insertion in model container [2021-12-15 17:20:20,580 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,585 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:20,614 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:20,726 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2021-12-15 17:20:20,758 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:20,766 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:20,775 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2021-12-15 17:20:20,792 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:20,805 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:20,806 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20 WrapperNode [2021-12-15 17:20:20,806 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:20,807 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:20,807 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:20,807 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:20,813 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,819 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,839 INFO L137 Inliner]: procedures = 29, calls = 31, calls flagged for inlining = 26, calls inlined = 27, statements flattened = 303 [2021-12-15 17:20:20,840 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:20,840 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:20,841 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:20,841 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:20,846 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,847 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,848 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,849 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,858 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,864 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,866 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,869 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:20,870 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:20,870 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:20,870 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:20,871 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,877 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:20,888 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:20,899 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:20,900 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:20,924 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:20,924 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:20,925 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:20,925 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:20,989 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:20,990 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:21,229 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:21,235 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:21,235 INFO L301 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-15 17:20:21,237 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:21 BoogieIcfgContainer [2021-12-15 17:20:21,237 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:21,238 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:21,238 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:21,241 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:21,241 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:21,241 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:20" (1/3) ... [2021-12-15 17:20:21,242 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@532b024a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:21, skipping insertion in model container [2021-12-15 17:20:21,243 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:21,243 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20" (2/3) ... [2021-12-15 17:20:21,243 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@532b024a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:21, skipping insertion in model container [2021-12-15 17:20:21,243 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:21,243 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:21" (3/3) ... [2021-12-15 17:20:21,244 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2021-12-15 17:20:21,278 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:21,279 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:21,279 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:21,279 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:21,279 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:21,279 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:21,279 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:21,280 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:21,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-12-15 17:20:21,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:21,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:21,332 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,332 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,333 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:21,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-12-15 17:20:21,349 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:21,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:21,352 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,353 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,360 INFO L791 eck$LassoCheckResult]: Stem: 99#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 30#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 64#L462true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68#L222true assume !(1 == ~q_req_up~0); 10#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 31#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 37#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86#L275true assume !(0 == ~q_read_ev~0); 93#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 105#L65true assume !(1 == ~p_dw_pc~0); 29#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 53#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 63#L77true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34#L315true assume !(0 != activate_threads_~tmp~1#1); 65#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 97#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 71#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 90#L96true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5#L323true assume !(0 != activate_threads_~tmp___0~1#1); 46#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98#L293true assume !(1 == ~q_read_ev~0); 3#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 35#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2021-12-15 17:20:21,362 INFO L793 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 101#L364true assume false; 60#L380true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82#L222-3true assume !(1 == ~q_req_up~0); 32#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 38#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 52#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 18#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 94#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 72#L77-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 39#L315-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 83#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 57#L84-3true assume !(1 == ~c_dr_pc~0); 88#L84-5true is_do_read_c_triggered_~__retres1~1#1 := 0; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 58#L96-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 103#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 6#L293-5true assume !(1 == ~q_write_ev~0); 51#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 55#L268-1true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 12#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70#L402true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2021-12-15 17:20:21,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,376 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2021-12-15 17:20:21,389 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493916808] [2021-12-15 17:20:21,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,583 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493916808] [2021-12-15 17:20:21,584 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493916808] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,585 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,586 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:21,588 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1399030288] [2021-12-15 17:20:21,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,593 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:21,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1951455462, now seen corresponding path program 1 times [2021-12-15 17:20:21,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788320664] [2021-12-15 17:20:21,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,630 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788320664] [2021-12-15 17:20:21,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1788320664] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,652 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,653 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:21,653 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423752643] [2021-12-15 17:20:21,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,654 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:21,656 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:21,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:21,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:21,716 INFO L87 Difference]: Start difference. First operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:21,756 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2021-12-15 17:20:21,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:21,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2021-12-15 17:20:21,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-15 17:20:21,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2021-12-15 17:20:21,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2021-12-15 17:20:21,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2021-12-15 17:20:21,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2021-12-15 17:20:21,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:21,777 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-15 17:20:21,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2021-12-15 17:20:21,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2021-12-15 17:20:21,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2021-12-15 17:20:21,808 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-15 17:20:21,808 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-15 17:20:21,808 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:21,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2021-12-15 17:20:21,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-15 17:20:21,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:21,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:21,814 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,814 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,815 INFO L791 eck$LassoCheckResult]: Stem: 307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 249#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 245#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 281#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 300#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 298#L275 assume !(0 == ~q_read_ev~0); 299#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 284#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 283#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 241#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 242#L315 assume !(0 != activate_threads_~tmp~1#1); 251#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 252#L84 assume 1 == ~c_dr_pc~0; 291#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 262#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 263#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 224#L323 assume !(0 != activate_threads_~tmp___0~1#1); 225#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306#L293 assume !(1 == ~q_read_ev~0); 213#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 214#L298-1 assume { :end_inline_reset_delta_events } true; 247#L419-2 [2021-12-15 17:20:21,815 INFO L793 eck$LassoCheckResult]: Loop: 247#L419-2 assume !false; 248#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 236#L364 assume !false; 285#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 259#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 266#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 267#L344 assume !(0 != eval_~tmp___1~0#1); 230#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231#L222-3 assume !(1 == ~q_req_up~0); 292#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 279#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 280#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 305#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 232#L65-3 assume !(1 == ~p_dw_pc~0); 233#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 270#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 264#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 265#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 293#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 278#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 222#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 223#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 276#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 228#L293-5 assume !(1 == ~q_write_ev~0); 229#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 288#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 289#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 215#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 216#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 239#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 240#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 261#L436 assume !(0 != start_simulation_~tmp~4#1); 247#L419-2 [2021-12-15 17:20:21,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,816 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2021-12-15 17:20:21,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039718799] [2021-12-15 17:20:21,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,817 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039718799] [2021-12-15 17:20:21,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039718799] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:21,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575073524] [2021-12-15 17:20:21,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,895 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:21,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,896 INFO L85 PathProgramCache]: Analyzing trace with hash -1517218729, now seen corresponding path program 1 times [2021-12-15 17:20:21,896 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679096022] [2021-12-15 17:20:21,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,925 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679096022] [2021-12-15 17:20:21,925 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679096022] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,925 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,925 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:21,925 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340059170] [2021-12-15 17:20:21,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,926 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:21,926 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:21,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:21,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:21,927 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:21,992 INFO L93 Difference]: Finished difference Result 211 states and 299 transitions. [2021-12-15 17:20:21,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:21,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 299 transitions. [2021-12-15 17:20:21,995 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 177 [2021-12-15 17:20:21,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 211 states and 299 transitions. [2021-12-15 17:20:21,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211 [2021-12-15 17:20:21,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211 [2021-12-15 17:20:21,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211 states and 299 transitions. [2021-12-15 17:20:21,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:21,999 INFO L681 BuchiCegarLoop]: Abstraction has 211 states and 299 transitions. [2021-12-15 17:20:21,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states and 299 transitions. [2021-12-15 17:20:22,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 196. [2021-12-15 17:20:22,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.4285714285714286) internal successors, (280), 195 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 280 transitions. [2021-12-15 17:20:22,012 INFO L704 BuchiCegarLoop]: Abstraction has 196 states and 280 transitions. [2021-12-15 17:20:22,013 INFO L587 BuchiCegarLoop]: Abstraction has 196 states and 280 transitions. [2021-12-15 17:20:22,013 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:22,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 280 transitions. [2021-12-15 17:20:22,019 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 164 [2021-12-15 17:20:22,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,020 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,020 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,020 INFO L791 eck$LassoCheckResult]: Stem: 624#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 564#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 565#L222 assume !(1 == ~q_req_up~0); 560#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 598#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 615#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 612#L275 assume !(0 == ~q_read_ev~0); 613#L275-2 assume !(0 == ~q_write_ev~0); 599#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 600#L65 assume !(1 == ~p_dw_pc~0); 606#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 607#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 556#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 557#L315 assume !(0 != activate_threads_~tmp~1#1); 566#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 567#L84 assume !(1 == ~c_dr_pc~0); 587#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 578#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 579#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 540#L323 assume !(0 != activate_threads_~tmp___0~1#1); 541#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 623#L293 assume !(1 == ~q_read_ev~0); 532#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 533#L298-1 assume { :end_inline_reset_delta_events } true; 619#L419-2 [2021-12-15 17:20:22,020 INFO L793 eck$LassoCheckResult]: Loop: 619#L419-2 assume !false; 695#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 692#L364 assume !false; 690#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 688#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 686#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 684#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 682#L344 assume !(0 != eval_~tmp___1~0#1); 679#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 676#L222-3 assume !(1 == ~q_req_up~0); 672#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 668#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 663#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 660#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 548#L65-3 assume !(1 == ~p_dw_pc~0); 549#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 586#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 580#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 581#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 724#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 723#L84-3 assume !(1 == ~c_dr_pc~0); 722#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 721#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 720#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 719#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 593#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 594#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 544#L293-5 assume !(1 == ~q_write_ev~0); 545#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 713#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 712#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 710#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 708#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 706#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 704#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 702#L436 assume !(0 != start_simulation_~tmp~4#1); 619#L419-2 [2021-12-15 17:20:22,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2021-12-15 17:20:22,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740254530] [2021-12-15 17:20:22,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,022 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,055 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,055 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740254530] [2021-12-15 17:20:22,055 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740254530] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,055 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,056 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:22,056 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710037719] [2021-12-15 17:20:22,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,056 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,057 INFO L85 PathProgramCache]: Analyzing trace with hash -340614410, now seen corresponding path program 1 times [2021-12-15 17:20:22,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105973136] [2021-12-15 17:20:22,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,058 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,098 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105973136] [2021-12-15 17:20:22,099 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105973136] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,099 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,099 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,099 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675012649] [2021-12-15 17:20:22,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,100 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,100 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:22,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:22,101 INFO L87 Difference]: Start difference. First operand 196 states and 280 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,188 INFO L93 Difference]: Finished difference Result 449 states and 621 transitions. [2021-12-15 17:20:22,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:22,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 621 transitions. [2021-12-15 17:20:22,193 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2021-12-15 17:20:22,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 621 transitions. [2021-12-15 17:20:22,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2021-12-15 17:20:22,199 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2021-12-15 17:20:22,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 621 transitions. [2021-12-15 17:20:22,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,206 INFO L681 BuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2021-12-15 17:20:22,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 621 transitions. [2021-12-15 17:20:22,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2021-12-15 17:20:22,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.3830734966592428) internal successors, (621), 448 states have internal predecessors, (621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 621 transitions. [2021-12-15 17:20:22,229 INFO L704 BuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2021-12-15 17:20:22,229 INFO L587 BuchiCegarLoop]: Abstraction has 449 states and 621 transitions. [2021-12-15 17:20:22,229 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:22,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 621 transitions. [2021-12-15 17:20:22,231 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 375 [2021-12-15 17:20:22,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,232 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,232 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,233 INFO L791 eck$LassoCheckResult]: Stem: 1299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1222#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1223#L222 assume !(1 == ~q_req_up~0); 1232#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1260#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1261#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1279#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1338#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1278#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1289#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1326#L65 assume !(1 == ~p_dw_pc~0); 1325#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1324#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1323#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1322#L315 assume !(0 != activate_threads_~tmp~1#1); 1321#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1320#L84 assume !(1 == ~c_dr_pc~0); 1319#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1318#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1317#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1316#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1315#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1314#L293 assume !(1 == ~q_read_ev~0); 1312#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1313#L298-1 assume { :end_inline_reset_delta_events } true; 1503#L419-2 [2021-12-15 17:20:22,233 INFO L793 eck$LassoCheckResult]: Loop: 1503#L419-2 assume !false; 1497#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1494#L364 assume !false; 1493#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1491#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1489#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1488#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1486#L344 assume !(0 != eval_~tmp___1~0#1); 1487#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1580#L222-3 assume !(1 == ~q_req_up~0); 1578#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1577#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1572#L275-5 assume !(0 == ~q_write_ev~0); 1570#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1568#L65-3 assume !(1 == ~p_dw_pc~0); 1566#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 1564#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1562#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1560#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1558#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1556#L84-3 assume !(1 == ~c_dr_pc~0); 1554#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1552#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1550#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1548#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1546#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1544#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1538#L293-5 assume !(1 == ~q_write_ev~0); 1537#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1533#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1530#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1528#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1527#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1526#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1517#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1507#L436 assume !(0 != start_simulation_~tmp~4#1); 1503#L419-2 [2021-12-15 17:20:22,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,233 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2021-12-15 17:20:22,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381115674] [2021-12-15 17:20:22,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,255 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381115674] [2021-12-15 17:20:22,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381115674] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,255 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,255 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104462880] [2021-12-15 17:20:22,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,256 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,256 INFO L85 PathProgramCache]: Analyzing trace with hash -474627916, now seen corresponding path program 1 times [2021-12-15 17:20:22,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567029686] [2021-12-15 17:20:22,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,257 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567029686] [2021-12-15 17:20:22,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1567029686] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,284 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,284 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,284 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324710596] [2021-12-15 17:20:22,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,285 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,285 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:22,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:22,286 INFO L87 Difference]: Start difference. First operand 449 states and 621 transitions. cyclomatic complexity: 176 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,309 INFO L93 Difference]: Finished difference Result 701 states and 951 transitions. [2021-12-15 17:20:22,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:22,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 951 transitions. [2021-12-15 17:20:22,316 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 586 [2021-12-15 17:20:22,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 701 states and 951 transitions. [2021-12-15 17:20:22,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 701 [2021-12-15 17:20:22,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 701 [2021-12-15 17:20:22,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 701 states and 951 transitions. [2021-12-15 17:20:22,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,321 INFO L681 BuchiCegarLoop]: Abstraction has 701 states and 951 transitions. [2021-12-15 17:20:22,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states and 951 transitions. [2021-12-15 17:20:22,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 510. [2021-12-15 17:20:22,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.3588235294117648) internal successors, (693), 509 states have internal predecessors, (693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 693 transitions. [2021-12-15 17:20:22,336 INFO L704 BuchiCegarLoop]: Abstraction has 510 states and 693 transitions. [2021-12-15 17:20:22,336 INFO L587 BuchiCegarLoop]: Abstraction has 510 states and 693 transitions. [2021-12-15 17:20:22,336 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:22,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 693 transitions. [2021-12-15 17:20:22,338 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 422 [2021-12-15 17:20:22,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,341 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,341 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,341 INFO L791 eck$LassoCheckResult]: Stem: 2451#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2380#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2381#L222 assume !(1 == ~q_req_up~0); 2376#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2377#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2418#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2436#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2433#L275 assume !(0 == ~q_read_ev~0); 2434#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2442#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2483#L65 assume !(1 == ~p_dw_pc~0); 2481#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2479#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2477#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2475#L315 assume !(0 != activate_threads_~tmp~1#1); 2473#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2471#L84 assume !(1 == ~c_dr_pc~0); 2469#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2467#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2465#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2463#L323 assume !(0 != activate_threads_~tmp___0~1#1); 2461#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2459#L293 assume !(1 == ~q_read_ev~0); 2456#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2348#L298-1 assume { :end_inline_reset_delta_events } true; 2441#L419-2 [2021-12-15 17:20:22,341 INFO L793 eck$LassoCheckResult]: Loop: 2441#L419-2 assume !false; 2425#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2393#L364 assume !false; 2421#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2391#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2354#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2535#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2532#L344 assume !(0 != eval_~tmp___1~0#1); 2533#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2853#L222-3 assume !(1 == ~q_req_up~0); 2851#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2850#L275-3 assume !(0 == ~q_read_ev~0); 2443#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2444#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2840#L65-3 assume !(1 == ~p_dw_pc~0); 2839#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2838#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2837#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2836#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2835#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2834#L84-3 assume !(1 == ~c_dr_pc~0); 2833#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2832#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2831#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2830#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2829#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2828#L293-3 assume !(1 == ~q_read_ev~0); 2702#L293-5 assume !(1 == ~q_write_ev~0); 2358#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2422#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2423#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2345#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2346#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2370#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2371#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2549#L436 assume !(0 != start_simulation_~tmp~4#1); 2441#L419-2 [2021-12-15 17:20:22,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,342 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2021-12-15 17:20:22,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673978084] [2021-12-15 17:20:22,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,342 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,377 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673978084] [2021-12-15 17:20:22,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673978084] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:22,378 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773336880] [2021-12-15 17:20:22,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,378 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,379 INFO L85 PathProgramCache]: Analyzing trace with hash -593092810, now seen corresponding path program 1 times [2021-12-15 17:20:22,379 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,379 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401334948] [2021-12-15 17:20:22,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,379 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,405 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,405 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401334948] [2021-12-15 17:20:22,405 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [401334948] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,405 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,405 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,405 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034618617] [2021-12-15 17:20:22,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,406 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,406 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:22,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:22,407 INFO L87 Difference]: Start difference. First operand 510 states and 693 transitions. cyclomatic complexity: 185 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,468 INFO L93 Difference]: Finished difference Result 745 states and 1002 transitions. [2021-12-15 17:20:22,468 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-15 17:20:22,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 1002 transitions. [2021-12-15 17:20:22,473 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 622 [2021-12-15 17:20:22,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 745 states and 1002 transitions. [2021-12-15 17:20:22,476 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 745 [2021-12-15 17:20:22,477 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 745 [2021-12-15 17:20:22,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 745 states and 1002 transitions. [2021-12-15 17:20:22,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,478 INFO L681 BuchiCegarLoop]: Abstraction has 745 states and 1002 transitions. [2021-12-15 17:20:22,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states and 1002 transitions. [2021-12-15 17:20:22,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 563. [2021-12-15 17:20:22,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 563 states, 563 states have (on average 1.3481349911190053) internal successors, (759), 562 states have internal predecessors, (759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 759 transitions. [2021-12-15 17:20:22,489 INFO L704 BuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2021-12-15 17:20:22,489 INFO L587 BuchiCegarLoop]: Abstraction has 563 states and 759 transitions. [2021-12-15 17:20:22,489 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:22,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 563 states and 759 transitions. [2021-12-15 17:20:22,492 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 458 [2021-12-15 17:20:22,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,492 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,493 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,493 INFO L791 eck$LassoCheckResult]: Stem: 3712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3645#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3646#L222 assume !(1 == ~q_req_up~0); 3641#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3642#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3771#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3705#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3696#L275 assume !(0 == ~q_read_ev~0); 3697#L275-2 assume !(0 == ~q_write_ev~0); 3683#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3684#L65 assume !(1 == ~p_dw_pc~0); 3690#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3691#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3639#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3640#L315 assume !(0 != activate_threads_~tmp~1#1); 3647#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3648#L84 assume !(1 == ~c_dr_pc~0); 3669#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3662#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3663#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3620#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3621#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3709#L293 assume !(1 == ~q_read_ev~0); 3612#L293-2 assume !(1 == ~q_write_ev~0); 3613#L298-1 assume { :end_inline_reset_delta_events } true; 3704#L419-2 [2021-12-15 17:20:22,493 INFO L793 eck$LassoCheckResult]: Loop: 3704#L419-2 assume !false; 3827#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3719#L364 assume !false; 3682#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3656#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3615#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3664#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3665#L344 assume !(0 != eval_~tmp___1~0#1); 3626#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3627#L222-3 assume !(1 == ~q_req_up~0); 3689#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3678#L275-3 assume !(0 == ~q_read_ev~0); 3679#L275-5 assume !(0 == ~q_write_ev~0); 3706#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3628#L65-3 assume !(1 == ~p_dw_pc~0); 3629#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3668#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3660#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3661#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 4157#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4156#L84-3 assume !(1 == ~c_dr_pc~0); 4155#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4153#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4152#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4150#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4149#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4148#L293-3 assume !(1 == ~q_read_ev~0); 4102#L293-5 assume !(1 == ~q_write_ev~0); 3720#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3721#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4098#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4095#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3834#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3832#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3831#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3828#L436 assume !(0 != start_simulation_~tmp~4#1); 3704#L419-2 [2021-12-15 17:20:22,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2021-12-15 17:20:22,494 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003168527] [2021-12-15 17:20:22,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,495 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,500 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:22,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,520 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:22,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,521 INFO L85 PathProgramCache]: Analyzing trace with hash -727106316, now seen corresponding path program 1 times [2021-12-15 17:20:22,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177938982] [2021-12-15 17:20:22,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,522 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177938982] [2021-12-15 17:20:22,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177938982] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,547 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,547 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334536006] [2021-12-15 17:20:22,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,548 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,548 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:22,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:22,549 INFO L87 Difference]: Start difference. First operand 563 states and 759 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,604 INFO L93 Difference]: Finished difference Result 763 states and 1023 transitions. [2021-12-15 17:20:22,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:22,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 763 states and 1023 transitions. [2021-12-15 17:20:22,609 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 654 [2021-12-15 17:20:22,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 763 states to 763 states and 1023 transitions. [2021-12-15 17:20:22,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 763 [2021-12-15 17:20:22,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 763 [2021-12-15 17:20:22,614 INFO L73 IsDeterministic]: Start isDeterministic. Operand 763 states and 1023 transitions. [2021-12-15 17:20:22,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,615 INFO L681 BuchiCegarLoop]: Abstraction has 763 states and 1023 transitions. [2021-12-15 17:20:22,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states and 1023 transitions. [2021-12-15 17:20:22,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 581. [2021-12-15 17:20:22,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 581 states, 581 states have (on average 1.3373493975903614) internal successors, (777), 580 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 777 transitions. [2021-12-15 17:20:22,625 INFO L704 BuchiCegarLoop]: Abstraction has 581 states and 777 transitions. [2021-12-15 17:20:22,625 INFO L587 BuchiCegarLoop]: Abstraction has 581 states and 777 transitions. [2021-12-15 17:20:22,625 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:22,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 581 states and 777 transitions. [2021-12-15 17:20:22,628 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 476 [2021-12-15 17:20:22,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,629 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,629 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,630 INFO L791 eck$LassoCheckResult]: Stem: 5075#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 5044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4986#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4987#L222 assume !(1 == ~q_req_up~0); 4999#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5148#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5146#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5063#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5048#L275 assume !(0 == ~q_read_ev~0); 5049#L275-2 assume !(0 == ~q_write_ev~0); 5064#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5121#L65 assume !(1 == ~p_dw_pc~0); 5119#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 5117#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5115#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5113#L315 assume !(0 != activate_threads_~tmp~1#1); 5111#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5109#L84 assume !(1 == ~c_dr_pc~0); 5107#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 5105#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5103#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5101#L323 assume !(0 != activate_threads_~tmp___0~1#1); 5099#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5097#L293 assume !(1 == ~q_read_ev~0); 4952#L293-2 assume !(1 == ~q_write_ev~0); 4953#L298-1 assume { :end_inline_reset_delta_events } true; 5467#L419-2 [2021-12-15 17:20:22,630 INFO L793 eck$LassoCheckResult]: Loop: 5467#L419-2 assume !false; 5466#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5460#L364 assume !false; 5454#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5449#L255 assume !(0 == ~p_dw_st~0); 5439#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5427#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5422#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5421#L344 assume !(0 != eval_~tmp___1~0#1); 5420#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5037#L222-3 assume !(1 == ~q_req_up~0); 5038#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5027#L275-3 assume !(0 == ~q_read_ev~0); 5028#L275-5 assume !(0 == ~q_write_ev~0); 5067#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4971#L65-3 assume !(1 == ~p_dw_pc~0); 4972#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5518#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5517#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5516#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5515#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5514#L84-3 assume !(1 == ~c_dr_pc~0); 5513#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5512#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5511#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5510#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5492#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5487#L293-3 assume !(1 == ~q_read_ev~0); 5483#L293-5 assume !(1 == ~q_write_ev~0); 5482#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5480#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5478#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5476#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5475#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5473#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5471#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5470#L436 assume !(0 != start_simulation_~tmp~4#1); 5467#L419-2 [2021-12-15 17:20:22,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2021-12-15 17:20:22,631 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286725462] [2021-12-15 17:20:22,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,632 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,641 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:22,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,654 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:22,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,654 INFO L85 PathProgramCache]: Analyzing trace with hash -366252558, now seen corresponding path program 1 times [2021-12-15 17:20:22,655 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,655 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740895876] [2021-12-15 17:20:22,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,655 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,724 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740895876] [2021-12-15 17:20:22,725 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740895876] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,725 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,725 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,725 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551717517] [2021-12-15 17:20:22,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,725 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,726 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:22,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:22,726 INFO L87 Difference]: Start difference. First operand 581 states and 777 transitions. cyclomatic complexity: 198 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,784 INFO L93 Difference]: Finished difference Result 1103 states and 1485 transitions. [2021-12-15 17:20:22,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:22,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1103 states and 1485 transitions. [2021-12-15 17:20:22,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 998 [2021-12-15 17:20:22,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1103 states to 1103 states and 1485 transitions. [2021-12-15 17:20:22,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1103 [2021-12-15 17:20:22,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1103 [2021-12-15 17:20:22,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1103 states and 1485 transitions. [2021-12-15 17:20:22,797 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,797 INFO L681 BuchiCegarLoop]: Abstraction has 1103 states and 1485 transitions. [2021-12-15 17:20:22,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1103 states and 1485 transitions. [2021-12-15 17:20:22,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1103 to 593. [2021-12-15 17:20:22,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 593 states, 593 states have (on average 1.3102866779089377) internal successors, (777), 592 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 593 states to 593 states and 777 transitions. [2021-12-15 17:20:22,809 INFO L704 BuchiCegarLoop]: Abstraction has 593 states and 777 transitions. [2021-12-15 17:20:22,809 INFO L587 BuchiCegarLoop]: Abstraction has 593 states and 777 transitions. [2021-12-15 17:20:22,809 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:22,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 593 states and 777 transitions. [2021-12-15 17:20:22,812 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2021-12-15 17:20:22,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,812 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,812 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,813 INFO L791 eck$LassoCheckResult]: Stem: 6766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6685#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6686#L222 assume !(1 == ~q_req_up~0); 6681#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6682#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6726#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6743#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6817#L275 assume !(0 == ~q_read_ev~0); 6756#L275-2 assume !(0 == ~q_write_ev~0); 6757#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6805#L65 assume !(1 == ~p_dw_pc~0); 6803#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6801#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6799#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6797#L315 assume !(0 != activate_threads_~tmp~1#1); 6795#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6793#L84 assume !(1 == ~c_dr_pc~0); 6791#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6789#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6787#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6785#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6783#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6781#L293 assume !(1 == ~q_read_ev~0); 6780#L293-2 assume !(1 == ~q_write_ev~0); 6753#L298-1 assume { :end_inline_reset_delta_events } true; 6754#L419-2 [2021-12-15 17:20:22,813 INFO L793 eck$LassoCheckResult]: Loop: 6754#L419-2 assume !false; 6904#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6898#L364 assume !false; 6896#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6894#L255 assume !(0 == ~p_dw_st~0); 6891#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6888#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6886#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6883#L344 assume !(0 != eval_~tmp___1~0#1); 6880#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6877#L222-3 assume !(1 == ~q_req_up~0); 6878#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6931#L275-3 assume !(0 == ~q_read_ev~0); 6932#L275-5 assume !(0 == ~q_write_ev~0); 6991#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6668#L65-3 assume !(1 == ~p_dw_pc~0); 6669#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6990#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6989#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6985#L315-3 assume !(0 != activate_threads_~tmp~1#1); 6981#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6977#L84-3 assume !(1 == ~c_dr_pc~0); 6973#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6969#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6965#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6961#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6957#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6953#L293-3 assume !(1 == ~q_read_ev~0); 6934#L293-5 assume !(1 == ~q_write_ev~0); 6942#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6937#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6929#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6926#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6924#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6921#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6918#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6915#L436 assume !(0 != start_simulation_~tmp~4#1); 6754#L419-2 [2021-12-15 17:20:22,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2021-12-15 17:20:22,813 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486133380] [2021-12-15 17:20:22,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,814 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,818 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:22,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,824 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:22,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1934570032, now seen corresponding path program 1 times [2021-12-15 17:20:22,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017276276] [2021-12-15 17:20:22,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,839 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,839 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017276276] [2021-12-15 17:20:22,840 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017276276] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,840 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,840 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,840 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545313374] [2021-12-15 17:20:22,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,840 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,840 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,841 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:22,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:22,841 INFO L87 Difference]: Start difference. First operand 593 states and 777 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,859 INFO L93 Difference]: Finished difference Result 832 states and 1065 transitions. [2021-12-15 17:20:22,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:22,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 832 states and 1065 transitions. [2021-12-15 17:20:22,864 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-15 17:20:22,867 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 832 states to 832 states and 1065 transitions. [2021-12-15 17:20:22,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 832 [2021-12-15 17:20:22,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 832 [2021-12-15 17:20:22,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 832 states and 1065 transitions. [2021-12-15 17:20:22,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,869 INFO L681 BuchiCegarLoop]: Abstraction has 832 states and 1065 transitions. [2021-12-15 17:20:22,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 832 states and 1065 transitions. [2021-12-15 17:20:22,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 832 to 832. [2021-12-15 17:20:22,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 832 states, 832 states have (on average 1.2800480769230769) internal successors, (1065), 831 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 832 states to 832 states and 1065 transitions. [2021-12-15 17:20:22,901 INFO L704 BuchiCegarLoop]: Abstraction has 832 states and 1065 transitions. [2021-12-15 17:20:22,901 INFO L587 BuchiCegarLoop]: Abstraction has 832 states and 1065 transitions. [2021-12-15 17:20:22,901 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:22,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 832 states and 1065 transitions. [2021-12-15 17:20:22,904 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-15 17:20:22,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,905 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,905 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,905 INFO L791 eck$LassoCheckResult]: Stem: 8200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8114#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8115#L222 assume !(1 == ~q_req_up~0); 8112#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8113#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 8155#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8329#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8327#L275 assume !(0 == ~q_read_ev~0); 8325#L275-2 assume !(0 == ~q_write_ev~0); 8280#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8323#L65 assume !(1 == ~p_dw_pc~0); 8321#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8319#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8317#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8315#L315 assume !(0 != activate_threads_~tmp~1#1); 8313#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8311#L84 assume !(1 == ~c_dr_pc~0); 8309#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8307#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8305#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8303#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8301#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8299#L293 assume !(1 == ~q_read_ev~0); 8298#L293-2 assume !(1 == ~q_write_ev~0); 8186#L298-1 assume { :end_inline_reset_delta_events } true; 8116#L419-2 [2021-12-15 17:20:22,905 INFO L793 eck$LassoCheckResult]: Loop: 8116#L419-2 assume !false; 8117#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8173#L364 assume !false; 8213#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8835#L255 assume !(0 == ~p_dw_st~0); 8237#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8833#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8911#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8901#L344 assume !(0 != eval_~tmp___1~0#1); 8899#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8897#L222-3 assume !(1 == ~q_req_up~0); 8183#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8153#L275-3 assume !(0 == ~q_read_ev~0); 8154#L275-5 assume !(0 == ~q_write_ev~0); 8193#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8216#L65-3 assume !(1 == ~p_dw_pc~0); 8877#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8191#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8192#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8870#L315-3 assume !(0 != activate_threads_~tmp~1#1); 8169#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8087#L84-3 assume !(1 == ~c_dr_pc~0); 8088#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8152#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8089#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8090#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8150#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8151#L293-3 assume !(1 == ~q_read_ev~0); 8188#L293-5 assume !(1 == ~q_write_ev~0); 8215#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8160#L255-1 assume !(0 == ~p_dw_st~0); 8161#L259-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8162#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8163#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8842#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8841#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8840#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8166#L436 assume !(0 != start_simulation_~tmp~4#1); 8116#L419-2 [2021-12-15 17:20:22,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,906 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2021-12-15 17:20:22,906 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507520102] [2021-12-15 17:20:22,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,906 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,919 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,919 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [507520102] [2021-12-15 17:20:22,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [507520102] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,919 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,919 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,920 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082035836] [2021-12-15 17:20:22,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,920 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,920 INFO L85 PathProgramCache]: Analyzing trace with hash -282414912, now seen corresponding path program 1 times [2021-12-15 17:20:22,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310662136] [2021-12-15 17:20:22,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,971 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,971 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310662136] [2021-12-15 17:20:22,971 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1310662136] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,972 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,972 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,972 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756091746] [2021-12-15 17:20:22,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,972 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,972 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:22,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:22,973 INFO L87 Difference]: Start difference. First operand 832 states and 1065 transitions. cyclomatic complexity: 237 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,979 INFO L93 Difference]: Finished difference Result 754 states and 971 transitions. [2021-12-15 17:20:22,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:22,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 754 states and 971 transitions. [2021-12-15 17:20:22,983 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-15 17:20:22,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 754 states to 754 states and 971 transitions. [2021-12-15 17:20:22,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 754 [2021-12-15 17:20:22,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 754 [2021-12-15 17:20:22,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 754 states and 971 transitions. [2021-12-15 17:20:22,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,988 INFO L681 BuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2021-12-15 17:20:22,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states and 971 transitions. [2021-12-15 17:20:22,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 754. [2021-12-15 17:20:22,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 754 states, 754 states have (on average 1.2877984084880636) internal successors, (971), 753 states have internal predecessors, (971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 971 transitions. [2021-12-15 17:20:22,998 INFO L704 BuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2021-12-15 17:20:22,998 INFO L587 BuchiCegarLoop]: Abstraction has 754 states and 971 transitions. [2021-12-15 17:20:22,998 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:22,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 754 states and 971 transitions. [2021-12-15 17:20:23,001 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 645 [2021-12-15 17:20:23,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,002 INFO L791 eck$LassoCheckResult]: Stem: 9790#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 9769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9711#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9712#L222 assume !(1 == ~q_req_up~0); 9722#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9753#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9754#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9774#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9771#L275 assume !(0 == ~q_read_ev~0); 9772#L275-2 assume !(0 == ~q_write_ev~0); 9783#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9829#L65 assume !(1 == ~p_dw_pc~0); 9827#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 9825#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9823#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9821#L315 assume !(0 != activate_threads_~tmp~1#1); 9819#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9817#L84 assume !(1 == ~c_dr_pc~0); 9815#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 9813#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9811#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9809#L323 assume !(0 != activate_threads_~tmp___0~1#1); 9807#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9805#L293 assume !(1 == ~q_read_ev~0); 9804#L293-2 assume !(1 == ~q_write_ev~0); 9781#L298-1 assume { :end_inline_reset_delta_events } true; 9782#L419-2 assume !false; 10323#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10317#L364 [2021-12-15 17:20:23,003 INFO L793 eck$LassoCheckResult]: Loop: 10317#L364 assume !false; 10320#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10318#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10302#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10300#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10292#L344 assume 0 != eval_~tmp___1~0#1; 9876#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 9877#L353 assume !(0 != eval_~tmp~2#1); 10225#L349 assume !(0 == ~c_dr_st~0); 10317#L364 [2021-12-15 17:20:23,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,003 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2021-12-15 17:20:23,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569246284] [2021-12-15 17:20:23,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,004 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,008 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:23,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,016 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:23,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,017 INFO L85 PathProgramCache]: Analyzing trace with hash -479000201, now seen corresponding path program 1 times [2021-12-15 17:20:23,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616956597] [2021-12-15 17:20:23,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,018 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,021 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:23,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,024 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:23,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,025 INFO L85 PathProgramCache]: Analyzing trace with hash 519639655, now seen corresponding path program 1 times [2021-12-15 17:20:23,025 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1559818249] [2021-12-15 17:20:23,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,026 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,041 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1559818249] [2021-12-15 17:20:23,041 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1559818249] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,041 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,041 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:23,041 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524785931] [2021-12-15 17:20:23,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,086 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:23,091 INFO L158 Benchmark]: Toolchain (without parser) took 2516.79ms. Allocated memory was 102.8MB in the beginning and 134.2MB in the end (delta: 31.5MB). Free memory was 63.4MB in the beginning and 72.9MB in the end (delta: -9.5MB). Peak memory consumption was 20.9MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,092 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 102.8MB. Free memory is still 79.7MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:23,093 INFO L158 Benchmark]: CACSL2BoogieTranslator took 231.53ms. Allocated memory is still 102.8MB. Free memory was 63.2MB in the beginning and 75.4MB in the end (delta: -12.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,094 INFO L158 Benchmark]: Boogie Procedure Inliner took 33.28ms. Allocated memory is still 102.8MB. Free memory was 75.4MB in the beginning and 73.3MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,094 INFO L158 Benchmark]: Boogie Preprocessor took 28.58ms. Allocated memory is still 102.8MB. Free memory was 73.3MB in the beginning and 71.7MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,095 INFO L158 Benchmark]: RCFGBuilder took 367.34ms. Allocated memory is still 102.8MB. Free memory was 71.7MB in the beginning and 56.6MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,095 INFO L158 Benchmark]: BuchiAutomizer took 1851.08ms. Allocated memory was 102.8MB in the beginning and 134.2MB in the end (delta: 31.5MB). Free memory was 56.6MB in the beginning and 72.9MB in the end (delta: -16.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,098 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 102.8MB. Free memory is still 79.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 231.53ms. Allocated memory is still 102.8MB. Free memory was 63.2MB in the beginning and 75.4MB in the end (delta: -12.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 33.28ms. Allocated memory is still 102.8MB. Free memory was 75.4MB in the beginning and 73.3MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 28.58ms. Allocated memory is still 102.8MB. Free memory was 73.3MB in the beginning and 71.7MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 367.34ms. Allocated memory is still 102.8MB. Free memory was 71.7MB in the beginning and 56.6MB in the end (delta: 15.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 1851.08ms. Allocated memory was 102.8MB in the beginning and 134.2MB in the end (delta: 31.5MB). Free memory was 56.6MB in the beginning and 72.9MB in the end (delta: -16.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:23,128 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable