./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:19,478 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:19,480 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:19,527 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:19,528 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:19,529 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:19,530 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:19,531 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:19,532 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:19,533 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:19,533 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:19,534 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:19,534 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:19,535 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:19,536 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:19,537 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:19,537 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:19,538 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:19,539 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:19,540 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:19,541 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:19,549 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:19,550 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:19,550 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:19,552 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:19,552 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:19,552 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:19,553 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:19,553 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:19,560 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:19,560 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:19,560 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:19,561 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:19,561 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:19,562 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:19,562 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:19,563 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:19,563 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:19,563 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:19,564 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:19,564 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:19,565 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:19,594 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:19,595 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:19,595 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:19,595 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:19,596 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:19,596 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:19,596 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:19,596 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:19,596 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:19,596 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:19,597 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:19,597 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:19,597 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:19,597 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:19,597 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:19,602 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:19,602 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:19,602 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:19,602 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:19,603 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:19,603 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:19,603 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:19,603 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:19,603 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:19,603 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:19,603 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:19,604 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:19,604 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:19,604 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:19,604 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:19,604 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:19,604 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:19,605 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:19,605 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de [2021-12-15 17:20:19,790 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:19,817 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:19,819 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:19,820 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:19,820 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:19,821 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2021-12-15 17:20:19,917 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3721a79e6/12d2527cd8704332b14b125871cdd4fa/FLAG05afdaf78 [2021-12-15 17:20:20,250 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:20,252 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2021-12-15 17:20:20,262 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3721a79e6/12d2527cd8704332b14b125871cdd4fa/FLAG05afdaf78 [2021-12-15 17:20:20,692 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3721a79e6/12d2527cd8704332b14b125871cdd4fa [2021-12-15 17:20:20,704 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:20,705 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:20,711 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:20,712 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:20,725 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:20,725 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,726 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6635f824 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:20, skipping insertion in model container [2021-12-15 17:20:20,726 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:20" (1/1) ... [2021-12-15 17:20:20,734 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:20,781 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:20,932 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c[643,656] [2021-12-15 17:20:20,982 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:20,993 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:21,002 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c[643,656] [2021-12-15 17:20:21,030 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:21,049 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:21,050 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21 WrapperNode [2021-12-15 17:20:21,050 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:21,051 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:21,052 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:21,052 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:21,056 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,069 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,096 INFO L137 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 28, statements flattened = 308 [2021-12-15 17:20:21,096 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:21,097 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:21,097 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:21,097 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:21,103 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,103 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,112 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,113 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,120 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,128 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,137 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,138 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:21,139 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:21,139 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:21,139 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:21,143 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (1/1) ... [2021-12-15 17:20:21,147 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:21,154 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:21,176 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:21,193 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:21,206 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:21,207 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:21,207 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:21,207 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:21,261 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:21,262 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:21,449 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:21,454 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:21,455 INFO L301 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-15 17:20:21,456 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:21 BoogieIcfgContainer [2021-12-15 17:20:21,456 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:21,457 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:21,457 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:21,459 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:21,459 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:21,460 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:20" (1/3) ... [2021-12-15 17:20:21,461 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2866e861 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:21, skipping insertion in model container [2021-12-15 17:20:21,461 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:21,461 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:21" (2/3) ... [2021-12-15 17:20:21,461 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2866e861 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:21, skipping insertion in model container [2021-12-15 17:20:21,461 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:21,462 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:21" (3/3) ... [2021-12-15 17:20:21,462 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-2.c [2021-12-15 17:20:21,488 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:21,489 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:21,489 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:21,489 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:21,489 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:21,489 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:21,489 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:21,490 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:21,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2021-12-15 17:20:21,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:21,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:21,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,541 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,541 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:21,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2021-12-15 17:20:21,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:21,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:21,557 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,557 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,563 INFO L791 eck$LassoCheckResult]: Stem: 101#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 30#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 65#L462true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69#L222true assume !(1 == ~q_req_up~0); 10#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 31#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 37#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L275true assume !(0 == ~q_read_ev~0); 95#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 107#L65true assume !(1 == ~p_dw_pc~0); 29#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 54#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 64#L77true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34#L315true assume !(0 != activate_threads_~tmp~1#1); 66#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 99#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 72#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 91#L96true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5#L323true assume !(0 != activate_threads_~tmp___0~1#1); 47#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100#L293true assume !(1 == ~q_read_ev~0); 3#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 35#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2021-12-15 17:20:21,564 INFO L793 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 103#L364true assume !true; 61#L380true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83#L222-3true assume !(1 == ~q_req_up~0); 32#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 39#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 53#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 62#L65-3true assume !(1 == ~p_dw_pc~0); 18#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 96#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 73#L77-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 40#L315-3true assume !(0 != activate_threads_~tmp~1#1); 84#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 58#L84-3true assume 1 == ~c_dr_pc~0; 42#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 79#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 59#L96-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 105#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 78#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 6#L293-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 52#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 56#L268-1true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 12#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71#L402true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2021-12-15 17:20:21,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,568 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2021-12-15 17:20:21,574 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348117777] [2021-12-15 17:20:21,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,575 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,677 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,678 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1348117777] [2021-12-15 17:20:21,678 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1348117777] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,678 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,679 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:21,680 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537428657] [2021-12-15 17:20:21,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,684 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:21,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,687 INFO L85 PathProgramCache]: Analyzing trace with hash -573197680, now seen corresponding path program 1 times [2021-12-15 17:20:21,687 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400366747] [2021-12-15 17:20:21,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,688 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,712 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400366747] [2021-12-15 17:20:21,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [400366747] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,713 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:21,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153371429] [2021-12-15 17:20:21,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,714 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:21,715 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:21,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:21,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:21,741 INFO L87 Difference]: Start difference. First operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:21,760 INFO L93 Difference]: Finished difference Result 102 states and 144 transitions. [2021-12-15 17:20:21,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:21,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 144 transitions. [2021-12-15 17:20:21,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-15 17:20:21,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 95 states and 137 transitions. [2021-12-15 17:20:21,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2021-12-15 17:20:21,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2021-12-15 17:20:21,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 137 transitions. [2021-12-15 17:20:21,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:21,775 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2021-12-15 17:20:21,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 137 transitions. [2021-12-15 17:20:21,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2021-12-15 17:20:21,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 137 transitions. [2021-12-15 17:20:21,802 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2021-12-15 17:20:21,802 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2021-12-15 17:20:21,803 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:21,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 137 transitions. [2021-12-15 17:20:21,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-15 17:20:21,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:21,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:21,807 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,807 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:21,808 INFO L791 eck$LassoCheckResult]: Stem: 310#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 252#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253#L222 assume !(1 == ~q_req_up~0); 248#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 249#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 284#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 303#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 301#L275 assume !(0 == ~q_read_ev~0); 302#L275-2 assume !(0 == ~q_write_ev~0); 288#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 289#L65 assume !(1 == ~p_dw_pc~0); 287#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 286#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 244#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 245#L315 assume !(0 != activate_threads_~tmp~1#1); 254#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 255#L84 assume 1 == ~c_dr_pc~0; 294#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 265#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 266#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 227#L323 assume !(0 != activate_threads_~tmp___0~1#1); 228#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L293 assume !(1 == ~q_read_ev~0); 216#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 217#L298-1 assume { :end_inline_reset_delta_events } true; 250#L419-2 [2021-12-15 17:20:21,808 INFO L793 eck$LassoCheckResult]: Loop: 250#L419-2 assume !false; 251#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 239#L364 assume !false; 290#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 262#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 221#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 269#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 270#L344 assume !(0 != eval_~tmp___1~0#1); 233#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 234#L222-3 assume !(1 == ~q_req_up~0); 295#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 283#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 308#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 235#L65-3 assume !(1 == ~p_dw_pc~0); 236#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 273#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 267#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 268#L315-3 assume !(0 != activate_threads_~tmp~1#1); 296#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 222#L84-3 assume !(1 == ~c_dr_pc~0); 224#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 281#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 225#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 226#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 279#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 231#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 232#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 291#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 292#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 218#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 219#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 242#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 243#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 264#L436 assume !(0 != start_simulation_~tmp~4#1); 250#L419-2 [2021-12-15 17:20:21,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,809 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2021-12-15 17:20:21,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285167407] [2021-12-15 17:20:21,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,810 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,862 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285167407] [2021-12-15 17:20:21,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285167407] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,863 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:21,863 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004167499] [2021-12-15 17:20:21,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,864 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:21,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:21,864 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 1 times [2021-12-15 17:20:21,864 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:21,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739808295] [2021-12-15 17:20:21,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:21,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:21,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:21,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:21,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:21,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739808295] [2021-12-15 17:20:21,924 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [739808295] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:21,924 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:21,924 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:21,924 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070577950] [2021-12-15 17:20:21,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:21,925 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:21,925 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:21,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:21,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:21,926 INFO L87 Difference]: Start difference. First operand 95 states and 137 transitions. cyclomatic complexity: 43 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:21,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:21,991 INFO L93 Difference]: Finished difference Result 211 states and 296 transitions. [2021-12-15 17:20:21,998 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:21,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 296 transitions. [2021-12-15 17:20:22,000 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 176 [2021-12-15 17:20:22,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 211 states and 296 transitions. [2021-12-15 17:20:22,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211 [2021-12-15 17:20:22,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211 [2021-12-15 17:20:22,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211 states and 296 transitions. [2021-12-15 17:20:22,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,006 INFO L681 BuchiCegarLoop]: Abstraction has 211 states and 296 transitions. [2021-12-15 17:20:22,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states and 296 transitions. [2021-12-15 17:20:22,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 196. [2021-12-15 17:20:22,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.413265306122449) internal successors, (277), 195 states have internal predecessors, (277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 277 transitions. [2021-12-15 17:20:22,019 INFO L704 BuchiCegarLoop]: Abstraction has 196 states and 277 transitions. [2021-12-15 17:20:22,019 INFO L587 BuchiCegarLoop]: Abstraction has 196 states and 277 transitions. [2021-12-15 17:20:22,020 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:22,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 277 transitions. [2021-12-15 17:20:22,021 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 163 [2021-12-15 17:20:22,023 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,023 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,024 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,024 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,025 INFO L791 eck$LassoCheckResult]: Stem: 631#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 569#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 570#L222 assume !(1 == ~q_req_up~0); 565#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 566#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 605#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 623#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 619#L275 assume !(0 == ~q_read_ev~0); 620#L275-2 assume !(0 == ~q_write_ev~0); 606#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 607#L65 assume !(1 == ~p_dw_pc~0); 613#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 614#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 561#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 562#L315 assume !(0 != activate_threads_~tmp~1#1); 571#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 572#L84 assume !(1 == ~c_dr_pc~0); 595#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 585#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 586#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 545#L323 assume !(0 != activate_threads_~tmp___0~1#1); 546#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 630#L293 assume !(1 == ~q_read_ev~0); 537#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 538#L298-1 assume { :end_inline_reset_delta_events } true; 627#L419-2 [2021-12-15 17:20:22,025 INFO L793 eck$LassoCheckResult]: Loop: 627#L419-2 assume !false; 702#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 699#L364 assume !false; 697#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 695#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 692#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 589#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 590#L344 assume !(0 != eval_~tmp___1~0#1); 551#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 552#L222-3 assume !(1 == ~q_req_up~0); 612#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 603#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 604#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 629#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 553#L65-3 assume !(1 == ~p_dw_pc~0); 554#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 594#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 587#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 588#L315-3 assume !(0 != activate_threads_~tmp~1#1); 615#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 541#L84-3 assume !(1 == ~c_dr_pc~0); 542#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 602#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 543#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 544#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 600#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 601#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 547#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 548#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 643#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 717#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 716#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 573#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 557#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 558#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 711#L436 assume !(0 != start_simulation_~tmp~4#1); 627#L419-2 [2021-12-15 17:20:22,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,026 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2021-12-15 17:20:22,026 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643150077] [2021-12-15 17:20:22,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,026 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,060 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643150077] [2021-12-15 17:20:22,060 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643150077] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,060 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,060 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:22,060 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140431120] [2021-12-15 17:20:22,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,061 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,061 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 2 times [2021-12-15 17:20:22,062 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,062 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727333592] [2021-12-15 17:20:22,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,062 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,102 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,103 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [727333592] [2021-12-15 17:20:22,103 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [727333592] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,103 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,103 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,104 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152401997] [2021-12-15 17:20:22,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,105 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,105 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:22,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:22,107 INFO L87 Difference]: Start difference. First operand 196 states and 277 transitions. cyclomatic complexity: 83 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,197 INFO L93 Difference]: Finished difference Result 449 states and 615 transitions. [2021-12-15 17:20:22,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:22,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 615 transitions. [2021-12-15 17:20:22,200 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 373 [2021-12-15 17:20:22,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 615 transitions. [2021-12-15 17:20:22,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2021-12-15 17:20:22,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2021-12-15 17:20:22,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 615 transitions. [2021-12-15 17:20:22,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,205 INFO L681 BuchiCegarLoop]: Abstraction has 449 states and 615 transitions. [2021-12-15 17:20:22,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 615 transitions. [2021-12-15 17:20:22,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2021-12-15 17:20:22,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.3697104677060135) internal successors, (615), 448 states have internal predecessors, (615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 615 transitions. [2021-12-15 17:20:22,220 INFO L704 BuchiCegarLoop]: Abstraction has 449 states and 615 transitions. [2021-12-15 17:20:22,220 INFO L587 BuchiCegarLoop]: Abstraction has 449 states and 615 transitions. [2021-12-15 17:20:22,220 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:22,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 615 transitions. [2021-12-15 17:20:22,222 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 373 [2021-12-15 17:20:22,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,223 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,223 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,223 INFO L791 eck$LassoCheckResult]: Stem: 1307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1227#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1228#L222 assume !(1 == ~q_req_up~0); 1237#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1266#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1267#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1286#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1351#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1285#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1297#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1336#L65 assume !(1 == ~p_dw_pc~0); 1335#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1334#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1333#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1332#L315 assume !(0 != activate_threads_~tmp~1#1); 1331#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1330#L84 assume !(1 == ~c_dr_pc~0); 1329#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1328#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1327#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1326#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1325#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1324#L293 assume !(1 == ~q_read_ev~0); 1323#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1196#L298-1 assume { :end_inline_reset_delta_events } true; 1523#L419-2 [2021-12-15 17:20:22,223 INFO L793 eck$LassoCheckResult]: Loop: 1523#L419-2 assume !false; 1513#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1510#L364 assume !false; 1506#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1502#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1498#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1495#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1492#L344 assume !(0 != eval_~tmp___1~0#1); 1209#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1210#L222-3 assume !(1 == ~q_req_up~0); 1275#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1264#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1265#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1299#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1211#L65-3 assume !(1 == ~p_dw_pc~0); 1212#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 1252#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1244#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1245#L315-3 assume !(0 != activate_threads_~tmp~1#1); 1279#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1197#L84-3 assume !(1 == ~c_dr_pc~0); 1198#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1262#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1263#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1626#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1623#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1622#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1621#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1206#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1272#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1273#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1193#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1194#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1533#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1532#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1526#L436 assume !(0 != start_simulation_~tmp~4#1); 1523#L419-2 [2021-12-15 17:20:22,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,224 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2021-12-15 17:20:22,224 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123633551] [2021-12-15 17:20:22,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123633551] [2021-12-15 17:20:22,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123633551] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011022170] [2021-12-15 17:20:22,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,247 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,247 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 3 times [2021-12-15 17:20:22,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504761461] [2021-12-15 17:20:22,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,273 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504761461] [2021-12-15 17:20:22,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [504761461] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,274 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,274 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,274 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068488719] [2021-12-15 17:20:22,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,274 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,274 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:22,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:22,275 INFO L87 Difference]: Start difference. First operand 449 states and 615 transitions. cyclomatic complexity: 170 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,295 INFO L93 Difference]: Finished difference Result 701 states and 942 transitions. [2021-12-15 17:20:22,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:22,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 942 transitions. [2021-12-15 17:20:22,299 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 583 [2021-12-15 17:20:22,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 701 states and 942 transitions. [2021-12-15 17:20:22,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 701 [2021-12-15 17:20:22,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 701 [2021-12-15 17:20:22,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 701 states and 942 transitions. [2021-12-15 17:20:22,304 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,304 INFO L681 BuchiCegarLoop]: Abstraction has 701 states and 942 transitions. [2021-12-15 17:20:22,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states and 942 transitions. [2021-12-15 17:20:22,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 510. [2021-12-15 17:20:22,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.3470588235294119) internal successors, (687), 509 states have internal predecessors, (687), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 687 transitions. [2021-12-15 17:20:22,321 INFO L704 BuchiCegarLoop]: Abstraction has 510 states and 687 transitions. [2021-12-15 17:20:22,321 INFO L587 BuchiCegarLoop]: Abstraction has 510 states and 687 transitions. [2021-12-15 17:20:22,321 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:22,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 687 transitions. [2021-12-15 17:20:22,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 420 [2021-12-15 17:20:22,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,325 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,325 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,325 INFO L791 eck$LassoCheckResult]: Stem: 2457#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2386#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2387#L222 assume !(1 == ~q_req_up~0); 2382#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2383#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2424#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2443#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2439#L275 assume !(0 == ~q_read_ev~0); 2440#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2450#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2490#L65 assume !(1 == ~p_dw_pc~0); 2488#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2486#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2484#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2482#L315 assume !(0 != activate_threads_~tmp~1#1); 2480#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2478#L84 assume !(1 == ~c_dr_pc~0); 2476#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2474#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2472#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2470#L323 assume !(0 != activate_threads_~tmp___0~1#1); 2468#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2466#L293 assume !(1 == ~q_read_ev~0); 2463#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2355#L298-1 assume { :end_inline_reset_delta_events } true; 2449#L419-2 [2021-12-15 17:20:22,325 INFO L793 eck$LassoCheckResult]: Loop: 2449#L419-2 assume !false; 2778#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2462#L364 assume !false; 2427#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2397#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2361#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2412#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2539#L344 assume !(0 != eval_~tmp___1~0#1); 2368#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2369#L222-3 assume !(1 == ~q_req_up~0); 2432#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2422#L275-3 assume !(0 == ~q_read_ev~0); 2423#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2451#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2850#L65-3 assume !(1 == ~p_dw_pc~0); 2849#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2848#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2847#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2846#L315-3 assume !(0 != activate_threads_~tmp~1#1); 2845#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2844#L84-3 assume !(1 == ~c_dr_pc~0); 2843#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2842#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2841#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2840#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2839#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2838#L293-3 assume !(1 == ~q_read_ev~0); 2704#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2365#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2428#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2429#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2352#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2353#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2376#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2377#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2779#L436 assume !(0 != start_simulation_~tmp~4#1); 2449#L419-2 [2021-12-15 17:20:22,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,326 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2021-12-15 17:20:22,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524061179] [2021-12-15 17:20:22,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524061179] [2021-12-15 17:20:22,348 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524061179] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,348 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,348 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:22,348 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047341430] [2021-12-15 17:20:22,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,349 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,349 INFO L85 PathProgramCache]: Analyzing trace with hash -884233102, now seen corresponding path program 1 times [2021-12-15 17:20:22,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101125739] [2021-12-15 17:20:22,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,350 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,371 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,371 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101125739] [2021-12-15 17:20:22,371 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [101125739] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,371 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,371 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,372 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955632094] [2021-12-15 17:20:22,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,372 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,372 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:22,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:22,373 INFO L87 Difference]: Start difference. First operand 510 states and 687 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,413 INFO L93 Difference]: Finished difference Result 745 states and 993 transitions. [2021-12-15 17:20:22,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-15 17:20:22,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 993 transitions. [2021-12-15 17:20:22,417 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 619 [2021-12-15 17:20:22,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 745 states and 993 transitions. [2021-12-15 17:20:22,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 745 [2021-12-15 17:20:22,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 745 [2021-12-15 17:20:22,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 745 states and 993 transitions. [2021-12-15 17:20:22,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,421 INFO L681 BuchiCegarLoop]: Abstraction has 745 states and 993 transitions. [2021-12-15 17:20:22,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states and 993 transitions. [2021-12-15 17:20:22,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 563. [2021-12-15 17:20:22,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 563 states, 563 states have (on average 1.3374777975133214) internal successors, (753), 562 states have internal predecessors, (753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 753 transitions. [2021-12-15 17:20:22,429 INFO L704 BuchiCegarLoop]: Abstraction has 563 states and 753 transitions. [2021-12-15 17:20:22,429 INFO L587 BuchiCegarLoop]: Abstraction has 563 states and 753 transitions. [2021-12-15 17:20:22,429 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:22,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 563 states and 753 transitions. [2021-12-15 17:20:22,431 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 456 [2021-12-15 17:20:22,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,432 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,432 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,432 INFO L791 eck$LassoCheckResult]: Stem: 3725#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3655#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3656#L222 assume !(1 == ~q_req_up~0); 3651#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3652#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3781#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3720#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3708#L275 assume !(0 == ~q_read_ev~0); 3709#L275-2 assume !(0 == ~q_write_ev~0); 3694#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3695#L65 assume !(1 == ~p_dw_pc~0); 3702#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3703#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3649#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3650#L315 assume !(0 != activate_threads_~tmp~1#1); 3657#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3658#L84 assume !(1 == ~c_dr_pc~0); 3679#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3672#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3673#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3629#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3630#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3723#L293 assume !(1 == ~q_read_ev~0); 3621#L293-2 assume !(1 == ~q_write_ev~0); 3622#L298-1 assume { :end_inline_reset_delta_events } true; 3719#L419-2 [2021-12-15 17:20:22,433 INFO L793 eck$LassoCheckResult]: Loop: 3719#L419-2 assume !false; 3831#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3828#L364 assume !false; 3826#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3666#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3624#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3674#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3675#L344 assume !(0 != eval_~tmp___1~0#1); 3819#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3940#L222-3 assume !(1 == ~q_req_up~0); 3941#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4162#L275-3 assume !(0 == ~q_read_ev~0); 4161#L275-5 assume !(0 == ~q_write_ev~0); 3879#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4160#L65-3 assume !(1 == ~p_dw_pc~0); 4159#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 4158#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4157#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4155#L315-3 assume !(0 != activate_threads_~tmp~1#1); 4154#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4152#L84-3 assume !(1 == ~c_dr_pc~0); 4150#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4149#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4143#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4141#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3993#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3944#L293-3 assume !(1 == ~q_read_ev~0); 3846#L293-5 assume !(1 == ~q_write_ev~0); 3844#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3843#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3840#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3839#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3838#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3837#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3836#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3834#L436 assume !(0 != start_simulation_~tmp~4#1); 3719#L419-2 [2021-12-15 17:20:22,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,433 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2021-12-15 17:20:22,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470539182] [2021-12-15 17:20:22,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,444 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:22,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,463 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:22,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,464 INFO L85 PathProgramCache]: Analyzing trace with hash -338188238, now seen corresponding path program 1 times [2021-12-15 17:20:22,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288389793] [2021-12-15 17:20:22,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,464 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,486 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,486 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288389793] [2021-12-15 17:20:22,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [288389793] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,487 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,487 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,487 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876045574] [2021-12-15 17:20:22,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,487 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,488 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:22,488 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:22,488 INFO L87 Difference]: Start difference. First operand 563 states and 753 transitions. cyclomatic complexity: 192 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,533 INFO L93 Difference]: Finished difference Result 763 states and 1011 transitions. [2021-12-15 17:20:22,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:22,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 763 states and 1011 transitions. [2021-12-15 17:20:22,538 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 650 [2021-12-15 17:20:22,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 763 states to 763 states and 1011 transitions. [2021-12-15 17:20:22,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 763 [2021-12-15 17:20:22,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 763 [2021-12-15 17:20:22,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 763 states and 1011 transitions. [2021-12-15 17:20:22,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,567 INFO L681 BuchiCegarLoop]: Abstraction has 763 states and 1011 transitions. [2021-12-15 17:20:22,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states and 1011 transitions. [2021-12-15 17:20:22,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 581. [2021-12-15 17:20:22,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 581 states, 581 states have (on average 1.3270223752151462) internal successors, (771), 580 states have internal predecessors, (771), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 771 transitions. [2021-12-15 17:20:22,574 INFO L704 BuchiCegarLoop]: Abstraction has 581 states and 771 transitions. [2021-12-15 17:20:22,574 INFO L587 BuchiCegarLoop]: Abstraction has 581 states and 771 transitions. [2021-12-15 17:20:22,575 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:22,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 581 states and 771 transitions. [2021-12-15 17:20:22,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 474 [2021-12-15 17:20:22,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,578 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,578 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,578 INFO L791 eck$LassoCheckResult]: Stem: 5083#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 5051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4995#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4996#L222 assume !(1 == ~q_req_up~0); 5008#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5155#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5153#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5071#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5054#L275 assume !(0 == ~q_read_ev~0); 5055#L275-2 assume !(0 == ~q_write_ev~0); 5072#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5129#L65 assume !(1 == ~p_dw_pc~0); 5127#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 5125#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5123#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5121#L315 assume !(0 != activate_threads_~tmp~1#1); 5119#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5117#L84 assume !(1 == ~c_dr_pc~0); 5115#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 5113#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5111#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5109#L323 assume !(0 != activate_threads_~tmp___0~1#1); 5107#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5105#L293 assume !(1 == ~q_read_ev~0); 5104#L293-2 assume !(1 == ~q_write_ev~0); 5067#L298-1 assume { :end_inline_reset_delta_events } true; 5068#L419-2 [2021-12-15 17:20:22,580 INFO L793 eck$LassoCheckResult]: Loop: 5068#L419-2 assume !false; 5043#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5044#L364 assume !false; 5441#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5438#L255 assume !(0 == ~p_dw_st~0); 5428#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5425#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5422#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5416#L344 assume !(0 != eval_~tmp___1~0#1); 5418#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5045#L222-3 assume !(1 == ~q_req_up~0); 5046#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5034#L275-3 assume !(0 == ~q_read_ev~0); 5035#L275-5 assume !(0 == ~q_write_ev~0); 5075#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4980#L65-3 assume !(1 == ~p_dw_pc~0); 4981#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5073#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5074#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5077#L315-3 assume !(0 != activate_threads_~tmp~1#1); 5078#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4968#L84-3 assume !(1 == ~c_dr_pc~0); 4969#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5032#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5033#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5099#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5100#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5070#L293-3 assume !(1 == ~q_read_ev~0); 4976#L293-5 assume !(1 == ~q_write_ev~0); 4977#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5096#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5539#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5538#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5537#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5536#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5535#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5534#L436 assume !(0 != start_simulation_~tmp~4#1); 5068#L419-2 [2021-12-15 17:20:22,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2021-12-15 17:20:22,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836784649] [2021-12-15 17:20:22,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,581 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,597 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:22,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,610 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:22,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,610 INFO L85 PathProgramCache]: Analyzing trace with hash 22665520, now seen corresponding path program 1 times [2021-12-15 17:20:22,610 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653689256] [2021-12-15 17:20:22,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,611 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,625 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [653689256] [2021-12-15 17:20:22,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [653689256] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,626 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,626 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,626 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604348972] [2021-12-15 17:20:22,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,626 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,626 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:22,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:22,627 INFO L87 Difference]: Start difference. First operand 581 states and 771 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,644 INFO L93 Difference]: Finished difference Result 871 states and 1113 transitions. [2021-12-15 17:20:22,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:22,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 871 states and 1113 transitions. [2021-12-15 17:20:22,648 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 686 [2021-12-15 17:20:22,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 871 states to 871 states and 1113 transitions. [2021-12-15 17:20:22,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2021-12-15 17:20:22,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2021-12-15 17:20:22,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1113 transitions. [2021-12-15 17:20:22,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,653 INFO L681 BuchiCegarLoop]: Abstraction has 871 states and 1113 transitions. [2021-12-15 17:20:22,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1113 transitions. [2021-12-15 17:20:22,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2021-12-15 17:20:22,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.277841561423651) internal successors, (1113), 870 states have internal predecessors, (1113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1113 transitions. [2021-12-15 17:20:22,662 INFO L704 BuchiCegarLoop]: Abstraction has 871 states and 1113 transitions. [2021-12-15 17:20:22,662 INFO L587 BuchiCegarLoop]: Abstraction has 871 states and 1113 transitions. [2021-12-15 17:20:22,662 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:22,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1113 transitions. [2021-12-15 17:20:22,664 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 686 [2021-12-15 17:20:22,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,665 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,665 INFO L791 eck$LassoCheckResult]: Stem: 6537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6506#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6456#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6457#L222 assume !(1 == ~q_req_up~0); 6452#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6453#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 6493#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6666#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6667#L275 assume !(0 == ~q_read_ev~0); 6659#L275-2 assume !(0 == ~q_write_ev~0); 6657#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6655#L65 assume !(1 == ~p_dw_pc~0); 6653#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6651#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6649#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6647#L315 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6520#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6533#L84 assume !(1 == ~c_dr_pc~0); 6534#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6706#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6704#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6702#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6701#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6535#L293 assume !(1 == ~q_read_ev~0); 6536#L293-2 assume !(1 == ~q_write_ev~0); 6615#L298-1 assume { :end_inline_reset_delta_events } true; 6616#L419-2 [2021-12-15 17:20:22,666 INFO L793 eck$LassoCheckResult]: Loop: 6616#L419-2 assume !false; 6604#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6599#L364 assume !false; 6593#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6594#L255 assume !(0 == ~p_dw_st~0); 6798#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6794#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6790#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6784#L344 assume !(0 != eval_~tmp___1~0#1); 6780#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6774#L222-3 assume !(1 == ~q_req_up~0); 6775#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6826#L275-3 assume !(0 == ~q_read_ev~0); 6824#L275-5 assume !(0 == ~q_write_ev~0); 6754#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6822#L65-3 assume !(1 == ~p_dw_pc~0); 6820#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6818#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6816#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6808#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6802#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6797#L84-3 assume !(1 == ~c_dr_pc~0); 6793#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6789#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6783#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6779#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6773#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6767#L293-3 assume !(1 == ~q_read_ev~0); 6719#L293-5 assume !(1 == ~q_write_ev~0); 6717#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6715#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6714#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6712#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6699#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6700#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6844#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6617#L436 assume !(0 != start_simulation_~tmp~4#1); 6616#L419-2 [2021-12-15 17:20:22,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1896010065, now seen corresponding path program 1 times [2021-12-15 17:20:22,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78036139] [2021-12-15 17:20:22,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,667 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,678 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,679 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78036139] [2021-12-15 17:20:22,679 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78036139] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,679 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,679 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:22,679 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675470271] [2021-12-15 17:20:22,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,680 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,680 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 1 times [2021-12-15 17:20:22,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095343619] [2021-12-15 17:20:22,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,681 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,717 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095343619] [2021-12-15 17:20:22,717 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095343619] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,717 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,717 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861264995] [2021-12-15 17:20:22,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,718 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,718 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:22,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:22,719 INFO L87 Difference]: Start difference. First operand 871 states and 1113 transitions. cyclomatic complexity: 244 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,724 INFO L93 Difference]: Finished difference Result 793 states and 1015 transitions. [2021-12-15 17:20:22,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:22,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 793 states and 1015 transitions. [2021-12-15 17:20:22,728 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 686 [2021-12-15 17:20:22,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 793 states to 793 states and 1015 transitions. [2021-12-15 17:20:22,730 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 793 [2021-12-15 17:20:22,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 793 [2021-12-15 17:20:22,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 793 states and 1015 transitions. [2021-12-15 17:20:22,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,732 INFO L681 BuchiCegarLoop]: Abstraction has 793 states and 1015 transitions. [2021-12-15 17:20:22,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 793 states and 1015 transitions. [2021-12-15 17:20:22,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 793 to 793. [2021-12-15 17:20:22,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 793 states, 793 states have (on average 1.2799495586380831) internal successors, (1015), 792 states have internal predecessors, (1015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 793 states to 793 states and 1015 transitions. [2021-12-15 17:20:22,740 INFO L704 BuchiCegarLoop]: Abstraction has 793 states and 1015 transitions. [2021-12-15 17:20:22,740 INFO L587 BuchiCegarLoop]: Abstraction has 793 states and 1015 transitions. [2021-12-15 17:20:22,740 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:22,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 793 states and 1015 transitions. [2021-12-15 17:20:22,742 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 686 [2021-12-15 17:20:22,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,743 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,743 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,743 INFO L791 eck$LassoCheckResult]: Stem: 8208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8127#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8128#L222 assume !(1 == ~q_req_up~0); 8139#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8168#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8169#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8187#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8185#L275 assume !(0 == ~q_read_ev~0); 8186#L275-2 assume !(0 == ~q_write_ev~0); 8197#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8218#L65 assume !(1 == ~p_dw_pc~0); 8178#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8179#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8515#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8512#L315 assume !(0 != activate_threads_~tmp~1#1); 8131#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8132#L84 assume !(1 == ~c_dr_pc~0); 8156#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8146#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8147#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8103#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8104#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8206#L293 assume !(1 == ~q_read_ev~0); 8207#L293-2 assume !(1 == ~q_write_ev~0); 8194#L298-1 assume { :end_inline_reset_delta_events } true; 8195#L419-2 [2021-12-15 17:20:22,743 INFO L793 eck$LassoCheckResult]: Loop: 8195#L419-2 assume !false; 8315#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8450#L364 assume !false; 8449#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8303#L255 assume !(0 == ~p_dw_st~0); 8305#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8438#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8434#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8429#L344 assume !(0 != eval_~tmp___1~0#1); 8424#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8419#L222-3 assume !(1 == ~q_req_up~0); 8420#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8482#L275-3 assume !(0 == ~q_read_ev~0); 8480#L275-5 assume !(0 == ~q_write_ev~0); 8394#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8478#L65-3 assume !(1 == ~p_dw_pc~0); 8476#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8475#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8473#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8454#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 8446#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8442#L84-3 assume !(1 == ~c_dr_pc~0); 8437#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8433#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8428#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8423#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8418#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8409#L293-3 assume !(1 == ~q_read_ev~0); 8408#L293-5 assume !(1 == ~q_write_ev~0); 8492#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8490#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8489#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8488#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8487#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8486#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8319#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8317#L436 assume !(0 != start_simulation_~tmp~4#1); 8195#L419-2 [2021-12-15 17:20:22,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,744 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2021-12-15 17:20:22,744 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117020184] [2021-12-15 17:20:22,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,744 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,748 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:22,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:22,754 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:22,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,754 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 2 times [2021-12-15 17:20:22,754 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277303503] [2021-12-15 17:20:22,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,755 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277303503] [2021-12-15 17:20:22,785 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277303503] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,785 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,785 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:22,785 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772197865] [2021-12-15 17:20:22,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,785 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,785 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:22,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:22,786 INFO L87 Difference]: Start difference. First operand 793 states and 1015 transitions. cyclomatic complexity: 224 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,819 INFO L93 Difference]: Finished difference Result 1133 states and 1453 transitions. [2021-12-15 17:20:22,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:22,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1133 states and 1453 transitions. [2021-12-15 17:20:22,824 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1006 [2021-12-15 17:20:22,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1133 states to 1133 states and 1453 transitions. [2021-12-15 17:20:22,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1133 [2021-12-15 17:20:22,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1133 [2021-12-15 17:20:22,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1133 states and 1453 transitions. [2021-12-15 17:20:22,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,829 INFO L681 BuchiCegarLoop]: Abstraction has 1133 states and 1453 transitions. [2021-12-15 17:20:22,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1133 states and 1453 transitions. [2021-12-15 17:20:22,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1133 to 720. [2021-12-15 17:20:22,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 720 states, 720 states have (on average 1.2652777777777777) internal successors, (911), 719 states have internal predecessors, (911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 720 states to 720 states and 911 transitions. [2021-12-15 17:20:22,837 INFO L704 BuchiCegarLoop]: Abstraction has 720 states and 911 transitions. [2021-12-15 17:20:22,837 INFO L587 BuchiCegarLoop]: Abstraction has 720 states and 911 transitions. [2021-12-15 17:20:22,838 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:22,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 720 states and 911 transitions. [2021-12-15 17:20:22,840 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 595 [2021-12-15 17:20:22,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,840 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,841 INFO L791 eck$LassoCheckResult]: Stem: 10153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 10124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10066#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10067#L222 assume !(1 == ~q_req_up~0); 10079#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10222#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10221#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10220#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10217#L275 assume !(0 == ~q_read_ev~0); 10141#L275-2 assume !(0 == ~q_write_ev~0); 10142#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10200#L65 assume !(1 == ~p_dw_pc~0); 10198#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 10196#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10194#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10192#L315 assume !(0 != activate_threads_~tmp~1#1); 10190#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10188#L84 assume !(1 == ~c_dr_pc~0); 10186#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 10184#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10182#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10180#L323 assume !(0 != activate_threads_~tmp___0~1#1); 10178#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10176#L293 assume !(1 == ~q_read_ev~0); 10175#L293-2 assume !(1 == ~q_write_ev~0); 10507#L298-1 assume { :end_inline_reset_delta_events } true; 10506#L419-2 assume !false; 10505#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10504#L364 assume !false; 10503#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10501#L255 assume !(0 == ~p_dw_st~0); 10502#L259 [2021-12-15 17:20:22,841 INFO L793 eck$LassoCheckResult]: Loop: 10502#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10518#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10519#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10513#L344 assume 0 != eval_~tmp___1~0#1; 10514#L344-1 assume !(0 == ~p_dw_st~0); 10497#L349 assume !(0 == ~c_dr_st~0); 10525#L364 assume !false; 10526#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10522#L255 assume !(0 == ~p_dw_st~0); 10502#L259 [2021-12-15 17:20:22,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 1 times [2021-12-15 17:20:22,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940478931] [2021-12-15 17:20:22,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,854 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,855 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940478931] [2021-12-15 17:20:22,855 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940478931] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,855 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,855 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:22,855 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948381511] [2021-12-15 17:20:22,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,855 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,856 INFO L85 PathProgramCache]: Analyzing trace with hash 114351557, now seen corresponding path program 1 times [2021-12-15 17:20:22,856 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265410442] [2021-12-15 17:20:22,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,856 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,880 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265410442] [2021-12-15 17:20:22,881 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265410442] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,881 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,881 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:22,881 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164400262] [2021-12-15 17:20:22,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,881 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,882 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:22,882 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:22,882 INFO L87 Difference]: Start difference. First operand 720 states and 911 transitions. cyclomatic complexity: 193 Second operand has 5 states, 5 states have (on average 1.8) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,920 INFO L93 Difference]: Finished difference Result 780 states and 971 transitions. [2021-12-15 17:20:22,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:22,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 780 states and 971 transitions. [2021-12-15 17:20:22,923 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 655 [2021-12-15 17:20:22,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 780 states to 780 states and 971 transitions. [2021-12-15 17:20:22,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 780 [2021-12-15 17:20:22,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 780 [2021-12-15 17:20:22,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 780 states and 971 transitions. [2021-12-15 17:20:22,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,927 INFO L681 BuchiCegarLoop]: Abstraction has 780 states and 971 transitions. [2021-12-15 17:20:22,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 780 states and 971 transitions. [2021-12-15 17:20:22,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 780 to 720. [2021-12-15 17:20:22,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 720 states, 720 states have (on average 1.2569444444444444) internal successors, (905), 719 states have internal predecessors, (905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 720 states to 720 states and 905 transitions. [2021-12-15 17:20:22,952 INFO L704 BuchiCegarLoop]: Abstraction has 720 states and 905 transitions. [2021-12-15 17:20:22,952 INFO L587 BuchiCegarLoop]: Abstraction has 720 states and 905 transitions. [2021-12-15 17:20:22,952 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:22,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 720 states and 905 transitions. [2021-12-15 17:20:22,954 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 595 [2021-12-15 17:20:22,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:22,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:22,955 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,955 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:22,955 INFO L791 eck$LassoCheckResult]: Stem: 11663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 11638#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11580#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11581#L222 assume !(1 == ~q_req_up~0); 11593#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11622#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 11623#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 11643#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11641#L275 assume !(0 == ~q_read_ev~0); 11642#L275-2 assume !(0 == ~q_write_ev~0); 11652#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11684#L65 assume !(1 == ~p_dw_pc~0); 11635#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 11636#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11763#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11762#L315 assume !(0 != activate_threads_~tmp~1#1); 11584#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11585#L84 assume !(1 == ~c_dr_pc~0); 11611#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 11601#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 11602#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11557#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11558#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11662#L293 assume !(1 == ~q_read_ev~0); 11546#L293-2 assume !(1 == ~q_write_ev~0); 11547#L298-1 assume { :end_inline_reset_delta_events } true; 11798#L419-2 assume !false; 11799#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 11790#L364 assume !false; 11791#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11784#L255 assume !(0 == ~p_dw_st~0); 11596#L259 [2021-12-15 17:20:22,955 INFO L793 eck$LassoCheckResult]: Loop: 11596#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12040#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12038#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12036#L344 assume 0 != eval_~tmp___1~0#1; 12035#L344-1 assume !(0 == ~p_dw_st~0); 11956#L349 assume !(0 == ~c_dr_st~0); 11631#L364 assume !false; 12042#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11595#L255 assume !(0 == ~p_dw_st~0); 11596#L259 [2021-12-15 17:20:22,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,955 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 2 times [2021-12-15 17:20:22,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476235798] [2021-12-15 17:20:22,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,956 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,968 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476235798] [2021-12-15 17:20:22,968 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476235798] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,968 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,968 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:22,968 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366673683] [2021-12-15 17:20:22,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,969 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:22,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:22,969 INFO L85 PathProgramCache]: Analyzing trace with hash -565706813, now seen corresponding path program 1 times [2021-12-15 17:20:22,969 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:22,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990153646] [2021-12-15 17:20:22,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:22,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:22,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:22,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:22,977 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:22,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990153646] [2021-12-15 17:20:22,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990153646] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:22,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:22,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:22,977 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148762685] [2021-12-15 17:20:22,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:22,977 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:22,978 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:22,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:22,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:22,978 INFO L87 Difference]: Start difference. First operand 720 states and 905 transitions. cyclomatic complexity: 187 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:22,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:22,992 INFO L93 Difference]: Finished difference Result 802 states and 1007 transitions. [2021-12-15 17:20:22,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:22,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 802 states and 1007 transitions. [2021-12-15 17:20:22,995 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 677 [2021-12-15 17:20:22,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 802 states to 802 states and 1007 transitions. [2021-12-15 17:20:22,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 802 [2021-12-15 17:20:22,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 802 [2021-12-15 17:20:22,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 802 states and 1007 transitions. [2021-12-15 17:20:22,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:22,999 INFO L681 BuchiCegarLoop]: Abstraction has 802 states and 1007 transitions. [2021-12-15 17:20:23,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 802 states and 1007 transitions. [2021-12-15 17:20:23,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 802 to 782. [2021-12-15 17:20:23,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 782 states, 782 states have (on average 1.2595907928388748) internal successors, (985), 781 states have internal predecessors, (985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 782 states to 782 states and 985 transitions. [2021-12-15 17:20:23,008 INFO L704 BuchiCegarLoop]: Abstraction has 782 states and 985 transitions. [2021-12-15 17:20:23,008 INFO L587 BuchiCegarLoop]: Abstraction has 782 states and 985 transitions. [2021-12-15 17:20:23,008 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:23,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 782 states and 985 transitions. [2021-12-15 17:20:23,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 657 [2021-12-15 17:20:23,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,010 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,011 INFO L791 eck$LassoCheckResult]: Stem: 13195#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 13169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 13111#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13112#L222 assume !(1 == ~q_req_up~0); 13107#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13108#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 13264#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 13183#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13171#L275 assume !(0 == ~q_read_ev~0); 13172#L275-2 assume !(0 == ~q_write_ev~0); 13184#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 13210#L65 assume !(1 == ~p_dw_pc~0); 13211#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 13271#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 13102#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 13103#L315 assume !(0 != activate_threads_~tmp~1#1); 13113#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 13114#L84 assume !(1 == ~c_dr_pc~0); 13138#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 13128#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 13129#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13085#L323 assume !(0 != activate_threads_~tmp___0~1#1); 13086#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13193#L293 assume !(1 == ~q_read_ev~0); 13075#L293-2 assume !(1 == ~q_write_ev~0); 13076#L298-1 assume { :end_inline_reset_delta_events } true; 13179#L419-2 assume !false; 13665#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 13666#L364 assume !false; 13659#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13660#L255 assume !(0 == ~p_dw_st~0); 13079#L259 [2021-12-15 17:20:23,011 INFO L793 eck$LassoCheckResult]: Loop: 13079#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 13080#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 13132#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 13133#L344 assume 0 != eval_~tmp___1~0#1; 13143#L344-1 assume !(0 == ~p_dw_st~0); 13120#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 13125#L368 assume !(0 != eval_~tmp___0~2#1); 13205#L364 assume !false; 13153#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13124#L255 assume !(0 == ~p_dw_st~0); 13079#L259 [2021-12-15 17:20:23,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,011 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 3 times [2021-12-15 17:20:23,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108127184] [2021-12-15 17:20:23,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,023 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,023 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108127184] [2021-12-15 17:20:23,023 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108127184] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,023 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,023 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:23,023 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139611618] [2021-12-15 17:20:23,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,024 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,024 INFO L85 PathProgramCache]: Analyzing trace with hash -410340052, now seen corresponding path program 1 times [2021-12-15 17:20:23,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707524722] [2021-12-15 17:20:23,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,025 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,027 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:23,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,029 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:23,064 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:818) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:23,067 INFO L158 Benchmark]: Toolchain (without parser) took 2360.67ms. Allocated memory was 104.9MB in the beginning and 161.5MB in the end (delta: 56.6MB). Free memory was 76.9MB in the beginning and 102.5MB in the end (delta: -25.6MB). Peak memory consumption was 29.5MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,067 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 104.9MB. Free memory is still 63.4MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:23,067 INFO L158 Benchmark]: CACSL2BoogieTranslator took 339.12ms. Allocated memory was 104.9MB in the beginning and 161.5MB in the end (delta: 56.6MB). Free memory was 76.7MB in the beginning and 135.1MB in the end (delta: -58.5MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,067 INFO L158 Benchmark]: Boogie Procedure Inliner took 45.15ms. Allocated memory is still 161.5MB. Free memory was 135.1MB in the beginning and 133.2MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,068 INFO L158 Benchmark]: Boogie Preprocessor took 40.98ms. Allocated memory is still 161.5MB. Free memory was 133.2MB in the beginning and 131.6MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,068 INFO L158 Benchmark]: RCFGBuilder took 317.47ms. Allocated memory is still 161.5MB. Free memory was 131.1MB in the beginning and 116.2MB in the end (delta: 14.9MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,068 INFO L158 Benchmark]: BuchiAutomizer took 1609.11ms. Allocated memory is still 161.5MB. Free memory was 115.9MB in the beginning and 102.5MB in the end (delta: 13.4MB). Peak memory consumption was 13.4MB. Max. memory is 16.1GB. [2021-12-15 17:20:23,069 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 104.9MB. Free memory is still 63.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 339.12ms. Allocated memory was 104.9MB in the beginning and 161.5MB in the end (delta: 56.6MB). Free memory was 76.7MB in the beginning and 135.1MB in the end (delta: -58.5MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 45.15ms. Allocated memory is still 161.5MB. Free memory was 135.1MB in the beginning and 133.2MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 40.98ms. Allocated memory is still 161.5MB. Free memory was 133.2MB in the beginning and 131.6MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 317.47ms. Allocated memory is still 161.5MB. Free memory was 131.1MB in the beginning and 116.2MB in the end (delta: 14.9MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 1609.11ms. Allocated memory is still 161.5MB. Free memory was 115.9MB in the beginning and 102.5MB in the end (delta: 13.4MB). Peak memory consumption was 13.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:23,093 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable