./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:20,899 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:20,900 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:20,941 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:20,942 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:20,944 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:20,945 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:20,949 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:20,951 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:20,954 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:20,955 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:20,956 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:20,956 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:20,958 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:20,959 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:20,962 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:20,962 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:20,963 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:20,965 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:20,969 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:20,970 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:20,971 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:20,972 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:20,972 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:20,977 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:20,977 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:20,977 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:20,978 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:20,979 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:20,979 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:20,980 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:20,981 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:20,982 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:20,983 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:20,984 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:20,984 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:20,985 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:20,985 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:20,985 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:20,986 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:20,986 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:20,988 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:21,018 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:21,018 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:21,019 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:21,019 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:21,020 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:21,020 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:21,020 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:21,021 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:21,021 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:21,021 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:21,022 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:21,022 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:21,022 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:21,022 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:21,022 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:21,022 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:21,023 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:21,023 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:21,023 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:21,023 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:21,023 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:21,024 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:21,024 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:21,024 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:21,025 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:21,025 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:21,025 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:21,025 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:21,026 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:21,026 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:21,026 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:21,026 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:21,027 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:21,027 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2021-12-15 17:20:21,240 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:21,261 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:21,263 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:21,264 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:21,264 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:21,265 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-12-15 17:20:21,314 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f06c479d8/fa967c10a56947e09dd21b8eb0b9af81/FLAGd0d96ae51 [2021-12-15 17:20:21,595 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:21,596 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-12-15 17:20:21,605 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f06c479d8/fa967c10a56947e09dd21b8eb0b9af81/FLAGd0d96ae51 [2021-12-15 17:20:22,035 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f06c479d8/fa967c10a56947e09dd21b8eb0b9af81 [2021-12-15 17:20:22,038 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:22,040 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:22,043 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:22,043 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:22,045 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:22,045 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,047 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a0b36 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22, skipping insertion in model container [2021-12-15 17:20:22,047 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,051 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:22,084 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:22,220 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2021-12-15 17:20:22,254 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:22,261 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:22,268 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2021-12-15 17:20:22,298 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:22,307 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:22,308 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22 WrapperNode [2021-12-15 17:20:22,308 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:22,309 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:22,309 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:22,309 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:22,326 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,331 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,363 INFO L137 Inliner]: procedures = 31, calls = 35, calls flagged for inlining = 30, calls inlined = 33, statements flattened = 406 [2021-12-15 17:20:22,365 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:22,366 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:22,366 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:22,366 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:22,372 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,372 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,375 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,375 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,379 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,384 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,386 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,388 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:22,389 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:22,389 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:22,389 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:22,390 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,405 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:22,414 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:22,433 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:22,434 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:22,464 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:22,464 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:22,464 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:22,464 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:22,562 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:22,564 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:22,927 INFO L768 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2021-12-15 17:20:22,927 INFO L768 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2021-12-15 17:20:22,927 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:22,933 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:22,933 INFO L301 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-15 17:20:22,934 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:22 BoogieIcfgContainer [2021-12-15 17:20:22,935 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:22,935 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:22,935 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:22,938 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:22,938 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:22,938 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:22" (1/3) ... [2021-12-15 17:20:22,942 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b28da52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:22, skipping insertion in model container [2021-12-15 17:20:22,942 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:22,942 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (2/3) ... [2021-12-15 17:20:22,942 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b28da52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:22, skipping insertion in model container [2021-12-15 17:20:22,943 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:22,943 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:22" (3/3) ... [2021-12-15 17:20:22,944 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2021-12-15 17:20:22,978 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:22,978 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:22,978 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:22,978 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:22,978 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:22,978 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:22,978 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:22,979 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:22,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-12-15 17:20:23,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,017 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,017 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,017 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:23,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-12-15 17:20:23,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,026 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,026 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,029 INFO L791 eck$LassoCheckResult]: Stem: 131#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 39#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 29#L551true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31#L258true assume !(1 == ~q_req_up~0); 68#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 109#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 97#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48#L311true assume !(0 == ~q_read_ev~0); 98#L311-2true assume !(0 == ~q_write_ev~0); 76#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 35#L66true assume 1 == ~p_dw_pc~0; 130#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 55#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 90#L88true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 53#L387true assume !(0 != activate_threads_~tmp~1#1); 103#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 82#L95true assume 1 == ~c_dr_pc~0; 116#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 27#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7#L117true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 77#L395true assume !(0 != activate_threads_~tmp___0~1#1); 14#L395-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 56#L329-2true assume !(1 == ~q_write_ev~0); 37#L334-1true assume { :end_inline_reset_delta_events } true; 127#L491-2true [2021-12-15 17:20:23,030 INFO L793 eck$LassoCheckResult]: Loop: 127#L491-2true assume !false; 128#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 94#L435true assume !true; 144#L451true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L258-3true assume !(1 == ~q_req_up~0); 106#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 110#L311-5true assume !(0 == ~q_write_ev~0); 69#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 108#L66-3true assume 1 == ~p_dw_pc~0; 91#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 11#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 126#L88-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 121#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 36#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 124#L95-3true assume 1 == ~c_dr_pc~0; 64#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 100#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 95#L117-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 133#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 20#L395-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 85#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 140#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 51#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 101#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 102#L304-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 78#L510true assume !(0 == start_simulation_~tmp~4#1); 8#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 73#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 89#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 93#L304-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 141#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 34#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 137#L473true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 75#L523true assume !(0 != start_simulation_~tmp___0~3#1); 127#L491-2true [2021-12-15 17:20:23,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,034 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2021-12-15 17:20:23,040 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573515541] [2021-12-15 17:20:23,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,041 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,186 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,186 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573515541] [2021-12-15 17:20:23,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573515541] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,188 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:23,190 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1091462801] [2021-12-15 17:20:23,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,193 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,196 INFO L85 PathProgramCache]: Analyzing trace with hash 784504738, now seen corresponding path program 1 times [2021-12-15 17:20:23,196 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771469573] [2021-12-15 17:20:23,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,226 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771469573] [2021-12-15 17:20:23,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771469573] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,227 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,227 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:23,228 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663498459] [2021-12-15 17:20:23,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,229 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,230 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:23,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:23,255 INFO L87 Difference]: Start difference. First operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:23,292 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2021-12-15 17:20:23,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:23,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2021-12-15 17:20:23,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-12-15 17:20:23,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2021-12-15 17:20:23,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2021-12-15 17:20:23,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2021-12-15 17:20:23,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2021-12-15 17:20:23,314 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:23,315 INFO L681 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-15 17:20:23,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2021-12-15 17:20:23,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2021-12-15 17:20:23,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2021-12-15 17:20:23,345 INFO L704 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-15 17:20:23,345 INFO L587 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-15 17:20:23,345 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:23,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2021-12-15 17:20:23,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-12-15 17:20:23,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,350 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,350 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,351 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 336#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 387#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 410#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365#L311 assume !(0 == ~q_read_ev~0); 366#L311-2 assume !(0 == ~q_write_ev~0); 396#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 345#L66 assume 1 == ~p_dw_pc~0; 347#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 379#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 380#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 375#L387 assume !(0 != activate_threads_~tmp~1#1); 376#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 400#L95 assume 1 == ~c_dr_pc~0; 402#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 333#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 298#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 299#L395 assume !(0 != activate_threads_~tmp___0~1#1); 311#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 344#L329-2 assume !(1 == ~q_write_ev~0); 350#L334-1 assume { :end_inline_reset_delta_events } true; 351#L491-2 [2021-12-15 17:20:23,354 INFO L793 eck$LassoCheckResult]: Loop: 351#L491-2 assume !false; 423#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 352#L435 assume !false; 381#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 382#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 297#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 411#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 412#L415 assume !(0 != eval_~tmp___1~0#1); 420#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#L258-3 assume !(1 == ~q_req_up~0); 385#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 415#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 418#L311-5 assume !(0 == ~q_write_ev~0); 393#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 394#L66-3 assume 1 == ~p_dw_pc~0; 406#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 308#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 422#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 348#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 349#L95-3 assume 1 == ~c_dr_pc~0; 389#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 390#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 408#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 409#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 361#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 403#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 372#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 373#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 413#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 397#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 335#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 405#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 407#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 342#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 395#L523 assume !(0 != start_simulation_~tmp___0~3#1); 351#L491-2 [2021-12-15 17:20:23,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,355 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2021-12-15 17:20:23,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447758208] [2021-12-15 17:20:23,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,414 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447758208] [2021-12-15 17:20:23,414 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447758208] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,415 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,415 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:23,415 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596979558] [2021-12-15 17:20:23,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,416 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,426 INFO L85 PathProgramCache]: Analyzing trace with hash 2119142840, now seen corresponding path program 1 times [2021-12-15 17:20:23,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106013129] [2021-12-15 17:20:23,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,481 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106013129] [2021-12-15 17:20:23,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106013129] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,482 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:23,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633989362] [2021-12-15 17:20:23,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,483 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,483 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:23,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:23,485 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:23,538 INFO L93 Difference]: Finished difference Result 221 states and 321 transitions. [2021-12-15 17:20:23,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:23,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 221 states and 321 transitions. [2021-12-15 17:20:23,541 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 186 [2021-12-15 17:20:23,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 221 states to 221 states and 321 transitions. [2021-12-15 17:20:23,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2021-12-15 17:20:23,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2021-12-15 17:20:23,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 321 transitions. [2021-12-15 17:20:23,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:23,547 INFO L681 BuchiCegarLoop]: Abstraction has 221 states and 321 transitions. [2021-12-15 17:20:23,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 321 transitions. [2021-12-15 17:20:23,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 219. [2021-12-15 17:20:23,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 219 states have (on average 1.45662100456621) internal successors, (319), 218 states have internal predecessors, (319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 319 transitions. [2021-12-15 17:20:23,553 INFO L704 BuchiCegarLoop]: Abstraction has 219 states and 319 transitions. [2021-12-15 17:20:23,553 INFO L587 BuchiCegarLoop]: Abstraction has 219 states and 319 transitions. [2021-12-15 17:20:23,553 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:23,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219 states and 319 transitions. [2021-12-15 17:20:23,554 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 184 [2021-12-15 17:20:23,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,555 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,555 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,556 INFO L791 eck$LassoCheckResult]: Stem: 793#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 719#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 704#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 705#L258 assume !(1 == ~q_req_up~0); 707#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 751#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 752#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 779#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 731#L311 assume !(0 == ~q_read_ev~0); 732#L311-2 assume !(0 == ~q_write_ev~0); 761#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 713#L66 assume !(1 == ~p_dw_pc~0); 714#L66-2 assume !(2 == ~p_dw_pc~0); 725#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 744#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 745#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 740#L387 assume !(0 != activate_threads_~tmp~1#1); 741#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 768#L95 assume 1 == ~c_dr_pc~0; 770#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 699#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 662#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 663#L395 assume !(0 != activate_threads_~tmp___0~1#1); 676#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 677#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 710#L329-2 assume !(1 == ~q_write_ev~0); 715#L334-1 assume { :end_inline_reset_delta_events } true; 716#L491-2 [2021-12-15 17:20:23,556 INFO L793 eck$LassoCheckResult]: Loop: 716#L491-2 assume !false; 792#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 717#L435 assume !false; 746#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 747#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 661#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 780#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 781#L415 assume !(0 != eval_~tmp___1~0#1); 789#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 748#L258-3 assume !(1 == ~q_req_up~0); 750#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 786#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 787#L311-5 assume !(0 == ~q_write_ev~0); 758#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 759#L66-3 assume !(1 == ~p_dw_pc~0); 733#L66-5 assume !(2 == ~p_dw_pc~0); 666#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 667#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 671#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 791#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 711#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 712#L95-3 assume 1 == ~c_dr_pc~0; 754#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 755#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 777#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 778#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 683#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 724#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 771#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 737#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 738#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 782#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 762#L510 assume !(0 == start_simulation_~tmp~4#1); 664#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 665#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 701#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 773#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 776#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 708#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 709#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 760#L523 assume !(0 != start_simulation_~tmp___0~3#1); 716#L491-2 [2021-12-15 17:20:23,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,556 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2021-12-15 17:20:23,556 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892859769] [2021-12-15 17:20:23,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,557 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892859769] [2021-12-15 17:20:23,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892859769] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,597 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,598 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:23,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930345163] [2021-12-15 17:20:23,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,599 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1851475893, now seen corresponding path program 1 times [2021-12-15 17:20:23,600 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251637944] [2021-12-15 17:20:23,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,601 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251637944] [2021-12-15 17:20:23,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251637944] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,641 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:23,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185769958] [2021-12-15 17:20:23,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,642 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,643 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:23,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:23,643 INFO L87 Difference]: Start difference. First operand 219 states and 319 transitions. cyclomatic complexity: 102 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:23,724 INFO L93 Difference]: Finished difference Result 471 states and 676 transitions. [2021-12-15 17:20:23,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:23,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 676 transitions. [2021-12-15 17:20:23,728 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 425 [2021-12-15 17:20:23,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 676 transitions. [2021-12-15 17:20:23,730 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2021-12-15 17:20:23,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2021-12-15 17:20:23,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 676 transitions. [2021-12-15 17:20:23,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:23,735 INFO L681 BuchiCegarLoop]: Abstraction has 471 states and 676 transitions. [2021-12-15 17:20:23,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 676 transitions. [2021-12-15 17:20:23,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 377. [2021-12-15 17:20:23,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 377 states, 377 states have (on average 1.4456233421750664) internal successors, (545), 376 states have internal predecessors, (545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 545 transitions. [2021-12-15 17:20:23,753 INFO L704 BuchiCegarLoop]: Abstraction has 377 states and 545 transitions. [2021-12-15 17:20:23,753 INFO L587 BuchiCegarLoop]: Abstraction has 377 states and 545 transitions. [2021-12-15 17:20:23,753 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:23,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 377 states and 545 transitions. [2021-12-15 17:20:23,755 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 342 [2021-12-15 17:20:23,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,757 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,757 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,757 INFO L791 eck$LassoCheckResult]: Stem: 1500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 1424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1409#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1410#L258 assume !(1 == ~q_req_up~0); 1412#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1457#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1458#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1485#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1436#L311 assume !(0 == ~q_read_ev~0); 1437#L311-2 assume !(0 == ~q_write_ev~0); 1468#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1418#L66 assume !(1 == ~p_dw_pc~0); 1419#L66-2 assume !(2 == ~p_dw_pc~0); 1430#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1452#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1453#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1446#L387 assume !(0 != activate_threads_~tmp~1#1); 1447#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1475#L95 assume !(1 == ~c_dr_pc~0); 1476#L95-2 assume 2 == ~c_dr_pc~0; 1490#L106 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1404#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1365#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1366#L395 assume !(0 != activate_threads_~tmp___0~1#1); 1379#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1380#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1415#L329-2 assume !(1 == ~q_write_ev~0); 1422#L334-1 assume { :end_inline_reset_delta_events } true; 1423#L491-2 [2021-12-15 17:20:23,757 INFO L793 eck$LassoCheckResult]: Loop: 1423#L491-2 assume !false; 1499#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1420#L435 assume !false; 1450#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1451#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1364#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1488#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1489#L415 assume !(0 != eval_~tmp___1~0#1); 1496#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1454#L258-3 assume !(1 == ~q_req_up~0); 1456#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1493#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1494#L311-5 assume !(0 == ~q_write_ev~0); 1465#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1466#L66-3 assume !(1 == ~p_dw_pc~0); 1438#L66-5 assume !(2 == ~p_dw_pc~0); 1369#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 1370#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1374#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1498#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1416#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1417#L95-3 assume !(1 == ~c_dr_pc~0); 1358#L95-5 assume !(2 == ~c_dr_pc~0); 1360#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 1487#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1483#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1484#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1387#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1388#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1429#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1477#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1442#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1443#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1486#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1469#L510 assume !(0 == start_simulation_~tmp~4#1); 1367#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1368#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1406#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1479#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1482#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1413#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1414#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1467#L523 assume !(0 != start_simulation_~tmp___0~3#1); 1423#L491-2 [2021-12-15 17:20:23,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1943531092, now seen corresponding path program 1 times [2021-12-15 17:20:23,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268781551] [2021-12-15 17:20:23,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,759 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268781551] [2021-12-15 17:20:23,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268781551] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-15 17:20:23,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [646755685] [2021-12-15 17:20:23,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,800 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1021819368, now seen corresponding path program 1 times [2021-12-15 17:20:23,801 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340697325] [2021-12-15 17:20:23,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,801 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,823 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340697325] [2021-12-15 17:20:23,824 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [340697325] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,824 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,824 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:23,824 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625075648] [2021-12-15 17:20:23,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,825 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,825 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:23,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:23,825 INFO L87 Difference]: Start difference. First operand 377 states and 545 transitions. cyclomatic complexity: 170 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:23,874 INFO L93 Difference]: Finished difference Result 555 states and 772 transitions. [2021-12-15 17:20:23,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:23,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 772 transitions. [2021-12-15 17:20:23,878 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2021-12-15 17:20:23,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 555 states and 772 transitions. [2021-12-15 17:20:23,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 555 [2021-12-15 17:20:23,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 555 [2021-12-15 17:20:23,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 555 states and 772 transitions. [2021-12-15 17:20:23,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:23,881 INFO L681 BuchiCegarLoop]: Abstraction has 555 states and 772 transitions. [2021-12-15 17:20:23,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states and 772 transitions. [2021-12-15 17:20:23,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 551. [2021-12-15 17:20:23,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.3938294010889292) internal successors, (768), 550 states have internal predecessors, (768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 768 transitions. [2021-12-15 17:20:23,887 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 768 transitions. [2021-12-15 17:20:23,887 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 768 transitions. [2021-12-15 17:20:23,887 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:23,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 768 transitions. [2021-12-15 17:20:23,889 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2021-12-15 17:20:23,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,890 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,890 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,890 INFO L791 eck$LassoCheckResult]: Stem: 2476#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2344#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2345#L258 assume !(1 == ~q_req_up~0); 2350#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2397#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2398#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2460#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2376#L311 assume !(0 == ~q_read_ev~0); 2377#L311-2 assume !(0 == ~q_write_ev~0); 2413#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2356#L66 assume !(1 == ~p_dw_pc~0); 2357#L66-2 assume !(2 == ~p_dw_pc~0); 2473#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2474#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2433#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2434#L387 assume !(0 != activate_threads_~tmp~1#1); 2452#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2453#L95 assume !(1 == ~c_dr_pc~0); 2454#L95-2 assume !(2 == ~c_dr_pc~0); 2455#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2341#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2306#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2307#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2319#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2320#L329 assume !(1 == ~q_read_ev~0); 2353#L329-2 assume !(1 == ~q_write_ev~0); 2523#L334-1 assume { :end_inline_reset_delta_events } true; 2521#L491-2 [2021-12-15 17:20:23,890 INFO L793 eck$LassoCheckResult]: Loop: 2521#L491-2 assume !false; 2519#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2518#L435 assume !false; 2517#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2514#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2512#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2509#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2507#L415 assume !(0 != eval_~tmp___1~0#1); 2508#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2578#L258-3 assume !(1 == ~q_req_up~0); 2576#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2575#L311-3 assume !(0 == ~q_read_ev~0); 2574#L311-5 assume !(0 == ~q_write_ev~0); 2573#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2572#L66-3 assume !(1 == ~p_dw_pc~0); 2571#L66-5 assume !(2 == ~p_dw_pc~0); 2570#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 2569#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2567#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2565#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2563#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2561#L95-3 assume !(1 == ~c_dr_pc~0); 2559#L95-5 assume !(2 == ~c_dr_pc~0); 2557#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 2555#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2553#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2551#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2549#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2547#L329-3 assume !(1 == ~q_read_ev~0); 2545#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2543#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2541#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2538#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2536#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2533#L510 assume !(0 == start_simulation_~tmp~4#1); 2531#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2530#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2528#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2527#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2526#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2525#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2524#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2522#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2521#L491-2 [2021-12-15 17:20:23,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,890 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2021-12-15 17:20:23,891 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133037957] [2021-12-15 17:20:23,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,891 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,896 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:23,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,927 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:23,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,927 INFO L85 PathProgramCache]: Analyzing trace with hash 16715304, now seen corresponding path program 1 times [2021-12-15 17:20:23,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226130954] [2021-12-15 17:20:23,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,928 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,957 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226130954] [2021-12-15 17:20:23,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226130954] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,958 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,958 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:23,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017138495] [2021-12-15 17:20:23,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,958 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,958 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:23,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:23,959 INFO L87 Difference]: Start difference. First operand 551 states and 768 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,012 INFO L93 Difference]: Finished difference Result 886 states and 1210 transitions. [2021-12-15 17:20:24,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:24,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 886 states and 1210 transitions. [2021-12-15 17:20:24,018 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 818 [2021-12-15 17:20:24,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 886 states to 886 states and 1210 transitions. [2021-12-15 17:20:24,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 886 [2021-12-15 17:20:24,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 886 [2021-12-15 17:20:24,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 886 states and 1210 transitions. [2021-12-15 17:20:24,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,023 INFO L681 BuchiCegarLoop]: Abstraction has 886 states and 1210 transitions. [2021-12-15 17:20:24,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states and 1210 transitions. [2021-12-15 17:20:24,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 569. [2021-12-15 17:20:24,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.3813708260105448) internal successors, (786), 568 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 786 transitions. [2021-12-15 17:20:24,030 INFO L704 BuchiCegarLoop]: Abstraction has 569 states and 786 transitions. [2021-12-15 17:20:24,030 INFO L587 BuchiCegarLoop]: Abstraction has 569 states and 786 transitions. [2021-12-15 17:20:24,030 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:24,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 786 transitions. [2021-12-15 17:20:24,032 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 506 [2021-12-15 17:20:24,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,033 INFO L791 eck$LassoCheckResult]: Stem: 3917#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 3814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3797#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3798#L258 assume !(1 == ~q_req_up~0); 3802#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3848#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3849#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3905#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3827#L311 assume !(0 == ~q_read_ev~0); 3828#L311-2 assume !(0 == ~q_write_ev~0); 3863#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3806#L66 assume !(1 == ~p_dw_pc~0); 3807#L66-2 assume !(2 == ~p_dw_pc~0); 3914#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 3915#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3878#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3879#L387 assume !(0 != activate_threads_~tmp~1#1); 3897#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3898#L95 assume !(1 == ~c_dr_pc~0); 3899#L95-2 assume !(2 == ~c_dr_pc~0); 3900#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 3794#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3760#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3761#L395 assume !(0 != activate_threads_~tmp___0~1#1); 3773#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3774#L329 assume !(1 == ~q_read_ev~0); 3803#L329-2 assume !(1 == ~q_write_ev~0); 3810#L334-1 assume { :end_inline_reset_delta_events } true; 3811#L491-2 [2021-12-15 17:20:24,034 INFO L793 eck$LassoCheckResult]: Loop: 3811#L491-2 assume !false; 3916#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3885#L435 assume !false; 3886#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4156#L291 assume !(0 == ~p_dw_st~0); 4157#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4151#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4117#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4118#L415 assume !(0 != eval_~tmp___1~0#1); 4147#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3845#L258-3 assume !(1 == ~q_req_up~0); 3847#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3901#L311-3 assume !(0 == ~q_read_ev~0); 3906#L311-5 assume !(0 == ~q_write_ev~0); 3858#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3859#L66-3 assume !(1 == ~p_dw_pc~0); 3904#L66-5 assume !(2 == ~p_dw_pc~0); 4269#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 4268#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4267#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4266#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 4264#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4262#L95-3 assume !(1 == ~c_dr_pc~0); 4260#L95-5 assume !(2 == ~c_dr_pc~0); 4258#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 4257#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4256#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4255#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3781#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3782#L329-3 assume !(1 == ~q_read_ev~0); 3821#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3874#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3832#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3833#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3896#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3866#L510 assume !(0 == start_simulation_~tmp~4#1); 3762#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3763#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4298#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4297#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4296#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 4295#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4294#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3862#L523 assume !(0 != start_simulation_~tmp___0~3#1); 3811#L491-2 [2021-12-15 17:20:24,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,034 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2021-12-15 17:20:24,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817067823] [2021-12-15 17:20:24,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,043 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,050 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,050 INFO L85 PathProgramCache]: Analyzing trace with hash 526545300, now seen corresponding path program 1 times [2021-12-15 17:20:24,051 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12648849] [2021-12-15 17:20:24,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,051 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,108 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12648849] [2021-12-15 17:20:24,108 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12648849] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,108 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,108 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:24,108 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645408945] [2021-12-15 17:20:24,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,109 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,109 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:24,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:24,110 INFO L87 Difference]: Start difference. First operand 569 states and 786 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,157 INFO L93 Difference]: Finished difference Result 1035 states and 1424 transitions. [2021-12-15 17:20:24,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:24,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1035 states and 1424 transitions. [2021-12-15 17:20:24,162 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 970 [2021-12-15 17:20:24,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1035 states to 1035 states and 1424 transitions. [2021-12-15 17:20:24,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1035 [2021-12-15 17:20:24,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1035 [2021-12-15 17:20:24,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1035 states and 1424 transitions. [2021-12-15 17:20:24,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,168 INFO L681 BuchiCegarLoop]: Abstraction has 1035 states and 1424 transitions. [2021-12-15 17:20:24,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1035 states and 1424 transitions. [2021-12-15 17:20:24,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1035 to 587. [2021-12-15 17:20:24,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.3560477001703577) internal successors, (796), 586 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 796 transitions. [2021-12-15 17:20:24,175 INFO L704 BuchiCegarLoop]: Abstraction has 587 states and 796 transitions. [2021-12-15 17:20:24,176 INFO L587 BuchiCegarLoop]: Abstraction has 587 states and 796 transitions. [2021-12-15 17:20:24,176 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:24,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 796 transitions. [2021-12-15 17:20:24,178 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 524 [2021-12-15 17:20:24,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,178 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,178 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,179 INFO L791 eck$LassoCheckResult]: Stem: 5540#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 5433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5416#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5417#L258 assume !(1 == ~q_req_up~0); 5421#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5470#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5471#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5528#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5448#L311 assume !(0 == ~q_read_ev~0); 5449#L311-2 assume !(0 == ~q_write_ev~0); 5514#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5425#L66 assume !(1 == ~p_dw_pc~0); 5426#L66-2 assume !(2 == ~p_dw_pc~0); 5536#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 5537#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5504#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5505#L387 assume !(0 != activate_threads_~tmp~1#1); 5519#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5520#L95 assume !(1 == ~c_dr_pc~0); 5521#L95-2 assume !(2 == ~c_dr_pc~0); 5522#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 5413#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5377#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5378#L395 assume !(0 != activate_threads_~tmp___0~1#1); 5391#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5392#L329 assume !(1 == ~q_read_ev~0); 5422#L329-2 assume !(1 == ~q_write_ev~0); 5463#L334-1 assume { :end_inline_reset_delta_events } true; 5692#L491-2 [2021-12-15 17:20:24,179 INFO L793 eck$LassoCheckResult]: Loop: 5692#L491-2 assume !false; 5691#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5653#L435 assume !false; 5690#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5687#L291 assume !(0 == ~p_dw_st~0); 5688#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5689#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5679#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5680#L415 assume !(0 != eval_~tmp___1~0#1); 5747#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5744#L258-3 assume !(1 == ~q_req_up~0); 5742#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5741#L311-3 assume !(0 == ~q_read_ev~0); 5740#L311-5 assume !(0 == ~q_write_ev~0); 5739#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5526#L66-3 assume !(1 == ~p_dw_pc~0); 5527#L66-5 assume !(2 == ~p_dw_pc~0); 5738#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 5737#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5735#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5734#L387-3 assume !(0 != activate_threads_~tmp~1#1); 5733#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5731#L95-3 assume !(1 == ~c_dr_pc~0); 5729#L95-5 assume !(2 == ~c_dr_pc~0); 5727#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5725#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5723#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5721#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5719#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5717#L329-3 assume !(1 == ~q_read_ev~0); 5715#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5713#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5711#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5708#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5706#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5703#L510 assume !(0 == start_simulation_~tmp~4#1); 5701#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5700#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5698#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5697#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5696#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5695#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5694#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5693#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5692#L491-2 [2021-12-15 17:20:24,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,179 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2021-12-15 17:20:24,179 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100720621] [2021-12-15 17:20:24,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,184 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,190 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,190 INFO L85 PathProgramCache]: Analyzing trace with hash 392531794, now seen corresponding path program 1 times [2021-12-15 17:20:24,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148776003] [2021-12-15 17:20:24,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,191 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,224 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,224 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148776003] [2021-12-15 17:20:24,224 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148776003] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,224 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,224 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502551200] [2021-12-15 17:20:24,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,225 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,225 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,226 INFO L87 Difference]: Start difference. First operand 587 states and 796 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,246 INFO L93 Difference]: Finished difference Result 850 states and 1119 transitions. [2021-12-15 17:20:24,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 850 states and 1119 transitions. [2021-12-15 17:20:24,252 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-15 17:20:24,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 850 states to 850 states and 1119 transitions. [2021-12-15 17:20:24,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 850 [2021-12-15 17:20:24,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 850 [2021-12-15 17:20:24,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 850 states and 1119 transitions. [2021-12-15 17:20:24,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,257 INFO L681 BuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2021-12-15 17:20:24,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states and 1119 transitions. [2021-12-15 17:20:24,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 850. [2021-12-15 17:20:24,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 850 states, 850 states have (on average 1.316470588235294) internal successors, (1119), 849 states have internal predecessors, (1119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 1119 transitions. [2021-12-15 17:20:24,266 INFO L704 BuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2021-12-15 17:20:24,266 INFO L587 BuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2021-12-15 17:20:24,266 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:24,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 850 states and 1119 transitions. [2021-12-15 17:20:24,269 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-15 17:20:24,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,270 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,270 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,270 INFO L791 eck$LassoCheckResult]: Stem: 6956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 6875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6860#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6861#L258 assume !(1 == ~q_req_up~0); 6863#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6904#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 6905#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 7662#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7661#L311 assume !(0 == ~q_read_ev~0); 7660#L311-2 assume !(0 == ~q_write_ev~0); 7659#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 7658#L66 assume !(1 == ~p_dw_pc~0); 6880#L66-2 assume !(2 == ~p_dw_pc~0); 6881#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 6954#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 7656#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7655#L387 assume !(0 != activate_threads_~tmp~1#1); 7654#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7653#L95 assume !(1 == ~c_dr_pc~0); 7652#L95-2 assume !(2 == ~c_dr_pc~0); 7651#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 7650#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6820#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6821#L395 assume !(0 != activate_threads_~tmp___0~1#1); 6834#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6835#L329 assume !(1 == ~q_read_ev~0); 6866#L329-2 assume !(1 == ~q_write_ev~0); 6873#L334-1 assume { :end_inline_reset_delta_events } true; 6874#L491-2 [2021-12-15 17:20:24,270 INFO L793 eck$LassoCheckResult]: Loop: 6874#L491-2 assume !false; 6955#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6934#L435 assume !false; 6897#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6898#L291 assume !(0 == ~p_dw_st~0); 6817#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6819#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7518#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 7502#L415 assume !(0 != eval_~tmp___1~0#1); 6959#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6901#L258-3 assume !(1 == ~q_req_up~0); 6903#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6943#L311-3 assume !(0 == ~q_read_ev~0); 6946#L311-5 assume !(0 == ~q_write_ev~0); 6912#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6913#L66-3 assume !(1 == ~p_dw_pc~0); 6890#L66-5 assume !(2 == ~p_dw_pc~0); 6824#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 6825#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6829#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6953#L387-3 assume !(0 != activate_threads_~tmp~1#1); 6867#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6868#L95-3 assume !(1 == ~c_dr_pc~0); 6813#L95-5 assume !(2 == ~c_dr_pc~0); 6814#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 6940#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6935#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6936#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6841#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6842#L329-3 assume !(1 == ~q_read_ev~0); 6879#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 6926#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6891#L291-1 assume !(0 == ~p_dw_st~0); 6892#L295-1 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6941#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6942#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6917#L510 assume !(0 == start_simulation_~tmp~4#1); 6822#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6823#L291-2 assume !(0 == ~p_dw_st~0); 6856#L295-2 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6857#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6929#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6933#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6864#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6865#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6915#L523 assume !(0 != start_simulation_~tmp___0~3#1); 6874#L491-2 [2021-12-15 17:20:24,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2021-12-15 17:20:24,271 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382915835] [2021-12-15 17:20:24,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,271 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,283 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,283 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382915835] [2021-12-15 17:20:24,283 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382915835] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,283 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,283 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144872298] [2021-12-15 17:20:24,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,284 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:24,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,284 INFO L85 PathProgramCache]: Analyzing trace with hash 2092921140, now seen corresponding path program 1 times [2021-12-15 17:20:24,284 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046418555] [2021-12-15 17:20:24,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,285 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,297 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046418555] [2021-12-15 17:20:24,297 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046418555] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,297 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,297 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,298 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866524794] [2021-12-15 17:20:24,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,298 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,298 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,299 INFO L87 Difference]: Start difference. First operand 850 states and 1119 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,304 INFO L93 Difference]: Finished difference Result 806 states and 1065 transitions. [2021-12-15 17:20:24,305 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 806 states and 1065 transitions. [2021-12-15 17:20:24,309 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-15 17:20:24,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 806 states to 806 states and 1065 transitions. [2021-12-15 17:20:24,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 806 [2021-12-15 17:20:24,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 806 [2021-12-15 17:20:24,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 806 states and 1065 transitions. [2021-12-15 17:20:24,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,313 INFO L681 BuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2021-12-15 17:20:24,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 806 states and 1065 transitions. [2021-12-15 17:20:24,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 806 to 806. [2021-12-15 17:20:24,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 806 states, 806 states have (on average 1.3213399503722085) internal successors, (1065), 805 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 806 states to 806 states and 1065 transitions. [2021-12-15 17:20:24,322 INFO L704 BuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2021-12-15 17:20:24,322 INFO L587 BuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2021-12-15 17:20:24,322 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:24,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 806 states and 1065 transitions. [2021-12-15 17:20:24,325 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-15 17:20:24,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,326 INFO L791 eck$LassoCheckResult]: Stem: 8640#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 8538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8523#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8524#L258 assume !(1 == ~q_req_up~0); 8526#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8581#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8626#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8627#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8551#L311 assume !(0 == ~q_read_ev~0); 8552#L311-2 assume !(0 == ~q_write_ev~0); 8614#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8648#L66 assume !(1 == ~p_dw_pc~0); 8542#L66-2 assume !(2 == ~p_dw_pc~0); 8543#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 8564#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8565#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8558#L387 assume !(0 != activate_threads_~tmp~1#1); 8559#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8593#L95 assume !(1 == ~c_dr_pc~0); 8594#L95-2 assume !(2 == ~c_dr_pc~0); 8575#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 8576#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8483#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8484#L395 assume !(0 != activate_threads_~tmp___0~1#1); 8496#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8497#L329 assume !(1 == ~q_read_ev~0); 8529#L329-2 assume !(1 == ~q_write_ev~0); 8979#L334-1 assume { :end_inline_reset_delta_events } true; 8978#L491-2 assume !false; 8911#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8909#L435 [2021-12-15 17:20:24,326 INFO L793 eck$LassoCheckResult]: Loop: 8909#L435 assume !false; 8907#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8904#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8902#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8900#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8898#L415 assume 0 != eval_~tmp___1~0#1; 8896#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 8894#L424 assume !(0 != eval_~tmp~2#1); 8895#L420 assume !(0 == ~c_dr_st~0); 8909#L435 [2021-12-15 17:20:24,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,326 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2021-12-15 17:20:24,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255727191] [2021-12-15 17:20:24,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,331 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,337 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,338 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877037, now seen corresponding path program 1 times [2021-12-15 17:20:24,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446511178] [2021-12-15 17:20:24,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,338 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,340 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,342 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124195, now seen corresponding path program 1 times [2021-12-15 17:20:24,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653565243] [2021-12-15 17:20:24,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,376 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653565243] [2021-12-15 17:20:24,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653565243] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,377 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,377 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:24,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698538931] [2021-12-15 17:20:24,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,413 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:24,416 INFO L158 Benchmark]: Toolchain (without parser) took 2375.38ms. Allocated memory was 90.2MB in the beginning and 130.0MB in the end (delta: 39.8MB). Free memory was 60.3MB in the beginning and 98.0MB in the end (delta: -37.7MB). Peak memory consumption was 2.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,416 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 90.2MB. Free memory was 46.8MB in the beginning and 46.8MB in the end (delta: 40.9kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:24,417 INFO L158 Benchmark]: CACSL2BoogieTranslator took 265.49ms. Allocated memory was 90.2MB in the beginning and 130.0MB in the end (delta: 39.8MB). Free memory was 60.0MB in the beginning and 105.0MB in the end (delta: -44.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,418 INFO L158 Benchmark]: Boogie Procedure Inliner took 56.50ms. Allocated memory is still 130.0MB. Free memory was 105.0MB in the beginning and 102.1MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,418 INFO L158 Benchmark]: Boogie Preprocessor took 22.68ms. Allocated memory is still 130.0MB. Free memory was 102.1MB in the beginning and 100.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,421 INFO L158 Benchmark]: RCFGBuilder took 545.78ms. Allocated memory is still 130.0MB. Free memory was 100.0MB in the beginning and 81.9MB in the end (delta: 18.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,421 INFO L158 Benchmark]: BuchiAutomizer took 1479.48ms. Allocated memory is still 130.0MB. Free memory was 81.1MB in the beginning and 98.0MB in the end (delta: -16.9MB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:24,425 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 90.2MB. Free memory was 46.8MB in the beginning and 46.8MB in the end (delta: 40.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 265.49ms. Allocated memory was 90.2MB in the beginning and 130.0MB in the end (delta: 39.8MB). Free memory was 60.0MB in the beginning and 105.0MB in the end (delta: -44.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 56.50ms. Allocated memory is still 130.0MB. Free memory was 105.0MB in the beginning and 102.1MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 22.68ms. Allocated memory is still 130.0MB. Free memory was 102.1MB in the beginning and 100.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 545.78ms. Allocated memory is still 130.0MB. Free memory was 100.0MB in the beginning and 81.9MB in the end (delta: 18.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 1479.48ms. Allocated memory is still 130.0MB. Free memory was 81.1MB in the beginning and 98.0MB in the end (delta: -16.9MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:24,448 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable