./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.01.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.01.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7b0a21004c99a1cc1588d43a2481960a2ce9f2cdf68e9a363306433e7d24bd30 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:21,683 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:21,685 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:21,743 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:21,743 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:21,745 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:21,746 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:21,748 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:21,750 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:21,753 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:21,754 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:21,755 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:21,755 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:21,757 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:21,758 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:21,762 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:21,763 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:21,764 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:21,765 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:21,769 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:21,770 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:21,771 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:21,772 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:21,772 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:21,777 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:21,777 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:21,777 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:21,778 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:21,779 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:21,779 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:21,779 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:21,780 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:21,781 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:21,782 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:21,783 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:21,783 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:21,784 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:21,784 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:21,784 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:21,785 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:21,785 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:21,786 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:21,809 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:21,809 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:21,810 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:21,810 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:21,811 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:21,811 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:21,811 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:21,811 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:21,812 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:21,812 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:21,812 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:21,812 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:21,813 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:21,813 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:21,813 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:21,813 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:21,813 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:21,813 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:21,813 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:21,814 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:21,814 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:21,814 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:21,814 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:21,814 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:21,815 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:21,815 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:21,816 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:21,816 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:21,816 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:21,816 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:21,816 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:21,816 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:21,817 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:21,817 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7b0a21004c99a1cc1588d43a2481960a2ce9f2cdf68e9a363306433e7d24bd30 [2021-12-15 17:20:21,994 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:22,013 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:22,015 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:22,015 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:22,016 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:22,017 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.01.cil-1.c [2021-12-15 17:20:22,080 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1546617c5/bf2d8c94c1e04ee29ca905af2cedd951/FLAG762a4a1b4 [2021-12-15 17:20:22,466 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:22,469 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.01.cil-1.c [2021-12-15 17:20:22,480 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1546617c5/bf2d8c94c1e04ee29ca905af2cedd951/FLAG762a4a1b4 [2021-12-15 17:20:22,493 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1546617c5/bf2d8c94c1e04ee29ca905af2cedd951 [2021-12-15 17:20:22,495 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:22,496 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:22,499 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:22,499 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:22,501 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:22,501 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,502 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2cd92375 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22, skipping insertion in model container [2021-12-15 17:20:22,502 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,506 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:22,534 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:22,665 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.01.cil-1.c[671,684] [2021-12-15 17:20:22,690 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:22,696 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:22,704 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.01.cil-1.c[671,684] [2021-12-15 17:20:22,718 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:22,728 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:22,728 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22 WrapperNode [2021-12-15 17:20:22,728 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:22,729 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:22,729 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:22,729 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:22,733 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,738 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,758 INFO L137 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 38, statements flattened = 405 [2021-12-15 17:20:22,758 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:22,759 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:22,761 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:22,761 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:22,766 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,766 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,768 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,775 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,780 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,784 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,785 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,787 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:22,788 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:22,788 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:22,788 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:22,789 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (1/1) ... [2021-12-15 17:20:22,795 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:22,805 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:22,818 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:22,823 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:22,847 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:22,847 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:22,847 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:22,847 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:22,892 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:22,893 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:23,212 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:23,217 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:23,217 INFO L301 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-15 17:20:23,218 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:23 BoogieIcfgContainer [2021-12-15 17:20:23,219 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:23,219 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:23,221 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:23,223 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:23,224 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:23,224 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:22" (1/3) ... [2021-12-15 17:20:23,225 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@486a5008 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:23, skipping insertion in model container [2021-12-15 17:20:23,225 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:23,225 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:22" (2/3) ... [2021-12-15 17:20:23,225 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@486a5008 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:23, skipping insertion in model container [2021-12-15 17:20:23,225 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:23,225 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:23" (3/3) ... [2021-12-15 17:20:23,226 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.01.cil-1.c [2021-12-15 17:20:23,252 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:23,254 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:23,254 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:23,254 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:23,254 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:23,254 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:23,255 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:23,255 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:23,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 117 [2021-12-15 17:20:23,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,305 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,306 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:23,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 117 [2021-12-15 17:20:23,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,328 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,329 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,334 INFO L791 eck$LassoCheckResult]: Stem: 140#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 49#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 98#L391true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60#L163true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77#L170true assume !(1 == ~m_i~0);~m_st~0 := 2; 57#L170-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 141#L175-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79#L259true assume !(0 == ~M_E~0); 136#L259-2true assume !(0 == ~T1_E~0); 96#L264-1true assume !(0 == ~E_M~0); 114#L269-1true assume !(0 == ~E_1~0); 89#L274-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L124true assume 1 == ~m_pc~0; 100#L125true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 127#L135true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20#L136true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 154#L319true assume !(0 != activate_threads_~tmp~1#1); 21#L319-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119#L143true assume 1 == ~t1_pc~0; 8#L144true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 104#L154true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56#L155true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28#L327true assume !(0 != activate_threads_~tmp___0~0#1); 43#L327-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74#L287true assume !(1 == ~M_E~0); 106#L287-2true assume !(1 == ~T1_E~0); 39#L292-1true assume !(1 == ~E_M~0); 42#L297-1true assume !(1 == ~E_1~0); 29#L302-1true assume { :end_inline_reset_delta_events } true; 54#L428-2true [2021-12-15 17:20:23,336 INFO L793 eck$LassoCheckResult]: Loop: 54#L428-2true assume !false; 93#L429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80#L234true assume false; 6#L249true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26#L163-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145#L259-3true assume 0 == ~M_E~0;~M_E~0 := 1; 138#L259-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 113#L264-3true assume 0 == ~E_M~0;~E_M~0 := 1; 18#L269-3true assume 0 == ~E_1~0;~E_1~0 := 1; 67#L274-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14#L124-9true assume 1 == ~m_pc~0; 33#L125-3true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 72#L135-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25#L136-3true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 90#L319-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51#L319-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65#L143-9true assume !(1 == ~t1_pc~0); 27#L143-11true is_transmit1_triggered_~__retres1~1#1 := 0; 66#L154-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17#L155-3true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 116#L327-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 153#L327-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 142#L287-3true assume !(1 == ~M_E~0); 75#L287-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 83#L292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 87#L297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 7#L302-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 130#L188-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 31#L200-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 111#L201-1true start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 38#L447true assume !(0 == start_simulation_~tmp~3#1); 108#L447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9#L188-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 99#L200-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 134#L201-2true stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 101#L402true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 144#L409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118#L410true start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 68#L460true assume !(0 != start_simulation_~tmp___0~1#1); 54#L428-2true [2021-12-15 17:20:23,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,344 INFO L85 PathProgramCache]: Analyzing trace with hash -704910459, now seen corresponding path program 1 times [2021-12-15 17:20:23,351 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150930711] [2021-12-15 17:20:23,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,353 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150930711] [2021-12-15 17:20:23,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150930711] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,482 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:23,484 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525386884] [2021-12-15 17:20:23,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,488 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,491 INFO L85 PathProgramCache]: Analyzing trace with hash 180057256, now seen corresponding path program 1 times [2021-12-15 17:20:23,491 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,491 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631675186] [2021-12-15 17:20:23,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,491 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,524 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,524 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631675186] [2021-12-15 17:20:23,525 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [631675186] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,525 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,525 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:23,525 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790924700] [2021-12-15 17:20:23,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,526 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,527 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:23,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:23,552 INFO L87 Difference]: Start difference. First operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:23,584 INFO L93 Difference]: Finished difference Result 151 states and 219 transitions. [2021-12-15 17:20:23,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:23,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 219 transitions. [2021-12-15 17:20:23,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 115 [2021-12-15 17:20:23,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 146 states and 214 transitions. [2021-12-15 17:20:23,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146 [2021-12-15 17:20:23,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146 [2021-12-15 17:20:23,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 214 transitions. [2021-12-15 17:20:23,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:23,603 INFO L681 BuchiCegarLoop]: Abstraction has 146 states and 214 transitions. [2021-12-15 17:20:23,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 214 transitions. [2021-12-15 17:20:23,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2021-12-15 17:20:23,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 214 transitions. [2021-12-15 17:20:23,626 INFO L704 BuchiCegarLoop]: Abstraction has 146 states and 214 transitions. [2021-12-15 17:20:23,626 INFO L587 BuchiCegarLoop]: Abstraction has 146 states and 214 transitions. [2021-12-15 17:20:23,626 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:23,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 214 transitions. [2021-12-15 17:20:23,628 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 115 [2021-12-15 17:20:23,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,630 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,630 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,630 INFO L791 eck$LassoCheckResult]: Stem: 456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 396#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 408#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 409#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 404#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 424#L259 assume !(0 == ~M_E~0); 425#L259-2 assume !(0 == ~T1_E~0); 441#L264-1 assume !(0 == ~E_M~0); 442#L269-1 assume !(0 == ~E_1~0); 435#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 436#L124 assume 1 == ~m_pc~0; 437#L125 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 416#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 344#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 345#L319 assume !(0 != activate_threads_~tmp~1#1); 346#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347#L143 assume 1 == ~t1_pc~0; 326#L144 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 327#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 403#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 360#L327 assume !(0 != activate_threads_~tmp___0~0#1); 361#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 384#L287 assume !(1 == ~M_E~0); 423#L287-2 assume !(1 == ~T1_E~0); 379#L292-1 assume !(1 == ~E_M~0); 380#L297-1 assume !(1 == ~E_1~0); 362#L302-1 assume { :end_inline_reset_delta_events } true; 363#L428-2 [2021-12-15 17:20:23,631 INFO L793 eck$LassoCheckResult]: Loop: 363#L428-2 assume !false; 401#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 420#L234 assume !false; 426#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 348#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 349#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 417#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 418#L215 assume !(0 != eval_~tmp~0#1); 319#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 320#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 355#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 455#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 447#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 342#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332#L124-9 assume 1 == ~m_pc~0; 333#L125-3 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 368#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 353#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 354#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 397#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 398#L143-9 assume !(1 == ~t1_pc~0); 356#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 357#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 337#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 338#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 449#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 457#L287-3 assume !(1 == ~M_E~0); 421#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 422#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 432#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 317#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 318#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 358#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 359#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 376#L447 assume !(0 == start_simulation_~tmp~3#1); 377#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 321#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 322#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 443#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 444#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 445#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 450#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 414#L460 assume !(0 != start_simulation_~tmp___0~1#1); 363#L428-2 [2021-12-15 17:20:23,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,631 INFO L85 PathProgramCache]: Analyzing trace with hash -845459069, now seen corresponding path program 1 times [2021-12-15 17:20:23,635 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,635 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101435510] [2021-12-15 17:20:23,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,635 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,668 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101435510] [2021-12-15 17:20:23,670 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1101435510] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,670 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,671 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:23,671 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164162619] [2021-12-15 17:20:23,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,672 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1897027051, now seen corresponding path program 1 times [2021-12-15 17:20:23,676 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815840034] [2021-12-15 17:20:23,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,709 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,710 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815840034] [2021-12-15 17:20:23,710 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815840034] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,710 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,710 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:23,710 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540718522] [2021-12-15 17:20:23,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,711 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,711 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:23,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:23,712 INFO L87 Difference]: Start difference. First operand 146 states and 214 transitions. cyclomatic complexity: 69 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:23,751 INFO L93 Difference]: Finished difference Result 253 states and 362 transitions. [2021-12-15 17:20:23,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:23,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253 states and 362 transitions. [2021-12-15 17:20:23,754 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 222 [2021-12-15 17:20:23,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253 states to 253 states and 362 transitions. [2021-12-15 17:20:23,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 253 [2021-12-15 17:20:23,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 253 [2021-12-15 17:20:23,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253 states and 362 transitions. [2021-12-15 17:20:23,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:23,757 INFO L681 BuchiCegarLoop]: Abstraction has 253 states and 362 transitions. [2021-12-15 17:20:23,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states and 362 transitions. [2021-12-15 17:20:23,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 240. [2021-12-15 17:20:23,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 345 transitions. [2021-12-15 17:20:23,769 INFO L704 BuchiCegarLoop]: Abstraction has 240 states and 345 transitions. [2021-12-15 17:20:23,769 INFO L587 BuchiCegarLoop]: Abstraction has 240 states and 345 transitions. [2021-12-15 17:20:23,769 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:23,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 240 states and 345 transitions. [2021-12-15 17:20:23,770 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 209 [2021-12-15 17:20:23,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,771 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,771 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,774 INFO L791 eck$LassoCheckResult]: Stem: 876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 804#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 818#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 819#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 814#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 815#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 836#L259 assume !(0 == ~M_E~0); 837#L259-2 assume !(0 == ~T1_E~0); 855#L264-1 assume !(0 == ~E_M~0); 856#L269-1 assume !(0 == ~E_1~0); 849#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 850#L124 assume !(1 == ~m_pc~0); 826#L124-2 is_master_triggered_~__retres1~0#1 := 0; 827#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 749#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 750#L319 assume !(0 != activate_threads_~tmp~1#1); 751#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 752#L143 assume 1 == ~t1_pc~0; 732#L144 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 733#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 813#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 767#L327 assume !(0 != activate_threads_~tmp___0~0#1); 768#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 791#L287 assume !(1 == ~M_E~0); 835#L287-2 assume !(1 == ~T1_E~0); 786#L292-1 assume !(1 == ~E_M~0); 787#L297-1 assume !(1 == ~E_1~0); 769#L302-1 assume { :end_inline_reset_delta_events } true; 770#L428-2 [2021-12-15 17:20:23,774 INFO L793 eck$LassoCheckResult]: Loop: 770#L428-2 assume !false; 915#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 843#L234 assume !false; 844#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 753#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 754#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 828#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 829#L215 assume !(0 != eval_~tmp~0#1); 725#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 726#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 760#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 875#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 862#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 746#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 747#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 738#L124-9 assume !(1 == ~m_pc~0); 739#L124-11 is_master_triggered_~__retres1~0#1 := 0; 957#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 956#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 955#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 954#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 953#L143-9 assume !(1 == ~t1_pc~0); 951#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 950#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 744#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 745#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 865#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 877#L287-3 assume !(1 == ~M_E~0); 833#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 834#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 845#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 723#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 724#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 765#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 766#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 783#L447 assume !(0 == start_simulation_~tmp~3#1); 784#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 928#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 925#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 924#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 923#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 922#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 920#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 918#L460 assume !(0 != start_simulation_~tmp___0~1#1); 770#L428-2 [2021-12-15 17:20:23,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,775 INFO L85 PathProgramCache]: Analyzing trace with hash 1269536452, now seen corresponding path program 1 times [2021-12-15 17:20:23,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546553431] [2021-12-15 17:20:23,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,775 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,814 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546553431] [2021-12-15 17:20:23,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546553431] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,815 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:23,815 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487572265] [2021-12-15 17:20:23,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,816 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:23,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1426265558, now seen corresponding path program 1 times [2021-12-15 17:20:23,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982688531] [2021-12-15 17:20:23,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,817 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:23,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:23,840 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:23,840 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982688531] [2021-12-15 17:20:23,841 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982688531] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:23,841 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:23,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:23,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646408145] [2021-12-15 17:20:23,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:23,841 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:23,842 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:23,842 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:23,842 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:23,842 INFO L87 Difference]: Start difference. First operand 240 states and 345 transitions. cyclomatic complexity: 107 Second operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:23,931 INFO L93 Difference]: Finished difference Result 512 states and 719 transitions. [2021-12-15 17:20:23,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:23,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 719 transitions. [2021-12-15 17:20:23,935 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 461 [2021-12-15 17:20:23,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 512 states and 719 transitions. [2021-12-15 17:20:23,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2021-12-15 17:20:23,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2021-12-15 17:20:23,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512 states and 719 transitions. [2021-12-15 17:20:23,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:23,942 INFO L681 BuchiCegarLoop]: Abstraction has 512 states and 719 transitions. [2021-12-15 17:20:23,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states and 719 transitions. [2021-12-15 17:20:23,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 407. [2021-12-15 17:20:23,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:23,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 580 transitions. [2021-12-15 17:20:23,954 INFO L704 BuchiCegarLoop]: Abstraction has 407 states and 580 transitions. [2021-12-15 17:20:23,954 INFO L587 BuchiCegarLoop]: Abstraction has 407 states and 580 transitions. [2021-12-15 17:20:23,954 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:23,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 407 states and 580 transitions. [2021-12-15 17:20:23,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2021-12-15 17:20:23,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:23,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:23,956 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,956 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:23,957 INFO L791 eck$LassoCheckResult]: Stem: 1641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 1566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1567#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1579#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1580#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 1575#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1576#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1596#L259 assume !(0 == ~M_E~0); 1597#L259-2 assume !(0 == ~T1_E~0); 1618#L264-1 assume !(0 == ~E_M~0); 1619#L269-1 assume !(0 == ~E_1~0); 1612#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1613#L124 assume !(1 == ~m_pc~0); 1586#L124-2 is_master_triggered_~__retres1~0#1 := 0; 1587#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1511#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1512#L319 assume !(0 != activate_threads_~tmp~1#1); 1513#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1514#L143 assume !(1 == ~t1_pc~0); 1497#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1498#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1574#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1529#L327 assume !(0 != activate_threads_~tmp___0~0#1); 1530#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1551#L287 assume !(1 == ~M_E~0); 1595#L287-2 assume !(1 == ~T1_E~0); 1546#L292-1 assume !(1 == ~E_M~0); 1547#L297-1 assume !(1 == ~E_1~0); 1531#L302-1 assume { :end_inline_reset_delta_events } true; 1532#L428-2 [2021-12-15 17:20:23,957 INFO L793 eck$LassoCheckResult]: Loop: 1532#L428-2 assume !false; 1572#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1592#L234 assume !false; 1598#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1515#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1516#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1589#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1590#L215 assume !(0 != eval_~tmp~0#1); 1643#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1886#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1885#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1884#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1883#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1882#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1881#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1868#L124-9 assume !(1 == ~m_pc~0); 1623#L124-11 is_master_triggered_~__retres1~0#1 := 0; 1588#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1520#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1521#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1568#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1569#L143-9 assume !(1 == ~t1_pc~0); 1523#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 1524#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1506#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1507#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1626#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1642#L287-3 assume !(1 == ~M_E~0); 1593#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1594#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1604#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1487#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1488#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1527#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1528#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1543#L447 assume !(0 == start_simulation_~tmp~3#1); 1544#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1489#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1490#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1620#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 1621#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1622#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1628#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1585#L460 assume !(0 != start_simulation_~tmp___0~1#1); 1532#L428-2 [2021-12-15 17:20:23,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,957 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 1 times [2021-12-15 17:20:23,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378807537] [2021-12-15 17:20:23,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,968 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:23,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:23,990 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:23,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:23,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1426265558, now seen corresponding path program 2 times [2021-12-15 17:20:23,991 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:23,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333171995] [2021-12-15 17:20:23,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:23,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:23,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,018 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333171995] [2021-12-15 17:20:24,018 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1333171995] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,018 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,020 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,021 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277738018] [2021-12-15 17:20:24,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,021 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,021 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,022 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,022 INFO L87 Difference]: Start difference. First operand 407 states and 580 transitions. cyclomatic complexity: 175 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,035 INFO L93 Difference]: Finished difference Result 496 states and 698 transitions. [2021-12-15 17:20:24,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 496 states and 698 transitions. [2021-12-15 17:20:24,038 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 448 [2021-12-15 17:20:24,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 496 states to 496 states and 698 transitions. [2021-12-15 17:20:24,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 496 [2021-12-15 17:20:24,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 496 [2021-12-15 17:20:24,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 496 states and 698 transitions. [2021-12-15 17:20:24,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,041 INFO L681 BuchiCegarLoop]: Abstraction has 496 states and 698 transitions. [2021-12-15 17:20:24,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states and 698 transitions. [2021-12-15 17:20:24,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 496. [2021-12-15 17:20:24,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 698 transitions. [2021-12-15 17:20:24,049 INFO L704 BuchiCegarLoop]: Abstraction has 496 states and 698 transitions. [2021-12-15 17:20:24,049 INFO L587 BuchiCegarLoop]: Abstraction has 496 states and 698 transitions. [2021-12-15 17:20:24,049 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:24,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 496 states and 698 transitions. [2021-12-15 17:20:24,051 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 448 [2021-12-15 17:20:24,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,051 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,051 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,051 INFO L791 eck$LassoCheckResult]: Stem: 2562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 2474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2475#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2488#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2489#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 2484#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2485#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2507#L259 assume 0 == ~M_E~0;~M_E~0 := 1; 2508#L259-2 assume !(0 == ~T1_E~0); 2646#L264-1 assume !(0 == ~E_M~0); 2644#L269-1 assume !(0 == ~E_1~0); 2642#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2641#L124 assume !(1 == ~m_pc~0); 2640#L124-2 is_master_triggered_~__retres1~0#1 := 0; 2639#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2635#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2634#L319 assume !(0 != activate_threads_~tmp~1#1); 2632#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2631#L143 assume !(1 == ~t1_pc~0); 2628#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2626#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2624#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2614#L327 assume !(0 != activate_threads_~tmp___0~0#1); 2459#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2460#L287 assume 1 == ~M_E~0;~M_E~0 := 2; 2506#L287-2 assume !(1 == ~T1_E~0); 2454#L292-1 assume !(1 == ~E_M~0); 2455#L297-1 assume !(1 == ~E_1~0); 2439#L302-1 assume { :end_inline_reset_delta_events } true; 2440#L428-2 [2021-12-15 17:20:24,052 INFO L793 eck$LassoCheckResult]: Loop: 2440#L428-2 assume !false; 2845#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2549#L234 assume !false; 2844#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2842#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2841#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2680#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2678#L215 assume !(0 != eval_~tmp~0#1); 2679#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2839#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2836#L259-3 assume !(0 == ~M_E~0); 2834#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2832#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2830#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2828#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2826#L124-9 assume !(1 == ~m_pc~0); 2825#L124-11 is_master_triggered_~__retres1~0#1 := 0; 2824#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2823#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2525#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2526#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2822#L143-9 assume !(1 == ~t1_pc~0); 2790#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2818#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2815#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2807#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2808#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L287-3 assume !(1 == ~M_E~0); 2564#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2516#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2517#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2394#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2395#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2810#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2809#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2451#L447 assume !(0 == start_simulation_~tmp~3#1); 2452#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2853#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2851#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2850#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 2849#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2848#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2847#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2846#L460 assume !(0 != start_simulation_~tmp___0~1#1); 2440#L428-2 [2021-12-15 17:20:24,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,052 INFO L85 PathProgramCache]: Analyzing trace with hash 175996037, now seen corresponding path program 1 times [2021-12-15 17:20:24,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780585596] [2021-12-15 17:20:24,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,073 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780585596] [2021-12-15 17:20:24,074 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1780585596] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,074 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,074 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:24,074 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054552980] [2021-12-15 17:20:24,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,074 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:24,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,074 INFO L85 PathProgramCache]: Analyzing trace with hash -817717740, now seen corresponding path program 1 times [2021-12-15 17:20:24,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665581534] [2021-12-15 17:20:24,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,106 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665581534] [2021-12-15 17:20:24,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665581534] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,107 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,107 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:24,107 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700874883] [2021-12-15 17:20:24,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,107 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,107 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,108 INFO L87 Difference]: Start difference. First operand 496 states and 698 transitions. cyclomatic complexity: 204 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,116 INFO L93 Difference]: Finished difference Result 407 states and 566 transitions. [2021-12-15 17:20:24,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 407 states and 566 transitions. [2021-12-15 17:20:24,118 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2021-12-15 17:20:24,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 407 states to 407 states and 566 transitions. [2021-12-15 17:20:24,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 407 [2021-12-15 17:20:24,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 407 [2021-12-15 17:20:24,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 407 states and 566 transitions. [2021-12-15 17:20:24,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,121 INFO L681 BuchiCegarLoop]: Abstraction has 407 states and 566 transitions. [2021-12-15 17:20:24,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states and 566 transitions. [2021-12-15 17:20:24,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 407. [2021-12-15 17:20:24,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 566 transitions. [2021-12-15 17:20:24,125 INFO L704 BuchiCegarLoop]: Abstraction has 407 states and 566 transitions. [2021-12-15 17:20:24,125 INFO L587 BuchiCegarLoop]: Abstraction has 407 states and 566 transitions. [2021-12-15 17:20:24,125 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:24,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 407 states and 566 transitions. [2021-12-15 17:20:24,127 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2021-12-15 17:20:24,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,127 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,127 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,127 INFO L791 eck$LassoCheckResult]: Stem: 3479#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 3386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3387#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3402#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3403#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 3398#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3399#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3424#L259 assume !(0 == ~M_E~0); 3425#L259-2 assume !(0 == ~T1_E~0); 3449#L264-1 assume !(0 == ~E_M~0); 3450#L269-1 assume !(0 == ~E_1~0); 3440#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3441#L124 assume !(1 == ~m_pc~0); 3411#L124-2 is_master_triggered_~__retres1~0#1 := 0; 3412#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3332#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3333#L319 assume !(0 != activate_threads_~tmp~1#1); 3334#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3335#L143 assume !(1 == ~t1_pc~0); 3319#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3320#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3397#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3350#L327 assume !(0 != activate_threads_~tmp___0~0#1); 3351#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3374#L287 assume !(1 == ~M_E~0); 3420#L287-2 assume !(1 == ~T1_E~0); 3369#L292-1 assume !(1 == ~E_M~0); 3370#L297-1 assume !(1 == ~E_1~0); 3352#L302-1 assume { :end_inline_reset_delta_events } true; 3353#L428-2 [2021-12-15 17:20:24,127 INFO L793 eck$LassoCheckResult]: Loop: 3353#L428-2 assume !false; 3445#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3417#L234 assume !false; 3646#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3644#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3643#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3642#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3483#L215 assume !(0 != eval_~tmp~0#1); 3306#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3307#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3343#L259-3 assume !(0 == ~M_E~0); 3478#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3458#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3330#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3331#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3321#L124-9 assume !(1 == ~m_pc~0); 3322#L124-11 is_master_triggered_~__retres1~0#1 := 0; 3415#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3341#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3342#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3442#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3408#L143-9 assume !(1 == ~t1_pc~0); 3344#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3345#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3325#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3326#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3459#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3480#L287-3 assume !(1 == ~M_E~0); 3418#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3419#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3433#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3308#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3309#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3346#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3347#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3366#L447 assume !(0 == start_simulation_~tmp~3#1); 3367#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3310#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3311#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3651#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 3453#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3454#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3461#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3410#L460 assume !(0 != start_simulation_~tmp___0~1#1); 3353#L428-2 [2021-12-15 17:20:24,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,128 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 2 times [2021-12-15 17:20:24,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331367016] [2021-12-15 17:20:24,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,128 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,144 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,152 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,152 INFO L85 PathProgramCache]: Analyzing trace with hash -817717740, now seen corresponding path program 2 times [2021-12-15 17:20:24,152 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753083383] [2021-12-15 17:20:24,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,183 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753083383] [2021-12-15 17:20:24,184 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753083383] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,184 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,184 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:24,184 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130666117] [2021-12-15 17:20:24,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,184 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,184 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:24,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:24,185 INFO L87 Difference]: Start difference. First operand 407 states and 566 transitions. cyclomatic complexity: 161 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,233 INFO L93 Difference]: Finished difference Result 693 states and 942 transitions. [2021-12-15 17:20:24,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:24,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 942 transitions. [2021-12-15 17:20:24,237 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 660 [2021-12-15 17:20:24,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 942 transitions. [2021-12-15 17:20:24,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2021-12-15 17:20:24,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2021-12-15 17:20:24,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 942 transitions. [2021-12-15 17:20:24,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,240 INFO L681 BuchiCegarLoop]: Abstraction has 693 states and 942 transitions. [2021-12-15 17:20:24,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 942 transitions. [2021-12-15 17:20:24,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 419. [2021-12-15 17:20:24,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 419 states to 419 states and 578 transitions. [2021-12-15 17:20:24,246 INFO L704 BuchiCegarLoop]: Abstraction has 419 states and 578 transitions. [2021-12-15 17:20:24,246 INFO L587 BuchiCegarLoop]: Abstraction has 419 states and 578 transitions. [2021-12-15 17:20:24,246 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:24,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states and 578 transitions. [2021-12-15 17:20:24,247 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 388 [2021-12-15 17:20:24,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,248 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,248 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,248 INFO L791 eck$LassoCheckResult]: Stem: 4583#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 4500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4501#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4516#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4517#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 4512#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4513#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4536#L259 assume !(0 == ~M_E~0); 4537#L259-2 assume !(0 == ~T1_E~0); 4558#L264-1 assume !(0 == ~E_M~0); 4559#L269-1 assume !(0 == ~E_1~0); 4553#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4554#L124 assume !(1 == ~m_pc~0); 4525#L124-2 is_master_triggered_~__retres1~0#1 := 0; 4526#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4448#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4449#L319 assume !(0 != activate_threads_~tmp~1#1); 4450#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4451#L143 assume !(1 == ~t1_pc~0); 4434#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4435#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4511#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4466#L327 assume !(0 != activate_threads_~tmp___0~0#1); 4467#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4488#L287 assume !(1 == ~M_E~0); 4535#L287-2 assume !(1 == ~T1_E~0); 4483#L292-1 assume !(1 == ~E_M~0); 4484#L297-1 assume !(1 == ~E_1~0); 4468#L302-1 assume { :end_inline_reset_delta_events } true; 4469#L428-2 [2021-12-15 17:20:24,248 INFO L793 eck$LassoCheckResult]: Loop: 4469#L428-2 assume !false; 4691#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4676#L234 assume !false; 4674#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4671#L188 assume !(0 == ~m_st~0); 4667#L192 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4663#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4654#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4653#L215 assume !(0 != eval_~tmp~0#1); 4652#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4651#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4650#L259-3 assume !(0 == ~M_E~0); 4649#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4648#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4444#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4445#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4436#L124-9 assume !(1 == ~m_pc~0); 4437#L124-11 is_master_triggered_~__retres1~0#1 := 0; 4527#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4457#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4458#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4504#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4505#L143-9 assume !(1 == ~t1_pc~0); 4730#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4770#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4769#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4768#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4767#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4766#L287-3 assume !(1 == ~M_E~0); 4765#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4764#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4763#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4762#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4761#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4758#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4756#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 4753#L447 assume !(0 == start_simulation_~tmp~3#1); 4750#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4749#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4731#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4706#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 4704#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4702#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4700#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4698#L460 assume !(0 != start_simulation_~tmp___0~1#1); 4469#L428-2 [2021-12-15 17:20:24,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,248 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 3 times [2021-12-15 17:20:24,249 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,249 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873732479] [2021-12-15 17:20:24,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,249 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,253 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,259 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,271 INFO L85 PathProgramCache]: Analyzing trace with hash 56440981, now seen corresponding path program 1 times [2021-12-15 17:20:24,271 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366216372] [2021-12-15 17:20:24,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,271 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,312 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366216372] [2021-12-15 17:20:24,312 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366216372] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,312 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,312 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:24,312 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494348210] [2021-12-15 17:20:24,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,313 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,313 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:24,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:24,313 INFO L87 Difference]: Start difference. First operand 419 states and 578 transitions. cyclomatic complexity: 161 Second operand has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,381 INFO L93 Difference]: Finished difference Result 792 states and 1077 transitions. [2021-12-15 17:20:24,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:24,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 792 states and 1077 transitions. [2021-12-15 17:20:24,385 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 761 [2021-12-15 17:20:24,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 792 states to 792 states and 1077 transitions. [2021-12-15 17:20:24,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 792 [2021-12-15 17:20:24,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 792 [2021-12-15 17:20:24,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 792 states and 1077 transitions. [2021-12-15 17:20:24,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,389 INFO L681 BuchiCegarLoop]: Abstraction has 792 states and 1077 transitions. [2021-12-15 17:20:24,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states and 1077 transitions. [2021-12-15 17:20:24,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 440. [2021-12-15 17:20:24,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 593 transitions. [2021-12-15 17:20:24,395 INFO L704 BuchiCegarLoop]: Abstraction has 440 states and 593 transitions. [2021-12-15 17:20:24,395 INFO L587 BuchiCegarLoop]: Abstraction has 440 states and 593 transitions. [2021-12-15 17:20:24,395 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:24,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 440 states and 593 transitions. [2021-12-15 17:20:24,396 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 409 [2021-12-15 17:20:24,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,397 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,397 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,397 INFO L791 eck$LassoCheckResult]: Stem: 5815#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 5725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5726#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5743#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5744#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 5738#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5739#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5764#L259 assume !(0 == ~M_E~0); 5765#L259-2 assume !(0 == ~T1_E~0); 5786#L264-1 assume !(0 == ~E_M~0); 5787#L269-1 assume !(0 == ~E_1~0); 5780#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5781#L124 assume !(1 == ~m_pc~0); 5752#L124-2 is_master_triggered_~__retres1~0#1 := 0; 5753#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5672#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5673#L319 assume !(0 != activate_threads_~tmp~1#1); 5674#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5675#L143 assume !(1 == ~t1_pc~0); 5658#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5659#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5737#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5686#L327 assume !(0 != activate_threads_~tmp___0~0#1); 5687#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5712#L287 assume !(1 == ~M_E~0); 5760#L287-2 assume !(1 == ~T1_E~0); 5707#L292-1 assume !(1 == ~E_M~0); 5708#L297-1 assume !(1 == ~E_1~0); 5688#L302-1 assume { :end_inline_reset_delta_events } true; 5689#L428-2 [2021-12-15 17:20:24,397 INFO L793 eck$LassoCheckResult]: Loop: 5689#L428-2 assume !false; 5866#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5867#L234 assume !false; 5862#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5863#L188 assume !(0 == ~m_st~0); 5856#L192 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5858#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5852#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5853#L215 assume !(0 != eval_~tmp~0#1); 5847#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5848#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5843#L259-3 assume !(0 == ~M_E~0); 5844#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5839#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5840#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5748#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5749#L124-9 assume !(1 == ~m_pc~0); 5989#L124-11 is_master_triggered_~__retres1~0#1 := 0; 5986#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5983#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5980#L319-9 assume !(0 != activate_threads_~tmp~1#1); 5977#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5974#L143-9 assume !(1 == ~t1_pc~0); 5971#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5969#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5967#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5965#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5963#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5947#L287-3 assume !(1 == ~M_E~0); 5948#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5939#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5940#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5931#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5932#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5922#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5923#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 5915#L447 assume !(0 == start_simulation_~tmp~3#1); 5914#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5910#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5909#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5904#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 5905#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5900#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5901#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 5897#L460 assume !(0 != start_simulation_~tmp___0~1#1); 5689#L428-2 [2021-12-15 17:20:24,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,397 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 4 times [2021-12-15 17:20:24,397 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734293432] [2021-12-15 17:20:24,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,402 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,407 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,408 INFO L85 PathProgramCache]: Analyzing trace with hash 196989591, now seen corresponding path program 1 times [2021-12-15 17:20:24,408 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002038319] [2021-12-15 17:20:24,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,408 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,423 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002038319] [2021-12-15 17:20:24,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002038319] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,423 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,423 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143101955] [2021-12-15 17:20:24,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,423 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,423 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,424 INFO L87 Difference]: Start difference. First operand 440 states and 593 transitions. cyclomatic complexity: 155 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,443 INFO L93 Difference]: Finished difference Result 641 states and 847 transitions. [2021-12-15 17:20:24,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 641 states and 847 transitions. [2021-12-15 17:20:24,446 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 606 [2021-12-15 17:20:24,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 641 states to 641 states and 847 transitions. [2021-12-15 17:20:24,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 641 [2021-12-15 17:20:24,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 641 [2021-12-15 17:20:24,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 641 states and 847 transitions. [2021-12-15 17:20:24,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,449 INFO L681 BuchiCegarLoop]: Abstraction has 641 states and 847 transitions. [2021-12-15 17:20:24,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states and 847 transitions. [2021-12-15 17:20:24,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 624. [2021-12-15 17:20:24,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 624 states and 826 transitions. [2021-12-15 17:20:24,455 INFO L704 BuchiCegarLoop]: Abstraction has 624 states and 826 transitions. [2021-12-15 17:20:24,455 INFO L587 BuchiCegarLoop]: Abstraction has 624 states and 826 transitions. [2021-12-15 17:20:24,455 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:24,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 624 states and 826 transitions. [2021-12-15 17:20:24,457 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 589 [2021-12-15 17:20:24,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,458 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,458 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,458 INFO L791 eck$LassoCheckResult]: Stem: 6898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 6811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6812#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6826#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6827#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 6821#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6822#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6845#L259 assume !(0 == ~M_E~0); 6846#L259-2 assume !(0 == ~T1_E~0); 6866#L264-1 assume !(0 == ~E_M~0); 6867#L269-1 assume !(0 == ~E_1~0); 6862#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6863#L124 assume !(1 == ~m_pc~0); 6833#L124-2 is_master_triggered_~__retres1~0#1 := 0; 6834#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6756#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6757#L319 assume !(0 != activate_threads_~tmp~1#1); 6758#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6759#L143 assume !(1 == ~t1_pc~0); 6743#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6744#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6820#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6773#L327 assume !(0 != activate_threads_~tmp___0~0#1); 6774#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6796#L287 assume !(1 == ~M_E~0); 6842#L287-2 assume !(1 == ~T1_E~0); 6791#L292-1 assume !(1 == ~E_M~0); 6792#L297-1 assume !(1 == ~E_1~0); 6775#L302-1 assume { :end_inline_reset_delta_events } true; 6776#L428-2 assume !false; 7339#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7114#L234 [2021-12-15 17:20:24,458 INFO L793 eck$LassoCheckResult]: Loop: 7114#L234 assume !false; 7336#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7334#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7325#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7324#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7322#L215 assume 0 != eval_~tmp~0#1; 7321#L215-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 6843#L223 assume !(0 != eval_~tmp_ndt_1~0#1); 6844#L220 assume !(0 == ~t1_st~0); 7114#L234 [2021-12-15 17:20:24,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,458 INFO L85 PathProgramCache]: Analyzing trace with hash -1025502329, now seen corresponding path program 1 times [2021-12-15 17:20:24,458 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052233283] [2021-12-15 17:20:24,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,459 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,462 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,467 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,468 INFO L85 PathProgramCache]: Analyzing trace with hash 2078330545, now seen corresponding path program 1 times [2021-12-15 17:20:24,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070452623] [2021-12-15 17:20:24,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,468 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,470 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:24,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:24,472 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:24,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,472 INFO L85 PathProgramCache]: Analyzing trace with hash 1188516331, now seen corresponding path program 1 times [2021-12-15 17:20:24,473 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981877810] [2021-12-15 17:20:24,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,486 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,486 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981877810] [2021-12-15 17:20:24,486 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981877810] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,486 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,486 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:24,486 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932239565] [2021-12-15 17:20:24,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,518 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:24,521 INFO L158 Benchmark]: Toolchain (without parser) took 2023.79ms. Allocated memory was 107.0MB in the beginning and 142.6MB in the end (delta: 35.7MB). Free memory was 78.2MB in the beginning and 68.6MB in the end (delta: 9.6MB). Peak memory consumption was 45.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,521 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 107.0MB. Free memory was 63.5MB in the beginning and 63.5MB in the end (delta: 48.1kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:24,521 INFO L158 Benchmark]: CACSL2BoogieTranslator took 229.73ms. Allocated memory was 107.0MB in the beginning and 142.6MB in the end (delta: 35.7MB). Free memory was 77.8MB in the beginning and 116.5MB in the end (delta: -38.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,521 INFO L158 Benchmark]: Boogie Procedure Inliner took 29.77ms. Allocated memory is still 142.6MB. Free memory was 116.5MB in the beginning and 114.1MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,522 INFO L158 Benchmark]: Boogie Preprocessor took 28.35ms. Allocated memory is still 142.6MB. Free memory was 114.1MB in the beginning and 112.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,522 INFO L158 Benchmark]: RCFGBuilder took 430.71ms. Allocated memory is still 142.6MB. Free memory was 112.0MB in the beginning and 93.4MB in the end (delta: 18.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,522 INFO L158 Benchmark]: BuchiAutomizer took 1300.59ms. Allocated memory is still 142.6MB. Free memory was 93.1MB in the beginning and 68.6MB in the end (delta: 24.5MB). Peak memory consumption was 27.6MB. Max. memory is 16.1GB. [2021-12-15 17:20:24,524 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 107.0MB. Free memory was 63.5MB in the beginning and 63.5MB in the end (delta: 48.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 229.73ms. Allocated memory was 107.0MB in the beginning and 142.6MB in the end (delta: 35.7MB). Free memory was 77.8MB in the beginning and 116.5MB in the end (delta: -38.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 29.77ms. Allocated memory is still 142.6MB. Free memory was 116.5MB in the beginning and 114.1MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 28.35ms. Allocated memory is still 142.6MB. Free memory was 114.1MB in the beginning and 112.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 430.71ms. Allocated memory is still 142.6MB. Free memory was 112.0MB in the beginning and 93.4MB in the end (delta: 18.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 1300.59ms. Allocated memory is still 142.6MB. Free memory was 93.1MB in the beginning and 68.6MB in the end (delta: 24.5MB). Peak memory consumption was 27.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:24,545 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable