./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:22,226 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:22,229 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:22,270 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:22,270 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:22,271 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:22,272 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:22,280 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:22,282 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:22,282 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:22,283 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:22,284 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:22,285 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:22,285 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:22,286 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:22,287 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:22,288 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:22,289 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:22,290 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:22,292 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:22,293 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:22,294 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:22,295 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:22,296 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:22,303 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:22,310 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:22,310 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:22,311 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:22,312 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:22,313 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:22,313 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:22,314 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:22,315 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:22,316 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:22,317 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:22,318 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:22,319 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:22,319 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:22,319 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:22,320 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:22,321 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:22,321 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:22,348 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:22,348 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:22,348 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:22,349 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:22,350 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:22,350 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:22,350 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:22,350 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:22,350 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:22,351 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:22,351 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:22,351 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:22,351 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:22,351 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:22,352 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:22,353 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:22,353 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:22,353 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:22,353 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:22,353 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:22,354 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:22,354 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:22,354 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:22,354 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:22,355 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:22,355 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:22,355 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:22,355 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:22,356 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:22,356 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:22,356 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:22,356 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:22,357 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:22,357 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd [2021-12-15 17:20:22,576 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:22,599 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:22,602 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:22,603 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:22,603 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:22,604 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-12-15 17:20:22,663 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fafa936c5/899307c4f53e4b42ba0c82cb5b2591d5/FLAG1cf43cf6f [2021-12-15 17:20:23,089 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:23,091 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2021-12-15 17:20:23,107 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fafa936c5/899307c4f53e4b42ba0c82cb5b2591d5/FLAG1cf43cf6f [2021-12-15 17:20:23,460 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fafa936c5/899307c4f53e4b42ba0c82cb5b2591d5 [2021-12-15 17:20:23,462 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:23,463 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:23,465 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:23,465 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:23,468 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:23,468 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,469 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@12c8cc66 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23, skipping insertion in model container [2021-12-15 17:20:23,469 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,475 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:23,497 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:23,592 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2021-12-15 17:20:23,630 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:23,643 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:23,654 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2021-12-15 17:20:23,675 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:23,688 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:23,688 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23 WrapperNode [2021-12-15 17:20:23,689 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:23,690 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:23,690 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:23,690 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:23,696 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,702 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,739 INFO L137 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 49, statements flattened = 594 [2021-12-15 17:20:23,739 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:23,740 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:23,740 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:23,740 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:23,746 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,747 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,750 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,750 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,757 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,765 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,768 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,772 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:23,773 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:23,773 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:23,773 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:23,774 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,780 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:23,804 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:23,824 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:23,827 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:23,854 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:23,854 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:23,854 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:23,855 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:23,909 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:23,910 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:24,330 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:24,338 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:24,339 INFO L301 CfgBuilder]: Removed 5 assume(true) statements. [2021-12-15 17:20:24,340 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:24 BoogieIcfgContainer [2021-12-15 17:20:24,341 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:24,341 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:24,342 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:24,345 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:24,349 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,349 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:23" (1/3) ... [2021-12-15 17:20:24,350 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f1e0df4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:24, skipping insertion in model container [2021-12-15 17:20:24,351 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,351 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (2/3) ... [2021-12-15 17:20:24,351 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f1e0df4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:24, skipping insertion in model container [2021-12-15 17:20:24,371 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,372 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:24" (3/3) ... [2021-12-15 17:20:24,379 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2021-12-15 17:20:24,443 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:24,445 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:24,445 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:24,445 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:24,446 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:24,446 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:24,446 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:24,446 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:24,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2021-12-15 17:20:24,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,528 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,528 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,528 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:24,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2021-12-15 17:20:24,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,549 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,557 INFO L791 eck$LassoCheckResult]: Stem: 220#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 161#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 189#L516true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186#L224true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77#L231true assume !(1 == ~m_i~0);~m_st~0 := 2; 4#L231-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 129#L236-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 126#L241-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29#L344true assume !(0 == ~M_E~0); 182#L344-2true assume !(0 == ~T1_E~0); 156#L349-1true assume !(0 == ~T2_E~0); 38#L354-1true assume 0 == ~E_M~0;~E_M~0 := 1; 193#L359-1true assume !(0 == ~E_1~0); 36#L364-1true assume !(0 == ~E_2~0); 164#L369-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L166true assume 1 == ~m_pc~0; 151#L167true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 167#L177true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28#L178true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 210#L425true assume !(0 != activate_threads_~tmp~1#1); 226#L425-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101#L185true assume !(1 == ~t1_pc~0); 41#L185-2true is_transmit1_triggered_~__retres1~1#1 := 0; 61#L196true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70#L197true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 66#L433true assume !(0 != activate_threads_~tmp___0~0#1); 165#L433-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111#L204true assume 1 == ~t2_pc~0; 71#L205true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 130#L215true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 208#L216true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19#L441true assume !(0 != activate_threads_~tmp___1~0#1); 95#L441-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116#L382true assume !(1 == ~M_E~0); 13#L382-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 83#L387-1true assume !(1 == ~T2_E~0); 190#L392-1true assume !(1 == ~E_M~0); 106#L397-1true assume !(1 == ~E_1~0); 135#L402-1true assume !(1 == ~E_2~0); 96#L407-1true assume { :end_inline_reset_delta_events } true; 178#L553-2true [2021-12-15 17:20:24,564 INFO L793 eck$LassoCheckResult]: Loop: 178#L553-2true assume !false; 231#L554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 232#L319true assume !true; 32#L334true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 221#L224-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 196#L344-3true assume !(0 == ~M_E~0); 3#L344-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 78#L349-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 31#L354-3true assume 0 == ~E_M~0;~E_M~0 := 1; 103#L359-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L364-3true assume 0 == ~E_2~0;~E_2~0 := 1; 74#L369-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59#L166-12true assume !(1 == ~m_pc~0); 172#L166-14true is_master_triggered_~__retres1~0#1 := 0; 44#L177-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82#L178-4true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 56#L425-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119#L425-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 204#L185-12true assume !(1 == ~t1_pc~0); 34#L185-14true is_transmit1_triggered_~__retres1~1#1 := 0; 146#L196-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200#L197-4true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 197#L433-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136#L433-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199#L204-12true assume !(1 == ~t2_pc~0); 49#L204-14true is_transmit2_triggered_~__retres1~2#1 := 0; 104#L215-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42#L216-4true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 93#L441-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69#L441-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30#L382-3true assume 1 == ~M_E~0;~M_E~0 := 2; 79#L382-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 115#L387-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 143#L392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 9#L397-3true assume 1 == ~E_1~0;~E_1~0 := 2; 122#L402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 15#L407-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8#L254-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 20#L271-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 133#L272-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 108#L572true assume !(0 == start_simulation_~tmp~3#1); 150#L572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27#L254-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 80#L271-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18#L272-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 198#L527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87#L534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191#L535true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 184#L585true assume !(0 != start_simulation_~tmp___0~1#1); 178#L553-2true [2021-12-15 17:20:24,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,574 INFO L85 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2021-12-15 17:20:24,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946536863] [2021-12-15 17:20:24,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,775 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,776 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946536863] [2021-12-15 17:20:24,776 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946536863] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,777 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,778 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,779 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183046812] [2021-12-15 17:20:24,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,785 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:24,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,788 INFO L85 PathProgramCache]: Analyzing trace with hash -152738315, now seen corresponding path program 1 times [2021-12-15 17:20:24,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513030501] [2021-12-15 17:20:24,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,826 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513030501] [2021-12-15 17:20:24,827 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513030501] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,827 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:24,827 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162063217] [2021-12-15 17:20:24,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,829 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,830 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,857 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,859 INFO L87 Difference]: Start difference. First operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,905 INFO L93 Difference]: Finished difference Result 230 states and 340 transitions. [2021-12-15 17:20:24,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 340 transitions. [2021-12-15 17:20:24,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-15 17:20:24,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 225 states and 335 transitions. [2021-12-15 17:20:24,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2021-12-15 17:20:24,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2021-12-15 17:20:24,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 335 transitions. [2021-12-15 17:20:24,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,928 INFO L681 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2021-12-15 17:20:24,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 335 transitions. [2021-12-15 17:20:24,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2021-12-15 17:20:24,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 335 transitions. [2021-12-15 17:20:24,973 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2021-12-15 17:20:24,973 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2021-12-15 17:20:24,973 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:24,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 335 transitions. [2021-12-15 17:20:24,976 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-15 17:20:24,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,980 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,980 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,981 INFO L791 eck$LassoCheckResult]: Stem: 694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 673#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 683#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 600#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 472#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473#L236-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 648#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 520#L344 assume !(0 == ~M_E~0); 521#L344-2 assume !(0 == ~T1_E~0); 669#L349-1 assume !(0 == ~T2_E~0); 539#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 540#L359-1 assume !(0 == ~E_1~0); 534#L364-1 assume !(0 == ~E_2~0); 535#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L166 assume 1 == ~m_pc~0; 614#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 662#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 519#L425 assume !(0 != activate_threads_~tmp~1#1); 692#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623#L185 assume !(1 == ~t1_pc~0); 545#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 546#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 583#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 588#L433 assume !(0 != activate_threads_~tmp___0~0#1); 589#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 634#L204 assume 1 == ~t2_pc~0; 592#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 593#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 501#L441 assume !(0 != activate_threads_~tmp___1~0#1); 502#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 617#L382 assume !(1 == ~M_E~0); 491#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 492#L387-1 assume !(1 == ~T2_E~0); 603#L392-1 assume !(1 == ~E_M~0); 627#L397-1 assume !(1 == ~E_1~0); 628#L402-1 assume !(1 == ~E_2~0); 618#L407-1 assume { :end_inline_reset_delta_events } true; 619#L553-2 [2021-12-15 17:20:24,981 INFO L793 eck$LassoCheckResult]: Loop: 619#L553-2 assume !false; 679#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674#L319 assume !false; 651#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 553#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 554#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 543#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 544#L286 assume !(0 != eval_~tmp~0#1); 526#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 527#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 688#L344-3 assume !(0 == ~M_E~0); 470#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 471#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 524#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 525#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 599#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 597#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 579#L166-12 assume 1 == ~m_pc~0; 580#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 549#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 550#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 573#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 574#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643#L185-12 assume !(1 == ~t1_pc~0); 531#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 532#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 660#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 689#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 653#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 654#L204-12 assume 1 == ~t2_pc~0; 675#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 558#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 548#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 591#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 523#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 601#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 637#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 484#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 485#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 495#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 481#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 482#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 503#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 631#L572 assume !(0 == start_simulation_~tmp~3#1); 542#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 515#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 516#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 499#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 500#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 609#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 610#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 682#L585 assume !(0 != start_simulation_~tmp___0~1#1); 619#L553-2 [2021-12-15 17:20:24,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,982 INFO L85 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2021-12-15 17:20:24,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046680304] [2021-12-15 17:20:24,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,983 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,035 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,035 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046680304] [2021-12-15 17:20:25,035 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046680304] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,035 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,036 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,036 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315909753] [2021-12-15 17:20:25,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,036 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1606950136, now seen corresponding path program 1 times [2021-12-15 17:20:25,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699465776] [2021-12-15 17:20:25,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,096 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,096 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699465776] [2021-12-15 17:20:25,097 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1699465776] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,097 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,097 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,097 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1057879972] [2021-12-15 17:20:25,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,097 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,098 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,098 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,099 INFO L87 Difference]: Start difference. First operand 225 states and 335 transitions. cyclomatic complexity: 111 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,112 INFO L93 Difference]: Finished difference Result 225 states and 334 transitions. [2021-12-15 17:20:25,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 334 transitions. [2021-12-15 17:20:25,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-15 17:20:25,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 334 transitions. [2021-12-15 17:20:25,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2021-12-15 17:20:25,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2021-12-15 17:20:25,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 334 transitions. [2021-12-15 17:20:25,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,120 INFO L681 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2021-12-15 17:20:25,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 334 transitions. [2021-12-15 17:20:25,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2021-12-15 17:20:25,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 334 transitions. [2021-12-15 17:20:25,129 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2021-12-15 17:20:25,130 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2021-12-15 17:20:25,130 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:25,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 334 transitions. [2021-12-15 17:20:25,131 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2021-12-15 17:20:25,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,133 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,134 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,134 INFO L791 eck$LassoCheckResult]: Stem: 1153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1132#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1142#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1059#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 931#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1107#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 979#L344 assume !(0 == ~M_E~0); 980#L344-2 assume !(0 == ~T1_E~0); 1128#L349-1 assume !(0 == ~T2_E~0); 998#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 999#L359-1 assume !(0 == ~E_1~0); 993#L364-1 assume !(0 == ~E_2~0); 994#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1072#L166 assume 1 == ~m_pc~0; 1073#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1121#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 977#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 978#L425 assume !(0 != activate_threads_~tmp~1#1); 1151#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1082#L185 assume !(1 == ~t1_pc~0); 1004#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1005#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1042#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1047#L433 assume !(0 != activate_threads_~tmp___0~0#1); 1048#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1093#L204 assume 1 == ~t2_pc~0; 1051#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1052#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1109#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 960#L441 assume !(0 != activate_threads_~tmp___1~0#1); 961#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1076#L382 assume !(1 == ~M_E~0); 950#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 951#L387-1 assume !(1 == ~T2_E~0); 1062#L392-1 assume !(1 == ~E_M~0); 1086#L397-1 assume !(1 == ~E_1~0); 1087#L402-1 assume !(1 == ~E_2~0); 1077#L407-1 assume { :end_inline_reset_delta_events } true; 1078#L553-2 [2021-12-15 17:20:25,135 INFO L793 eck$LassoCheckResult]: Loop: 1078#L553-2 assume !false; 1138#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1133#L319 assume !false; 1110#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1012#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1013#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1002#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1003#L286 assume !(0 != eval_~tmp~0#1); 985#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 986#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147#L344-3 assume !(0 == ~M_E~0); 929#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 930#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 983#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 984#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1058#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1056#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1038#L166-12 assume !(1 == ~m_pc~0); 1040#L166-14 is_master_triggered_~__retres1~0#1 := 0; 1008#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1009#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1032#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1033#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1102#L185-12 assume 1 == ~t1_pc~0; 1120#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 991#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1119#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1148#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1112#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1113#L204-12 assume !(1 == ~t2_pc~0); 1016#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1017#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1007#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1050#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 981#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 982#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1060#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1096#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 943#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 944#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 954#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 940#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 941#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 962#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1090#L572 assume !(0 == start_simulation_~tmp~3#1); 1001#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 974#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 975#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 958#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 959#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1068#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1069#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1141#L585 assume !(0 != start_simulation_~tmp___0~1#1); 1078#L553-2 [2021-12-15 17:20:25,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,137 INFO L85 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2021-12-15 17:20:25,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597711947] [2021-12-15 17:20:25,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,188 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597711947] [2021-12-15 17:20:25,189 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1597711947] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,189 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127439172] [2021-12-15 17:20:25,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,190 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,190 INFO L85 PathProgramCache]: Analyzing trace with hash -1848890247, now seen corresponding path program 1 times [2021-12-15 17:20:25,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445968378] [2021-12-15 17:20:25,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,191 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,229 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445968378] [2021-12-15 17:20:25,230 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445968378] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,230 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,230 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,230 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440019209] [2021-12-15 17:20:25,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,231 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,231 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:25,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:25,232 INFO L87 Difference]: Start difference. First operand 225 states and 334 transitions. cyclomatic complexity: 110 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,345 INFO L93 Difference]: Finished difference Result 362 states and 534 transitions. [2021-12-15 17:20:25,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:25,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 362 states and 534 transitions. [2021-12-15 17:20:25,349 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2021-12-15 17:20:25,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 362 states to 362 states and 534 transitions. [2021-12-15 17:20:25,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 362 [2021-12-15 17:20:25,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 362 [2021-12-15 17:20:25,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 362 states and 534 transitions. [2021-12-15 17:20:25,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,357 INFO L681 BuchiCegarLoop]: Abstraction has 362 states and 534 transitions. [2021-12-15 17:20:25,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states and 534 transitions. [2021-12-15 17:20:25,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 361. [2021-12-15 17:20:25,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 361 states to 361 states and 533 transitions. [2021-12-15 17:20:25,374 INFO L704 BuchiCegarLoop]: Abstraction has 361 states and 533 transitions. [2021-12-15 17:20:25,374 INFO L587 BuchiCegarLoop]: Abstraction has 361 states and 533 transitions. [2021-12-15 17:20:25,374 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:25,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 361 states and 533 transitions. [2021-12-15 17:20:25,376 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2021-12-15 17:20:25,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,378 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,378 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,378 INFO L791 eck$LassoCheckResult]: Stem: 1776#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1749#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1761#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1659#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 1530#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1531#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1716#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1578#L344 assume !(0 == ~M_E~0); 1579#L344-2 assume !(0 == ~T1_E~0); 1743#L349-1 assume !(0 == ~T2_E~0); 1598#L354-1 assume !(0 == ~E_M~0); 1599#L359-1 assume !(0 == ~E_1~0); 1593#L364-1 assume !(0 == ~E_2~0); 1594#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1675#L166 assume 1 == ~m_pc~0; 1676#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1736#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1576#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1577#L425 assume !(0 != activate_threads_~tmp~1#1); 1774#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1685#L185 assume !(1 == ~t1_pc~0); 1604#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1605#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1642#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1647#L433 assume !(0 != activate_threads_~tmp___0~0#1); 1648#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1697#L204 assume 1 == ~t2_pc~0; 1651#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1652#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1718#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1559#L441 assume !(0 != activate_threads_~tmp___1~0#1); 1560#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1679#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 1701#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1826#L387-1 assume !(1 == ~T2_E~0); 1765#L392-1 assume !(1 == ~E_M~0); 1689#L397-1 assume !(1 == ~E_1~0); 1690#L402-1 assume !(1 == ~E_2~0); 1722#L407-1 assume { :end_inline_reset_delta_events } true; 1791#L553-2 [2021-12-15 17:20:25,379 INFO L793 eck$LassoCheckResult]: Loop: 1791#L553-2 assume !false; 1779#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1750#L319 assume !false; 1719#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1720#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1746#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1747#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1663#L286 assume !(0 != eval_~tmp~0#1); 1665#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1777#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1778#L344-3 assume !(0 == ~M_E~0); 1528#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1529#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1583#L354-3 assume !(0 == ~E_M~0); 1584#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1658#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1656#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1638#L166-12 assume 1 == ~m_pc~0; 1639#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1608#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1609#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1632#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1633#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1707#L185-12 assume !(1 == ~t1_pc~0); 1590#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1591#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1873#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1872#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1871#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1870#L204-12 assume 1 == ~t2_pc~0; 1868#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1867#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1866#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1865#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1864#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1863#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1581#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1862#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1861#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1731#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1860#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1859#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1856#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1855#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1854#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1853#L572 assume !(0 == start_simulation_~tmp~3#1); 1601#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1573#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1574#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1557#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1558#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1671#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1672#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1766#L585 assume !(0 != start_simulation_~tmp___0~1#1); 1791#L553-2 [2021-12-15 17:20:25,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,380 INFO L85 PathProgramCache]: Analyzing trace with hash -1712870137, now seen corresponding path program 1 times [2021-12-15 17:20:25,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734191439] [2021-12-15 17:20:25,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,382 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,443 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734191439] [2021-12-15 17:20:25,444 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734191439] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,444 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,444 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:25,446 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380333426] [2021-12-15 17:20:25,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,447 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,448 INFO L85 PathProgramCache]: Analyzing trace with hash 2030596858, now seen corresponding path program 1 times [2021-12-15 17:20:25,448 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093025284] [2021-12-15 17:20:25,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,449 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,505 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093025284] [2021-12-15 17:20:25,506 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093025284] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,506 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,506 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,506 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725070748] [2021-12-15 17:20:25,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,507 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,507 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,508 INFO L87 Difference]: Start difference. First operand 361 states and 533 transitions. cyclomatic complexity: 174 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,560 INFO L93 Difference]: Finished difference Result 660 states and 959 transitions. [2021-12-15 17:20:25,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 660 states and 959 transitions. [2021-12-15 17:20:25,565 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 608 [2021-12-15 17:20:25,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 660 states to 660 states and 959 transitions. [2021-12-15 17:20:25,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 660 [2021-12-15 17:20:25,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 660 [2021-12-15 17:20:25,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 660 states and 959 transitions. [2021-12-15 17:20:25,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,573 INFO L681 BuchiCegarLoop]: Abstraction has 660 states and 959 transitions. [2021-12-15 17:20:25,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 660 states and 959 transitions. [2021-12-15 17:20:25,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 660 to 620. [2021-12-15 17:20:25,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 620 states, 620 states have (on average 1.4596774193548387) internal successors, (905), 619 states have internal predecessors, (905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 620 states to 620 states and 905 transitions. [2021-12-15 17:20:25,591 INFO L704 BuchiCegarLoop]: Abstraction has 620 states and 905 transitions. [2021-12-15 17:20:25,591 INFO L587 BuchiCegarLoop]: Abstraction has 620 states and 905 transitions. [2021-12-15 17:20:25,591 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:25,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 620 states and 905 transitions. [2021-12-15 17:20:25,594 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 568 [2021-12-15 17:20:25,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,595 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,595 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,596 INFO L791 eck$LassoCheckResult]: Stem: 2838#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2797#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2814#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2701#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 2560#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2561#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2764#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2610#L344 assume !(0 == ~M_E~0); 2611#L344-2 assume !(0 == ~T1_E~0); 2793#L349-1 assume !(0 == ~T2_E~0); 2629#L354-1 assume !(0 == ~E_M~0); 2630#L359-1 assume !(0 == ~E_1~0); 2624#L364-1 assume !(0 == ~E_2~0); 2625#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2721#L166 assume !(1 == ~m_pc~0); 2722#L166-2 is_master_triggered_~__retres1~0#1 := 0; 2800#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2608#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2609#L425 assume !(0 != activate_threads_~tmp~1#1); 2828#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2730#L185 assume !(1 == ~t1_pc~0); 2635#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2636#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2676#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2680#L433 assume !(0 != activate_threads_~tmp___0~0#1); 2681#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2746#L204 assume 1 == ~t2_pc~0; 2688#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2689#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2766#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2590#L441 assume !(0 != activate_threads_~tmp___1~0#1); 2591#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2724#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 2753#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2704#L387-1 assume !(1 == ~T2_E~0); 2705#L392-1 assume !(1 == ~E_M~0); 2736#L397-1 assume !(1 == ~E_1~0); 2737#L402-1 assume !(1 == ~E_2~0); 2727#L407-1 assume { :end_inline_reset_delta_events } true; 2728#L553-2 [2021-12-15 17:20:25,596 INFO L793 eck$LassoCheckResult]: Loop: 2728#L553-2 assume !false; 2808#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3076#L319 assume !false; 3075#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2647#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2648#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2633#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2634#L286 assume !(0 != eval_~tmp~0#1); 2617#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2618#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2837#L344-3 assume !(0 == ~M_E~0); 2558#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2559#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2700#L354-3 assume !(0 == ~E_M~0); 2733#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2734#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2695#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2696#L166-12 assume !(1 == ~m_pc~0); 3158#L166-14 is_master_triggered_~__retres1~0#1 := 0; 2641#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2642#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2666#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2667#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2757#L185-12 assume 1 == ~t1_pc~0; 2785#L186-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2622#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2784#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3139#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3138#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3137#L204-12 assume !(1 == ~t2_pc~0); 3136#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 3134#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3133#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3132#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3131#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3130#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2613#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2749#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2750#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2780#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3150#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3149#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3146#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3145#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3143#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2741#L572 assume !(0 == start_simulation_~tmp~3#1); 2632#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2605#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2606#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2702#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3102#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3098#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3093#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2812#L585 assume !(0 != start_simulation_~tmp___0~1#1); 2728#L553-2 [2021-12-15 17:20:25,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,597 INFO L85 PathProgramCache]: Analyzing trace with hash 524493128, now seen corresponding path program 1 times [2021-12-15 17:20:25,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768138212] [2021-12-15 17:20:25,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,598 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768138212] [2021-12-15 17:20:25,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768138212] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,643 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,643 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617546597] [2021-12-15 17:20:25,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,644 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1425243525, now seen corresponding path program 1 times [2021-12-15 17:20:25,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818747186] [2021-12-15 17:20:25,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,699 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818747186] [2021-12-15 17:20:25,700 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818747186] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,700 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,701 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,701 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120716201] [2021-12-15 17:20:25,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,701 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,701 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:25,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:25,702 INFO L87 Difference]: Start difference. First operand 620 states and 905 transitions. cyclomatic complexity: 289 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,790 INFO L93 Difference]: Finished difference Result 1550 states and 2225 transitions. [2021-12-15 17:20:25,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:25,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1550 states and 2225 transitions. [2021-12-15 17:20:25,800 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1460 [2021-12-15 17:20:25,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1550 states to 1550 states and 2225 transitions. [2021-12-15 17:20:25,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1550 [2021-12-15 17:20:25,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1550 [2021-12-15 17:20:25,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1550 states and 2225 transitions. [2021-12-15 17:20:25,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,811 INFO L681 BuchiCegarLoop]: Abstraction has 1550 states and 2225 transitions. [2021-12-15 17:20:25,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1550 states and 2225 transitions. [2021-12-15 17:20:25,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1550 to 1510. [2021-12-15 17:20:25,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1510 states, 1510 states have (on average 1.443046357615894) internal successors, (2179), 1509 states have internal predecessors, (2179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1510 states to 1510 states and 2179 transitions. [2021-12-15 17:20:25,848 INFO L704 BuchiCegarLoop]: Abstraction has 1510 states and 2179 transitions. [2021-12-15 17:20:25,849 INFO L587 BuchiCegarLoop]: Abstraction has 1510 states and 2179 transitions. [2021-12-15 17:20:25,849 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:25,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1510 states and 2179 transitions. [2021-12-15 17:20:25,855 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1444 [2021-12-15 17:20:25,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,858 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,858 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,858 INFO L791 eck$LassoCheckResult]: Stem: 5016#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4972#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4993#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4875#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 4742#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4743#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4939#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4792#L344 assume !(0 == ~M_E~0); 4793#L344-2 assume !(0 == ~T1_E~0); 4968#L349-1 assume !(0 == ~T2_E~0); 4810#L354-1 assume !(0 == ~E_M~0); 4811#L359-1 assume !(0 == ~E_1~0); 4805#L364-1 assume !(0 == ~E_2~0); 4806#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4892#L166 assume !(1 == ~m_pc~0); 4893#L166-2 is_master_triggered_~__retres1~0#1 := 0; 4977#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4790#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4791#L425 assume !(0 != activate_threads_~tmp~1#1); 5009#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4905#L185 assume !(1 == ~t1_pc~0); 4816#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4817#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4857#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4861#L433 assume !(0 != activate_threads_~tmp___0~0#1); 4862#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4921#L204 assume !(1 == ~t2_pc~0); 4903#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4904#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4942#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4772#L441 assume !(0 != activate_threads_~tmp___1~0#1); 4773#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4896#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 4925#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5921#L387-1 assume !(1 == ~T2_E~0); 5920#L392-1 assume !(1 == ~E_M~0); 4995#L397-1 assume !(1 == ~E_1~0); 5919#L402-1 assume !(1 == ~E_2~0); 5918#L407-1 assume { :end_inline_reset_delta_events } true; 5914#L553-2 [2021-12-15 17:20:25,859 INFO L793 eck$LassoCheckResult]: Loop: 5914#L553-2 assume !false; 5913#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5910#L319 assume !false; 5909#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5907#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5905#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5904#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5902#L286 assume !(0 != eval_~tmp~0#1); 5903#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5999#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5997#L344-3 assume !(0 == ~M_E~0); 5995#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5993#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5991#L354-3 assume !(0 == ~E_M~0); 5989#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5987#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5985#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5983#L166-12 assume !(1 == ~m_pc~0); 5981#L166-14 is_master_triggered_~__retres1~0#1 := 0; 5979#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5977#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5975#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5973#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5971#L185-12 assume !(1 == ~t1_pc~0); 5969#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 5968#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5967#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5966#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5965#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5964#L204-12 assume !(1 == ~t2_pc~0); 5962#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 5960#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5958#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5956#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5954#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5952#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5948#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5946#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5944#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5940#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5939#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5938#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5935#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5934#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5933#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5932#L572 assume !(0 == start_simulation_~tmp~3#1); 5930#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5928#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5926#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5925#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5924#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5923#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5922#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5917#L585 assume !(0 != start_simulation_~tmp___0~1#1); 5914#L553-2 [2021-12-15 17:20:25,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,860 INFO L85 PathProgramCache]: Analyzing trace with hash -754831607, now seen corresponding path program 1 times [2021-12-15 17:20:25,860 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657604423] [2021-12-15 17:20:25,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,905 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657604423] [2021-12-15 17:20:25,906 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657604423] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,906 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,906 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:25,907 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858792676] [2021-12-15 17:20:25,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,907 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1098252796, now seen corresponding path program 1 times [2021-12-15 17:20:25,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889752683] [2021-12-15 17:20:25,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,913 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,954 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,955 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889752683] [2021-12-15 17:20:25,956 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889752683] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,957 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,957 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566697427] [2021-12-15 17:20:25,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,958 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,958 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,959 INFO L87 Difference]: Start difference. First operand 1510 states and 2179 transitions. cyclomatic complexity: 677 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,983 INFO L93 Difference]: Finished difference Result 2215 states and 3192 transitions. [2021-12-15 17:20:25,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2215 states and 3192 transitions. [2021-12-15 17:20:25,996 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2142 [2021-12-15 17:20:26,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2215 states to 2215 states and 3192 transitions. [2021-12-15 17:20:26,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2215 [2021-12-15 17:20:26,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2215 [2021-12-15 17:20:26,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2215 states and 3192 transitions. [2021-12-15 17:20:26,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,038 INFO L681 BuchiCegarLoop]: Abstraction has 2215 states and 3192 transitions. [2021-12-15 17:20:26,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2215 states and 3192 transitions. [2021-12-15 17:20:26,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2215 to 1585. [2021-12-15 17:20:26,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1585 states, 1585 states have (on average 1.4435331230283912) internal successors, (2288), 1584 states have internal predecessors, (2288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1585 states to 1585 states and 2288 transitions. [2021-12-15 17:20:26,065 INFO L704 BuchiCegarLoop]: Abstraction has 1585 states and 2288 transitions. [2021-12-15 17:20:26,066 INFO L587 BuchiCegarLoop]: Abstraction has 1585 states and 2288 transitions. [2021-12-15 17:20:26,066 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:26,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1585 states and 2288 transitions. [2021-12-15 17:20:26,072 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1525 [2021-12-15 17:20:26,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,075 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,075 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,075 INFO L791 eck$LassoCheckResult]: Stem: 8757#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8710#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8734#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8613#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 8476#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8477#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8673#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8527#L344 assume !(0 == ~M_E~0); 8528#L344-2 assume !(0 == ~T1_E~0); 8706#L349-1 assume !(0 == ~T2_E~0); 8546#L354-1 assume !(0 == ~E_M~0); 8547#L359-1 assume !(0 == ~E_1~0); 8541#L364-1 assume !(0 == ~E_2~0); 8542#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8629#L166 assume !(1 == ~m_pc~0); 8630#L166-2 is_master_triggered_~__retres1~0#1 := 0; 8715#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8525#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8526#L425 assume !(0 != activate_threads_~tmp~1#1); 8750#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8641#L185 assume !(1 == ~t1_pc~0); 8552#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8553#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8593#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8599#L433 assume !(0 != activate_threads_~tmp___0~0#1); 8600#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8655#L204 assume !(1 == ~t2_pc~0); 8639#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8640#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8676#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8507#L441 assume !(0 != activate_threads_~tmp___1~0#1); 8508#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8633#L382 assume !(1 == ~M_E~0); 8495#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8496#L387-1 assume !(1 == ~T2_E~0); 8616#L392-1 assume !(1 == ~E_M~0); 8646#L397-1 assume !(1 == ~E_1~0); 8647#L402-1 assume !(1 == ~E_2~0); 8636#L407-1 assume { :end_inline_reset_delta_events } true; 8637#L553-2 [2021-12-15 17:20:26,075 INFO L793 eck$LassoCheckResult]: Loop: 8637#L553-2 assume !false; 9392#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9310#L319 assume !false; 9386#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9382#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9378#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9375#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9371#L286 assume !(0 != eval_~tmp~0#1); 9372#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10046#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10044#L344-3 assume !(0 == ~M_E~0); 10041#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10039#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10038#L354-3 assume !(0 == ~E_M~0); 10037#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10036#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10035#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9980#L166-12 assume !(1 == ~m_pc~0); 9979#L166-14 is_master_triggered_~__retres1~0#1 := 0; 9978#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9977#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9975#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9973#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9971#L185-12 assume !(1 == ~t1_pc~0); 9969#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 9967#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9965#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9952#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9948#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9944#L204-12 assume !(1 == ~t2_pc~0); 9940#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 9937#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9934#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9931#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9927#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9923#L382-3 assume !(1 == ~M_E~0); 9156#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9915#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9914#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9913#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9912#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9911#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9674#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9672#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8677#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8648#L572 assume !(0 == start_simulation_~tmp~3#1); 8650#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9405#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9403#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9402#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9401#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9400#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9399#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 9398#L585 assume !(0 != start_simulation_~tmp___0~1#1); 8637#L553-2 [2021-12-15 17:20:26,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2021-12-15 17:20:26,076 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325762045] [2021-12-15 17:20:26,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,077 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,117 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325762045] [2021-12-15 17:20:26,118 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [325762045] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,118 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,118 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:26,118 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [390471403] [2021-12-15 17:20:26,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,119 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:26,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,120 INFO L85 PathProgramCache]: Analyzing trace with hash -590690946, now seen corresponding path program 1 times [2021-12-15 17:20:26,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513454879] [2021-12-15 17:20:26,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,120 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513454879] [2021-12-15 17:20:26,166 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513454879] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,166 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,166 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,166 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838352519] [2021-12-15 17:20:26,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,167 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,167 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:26,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:26,168 INFO L87 Difference]: Start difference. First operand 1585 states and 2288 transitions. cyclomatic complexity: 707 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,225 INFO L93 Difference]: Finished difference Result 2605 states and 3702 transitions. [2021-12-15 17:20:26,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:26,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2605 states and 3702 transitions. [2021-12-15 17:20:26,244 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2505 [2021-12-15 17:20:26,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2605 states to 2605 states and 3702 transitions. [2021-12-15 17:20:26,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2605 [2021-12-15 17:20:26,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2605 [2021-12-15 17:20:26,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2605 states and 3702 transitions. [2021-12-15 17:20:26,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,262 INFO L681 BuchiCegarLoop]: Abstraction has 2605 states and 3702 transitions. [2021-12-15 17:20:26,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2605 states and 3702 transitions. [2021-12-15 17:20:26,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2605 to 1928. [2021-12-15 17:20:26,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.420643153526971) internal successors, (2739), 1927 states have internal predecessors, (2739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2739 transitions. [2021-12-15 17:20:26,315 INFO L704 BuchiCegarLoop]: Abstraction has 1928 states and 2739 transitions. [2021-12-15 17:20:26,315 INFO L587 BuchiCegarLoop]: Abstraction has 1928 states and 2739 transitions. [2021-12-15 17:20:26,315 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:26,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2739 transitions. [2021-12-15 17:20:26,322 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1843 [2021-12-15 17:20:26,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,323 INFO L791 eck$LassoCheckResult]: Stem: 12946#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12896#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12918#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12808#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 12679#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12680#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12869#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12728#L344 assume !(0 == ~M_E~0); 12729#L344-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12915#L349-1 assume !(0 == ~T2_E~0); 12746#L354-1 assume !(0 == ~E_M~0); 12747#L359-1 assume !(0 == ~E_1~0); 12741#L364-1 assume !(0 == ~E_2~0); 12742#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12825#L166 assume !(1 == ~m_pc~0); 12826#L166-2 is_master_triggered_~__retres1~0#1 := 0; 12904#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12726#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12727#L425 assume !(0 != activate_threads_~tmp~1#1); 12964#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12963#L185 assume !(1 == ~t1_pc~0); 12752#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12753#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12789#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12961#L433 assume !(0 != activate_threads_~tmp___0~0#1); 12900#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12852#L204 assume !(1 == ~t2_pc~0); 12835#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12836#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12872#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12941#L441 assume !(0 != activate_threads_~tmp___1~0#1); 12956#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12955#L382 assume !(1 == ~M_E~0); 12954#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12699#L387-1 assume !(1 == ~T2_E~0); 12811#L392-1 assume !(1 == ~E_M~0); 12842#L397-1 assume !(1 == ~E_1~0); 12843#L402-1 assume !(1 == ~E_2~0); 12832#L407-1 assume { :end_inline_reset_delta_events } true; 12833#L553-2 [2021-12-15 17:20:26,323 INFO L793 eck$LassoCheckResult]: Loop: 12833#L553-2 assume !false; 13705#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13701#L319 assume !false; 13699#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13696#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13693#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13691#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13688#L286 assume !(0 != eval_~tmp~0#1); 13686#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13684#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13682#L344-3 assume !(0 == ~M_E~0); 13679#L344-5 assume !(0 == ~T1_E~0); 13680#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13735#L354-3 assume !(0 == ~E_M~0); 13734#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13733#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13727#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13726#L166-12 assume !(1 == ~m_pc~0); 13722#L166-14 is_master_triggered_~__retres1~0#1 := 0; 13720#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13718#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13716#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13714#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13712#L185-12 assume !(1 == ~t1_pc~0); 13709#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 13706#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13702#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13700#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13698#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13694#L204-12 assume !(1 == ~t2_pc~0); 13692#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 13690#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13687#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13685#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13683#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13681#L382-3 assume !(1 == ~M_E~0); 13336#L382-5 assume !(1 == ~T1_E~0); 13654#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13653#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13652#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13651#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13650#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13047#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13043#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13034#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 13027#L572 assume !(0 == start_simulation_~tmp~3#1); 13028#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13724#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13721#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13719#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 13717#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13715#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13713#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 13711#L585 assume !(0 != start_simulation_~tmp___0~1#1); 12833#L553-2 [2021-12-15 17:20:26,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,324 INFO L85 PathProgramCache]: Analyzing trace with hash 318575881, now seen corresponding path program 1 times [2021-12-15 17:20:26,324 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895593164] [2021-12-15 17:20:26,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,344 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895593164] [2021-12-15 17:20:26,344 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895593164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,345 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:26,346 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531569026] [2021-12-15 17:20:26,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,346 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:26,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,347 INFO L85 PathProgramCache]: Analyzing trace with hash 812738366, now seen corresponding path program 1 times [2021-12-15 17:20:26,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236828821] [2021-12-15 17:20:26,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,385 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236828821] [2021-12-15 17:20:26,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236828821] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,387 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,387 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,388 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569763507] [2021-12-15 17:20:26,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,388 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,388 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:26,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:26,389 INFO L87 Difference]: Start difference. First operand 1928 states and 2739 transitions. cyclomatic complexity: 815 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,426 INFO L93 Difference]: Finished difference Result 2257 states and 3198 transitions. [2021-12-15 17:20:26,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:26,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2257 states and 3198 transitions. [2021-12-15 17:20:26,440 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2187 [2021-12-15 17:20:26,450 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2257 states to 2257 states and 3198 transitions. [2021-12-15 17:20:26,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2257 [2021-12-15 17:20:26,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2257 [2021-12-15 17:20:26,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2257 states and 3198 transitions. [2021-12-15 17:20:26,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,455 INFO L681 BuchiCegarLoop]: Abstraction has 2257 states and 3198 transitions. [2021-12-15 17:20:26,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2257 states and 3198 transitions. [2021-12-15 17:20:26,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2257 to 1585. [2021-12-15 17:20:26,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1585 states, 1585 states have (on average 1.4195583596214512) internal successors, (2250), 1584 states have internal predecessors, (2250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1585 states to 1585 states and 2250 transitions. [2021-12-15 17:20:26,485 INFO L704 BuchiCegarLoop]: Abstraction has 1585 states and 2250 transitions. [2021-12-15 17:20:26,485 INFO L587 BuchiCegarLoop]: Abstraction has 1585 states and 2250 transitions. [2021-12-15 17:20:26,485 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:26,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1585 states and 2250 transitions. [2021-12-15 17:20:26,494 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1525 [2021-12-15 17:20:26,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,501 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,502 INFO L791 eck$LassoCheckResult]: Stem: 17132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17091#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17109#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17003#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 16875#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16876#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17066#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16924#L344 assume !(0 == ~M_E~0); 16925#L344-2 assume !(0 == ~T1_E~0); 17086#L349-1 assume !(0 == ~T2_E~0); 16942#L354-1 assume !(0 == ~E_M~0); 16943#L359-1 assume !(0 == ~E_1~0); 16937#L364-1 assume !(0 == ~E_2~0); 16938#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17021#L166 assume !(1 == ~m_pc~0); 17022#L166-2 is_master_triggered_~__retres1~0#1 := 0; 17096#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16922#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16923#L425 assume !(0 != activate_threads_~tmp~1#1); 17128#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17032#L185 assume !(1 == ~t1_pc~0); 16948#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16949#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16985#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16990#L433 assume !(0 != activate_threads_~tmp___0~0#1); 16991#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17049#L204 assume !(1 == ~t2_pc~0); 17030#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17031#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17068#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16905#L441 assume !(0 != activate_threads_~tmp___1~0#1); 16906#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17024#L382 assume !(1 == ~M_E~0); 16894#L382-2 assume !(1 == ~T1_E~0); 16895#L387-1 assume !(1 == ~T2_E~0); 17005#L392-1 assume !(1 == ~E_M~0); 17038#L397-1 assume !(1 == ~E_1~0); 17039#L402-1 assume !(1 == ~E_2~0); 17027#L407-1 assume { :end_inline_reset_delta_events } true; 17028#L553-2 [2021-12-15 17:20:26,502 INFO L793 eck$LassoCheckResult]: Loop: 17028#L553-2 assume !false; 18148#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18144#L319 assume !false; 18142#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18111#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18001#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18000#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17998#L286 assume !(0 != eval_~tmp~0#1); 17946#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17945#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17944#L344-3 assume !(0 == ~M_E~0); 17940#L344-5 assume !(0 == ~T1_E~0); 17938#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17936#L354-3 assume !(0 == ~E_M~0); 17934#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17932#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17413#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17410#L166-12 assume !(1 == ~m_pc~0); 17409#L166-14 is_master_triggered_~__retres1~0#1 := 0; 17408#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17406#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17401#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17398#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17397#L185-12 assume !(1 == ~t1_pc~0); 17393#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17391#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17389#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17387#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17384#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17382#L204-12 assume !(1 == ~t2_pc~0); 17380#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 17379#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17378#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17377#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17376#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17309#L382-3 assume !(1 == ~M_E~0); 17301#L382-5 assume !(1 == ~T1_E~0); 17296#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17291#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17292#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17416#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17414#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17278#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17194#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17186#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 17180#L572 assume !(0 == start_simulation_~tmp~3#1); 17181#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18261#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18247#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18237#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 18232#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18161#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18159#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 18157#L585 assume !(0 != start_simulation_~tmp___0~1#1); 17028#L553-2 [2021-12-15 17:20:26,502 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2021-12-15 17:20:26,503 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,503 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500425407] [2021-12-15 17:20:26,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,503 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,514 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,566 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,567 INFO L85 PathProgramCache]: Analyzing trace with hash 812738366, now seen corresponding path program 2 times [2021-12-15 17:20:26,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345545762] [2021-12-15 17:20:26,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,567 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345545762] [2021-12-15 17:20:26,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345545762] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,591 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,591 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706781963] [2021-12-15 17:20:26,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,591 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,591 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:26,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:26,592 INFO L87 Difference]: Start difference. First operand 1585 states and 2250 transitions. cyclomatic complexity: 669 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,662 INFO L93 Difference]: Finished difference Result 2704 states and 3771 transitions. [2021-12-15 17:20:26,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:26,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2704 states and 3771 transitions. [2021-12-15 17:20:26,674 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2624 [2021-12-15 17:20:26,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2704 states to 2704 states and 3771 transitions. [2021-12-15 17:20:26,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2704 [2021-12-15 17:20:26,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2704 [2021-12-15 17:20:26,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2704 states and 3771 transitions. [2021-12-15 17:20:26,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,691 INFO L681 BuchiCegarLoop]: Abstraction has 2704 states and 3771 transitions. [2021-12-15 17:20:26,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2704 states and 3771 transitions. [2021-12-15 17:20:26,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2704 to 1621. [2021-12-15 17:20:26,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1621 states, 1621 states have (on average 1.4102405922270203) internal successors, (2286), 1620 states have internal predecessors, (2286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1621 states to 1621 states and 2286 transitions. [2021-12-15 17:20:26,719 INFO L704 BuchiCegarLoop]: Abstraction has 1621 states and 2286 transitions. [2021-12-15 17:20:26,719 INFO L587 BuchiCegarLoop]: Abstraction has 1621 states and 2286 transitions. [2021-12-15 17:20:26,719 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:26,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1621 states and 2286 transitions. [2021-12-15 17:20:26,723 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1561 [2021-12-15 17:20:26,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,724 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,724 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,724 INFO L791 eck$LassoCheckResult]: Stem: 21446#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21401#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21419#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21310#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 21180#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21181#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21370#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21231#L344 assume !(0 == ~M_E~0); 21232#L344-2 assume !(0 == ~T1_E~0); 21395#L349-1 assume !(0 == ~T2_E~0); 21249#L354-1 assume !(0 == ~E_M~0); 21250#L359-1 assume !(0 == ~E_1~0); 21244#L364-1 assume !(0 == ~E_2~0); 21245#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21328#L166 assume !(1 == ~m_pc~0); 21329#L166-2 is_master_triggered_~__retres1~0#1 := 0; 21406#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21229#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21230#L425 assume !(0 != activate_threads_~tmp~1#1); 21438#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21339#L185 assume !(1 == ~t1_pc~0); 21255#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21256#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21292#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21297#L433 assume !(0 != activate_threads_~tmp___0~0#1); 21298#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21354#L204 assume !(1 == ~t2_pc~0); 21337#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21338#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21372#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21211#L441 assume !(0 != activate_threads_~tmp___1~0#1); 21212#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21331#L382 assume !(1 == ~M_E~0); 21199#L382-2 assume !(1 == ~T1_E~0); 21200#L387-1 assume !(1 == ~T2_E~0); 21312#L392-1 assume !(1 == ~E_M~0); 21344#L397-1 assume !(1 == ~E_1~0); 21345#L402-1 assume !(1 == ~E_2~0); 21334#L407-1 assume { :end_inline_reset_delta_events } true; 21335#L553-2 [2021-12-15 17:20:26,725 INFO L793 eck$LassoCheckResult]: Loop: 21335#L553-2 assume !false; 21415#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21450#L319 assume !false; 22343#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22342#L254 assume !(0 == ~m_st~0); 22338#L258 assume !(0 == ~t1_st~0); 22333#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 22329#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22321#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22320#L286 assume !(0 != eval_~tmp~0#1); 22313#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22314#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21428#L344-3 assume !(0 == ~M_E~0); 21178#L344-5 assume !(0 == ~T1_E~0); 21179#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21235#L354-3 assume !(0 == ~E_M~0); 21236#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21307#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21306#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21289#L166-12 assume !(1 == ~m_pc~0); 21290#L166-14 is_master_triggered_~__retres1~0#1 := 0; 22426#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22425#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22424#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22423#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22422#L185-12 assume !(1 == ~t1_pc~0); 22421#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 22420#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22419#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22418#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22417#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22416#L204-12 assume !(1 == ~t2_pc~0); 22415#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 22414#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22413#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22412#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22411#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22410#L382-3 assume !(1 == ~M_E~0); 22373#L382-5 assume !(1 == ~T1_E~0); 22409#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22408#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22407#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22406#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22405#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22402#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22400#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22398#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 22244#L572 assume !(0 == start_simulation_~tmp~3#1); 21252#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 21226#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 21227#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 21209#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 21210#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21318#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21319#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21417#L585 assume !(0 != start_simulation_~tmp___0~1#1); 21335#L553-2 [2021-12-15 17:20:26,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2021-12-15 17:20:26,725 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326373591] [2021-12-15 17:20:26,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,726 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,733 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,745 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,746 INFO L85 PathProgramCache]: Analyzing trace with hash -60432105, now seen corresponding path program 1 times [2021-12-15 17:20:26,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119920768] [2021-12-15 17:20:26,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,747 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,812 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,812 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119920768] [2021-12-15 17:20:26,812 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119920768] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,813 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,813 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,813 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [656813059] [2021-12-15 17:20:26,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,813 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,813 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:26,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:26,816 INFO L87 Difference]: Start difference. First operand 1621 states and 2286 transitions. cyclomatic complexity: 669 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,931 INFO L93 Difference]: Finished difference Result 3184 states and 4439 transitions. [2021-12-15 17:20:26,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:26,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3184 states and 4439 transitions. [2021-12-15 17:20:26,944 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3116 [2021-12-15 17:20:26,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3184 states to 3184 states and 4439 transitions. [2021-12-15 17:20:26,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3184 [2021-12-15 17:20:26,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3184 [2021-12-15 17:20:26,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3184 states and 4439 transitions. [2021-12-15 17:20:26,963 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,963 INFO L681 BuchiCegarLoop]: Abstraction has 3184 states and 4439 transitions. [2021-12-15 17:20:26,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3184 states and 4439 transitions. [2021-12-15 17:20:26,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3184 to 1684. [2021-12-15 17:20:26,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1684 states, 1684 states have (on average 1.3853919239904988) internal successors, (2333), 1683 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1684 states to 1684 states and 2333 transitions. [2021-12-15 17:20:26,998 INFO L704 BuchiCegarLoop]: Abstraction has 1684 states and 2333 transitions. [2021-12-15 17:20:26,998 INFO L587 BuchiCegarLoop]: Abstraction has 1684 states and 2333 transitions. [2021-12-15 17:20:26,998 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:26,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1684 states and 2333 transitions. [2021-12-15 17:20:27,002 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1624 [2021-12-15 17:20:27,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:27,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:27,003 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,003 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,003 INFO L791 eck$LassoCheckResult]: Stem: 26271#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 26219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 26220#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26243#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26130#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 25998#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25999#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26188#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26047#L344 assume !(0 == ~M_E~0); 26048#L344-2 assume !(0 == ~T1_E~0); 26214#L349-1 assume !(0 == ~T2_E~0); 26066#L354-1 assume !(0 == ~E_M~0); 26067#L359-1 assume !(0 == ~E_1~0); 26061#L364-1 assume !(0 == ~E_2~0); 26062#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26146#L166 assume !(1 == ~m_pc~0); 26147#L166-2 is_master_triggered_~__retres1~0#1 := 0; 26227#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26045#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26046#L425 assume !(0 != activate_threads_~tmp~1#1); 26260#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26158#L185 assume !(1 == ~t1_pc~0); 26072#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26073#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26111#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26116#L433 assume !(0 != activate_threads_~tmp___0~0#1); 26117#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26173#L204 assume !(1 == ~t2_pc~0); 26156#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26157#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26192#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26028#L441 assume !(0 != activate_threads_~tmp___1~0#1); 26029#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26149#L382 assume !(1 == ~M_E~0); 26017#L382-2 assume !(1 == ~T1_E~0); 26018#L387-1 assume !(1 == ~T2_E~0); 26134#L392-1 assume !(1 == ~E_M~0); 26163#L397-1 assume !(1 == ~E_1~0); 26164#L402-1 assume !(1 == ~E_2~0); 26152#L407-1 assume { :end_inline_reset_delta_events } true; 26153#L553-2 [2021-12-15 17:20:27,004 INFO L793 eck$LassoCheckResult]: Loop: 26153#L553-2 assume !false; 26687#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26685#L319 assume !false; 26684#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26682#L254 assume !(0 == ~m_st~0); 26683#L258 assume !(0 == ~t1_st~0); 26680#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 26681#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26663#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26664#L286 assume !(0 != eval_~tmp~0#1); 26794#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26792#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26790#L344-3 assume !(0 == ~M_E~0); 26788#L344-5 assume !(0 == ~T1_E~0); 26786#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26784#L354-3 assume !(0 == ~E_M~0); 26782#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26780#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26778#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26776#L166-12 assume !(1 == ~m_pc~0); 26774#L166-14 is_master_triggered_~__retres1~0#1 := 0; 26772#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26768#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26765#L425-12 assume !(0 != activate_threads_~tmp~1#1); 26763#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26760#L185-12 assume !(1 == ~t1_pc~0); 26757#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 26754#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26751#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26748#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26745#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26742#L204-12 assume !(1 == ~t2_pc~0); 26739#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 26736#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26733#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26730#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26727#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26724#L382-3 assume !(1 == ~M_E~0); 26720#L382-5 assume !(1 == ~T1_E~0); 26718#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26716#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26714#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26711#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26709#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26705#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26703#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26701#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 26699#L572 assume !(0 == start_simulation_~tmp~3#1); 26697#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 26695#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 26693#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26692#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 26691#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26690#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26689#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 26688#L585 assume !(0 != start_simulation_~tmp___0~1#1); 26153#L553-2 [2021-12-15 17:20:27,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,004 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2021-12-15 17:20:27,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840398913] [2021-12-15 17:20:27,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,011 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:27,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,036 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:27,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,037 INFO L85 PathProgramCache]: Analyzing trace with hash -132818663, now seen corresponding path program 1 times [2021-12-15 17:20:27,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485894047] [2021-12-15 17:20:27,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:27,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:27,058 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:27,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485894047] [2021-12-15 17:20:27,058 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485894047] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:27,058 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:27,058 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:27,058 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172949465] [2021-12-15 17:20:27,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:27,059 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:27,059 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:27,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:27,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:27,060 INFO L87 Difference]: Start difference. First operand 1684 states and 2333 transitions. cyclomatic complexity: 653 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:27,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:27,098 INFO L93 Difference]: Finished difference Result 2463 states and 3349 transitions. [2021-12-15 17:20:27,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:27,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2463 states and 3349 transitions. [2021-12-15 17:20:27,106 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2401 [2021-12-15 17:20:27,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2463 states to 2463 states and 3349 transitions. [2021-12-15 17:20:27,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2463 [2021-12-15 17:20:27,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2463 [2021-12-15 17:20:27,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2463 states and 3349 transitions. [2021-12-15 17:20:27,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:27,121 INFO L681 BuchiCegarLoop]: Abstraction has 2463 states and 3349 transitions. [2021-12-15 17:20:27,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2463 states and 3349 transitions. [2021-12-15 17:20:27,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2463 to 2373. [2021-12-15 17:20:27,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2373 states, 2373 states have (on average 1.3632532659081331) internal successors, (3235), 2372 states have internal predecessors, (3235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:27,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2373 states to 2373 states and 3235 transitions. [2021-12-15 17:20:27,158 INFO L704 BuchiCegarLoop]: Abstraction has 2373 states and 3235 transitions. [2021-12-15 17:20:27,158 INFO L587 BuchiCegarLoop]: Abstraction has 2373 states and 3235 transitions. [2021-12-15 17:20:27,159 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:27,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2373 states and 3235 transitions. [2021-12-15 17:20:27,164 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2311 [2021-12-15 17:20:27,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:27,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:27,165 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,165 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,166 INFO L791 eck$LassoCheckResult]: Stem: 30429#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 30381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 30382#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30405#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30282#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 30151#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30152#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30347#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30200#L344 assume !(0 == ~M_E~0); 30201#L344-2 assume !(0 == ~T1_E~0); 30376#L349-1 assume !(0 == ~T2_E~0); 30219#L354-1 assume !(0 == ~E_M~0); 30220#L359-1 assume !(0 == ~E_1~0); 30214#L364-1 assume !(0 == ~E_2~0); 30215#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30302#L166 assume !(1 == ~m_pc~0); 30303#L166-2 is_master_triggered_~__retres1~0#1 := 0; 30386#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30198#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 30199#L425 assume !(0 != activate_threads_~tmp~1#1); 30419#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30313#L185 assume !(1 == ~t1_pc~0); 30225#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30226#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30264#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30269#L433 assume !(0 != activate_threads_~tmp___0~0#1); 30270#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30328#L204 assume !(1 == ~t2_pc~0); 30311#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30312#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30350#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30182#L441 assume !(0 != activate_threads_~tmp___1~0#1); 30183#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30305#L382 assume !(1 == ~M_E~0); 30171#L382-2 assume !(1 == ~T1_E~0); 30172#L387-1 assume !(1 == ~T2_E~0); 30285#L392-1 assume !(1 == ~E_M~0); 30318#L397-1 assume !(1 == ~E_1~0); 30319#L402-1 assume !(1 == ~E_2~0); 30308#L407-1 assume { :end_inline_reset_delta_events } true; 30309#L553-2 assume !false; 31970#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31966#L319 [2021-12-15 17:20:27,166 INFO L793 eck$LassoCheckResult]: Loop: 31966#L319 assume !false; 31964#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31961#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31960#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31956#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31953#L286 assume 0 != eval_~tmp~0#1; 31951#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 30329#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 30330#L291 assume !(0 == ~t1_st~0); 31969#L305 assume !(0 == ~t2_st~0); 31966#L319 [2021-12-15 17:20:27,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,167 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 1 times [2021-12-15 17:20:27,167 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187052760] [2021-12-15 17:20:27,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,167 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,173 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:27,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,180 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:27,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,181 INFO L85 PathProgramCache]: Analyzing trace with hash 698755222, now seen corresponding path program 1 times [2021-12-15 17:20:27,181 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,181 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546200576] [2021-12-15 17:20:27,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,182 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,184 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:27,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,187 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:27,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1780390720, now seen corresponding path program 1 times [2021-12-15 17:20:27,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067027617] [2021-12-15 17:20:27,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:27,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:27,206 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:27,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067027617] [2021-12-15 17:20:27,207 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067027617] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:27,207 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:27,207 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:27,207 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [628215023] [2021-12-15 17:20:27,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:27,257 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:27,261 INFO L158 Benchmark]: Toolchain (without parser) took 3796.65ms. Allocated memory was 102.8MB in the beginning and 169.9MB in the end (delta: 67.1MB). Free memory was 74.3MB in the beginning and 75.0MB in the end (delta: -686.0kB). Peak memory consumption was 68.3MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,261 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 79.7MB. Free memory is still 46.8MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:27,261 INFO L158 Benchmark]: CACSL2BoogieTranslator took 224.21ms. Allocated memory is still 102.8MB. Free memory was 74.1MB in the beginning and 61.0MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,262 INFO L158 Benchmark]: Boogie Procedure Inliner took 49.80ms. Allocated memory is still 102.8MB. Free memory was 61.0MB in the beginning and 58.0MB in the end (delta: 3.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,262 INFO L158 Benchmark]: Boogie Preprocessor took 32.09ms. Allocated memory is still 102.8MB. Free memory was 58.0MB in the beginning and 55.7MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,262 INFO L158 Benchmark]: RCFGBuilder took 568.09ms. Allocated memory is still 102.8MB. Free memory was 55.5MB in the beginning and 31.7MB in the end (delta: 23.8MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,263 INFO L158 Benchmark]: BuchiAutomizer took 2918.19ms. Allocated memory was 102.8MB in the beginning and 169.9MB in the end (delta: 67.1MB). Free memory was 31.5MB in the beginning and 75.0MB in the end (delta: -43.4MB). Peak memory consumption was 26.3MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,264 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 79.7MB. Free memory is still 46.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 224.21ms. Allocated memory is still 102.8MB. Free memory was 74.1MB in the beginning and 61.0MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 49.80ms. Allocated memory is still 102.8MB. Free memory was 61.0MB in the beginning and 58.0MB in the end (delta: 3.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 32.09ms. Allocated memory is still 102.8MB. Free memory was 58.0MB in the beginning and 55.7MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 568.09ms. Allocated memory is still 102.8MB. Free memory was 55.5MB in the beginning and 31.7MB in the end (delta: 23.8MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 2918.19ms. Allocated memory was 102.8MB in the beginning and 169.9MB in the end (delta: 67.1MB). Free memory was 31.5MB in the beginning and 75.0MB in the end (delta: -43.4MB). Peak memory consumption was 26.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:27,290 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable