./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.02.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.02.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc8487f898950b83c481f83a71342af68752fb6e7598d76df123761c32c89f72 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:22,119 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:22,121 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:22,157 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:22,158 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:22,160 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:22,162 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:22,166 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:22,167 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:22,170 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:22,171 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:22,172 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:22,172 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:22,174 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:22,175 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:22,179 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:22,180 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:22,180 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:22,183 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:22,187 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:22,188 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:22,189 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:22,190 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:22,191 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:22,195 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:22,196 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:22,196 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:22,197 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:22,197 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:22,197 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:22,198 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:22,198 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:22,199 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:22,199 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:22,200 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:22,200 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:22,200 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:22,200 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:22,201 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:22,201 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:22,202 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:22,204 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:22,223 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:22,223 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:22,224 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:22,224 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:22,225 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:22,225 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:22,225 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:22,226 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:22,226 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:22,226 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:22,226 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:22,227 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:22,227 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:22,227 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:22,227 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:22,227 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:22,227 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:22,228 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:22,228 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:22,228 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:22,228 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:22,229 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:22,229 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:22,229 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:22,229 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:22,229 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:22,229 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:22,229 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:22,230 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:22,230 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:22,230 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:22,230 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:22,231 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:22,231 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc8487f898950b83c481f83a71342af68752fb6e7598d76df123761c32c89f72 [2021-12-15 17:20:22,440 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:22,466 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:22,468 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:22,469 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:22,469 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:22,470 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2021-12-15 17:20:22,543 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/08724c523/9ad786c1c6e247b88315db29fe837ff6/FLAG94e3aa4a0 [2021-12-15 17:20:22,834 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:22,834 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2021-12-15 17:20:22,841 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/08724c523/9ad786c1c6e247b88315db29fe837ff6/FLAG94e3aa4a0 [2021-12-15 17:20:23,262 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/08724c523/9ad786c1c6e247b88315db29fe837ff6 [2021-12-15 17:20:23,264 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:23,264 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:23,265 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:23,266 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:23,277 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:23,277 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,278 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3da7f312 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23, skipping insertion in model container [2021-12-15 17:20:23,278 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,283 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:23,306 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:23,408 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[671,684] [2021-12-15 17:20:23,438 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:23,445 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:23,452 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-2.c[671,684] [2021-12-15 17:20:23,471 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:23,481 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:23,481 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23 WrapperNode [2021-12-15 17:20:23,482 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:23,482 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:23,483 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:23,483 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:23,489 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,495 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,521 INFO L137 Inliner]: procedures = 32, calls = 38, calls flagged for inlining = 33, calls inlined = 50, statements flattened = 606 [2021-12-15 17:20:23,524 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:23,527 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:23,527 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:23,527 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:23,534 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,534 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,536 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,541 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,548 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,560 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,561 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,564 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:23,567 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:23,567 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:23,567 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:23,568 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,581 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:23,590 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:23,602 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:23,631 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:23,646 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:23,647 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:23,647 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:23,647 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:23,725 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:23,727 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:24,169 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:24,176 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:24,179 INFO L301 CfgBuilder]: Removed 5 assume(true) statements. [2021-12-15 17:20:24,181 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:24 BoogieIcfgContainer [2021-12-15 17:20:24,181 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:24,182 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:24,182 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:24,185 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:24,185 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,186 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:23" (1/3) ... [2021-12-15 17:20:24,186 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3f2d7033 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:24, skipping insertion in model container [2021-12-15 17:20:24,187 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,187 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (2/3) ... [2021-12-15 17:20:24,187 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3f2d7033 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:24, skipping insertion in model container [2021-12-15 17:20:24,187 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,187 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:24" (3/3) ... [2021-12-15 17:20:24,188 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-2.c [2021-12-15 17:20:24,222 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:24,222 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:24,222 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:24,223 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:24,223 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:24,223 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:24,223 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:24,223 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:24,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 191 [2021-12-15 17:20:24,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,297 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,297 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,297 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:24,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 191 [2021-12-15 17:20:24,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,315 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,315 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,321 INFO L791 eck$LassoCheckResult]: Stem: 227#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 151#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 153#L528true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162#L236true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180#L243true assume !(1 == ~m_i~0);~m_st~0 := 2; 110#L243-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 177#L248-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 16#L253-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 192#L356true assume !(0 == ~M_E~0); 68#L356-2true assume !(0 == ~T1_E~0); 134#L361-1true assume !(0 == ~T2_E~0); 132#L366-1true assume 0 == ~E_M~0;~E_M~0 := 1; 126#L371-1true assume !(0 == ~E_1~0); 49#L376-1true assume !(0 == ~E_2~0); 84#L381-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19#L178true assume 1 == ~m_pc~0; 232#L179true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 70#L189true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163#L190true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 118#L437true assume !(0 != activate_threads_~tmp~1#1); 29#L437-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57#L197true assume !(1 == ~t1_pc~0); 209#L197-2true is_transmit1_triggered_~__retres1~1#1 := 0; 211#L208true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 217#L209true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26#L445true assume !(0 != activate_threads_~tmp___0~0#1); 189#L445-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210#L216true assume 1 == ~t2_pc~0; 15#L217true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79#L227true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69#L228true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 154#L453true assume !(0 != activate_threads_~tmp___1~0#1); 125#L453-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129#L394true assume !(1 == ~M_E~0); 205#L394-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 101#L399-1true assume !(1 == ~T2_E~0); 221#L404-1true assume !(1 == ~E_M~0); 38#L409-1true assume !(1 == ~E_1~0); 160#L414-1true assume !(1 == ~E_2~0); 103#L419-1true assume { :end_inline_reset_delta_events } true; 164#L565-2true [2021-12-15 17:20:24,326 INFO L793 eck$LassoCheckResult]: Loop: 164#L565-2true assume !false; 92#L566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124#L331true assume !true; 33#L346true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108#L236-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 185#L356-3true assume !(0 == ~M_E~0); 148#L356-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 120#L361-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 172#L366-3true assume 0 == ~E_M~0;~E_M~0 := 1; 146#L371-3true assume 0 == ~E_1~0;~E_1~0 := 1; 85#L376-3true assume 0 == ~E_2~0;~E_2~0 := 1; 119#L381-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83#L178-12true assume !(1 == ~m_pc~0); 4#L178-14true is_master_triggered_~__retres1~0#1 := 0; 102#L189-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144#L190-4true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 190#L437-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L437-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141#L197-12true assume !(1 == ~t1_pc~0); 179#L197-14true is_transmit1_triggered_~__retres1~1#1 := 0; 42#L208-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216#L209-4true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3#L445-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50#L445-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40#L216-12true assume !(1 == ~t2_pc~0); 107#L216-14true is_transmit2_triggered_~__retres1~2#1 := 0; 64#L227-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22#L228-4true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35#L453-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 184#L453-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 239#L394-3true assume 1 == ~M_E~0;~M_E~0 := 2; 213#L394-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 13#L399-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 233#L404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 60#L409-3true assume 1 == ~E_1~0;~E_1~0 := 2; 183#L414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 166#L419-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 139#L266-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 55#L283-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#L284-1true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 159#L584true assume !(0 == start_simulation_~tmp~3#1); 105#L584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 112#L266-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 130#L283-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 138#L284-2true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 41#L539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25#L546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 149#L547true start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 95#L597true assume !(0 != start_simulation_~tmp___0~1#1); 164#L565-2true [2021-12-15 17:20:24,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,331 INFO L85 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2021-12-15 17:20:24,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113236033] [2021-12-15 17:20:24,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,345 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,496 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113236033] [2021-12-15 17:20:24,498 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113236033] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,498 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944446487] [2021-12-15 17:20:24,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,511 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:24,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,513 INFO L85 PathProgramCache]: Analyzing trace with hash -2092676298, now seen corresponding path program 1 times [2021-12-15 17:20:24,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458528067] [2021-12-15 17:20:24,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,542 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458528067] [2021-12-15 17:20:24,543 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458528067] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,543 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,543 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:24,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113750906] [2021-12-15 17:20:24,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,545 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,546 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,572 INFO L87 Difference]: Start difference. First operand has 238 states, 237 states have (on average 1.540084388185654) internal successors, (365), 237 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,611 INFO L93 Difference]: Finished difference Result 236 states and 350 transitions. [2021-12-15 17:20:24,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236 states and 350 transitions. [2021-12-15 17:20:24,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-12-15 17:20:24,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236 states to 230 states and 344 transitions. [2021-12-15 17:20:24,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2021-12-15 17:20:24,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2021-12-15 17:20:24,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 344 transitions. [2021-12-15 17:20:24,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,629 INFO L681 BuchiCegarLoop]: Abstraction has 230 states and 344 transitions. [2021-12-15 17:20:24,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 344 transitions. [2021-12-15 17:20:24,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2021-12-15 17:20:24,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.4956521739130435) internal successors, (344), 229 states have internal predecessors, (344), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 344 transitions. [2021-12-15 17:20:24,667 INFO L704 BuchiCegarLoop]: Abstraction has 230 states and 344 transitions. [2021-12-15 17:20:24,667 INFO L587 BuchiCegarLoop]: Abstraction has 230 states and 344 transitions. [2021-12-15 17:20:24,668 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:24,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 344 transitions. [2021-12-15 17:20:24,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-12-15 17:20:24,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,672 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,672 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,673 INFO L791 eck$LassoCheckResult]: Stem: 712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 688#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 690#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 696#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 647#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 648#L248-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 513#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 514#L356 assume !(0 == ~M_E~0); 605#L356-2 assume !(0 == ~T1_E~0); 606#L361-1 assume !(0 == ~T2_E~0); 671#L366-1 assume 0 == ~E_M~0;~E_M~0 := 1; 665#L371-1 assume !(0 == ~E_1~0); 580#L376-1 assume !(0 == ~E_2~0); 581#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517#L178 assume 1 == ~m_pc~0; 518#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 609#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 610#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 657#L437 assume !(0 != activate_threads_~tmp~1#1); 542#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 543#L197 assume !(1 == ~t1_pc~0); 589#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 588#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 710#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 535#L445 assume !(0 != activate_threads_~tmp___0~0#1); 536#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 706#L216 assume 1 == ~t2_pc~0; 510#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 511#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 608#L453 assume !(0 != activate_threads_~tmp___1~0#1); 663#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 664#L394 assume !(1 == ~M_E~0); 669#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 637#L399-1 assume !(1 == ~T2_E~0); 638#L404-1 assume !(1 == ~E_M~0); 560#L409-1 assume !(1 == ~E_1~0); 561#L414-1 assume !(1 == ~E_2~0); 640#L419-1 assume { :end_inline_reset_delta_events } true; 633#L565-2 [2021-12-15 17:20:24,673 INFO L793 eck$LassoCheckResult]: Loop: 633#L565-2 assume !false; 629#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 521#L331 assume !false; 631#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 492#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 488#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 578#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 579#L298 assume !(0 != eval_~tmp~0#1); 550#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 551#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 644#L356-3 assume !(0 == ~M_E~0); 686#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 658#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 659#L366-3 assume 0 == ~E_M~0;~E_M~0 := 1; 683#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 621#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 622#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 620#L178-12 assume !(1 == ~m_pc~0); 485#L178-14 is_master_triggered_~__retres1~0#1 := 0; 486#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 639#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 682#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 627#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 628#L197-12 assume !(1 == ~t1_pc~0); 676#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 566#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 483#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 484#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 562#L216-12 assume 1 == ~t2_pc~0; 563#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 600#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 526#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 527#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 555#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 705#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 711#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 506#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 507#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 594#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 595#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 699#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 675#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 496#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 558#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 559#L584 assume !(0 == start_simulation_~tmp~3#1); 583#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 642#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 650#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 670#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 565#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 533#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 534#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 632#L597 assume !(0 != start_simulation_~tmp___0~1#1); 633#L565-2 [2021-12-15 17:20:24,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,674 INFO L85 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2021-12-15 17:20:24,674 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394484629] [2021-12-15 17:20:24,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,675 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394484629] [2021-12-15 17:20:24,711 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394484629] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,711 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,712 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,712 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946095456] [2021-12-15 17:20:24,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,712 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:24,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,713 INFO L85 PathProgramCache]: Analyzing trace with hash 175779481, now seen corresponding path program 1 times [2021-12-15 17:20:24,713 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404448857] [2021-12-15 17:20:24,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,713 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,781 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404448857] [2021-12-15 17:20:24,781 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404448857] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,782 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,782 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:24,782 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895111899] [2021-12-15 17:20:24,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,783 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,783 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,784 INFO L87 Difference]: Start difference. First operand 230 states and 344 transitions. cyclomatic complexity: 115 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,795 INFO L93 Difference]: Finished difference Result 230 states and 343 transitions. [2021-12-15 17:20:24,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:24,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 343 transitions. [2021-12-15 17:20:24,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-12-15 17:20:24,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 230 states and 343 transitions. [2021-12-15 17:20:24,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230 [2021-12-15 17:20:24,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230 [2021-12-15 17:20:24,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230 states and 343 transitions. [2021-12-15 17:20:24,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,805 INFO L681 BuchiCegarLoop]: Abstraction has 230 states and 343 transitions. [2021-12-15 17:20:24,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states and 343 transitions. [2021-12-15 17:20:24,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 230. [2021-12-15 17:20:24,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 230 states have (on average 1.491304347826087) internal successors, (343), 229 states have internal predecessors, (343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 343 transitions. [2021-12-15 17:20:24,818 INFO L704 BuchiCegarLoop]: Abstraction has 230 states and 343 transitions. [2021-12-15 17:20:24,818 INFO L587 BuchiCegarLoop]: Abstraction has 230 states and 343 transitions. [2021-12-15 17:20:24,818 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:24,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 343 transitions. [2021-12-15 17:20:24,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 187 [2021-12-15 17:20:24,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,820 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,820 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,821 INFO L791 eck$LassoCheckResult]: Stem: 1181#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1157#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1159#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1165#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 1116#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1117#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 982#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 983#L356 assume !(0 == ~M_E~0); 1074#L356-2 assume !(0 == ~T1_E~0); 1075#L361-1 assume !(0 == ~T2_E~0); 1140#L366-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1134#L371-1 assume !(0 == ~E_1~0); 1049#L376-1 assume !(0 == ~E_2~0); 1050#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 986#L178 assume 1 == ~m_pc~0; 987#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1078#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1079#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1126#L437 assume !(0 != activate_threads_~tmp~1#1); 1011#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1012#L197 assume !(1 == ~t1_pc~0); 1058#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1057#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1179#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1004#L445 assume !(0 != activate_threads_~tmp___0~0#1); 1005#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1175#L216 assume 1 == ~t2_pc~0; 979#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 980#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1076#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1077#L453 assume !(0 != activate_threads_~tmp___1~0#1); 1132#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1133#L394 assume !(1 == ~M_E~0); 1138#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1106#L399-1 assume !(1 == ~T2_E~0); 1107#L404-1 assume !(1 == ~E_M~0); 1029#L409-1 assume !(1 == ~E_1~0); 1030#L414-1 assume !(1 == ~E_2~0); 1109#L419-1 assume { :end_inline_reset_delta_events } true; 1102#L565-2 [2021-12-15 17:20:24,822 INFO L793 eck$LassoCheckResult]: Loop: 1102#L565-2 assume !false; 1098#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 990#L331 assume !false; 1100#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 961#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 957#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1047#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1048#L298 assume !(0 != eval_~tmp~0#1); 1019#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1020#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1113#L356-3 assume !(0 == ~M_E~0); 1155#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1127#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1128#L366-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1152#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1090#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1091#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1089#L178-12 assume 1 == ~m_pc~0; 1059#L179-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 955#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1108#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1151#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1096#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1097#L197-12 assume !(1 == ~t1_pc~0); 1145#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1035#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1036#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 952#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 953#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1031#L216-12 assume 1 == ~t2_pc~0; 1032#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1069#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 996#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1024#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1174#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1180#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 975#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 976#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1063#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1064#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1168#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1144#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 965#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1027#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1028#L584 assume !(0 == start_simulation_~tmp~3#1); 1052#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1111#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1119#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1139#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1034#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1002#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1003#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1101#L597 assume !(0 != start_simulation_~tmp___0~1#1); 1102#L565-2 [2021-12-15 17:20:24,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,823 INFO L85 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2021-12-15 17:20:24,823 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747745794] [2021-12-15 17:20:24,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,824 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747745794] [2021-12-15 17:20:24,854 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747745794] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,854 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054169800] [2021-12-15 17:20:24,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,855 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:24,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,855 INFO L85 PathProgramCache]: Analyzing trace with hash -949480488, now seen corresponding path program 1 times [2021-12-15 17:20:24,855 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,855 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234611303] [2021-12-15 17:20:24,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,856 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234611303] [2021-12-15 17:20:24,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1234611303] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:24,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219413190] [2021-12-15 17:20:24,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,895 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,895 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:24,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:24,896 INFO L87 Difference]: Start difference. First operand 230 states and 343 transitions. cyclomatic complexity: 114 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:24,982 INFO L93 Difference]: Finished difference Result 372 states and 552 transitions. [2021-12-15 17:20:24,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:24,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 372 states and 552 transitions. [2021-12-15 17:20:24,985 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 322 [2021-12-15 17:20:24,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 372 states to 372 states and 552 transitions. [2021-12-15 17:20:24,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 372 [2021-12-15 17:20:24,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 372 [2021-12-15 17:20:24,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 372 states and 552 transitions. [2021-12-15 17:20:24,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:24,988 INFO L681 BuchiCegarLoop]: Abstraction has 372 states and 552 transitions. [2021-12-15 17:20:24,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 372 states and 552 transitions. [2021-12-15 17:20:24,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 372 to 371. [2021-12-15 17:20:24,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 371 states, 371 states have (on average 1.4851752021563343) internal successors, (551), 370 states have internal predecessors, (551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 371 states to 371 states and 551 transitions. [2021-12-15 17:20:24,995 INFO L704 BuchiCegarLoop]: Abstraction has 371 states and 551 transitions. [2021-12-15 17:20:24,995 INFO L587 BuchiCegarLoop]: Abstraction has 371 states and 551 transitions. [2021-12-15 17:20:24,995 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:24,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 371 states and 551 transitions. [2021-12-15 17:20:24,996 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 322 [2021-12-15 17:20:24,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,997 INFO L791 eck$LassoCheckResult]: Stem: 1800#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1774#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1776#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1782#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 1730#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1731#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1596#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1597#L356 assume !(0 == ~M_E~0); 1688#L356-2 assume !(0 == ~T1_E~0); 1689#L361-1 assume !(0 == ~T2_E~0); 1756#L366-1 assume !(0 == ~E_M~0); 1749#L371-1 assume !(0 == ~E_1~0); 1663#L376-1 assume !(0 == ~E_2~0); 1664#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1600#L178 assume 1 == ~m_pc~0; 1601#L179 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1692#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1693#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1741#L437 assume !(0 != activate_threads_~tmp~1#1); 1625#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1626#L197 assume !(1 == ~t1_pc~0); 1672#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1671#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1798#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1618#L445 assume !(0 != activate_threads_~tmp___0~0#1); 1619#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1794#L216 assume 1 == ~t2_pc~0; 1593#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1594#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1690#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1691#L453 assume !(0 != activate_threads_~tmp___1~0#1); 1747#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1748#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 1753#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1720#L399-1 assume !(1 == ~T2_E~0); 1721#L404-1 assume !(1 == ~E_M~0); 1643#L409-1 assume !(1 == ~E_1~0); 1644#L414-1 assume !(1 == ~E_2~0); 1723#L419-1 assume { :end_inline_reset_delta_events } true; 1716#L565-2 [2021-12-15 17:20:24,998 INFO L793 eck$LassoCheckResult]: Loop: 1716#L565-2 assume !false; 1712#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1604#L331 assume !false; 1714#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1575#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1571#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1661#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1662#L298 assume !(0 != eval_~tmp~0#1); 1633#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1634#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1727#L356-3 assume !(0 == ~M_E~0); 1772#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1742#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1743#L366-3 assume !(0 == ~E_M~0); 1769#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1704#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1705#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1703#L178-12 assume !(1 == ~m_pc~0); 1568#L178-14 is_master_triggered_~__retres1~0#1 := 0; 1569#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1722#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1768#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1710#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1711#L197-12 assume !(1 == ~t1_pc~0); 1762#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1649#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1650#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1566#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1567#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1646#L216-12 assume !(1 == ~t2_pc~0); 1648#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1683#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1609#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1610#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1638#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1791#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1799#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1589#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1590#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1677#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1678#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1785#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1760#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1579#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1641#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1642#L584 assume !(0 == start_simulation_~tmp~3#1); 1666#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1725#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1733#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1755#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1645#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1613#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1614#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1715#L597 assume !(0 != start_simulation_~tmp___0~1#1); 1716#L565-2 [2021-12-15 17:20:24,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,998 INFO L85 PathProgramCache]: Analyzing trace with hash -1712870137, now seen corresponding path program 1 times [2021-12-15 17:20:24,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288980800] [2021-12-15 17:20:24,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,998 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,017 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288980800] [2021-12-15 17:20:25,018 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288980800] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,018 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,018 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:25,018 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632561923] [2021-12-15 17:20:25,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,018 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1458177828, now seen corresponding path program 1 times [2021-12-15 17:20:25,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632937250] [2021-12-15 17:20:25,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,045 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632937250] [2021-12-15 17:20:25,045 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632937250] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,045 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,046 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,046 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168932987] [2021-12-15 17:20:25,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,046 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,046 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,047 INFO L87 Difference]: Start difference. First operand 371 states and 551 transitions. cyclomatic complexity: 182 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,076 INFO L93 Difference]: Finished difference Result 670 states and 977 transitions. [2021-12-15 17:20:25,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 670 states and 977 transitions. [2021-12-15 17:20:25,080 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 618 [2021-12-15 17:20:25,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 670 states to 670 states and 977 transitions. [2021-12-15 17:20:25,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 670 [2021-12-15 17:20:25,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 670 [2021-12-15 17:20:25,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 670 states and 977 transitions. [2021-12-15 17:20:25,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,084 INFO L681 BuchiCegarLoop]: Abstraction has 670 states and 977 transitions. [2021-12-15 17:20:25,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 670 states and 977 transitions. [2021-12-15 17:20:25,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 670 to 630. [2021-12-15 17:20:25,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 630 states, 630 states have (on average 1.465079365079365) internal successors, (923), 629 states have internal predecessors, (923), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 630 states to 630 states and 923 transitions. [2021-12-15 17:20:25,092 INFO L704 BuchiCegarLoop]: Abstraction has 630 states and 923 transitions. [2021-12-15 17:20:25,092 INFO L587 BuchiCegarLoop]: Abstraction has 630 states and 923 transitions. [2021-12-15 17:20:25,092 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:25,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 630 states and 923 transitions. [2021-12-15 17:20:25,094 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 578 [2021-12-15 17:20:25,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,095 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,095 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,095 INFO L791 eck$LassoCheckResult]: Stem: 2914#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2859#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2861#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2869#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 2803#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2804#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2646#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2647#L356 assume !(0 == ~M_E~0); 2745#L356-2 assume !(0 == ~T1_E~0); 2746#L361-1 assume !(0 == ~T2_E~0); 2832#L366-1 assume !(0 == ~E_M~0); 2823#L371-1 assume !(0 == ~E_1~0); 2711#L376-1 assume !(0 == ~E_2~0); 2712#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2650#L178 assume !(1 == ~m_pc~0); 2651#L178-2 is_master_triggered_~__retres1~0#1 := 0; 2750#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2751#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2809#L437 assume !(0 != activate_threads_~tmp~1#1); 2671#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2672#L197 assume !(1 == ~t1_pc~0); 2723#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2722#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2908#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2667#L445 assume !(0 != activate_threads_~tmp___0~0#1); 2668#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2892#L216 assume 1 == ~t2_pc~0; 2643#L217 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2644#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2747#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2748#L453 assume !(0 != activate_threads_~tmp___1~0#1); 2821#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2822#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 2827#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2903#L399-1 assume !(1 == ~T2_E~0); 3208#L404-1 assume !(1 == ~E_M~0); 2911#L409-1 assume !(1 == ~E_1~0); 3206#L414-1 assume !(1 == ~E_2~0); 2787#L419-1 assume { :end_inline_reset_delta_events } true; 2779#L565-2 [2021-12-15 17:20:25,095 INFO L793 eck$LassoCheckResult]: Loop: 2779#L565-2 assume !false; 2870#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2819#L331 assume !false; 2820#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2625#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2621#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2899#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2951#L298 assume !(0 != eval_~tmp~0#1); 2953#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2797#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2798#L356-3 assume !(0 == ~M_E~0); 2854#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2855#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2879#L366-3 assume !(0 == ~E_M~0); 2880#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2762#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2763#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2760#L178-12 assume !(1 == ~m_pc~0); 2761#L178-14 is_master_triggered_~__retres1~0#1 := 0; 3245#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2848#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2849#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2770#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2771#L197-12 assume !(1 == ~t1_pc~0); 2842#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 2857#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3239#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3238#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2713#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2714#L216-12 assume 1 == ~t2_pc~0; 2915#L217-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2738#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2739#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3236#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2886#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2887#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2920#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3235#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2916#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2917#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2885#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2873#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2874#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2724#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2725#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2865#L584 assume !(0 == start_simulation_~tmp~3#1); 2716#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2800#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2801#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2836#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2837#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3209#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3207#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2778#L597 assume !(0 != start_simulation_~tmp___0~1#1); 2779#L565-2 [2021-12-15 17:20:25,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,096 INFO L85 PathProgramCache]: Analyzing trace with hash 524493128, now seen corresponding path program 1 times [2021-12-15 17:20:25,096 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,096 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376369929] [2021-12-15 17:20:25,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,096 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,147 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376369929] [2021-12-15 17:20:25,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376369929] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,148 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,148 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466437294] [2021-12-15 17:20:25,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,149 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,163 INFO L85 PathProgramCache]: Analyzing trace with hash 599426203, now seen corresponding path program 1 times [2021-12-15 17:20:25,163 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936435774] [2021-12-15 17:20:25,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,164 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,193 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936435774] [2021-12-15 17:20:25,193 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936435774] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,194 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,194 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,194 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103032920] [2021-12-15 17:20:25,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,194 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,194 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:25,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:25,195 INFO L87 Difference]: Start difference. First operand 630 states and 923 transitions. cyclomatic complexity: 297 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,293 INFO L93 Difference]: Finished difference Result 1580 states and 2279 transitions. [2021-12-15 17:20:25,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:25,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1580 states and 2279 transitions. [2021-12-15 17:20:25,305 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1490 [2021-12-15 17:20:25,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1580 states to 1580 states and 2279 transitions. [2021-12-15 17:20:25,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1580 [2021-12-15 17:20:25,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1580 [2021-12-15 17:20:25,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1580 states and 2279 transitions. [2021-12-15 17:20:25,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,313 INFO L681 BuchiCegarLoop]: Abstraction has 1580 states and 2279 transitions. [2021-12-15 17:20:25,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1580 states and 2279 transitions. [2021-12-15 17:20:25,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1580 to 1540. [2021-12-15 17:20:25,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1540 states, 1540 states have (on average 1.45) internal successors, (2233), 1539 states have internal predecessors, (2233), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1540 states to 1540 states and 2233 transitions. [2021-12-15 17:20:25,331 INFO L704 BuchiCegarLoop]: Abstraction has 1540 states and 2233 transitions. [2021-12-15 17:20:25,331 INFO L587 BuchiCegarLoop]: Abstraction has 1540 states and 2233 transitions. [2021-12-15 17:20:25,331 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:25,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1540 states and 2233 transitions. [2021-12-15 17:20:25,335 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1474 [2021-12-15 17:20:25,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,336 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,336 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,336 INFO L791 eck$LassoCheckResult]: Stem: 5136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 5064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5065#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5068#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5077#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 5014#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5015#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4864#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4865#L356 assume !(0 == ~M_E~0); 4956#L356-2 assume !(0 == ~T1_E~0); 4957#L361-1 assume !(0 == ~T2_E~0); 5041#L366-1 assume !(0 == ~E_M~0); 5031#L371-1 assume !(0 == ~E_1~0); 4927#L376-1 assume !(0 == ~E_2~0); 4928#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4870#L178 assume !(1 == ~m_pc~0); 4871#L178-2 is_master_triggered_~__retres1~0#1 := 0; 4962#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4963#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5021#L437 assume !(0 != activate_threads_~tmp~1#1); 4891#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4892#L197 assume !(1 == ~t1_pc~0); 4937#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5123#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5128#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4887#L445 assume !(0 != activate_threads_~tmp___0~0#1); 4888#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5099#L216 assume !(1 == ~t2_pc~0); 4868#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4869#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4958#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4959#L453 assume !(0 != activate_threads_~tmp___1~0#1); 5029#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5030#L394 assume 1 == ~M_E~0;~M_E~0 := 2; 5036#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5000#L399-1 assume !(1 == ~T2_E~0); 5001#L404-1 assume !(1 == ~E_M~0); 5133#L409-1 assume !(1 == ~E_1~0); 5074#L414-1 assume !(1 == ~E_2~0); 5075#L419-1 assume { :end_inline_reset_delta_events } true; 5752#L565-2 [2021-12-15 17:20:25,337 INFO L793 eck$LassoCheckResult]: Loop: 5752#L565-2 assume !false; 5746#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5741#L331 assume !false; 5733#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5731#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5729#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5728#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5726#L298 assume !(0 != eval_~tmp~0#1); 5725#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5724#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5722#L356-3 assume !(0 == ~M_E~0); 5723#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5715#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5716#L366-3 assume !(0 == ~E_M~0); 5709#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5710#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5688#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5689#L178-12 assume !(1 == ~m_pc~0); 5673#L178-14 is_master_triggered_~__retres1~0#1 := 0; 5674#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5664#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5665#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5626#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5627#L197-12 assume !(1 == ~t1_pc~0); 5611#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 5612#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5597#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5598#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5507#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5508#L216-12 assume !(1 == ~t2_pc~0); 5501#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 5502#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5495#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5496#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5489#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5490#L394-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5483#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5484#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5477#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5478#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5471#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5472#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5465#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5466#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5459#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5460#L584 assume !(0 == start_simulation_~tmp~3#1); 5781#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5777#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5772#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5767#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 5764#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5762#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5758#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 5756#L597 assume !(0 != start_simulation_~tmp___0~1#1); 5752#L565-2 [2021-12-15 17:20:25,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,337 INFO L85 PathProgramCache]: Analyzing trace with hash -754831607, now seen corresponding path program 1 times [2021-12-15 17:20:25,337 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118213938] [2021-12-15 17:20:25,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,337 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118213938] [2021-12-15 17:20:25,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118213938] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,353 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:25,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030005845] [2021-12-15 17:20:25,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,353 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1458177828, now seen corresponding path program 2 times [2021-12-15 17:20:25,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,354 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13745356] [2021-12-15 17:20:25,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,354 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,373 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [13745356] [2021-12-15 17:20:25,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [13745356] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,373 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,373 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,374 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849760109] [2021-12-15 17:20:25,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,374 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,374 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,374 INFO L87 Difference]: Start difference. First operand 1540 states and 2233 transitions. cyclomatic complexity: 701 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,392 INFO L93 Difference]: Finished difference Result 2260 states and 3273 transitions. [2021-12-15 17:20:25,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2260 states and 3273 transitions. [2021-12-15 17:20:25,402 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2187 [2021-12-15 17:20:25,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2260 states to 2260 states and 3273 transitions. [2021-12-15 17:20:25,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2260 [2021-12-15 17:20:25,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2260 [2021-12-15 17:20:25,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2260 states and 3273 transitions. [2021-12-15 17:20:25,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,413 INFO L681 BuchiCegarLoop]: Abstraction has 2260 states and 3273 transitions. [2021-12-15 17:20:25,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2260 states and 3273 transitions. [2021-12-15 17:20:25,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2260 to 1615. [2021-12-15 17:20:25,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1615 states, 1615 states have (on average 1.45015479876161) internal successors, (2342), 1614 states have internal predecessors, (2342), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1615 states to 1615 states and 2342 transitions. [2021-12-15 17:20:25,447 INFO L704 BuchiCegarLoop]: Abstraction has 1615 states and 2342 transitions. [2021-12-15 17:20:25,447 INFO L587 BuchiCegarLoop]: Abstraction has 1615 states and 2342 transitions. [2021-12-15 17:20:25,447 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:25,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1615 states and 2342 transitions. [2021-12-15 17:20:25,451 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1555 [2021-12-15 17:20:25,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,452 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,452 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,452 INFO L791 eck$LassoCheckResult]: Stem: 8921#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8867#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8868#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8870#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8878#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 8816#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8817#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8673#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8674#L356 assume !(0 == ~M_E~0); 8765#L356-2 assume !(0 == ~T1_E~0); 8766#L361-1 assume !(0 == ~T2_E~0); 8844#L366-1 assume !(0 == ~E_M~0); 8836#L371-1 assume !(0 == ~E_1~0); 8737#L376-1 assume !(0 == ~E_2~0); 8738#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8679#L178 assume !(1 == ~m_pc~0); 8680#L178-2 is_master_triggered_~__retres1~0#1 := 0; 8771#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8772#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8826#L437 assume !(0 != activate_threads_~tmp~1#1); 8700#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8701#L197 assume !(1 == ~t1_pc~0); 8749#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8915#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8918#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8696#L445 assume !(0 != activate_threads_~tmp___0~0#1); 8697#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8897#L216 assume !(1 == ~t2_pc~0); 8677#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8678#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8767#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8768#L453 assume !(0 != activate_threads_~tmp___1~0#1); 8834#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8835#L394 assume !(1 == ~M_E~0); 8841#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8804#L399-1 assume !(1 == ~T2_E~0); 8805#L404-1 assume !(1 == ~E_M~0); 8718#L409-1 assume !(1 == ~E_1~0); 8719#L414-1 assume !(1 == ~E_2~0); 8807#L419-1 assume { :end_inline_reset_delta_events } true; 8808#L565-2 [2021-12-15 17:20:25,452 INFO L793 eck$LassoCheckResult]: Loop: 8808#L565-2 assume !false; 9650#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9647#L331 assume !false; 9646#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9641#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9638#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9636#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9634#L298 assume !(0 != eval_~tmp~0#1); 8708#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8709#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8814#L356-3 assume !(0 == ~M_E~0); 8863#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8827#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8828#L366-3 assume !(0 == ~E_M~0); 8860#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8784#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8785#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8783#L178-12 assume !(1 == ~m_pc~0); 8649#L178-14 is_master_triggered_~__retres1~0#1 := 0; 8650#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8806#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8857#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10236#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8851#L197-12 assume !(1 == ~t1_pc~0); 8852#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 8723#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8724#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10241#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10240#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8721#L216-12 assume !(1 == ~t2_pc~0); 8722#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8759#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8686#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8687#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8710#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8895#L394-3 assume !(1 == ~M_E~0); 8917#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8667#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8668#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8753#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8754#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8894#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10170#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10169#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10168#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8874#L584 assume !(0 == start_simulation_~tmp~3#1); 8876#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9660#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 9658#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9657#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 9656#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9655#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9654#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 9653#L597 assume !(0 != start_simulation_~tmp___0~1#1); 8808#L565-2 [2021-12-15 17:20:25,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2021-12-15 17:20:25,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239142155] [2021-12-15 17:20:25,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,469 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239142155] [2021-12-15 17:20:25,470 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239142155] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,470 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895720070] [2021-12-15 17:20:25,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,470 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1147845726, now seen corresponding path program 1 times [2021-12-15 17:20:25,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867547228] [2021-12-15 17:20:25,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,471 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,504 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867547228] [2021-12-15 17:20:25,504 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867547228] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,504 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626551676] [2021-12-15 17:20:25,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,505 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,505 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:25,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:25,506 INFO L87 Difference]: Start difference. First operand 1615 states and 2342 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,553 INFO L93 Difference]: Finished difference Result 2650 states and 3783 transitions. [2021-12-15 17:20:25,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:25,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2650 states and 3783 transitions. [2021-12-15 17:20:25,568 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2550 [2021-12-15 17:20:25,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2650 states to 2650 states and 3783 transitions. [2021-12-15 17:20:25,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2650 [2021-12-15 17:20:25,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2650 [2021-12-15 17:20:25,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2650 states and 3783 transitions. [2021-12-15 17:20:25,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,582 INFO L681 BuchiCegarLoop]: Abstraction has 2650 states and 3783 transitions. [2021-12-15 17:20:25,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2650 states and 3783 transitions. [2021-12-15 17:20:25,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2650 to 1958. [2021-12-15 17:20:25,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1958 states, 1958 states have (on average 1.4264555669050052) internal successors, (2793), 1957 states have internal predecessors, (2793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1958 states to 1958 states and 2793 transitions. [2021-12-15 17:20:25,606 INFO L704 BuchiCegarLoop]: Abstraction has 1958 states and 2793 transitions. [2021-12-15 17:20:25,607 INFO L587 BuchiCegarLoop]: Abstraction has 1958 states and 2793 transitions. [2021-12-15 17:20:25,607 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:25,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1958 states and 2793 transitions. [2021-12-15 17:20:25,612 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1873 [2021-12-15 17:20:25,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,613 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,613 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,613 INFO L791 eck$LassoCheckResult]: Stem: 13194#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13146#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13148#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13158#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 13101#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13102#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12950#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12951#L356 assume !(0 == ~M_E~0); 13040#L356-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13041#L361-1 assume !(0 == ~T2_E~0); 13211#L366-1 assume !(0 == ~E_M~0); 13210#L371-1 assume !(0 == ~E_1~0); 13014#L376-1 assume !(0 == ~E_2~0); 13015#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12956#L178 assume !(1 == ~m_pc~0); 12957#L178-2 is_master_triggered_~__retres1~0#1 := 0; 13115#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13159#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13108#L437 assume !(0 != activate_threads_~tmp~1#1); 13109#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13206#L197 assume !(1 == ~t1_pc~0); 13186#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13187#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13205#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13204#L445 assume !(0 != activate_threads_~tmp___0~0#1); 13173#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13174#L216 assume !(1 == ~t2_pc~0); 13203#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13057#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13058#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13149#L453 assume !(0 != activate_threads_~tmp___1~0#1); 13116#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13117#L394 assume !(1 == ~M_E~0); 13123#L394-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13087#L399-1 assume !(1 == ~T2_E~0); 13088#L404-1 assume !(1 == ~E_M~0); 12995#L409-1 assume !(1 == ~E_1~0); 12996#L414-1 assume !(1 == ~E_2~0); 13090#L419-1 assume { :end_inline_reset_delta_events } true; 13091#L565-2 [2021-12-15 17:20:25,613 INFO L793 eck$LassoCheckResult]: Loop: 13091#L565-2 assume !false; 14258#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14255#L331 assume !false; 14248#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14242#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14233#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14232#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14230#L298 assume !(0 != eval_~tmp~0#1); 14231#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14337#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14335#L356-3 assume !(0 == ~M_E~0); 14332#L356-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14331#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14330#L366-3 assume !(0 == ~E_M~0); 14329#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14328#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14327#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14326#L178-12 assume !(1 == ~m_pc~0); 14325#L178-14 is_master_triggered_~__retres1~0#1 := 0; 14324#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14323#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14322#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14321#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14320#L197-12 assume !(1 == ~t1_pc~0); 14319#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14318#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14317#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14316#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14315#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14314#L216-12 assume !(1 == ~t2_pc~0); 14313#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 14312#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14311#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14310#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14309#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14308#L394-3 assume !(1 == ~M_E~0); 13716#L394-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14307#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14306#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14305#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14304#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14303#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14300#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14299#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12993#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 12994#L584 assume !(0 == start_simulation_~tmp~3#1); 13156#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14283#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14279#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14277#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 14275#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14273#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14271#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 14269#L597 assume !(0 != start_simulation_~tmp___0~1#1); 13091#L565-2 [2021-12-15 17:20:25,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,614 INFO L85 PathProgramCache]: Analyzing trace with hash 318575881, now seen corresponding path program 1 times [2021-12-15 17:20:25,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537573942] [2021-12-15 17:20:25,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,635 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537573942] [2021-12-15 17:20:25,635 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537573942] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,635 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,635 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,636 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041959097] [2021-12-15 17:20:25,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,636 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,637 INFO L85 PathProgramCache]: Analyzing trace with hash 1147845726, now seen corresponding path program 2 times [2021-12-15 17:20:25,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435993742] [2021-12-15 17:20:25,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,674 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435993742] [2021-12-15 17:20:25,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435993742] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,674 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,675 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,675 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873031904] [2021-12-15 17:20:25,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,675 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,675 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:25,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:25,676 INFO L87 Difference]: Start difference. First operand 1958 states and 2793 transitions. cyclomatic complexity: 839 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,705 INFO L93 Difference]: Finished difference Result 2302 states and 3279 transitions. [2021-12-15 17:20:25,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:25,706 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2302 states and 3279 transitions. [2021-12-15 17:20:25,715 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2021-12-15 17:20:25,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2302 states to 2302 states and 3279 transitions. [2021-12-15 17:20:25,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2302 [2021-12-15 17:20:25,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2302 [2021-12-15 17:20:25,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2302 states and 3279 transitions. [2021-12-15 17:20:25,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,726 INFO L681 BuchiCegarLoop]: Abstraction has 2302 states and 3279 transitions. [2021-12-15 17:20:25,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2302 states and 3279 transitions. [2021-12-15 17:20:25,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2302 to 1615. [2021-12-15 17:20:25,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1615 states, 1615 states have (on average 1.426625386996904) internal successors, (2304), 1614 states have internal predecessors, (2304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1615 states to 1615 states and 2304 transitions. [2021-12-15 17:20:25,753 INFO L704 BuchiCegarLoop]: Abstraction has 1615 states and 2304 transitions. [2021-12-15 17:20:25,753 INFO L587 BuchiCegarLoop]: Abstraction has 1615 states and 2304 transitions. [2021-12-15 17:20:25,753 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:25,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1615 states and 2304 transitions. [2021-12-15 17:20:25,759 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1555 [2021-12-15 17:20:25,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,760 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,762 INFO L791 eck$LassoCheckResult]: Stem: 17459#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17413#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17415#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17423#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 17365#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17366#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17222#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17223#L356 assume !(0 == ~M_E~0); 17313#L356-2 assume !(0 == ~T1_E~0); 17314#L361-1 assume !(0 == ~T2_E~0); 17394#L366-1 assume !(0 == ~E_M~0); 17385#L371-1 assume !(0 == ~E_1~0); 17287#L376-1 assume !(0 == ~E_2~0); 17288#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17228#L178 assume !(1 == ~m_pc~0); 17229#L178-2 is_master_triggered_~__retres1~0#1 := 0; 17319#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17320#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17375#L437 assume !(0 != activate_threads_~tmp~1#1); 17249#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17250#L197 assume !(1 == ~t1_pc~0); 17298#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17452#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17454#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17245#L445 assume !(0 != activate_threads_~tmp___0~0#1); 17246#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17438#L216 assume !(1 == ~t2_pc~0); 17226#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17227#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17315#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17316#L453 assume !(0 != activate_threads_~tmp___1~0#1); 17383#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17384#L394 assume !(1 == ~M_E~0); 17390#L394-2 assume !(1 == ~T1_E~0); 17353#L399-1 assume !(1 == ~T2_E~0); 17354#L404-1 assume !(1 == ~E_M~0); 17267#L409-1 assume !(1 == ~E_1~0); 17268#L414-1 assume !(1 == ~E_2~0); 17356#L419-1 assume { :end_inline_reset_delta_events } true; 17357#L565-2 [2021-12-15 17:20:25,762 INFO L793 eck$LassoCheckResult]: Loop: 17357#L565-2 assume !false; 17873#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17866#L331 assume !false; 17861#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17855#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17852#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17850#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17845#L298 assume !(0 != eval_~tmp~0#1); 17843#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17841#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17838#L356-3 assume !(0 == ~M_E~0); 17836#L356-5 assume !(0 == ~T1_E~0); 17834#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17832#L366-3 assume !(0 == ~E_M~0); 17830#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17828#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17826#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17824#L178-12 assume !(1 == ~m_pc~0); 17822#L178-14 is_master_triggered_~__retres1~0#1 := 0; 17820#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17818#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17815#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17813#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17811#L197-12 assume !(1 == ~t1_pc~0); 17809#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17807#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17805#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17803#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17801#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17799#L216-12 assume !(1 == ~t2_pc~0); 17797#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 17795#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17793#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17791#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17789#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17780#L394-3 assume !(1 == ~M_E~0); 17561#L394-5 assume !(1 == ~T1_E~0); 17559#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17557#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17555#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17553#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17551#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17536#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17534#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17526#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17519#L584 assume !(0 == start_simulation_~tmp~3#1); 17520#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17907#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17899#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17897#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 17892#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17889#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17886#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 17883#L597 assume !(0 != start_simulation_~tmp___0~1#1); 17357#L565-2 [2021-12-15 17:20:25,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,763 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2021-12-15 17:20:25,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,763 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867413390] [2021-12-15 17:20:25,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:25,773 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:25,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:25,795 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:25,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1743692258, now seen corresponding path program 1 times [2021-12-15 17:20:25,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831270091] [2021-12-15 17:20:25,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,823 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831270091] [2021-12-15 17:20:25,823 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831270091] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,823 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,823 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,823 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900332358] [2021-12-15 17:20:25,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,824 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,824 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:25,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:25,824 INFO L87 Difference]: Start difference. First operand 1615 states and 2304 transitions. cyclomatic complexity: 693 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,890 INFO L93 Difference]: Finished difference Result 2764 states and 3879 transitions. [2021-12-15 17:20:25,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:25,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2764 states and 3879 transitions. [2021-12-15 17:20:25,910 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2684 [2021-12-15 17:20:25,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2764 states to 2764 states and 3879 transitions. [2021-12-15 17:20:25,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2764 [2021-12-15 17:20:25,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2764 [2021-12-15 17:20:25,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2764 states and 3879 transitions. [2021-12-15 17:20:25,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,922 INFO L681 BuchiCegarLoop]: Abstraction has 2764 states and 3879 transitions. [2021-12-15 17:20:25,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2764 states and 3879 transitions. [2021-12-15 17:20:25,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2764 to 1651. [2021-12-15 17:20:25,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1651 states, 1651 states have (on average 1.4173228346456692) internal successors, (2340), 1650 states have internal predecessors, (2340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1651 states to 1651 states and 2340 transitions. [2021-12-15 17:20:25,944 INFO L704 BuchiCegarLoop]: Abstraction has 1651 states and 2340 transitions. [2021-12-15 17:20:25,944 INFO L587 BuchiCegarLoop]: Abstraction has 1651 states and 2340 transitions. [2021-12-15 17:20:25,944 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:25,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1651 states and 2340 transitions. [2021-12-15 17:20:25,947 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1591 [2021-12-15 17:20:25,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,948 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,948 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,948 INFO L791 eck$LassoCheckResult]: Stem: 21878#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21826#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21828#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21835#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 21773#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21774#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21617#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21618#L356 assume !(0 == ~M_E~0); 21710#L356-2 assume !(0 == ~T1_E~0); 21711#L361-1 assume !(0 == ~T2_E~0); 21801#L366-1 assume !(0 == ~E_M~0); 21793#L371-1 assume !(0 == ~E_1~0); 21681#L376-1 assume !(0 == ~E_2~0); 21682#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21623#L178 assume !(1 == ~m_pc~0); 21624#L178-2 is_master_triggered_~__retres1~0#1 := 0; 21716#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21717#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21779#L437 assume !(0 != activate_threads_~tmp~1#1); 21644#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21645#L197 assume !(1 == ~t1_pc~0); 21694#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21870#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21873#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21640#L445 assume !(0 != activate_threads_~tmp___0~0#1); 21641#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21856#L216 assume !(1 == ~t2_pc~0); 21621#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21622#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21712#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21713#L453 assume !(0 != activate_threads_~tmp___1~0#1); 21791#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21792#L394 assume !(1 == ~M_E~0); 21798#L394-2 assume !(1 == ~T1_E~0); 21754#L399-1 assume !(1 == ~T2_E~0); 21755#L404-1 assume !(1 == ~E_M~0); 21663#L409-1 assume !(1 == ~E_1~0); 21664#L414-1 assume !(1 == ~E_2~0); 21758#L419-1 assume { :end_inline_reset_delta_events } true; 21759#L565-2 [2021-12-15 17:20:25,948 INFO L793 eck$LassoCheckResult]: Loop: 21759#L565-2 assume !false; 22755#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22753#L331 assume !false; 22752#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22750#L266 assume !(0 == ~m_st~0); 22751#L270 assume !(0 == ~t1_st~0); 22748#L274 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 22749#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22657#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22658#L298 assume !(0 != eval_~tmp~0#1); 22839#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22837#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22835#L356-3 assume !(0 == ~M_E~0); 22833#L356-5 assume !(0 == ~T1_E~0); 22831#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22829#L366-3 assume !(0 == ~E_M~0); 22827#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22825#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22823#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22821#L178-12 assume !(1 == ~m_pc~0); 22819#L178-14 is_master_triggered_~__retres1~0#1 := 0; 22817#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22815#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22813#L437-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22811#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22809#L197-12 assume !(1 == ~t1_pc~0); 22807#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 22805#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22803#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22801#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22799#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22797#L216-12 assume !(1 == ~t2_pc~0); 22795#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 22793#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22791#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22789#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22787#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22785#L394-3 assume !(1 == ~M_E~0); 22782#L394-5 assume !(1 == ~T1_E~0); 22781#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22780#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22779#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22778#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22777#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22774#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22772#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22770#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 22767#L584 assume !(0 == start_simulation_~tmp~3#1); 22765#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22763#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22761#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22760#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 22759#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22758#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22757#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 22756#L597 assume !(0 != start_simulation_~tmp___0~1#1); 21759#L565-2 [2021-12-15 17:20:25,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2021-12-15 17:20:25,949 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302806357] [2021-12-15 17:20:25,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,949 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:25,953 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:25,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:25,961 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:25,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1678104567, now seen corresponding path program 1 times [2021-12-15 17:20:25,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361071550] [2021-12-15 17:20:25,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,962 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,010 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,010 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361071550] [2021-12-15 17:20:26,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361071550] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,010 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,010 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350231739] [2021-12-15 17:20:26,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,011 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,011 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:26,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:26,011 INFO L87 Difference]: Start difference. First operand 1651 states and 2340 transitions. cyclomatic complexity: 693 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,100 INFO L93 Difference]: Finished difference Result 3274 states and 4601 transitions. [2021-12-15 17:20:26,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:26,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3274 states and 4601 transitions. [2021-12-15 17:20:26,111 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3206 [2021-12-15 17:20:26,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3274 states to 3274 states and 4601 transitions. [2021-12-15 17:20:26,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3274 [2021-12-15 17:20:26,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3274 [2021-12-15 17:20:26,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3274 states and 4601 transitions. [2021-12-15 17:20:26,126 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,126 INFO L681 BuchiCegarLoop]: Abstraction has 3274 states and 4601 transitions. [2021-12-15 17:20:26,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3274 states and 4601 transitions. [2021-12-15 17:20:26,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3274 to 1714. [2021-12-15 17:20:26,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1714 states, 1714 states have (on average 1.3926487747957994) internal successors, (2387), 1713 states have internal predecessors, (2387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1714 states to 1714 states and 2387 transitions. [2021-12-15 17:20:26,165 INFO L704 BuchiCegarLoop]: Abstraction has 1714 states and 2387 transitions. [2021-12-15 17:20:26,165 INFO L587 BuchiCegarLoop]: Abstraction has 1714 states and 2387 transitions. [2021-12-15 17:20:26,165 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:26,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1714 states and 2387 transitions. [2021-12-15 17:20:26,168 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1654 [2021-12-15 17:20:26,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,169 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,169 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,169 INFO L791 eck$LassoCheckResult]: Stem: 26813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 26761#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 26762#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26764#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26772#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 26710#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26711#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26557#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26558#L356 assume !(0 == ~M_E~0); 26648#L356-2 assume !(0 == ~T1_E~0); 26649#L361-1 assume !(0 == ~T2_E~0); 26739#L366-1 assume !(0 == ~E_M~0); 26730#L371-1 assume !(0 == ~E_1~0); 26622#L376-1 assume !(0 == ~E_2~0); 26623#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26563#L178 assume !(1 == ~m_pc~0); 26564#L178-2 is_master_triggered_~__retres1~0#1 := 0; 26654#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26655#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26717#L437 assume !(0 != activate_threads_~tmp~1#1); 26584#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26585#L197 assume !(1 == ~t1_pc~0); 26632#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26805#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26807#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26580#L445 assume !(0 != activate_threads_~tmp___0~0#1); 26581#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26792#L216 assume !(1 == ~t2_pc~0); 26561#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26562#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26650#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26651#L453 assume !(0 != activate_threads_~tmp___1~0#1); 26728#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26729#L394 assume !(1 == ~M_E~0); 26735#L394-2 assume !(1 == ~T1_E~0); 26692#L399-1 assume !(1 == ~T2_E~0); 26693#L404-1 assume !(1 == ~E_M~0); 26602#L409-1 assume !(1 == ~E_1~0); 26603#L414-1 assume !(1 == ~E_2~0); 26695#L419-1 assume { :end_inline_reset_delta_events } true; 26696#L565-2 [2021-12-15 17:20:26,169 INFO L793 eck$LassoCheckResult]: Loop: 26696#L565-2 assume !false; 27254#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27252#L331 assume !false; 27251#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27249#L266 assume !(0 == ~m_st~0); 27250#L270 assume !(0 == ~t1_st~0); 27247#L274 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 27248#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27231#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27232#L298 assume !(0 != eval_~tmp~0#1); 27361#L346 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27359#L236-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27357#L356-3 assume !(0 == ~M_E~0); 27355#L356-5 assume !(0 == ~T1_E~0); 27353#L361-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27351#L366-3 assume !(0 == ~E_M~0); 27349#L371-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27347#L376-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27345#L381-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27343#L178-12 assume !(1 == ~m_pc~0); 27341#L178-14 is_master_triggered_~__retres1~0#1 := 0; 27339#L189-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27335#L190-4 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27332#L437-12 assume !(0 != activate_threads_~tmp~1#1); 27330#L437-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27327#L197-12 assume !(1 == ~t1_pc~0); 27324#L197-14 is_transmit1_triggered_~__retres1~1#1 := 0; 27321#L208-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27318#L209-4 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27315#L445-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27312#L445-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27309#L216-12 assume !(1 == ~t2_pc~0); 27306#L216-14 is_transmit2_triggered_~__retres1~2#1 := 0; 27303#L227-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27300#L228-4 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27297#L453-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27294#L453-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27291#L394-3 assume !(1 == ~M_E~0); 27287#L394-5 assume !(1 == ~T1_E~0); 27285#L399-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27283#L404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27281#L409-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27278#L414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27276#L419-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27272#L266-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 27270#L283-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27268#L284-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 27266#L584 assume !(0 == start_simulation_~tmp~3#1); 27264#L584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27262#L266-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 27260#L283-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 27259#L284-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 27258#L539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27257#L546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27256#L547 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 27255#L597 assume !(0 != start_simulation_~tmp___0~1#1); 26696#L565-2 [2021-12-15 17:20:26,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2021-12-15 17:20:26,169 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704641268] [2021-12-15 17:20:26,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,170 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,173 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,179 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1605718009, now seen corresponding path program 1 times [2021-12-15 17:20:26,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792460122] [2021-12-15 17:20:26,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,192 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792460122] [2021-12-15 17:20:26,192 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792460122] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,192 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,192 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:26,192 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855868800] [2021-12-15 17:20:26,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,192 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,193 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:26,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:26,193 INFO L87 Difference]: Start difference. First operand 1714 states and 2387 transitions. cyclomatic complexity: 677 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,217 INFO L93 Difference]: Finished difference Result 2493 states and 3403 transitions. [2021-12-15 17:20:26,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:26,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2493 states and 3403 transitions. [2021-12-15 17:20:26,223 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2431 [2021-12-15 17:20:26,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2493 states to 2493 states and 3403 transitions. [2021-12-15 17:20:26,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2493 [2021-12-15 17:20:26,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2493 [2021-12-15 17:20:26,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2493 states and 3403 transitions. [2021-12-15 17:20:26,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,234 INFO L681 BuchiCegarLoop]: Abstraction has 2493 states and 3403 transitions. [2021-12-15 17:20:26,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2493 states and 3403 transitions. [2021-12-15 17:20:26,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2493 to 2403. [2021-12-15 17:20:26,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2403 states, 2403 states have (on average 1.3687057844361215) internal successors, (3289), 2402 states have internal predecessors, (3289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2403 states to 2403 states and 3289 transitions. [2021-12-15 17:20:26,259 INFO L704 BuchiCegarLoop]: Abstraction has 2403 states and 3289 transitions. [2021-12-15 17:20:26,259 INFO L587 BuchiCegarLoop]: Abstraction has 2403 states and 3289 transitions. [2021-12-15 17:20:26,259 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:26,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2403 states and 3289 transitions. [2021-12-15 17:20:26,264 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2341 [2021-12-15 17:20:26,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,264 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,264 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,264 INFO L791 eck$LassoCheckResult]: Stem: 31035#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 30972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 30973#L528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30975#L236 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30984#L243 assume 1 == ~m_i~0;~m_st~0 := 0; 30922#L243-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30923#L248-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30768#L253-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30769#L356 assume !(0 == ~M_E~0); 30860#L356-2 assume !(0 == ~T1_E~0); 30861#L361-1 assume !(0 == ~T2_E~0); 30952#L366-1 assume !(0 == ~E_M~0); 30942#L371-1 assume !(0 == ~E_1~0); 30832#L376-1 assume !(0 == ~E_2~0); 30833#L381-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30774#L178 assume !(1 == ~m_pc~0); 30775#L178-2 is_master_triggered_~__retres1~0#1 := 0; 30866#L189 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30867#L190 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30930#L437 assume !(0 != activate_threads_~tmp~1#1); 30795#L437-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30796#L197 assume !(1 == ~t1_pc~0); 30843#L197-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31024#L208 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31026#L209 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30791#L445 assume !(0 != activate_threads_~tmp___0~0#1); 30792#L445-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31005#L216 assume !(1 == ~t2_pc~0); 30772#L216-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30773#L227 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30862#L228 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30863#L453 assume !(0 != activate_threads_~tmp___1~0#1); 30940#L453-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30941#L394 assume !(1 == ~M_E~0); 30947#L394-2 assume !(1 == ~T1_E~0); 30905#L399-1 assume !(1 == ~T2_E~0); 30906#L404-1 assume !(1 == ~E_M~0); 30812#L409-1 assume !(1 == ~E_1~0); 30813#L414-1 assume !(1 == ~E_2~0); 30908#L419-1 assume { :end_inline_reset_delta_events } true; 30909#L565-2 assume !false; 31905#L566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31793#L331 [2021-12-15 17:20:26,264 INFO L793 eck$LassoCheckResult]: Loop: 31793#L331 assume !false; 31898#L294 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31894#L266 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31892#L283 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31890#L284 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31888#L298 assume 0 != eval_~tmp~0#1; 31885#L298-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 31881#L306 assume !(0 != eval_~tmp_ndt_1~0#1); 31799#L303 assume !(0 == ~t1_st~0); 31795#L317 assume !(0 == ~t2_st~0); 31793#L331 [2021-12-15 17:20:26,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,265 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 1 times [2021-12-15 17:20:26,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305396663] [2021-12-15 17:20:26,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,269 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,274 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,275 INFO L85 PathProgramCache]: Analyzing trace with hash 698787991, now seen corresponding path program 1 times [2021-12-15 17:20:26,275 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184176075] [2021-12-15 17:20:26,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,275 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,277 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,279 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1780423489, now seen corresponding path program 1 times [2021-12-15 17:20:26,279 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609386628] [2021-12-15 17:20:26,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,291 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609386628] [2021-12-15 17:20:26,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609386628] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,292 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,293 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:26,293 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087482366] [2021-12-15 17:20:26,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,350 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:26,353 INFO L158 Benchmark]: Toolchain (without parser) took 3088.01ms. Allocated memory was 107.0MB in the beginning and 157.3MB in the end (delta: 50.3MB). Free memory was 72.5MB in the beginning and 52.7MB in the end (delta: 19.9MB). Peak memory consumption was 71.6MB. Max. memory is 16.1GB. [2021-12-15 17:20:26,353 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 107.0MB. Free memory was 78.7MB in the beginning and 78.7MB in the end (delta: 21.2kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:26,354 INFO L158 Benchmark]: CACSL2BoogieTranslator took 216.47ms. Allocated memory is still 107.0MB. Free memory was 72.3MB in the beginning and 80.7MB in the end (delta: -8.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-15 17:20:26,354 INFO L158 Benchmark]: Boogie Procedure Inliner took 43.76ms. Allocated memory is still 107.0MB. Free memory was 80.7MB in the beginning and 77.5MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:26,354 INFO L158 Benchmark]: Boogie Preprocessor took 39.32ms. Allocated memory is still 107.0MB. Free memory was 77.5MB in the beginning and 74.9MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:26,354 INFO L158 Benchmark]: RCFGBuilder took 614.77ms. Allocated memory is still 107.0MB. Free memory was 74.9MB in the beginning and 50.8MB in the end (delta: 24.1MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:26,355 INFO L158 Benchmark]: BuchiAutomizer took 2170.17ms. Allocated memory was 107.0MB in the beginning and 157.3MB in the end (delta: 50.3MB). Free memory was 50.3MB in the beginning and 52.7MB in the end (delta: -2.4MB). Peak memory consumption was 51.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:26,356 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 107.0MB. Free memory was 78.7MB in the beginning and 78.7MB in the end (delta: 21.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 216.47ms. Allocated memory is still 107.0MB. Free memory was 72.3MB in the beginning and 80.7MB in the end (delta: -8.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 43.76ms. Allocated memory is still 107.0MB. Free memory was 80.7MB in the beginning and 77.5MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 39.32ms. Allocated memory is still 107.0MB. Free memory was 77.5MB in the beginning and 74.9MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 614.77ms. Allocated memory is still 107.0MB. Free memory was 74.9MB in the beginning and 50.8MB in the end (delta: 24.1MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 2170.17ms. Allocated memory was 107.0MB in the beginning and 157.3MB in the end (delta: 50.3MB). Free memory was 50.3MB in the beginning and 52.7MB in the end (delta: -2.4MB). Peak memory consumption was 51.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:26,383 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable