./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:22,331 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:22,336 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:22,373 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:22,374 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:22,377 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:22,377 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:22,379 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:22,381 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:22,384 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:22,385 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:22,386 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:22,386 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:22,387 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:22,389 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:22,393 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:22,394 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:22,394 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:22,396 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:22,398 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:22,400 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:22,401 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:22,401 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:22,402 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:22,405 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:22,408 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:22,408 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:22,409 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:22,410 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:22,410 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:22,411 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:22,411 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:22,412 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:22,413 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:22,414 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:22,414 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:22,415 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:22,415 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:22,415 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:22,416 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:22,417 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:22,418 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:22,438 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:22,439 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:22,439 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:22,439 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:22,440 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:22,440 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:22,441 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:22,441 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:22,441 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:22,441 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:22,442 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:22,442 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:22,442 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:22,442 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:22,442 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:22,442 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:22,443 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:22,443 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:22,443 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:22,443 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:22,443 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:22,443 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:22,443 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:22,444 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:22,444 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:22,444 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:22,444 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:22,444 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:22,444 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:22,445 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:22,445 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:22,445 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:22,446 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:22,446 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2021-12-15 17:20:22,625 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:22,658 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:22,660 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:22,660 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:22,661 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:22,662 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2021-12-15 17:20:22,719 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d953d9b2f/d4a9a35e663b4f58b83917ddd3ac3c8d/FLAG953a6a52b [2021-12-15 17:20:23,107 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:23,108 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2021-12-15 17:20:23,119 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d953d9b2f/d4a9a35e663b4f58b83917ddd3ac3c8d/FLAG953a6a52b [2021-12-15 17:20:23,493 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d953d9b2f/d4a9a35e663b4f58b83917ddd3ac3c8d [2021-12-15 17:20:23,496 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:23,497 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:23,500 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:23,500 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:23,503 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:23,503 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,505 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4cceda3a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23, skipping insertion in model container [2021-12-15 17:20:23,505 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,509 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:23,535 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:23,704 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2021-12-15 17:20:23,759 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:23,777 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:23,786 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2021-12-15 17:20:23,829 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:23,845 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:23,846 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23 WrapperNode [2021-12-15 17:20:23,846 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:23,847 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:23,847 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:23,847 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:23,854 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,872 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,914 INFO L137 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 825 [2021-12-15 17:20:23,916 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:23,917 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:23,917 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:23,917 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:23,923 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,923 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,931 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,932 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,944 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,961 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,972 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,978 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:23,982 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:23,982 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:23,982 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:23,983 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (1/1) ... [2021-12-15 17:20:23,989 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:23,998 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:24,011 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:24,019 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:24,054 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:24,054 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:24,054 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:24,054 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:24,113 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:24,115 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:24,668 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:24,675 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:24,675 INFO L301 CfgBuilder]: Removed 6 assume(true) statements. [2021-12-15 17:20:24,677 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:24 BoogieIcfgContainer [2021-12-15 17:20:24,677 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:24,678 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:24,678 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:24,680 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:24,680 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,681 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:23" (1/3) ... [2021-12-15 17:20:24,682 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d53c7e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:24, skipping insertion in model container [2021-12-15 17:20:24,682 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,682 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:23" (2/3) ... [2021-12-15 17:20:24,682 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d53c7e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:24, skipping insertion in model container [2021-12-15 17:20:24,682 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:24,682 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:24" (3/3) ... [2021-12-15 17:20:24,683 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2021-12-15 17:20:24,709 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:24,709 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:24,709 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:24,709 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:24,709 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:24,709 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:24,709 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:24,710 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:24,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2021-12-15 17:20:24,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,758 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,758 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:24,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:24,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2021-12-15 17:20:24,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:24,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:24,778 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,778 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:24,783 INFO L791 eck$LassoCheckResult]: Stem: 311#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 217#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 65#L653true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47#L297true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 282#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 123#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 25#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 235#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 138#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31#L441true assume !(0 == ~M_E~0); 120#L441-2true assume !(0 == ~T1_E~0); 253#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 96#L451-1true assume !(0 == ~T3_E~0); 275#L456-1true assume !(0 == ~E_M~0); 226#L461-1true assume !(0 == ~E_1~0); 248#L466-1true assume !(0 == ~E_2~0); 294#L471-1true assume !(0 == ~E_3~0); 51#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88#L220true assume 1 == ~m_pc~0; 264#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 105#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179#L232true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68#L543true assume !(0 != activate_threads_~tmp~1#1); 323#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203#L239true assume !(1 == ~t1_pc~0); 223#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 271#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261#L251true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 208#L551true assume !(0 != activate_threads_~tmp___0~0#1); 327#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209#L258true assume 1 == ~t2_pc~0; 246#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12#L270true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 221#L559true assume !(0 != activate_threads_~tmp___1~0#1); 130#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170#L277true assume !(1 == ~t3_pc~0); 324#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 39#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214#L289true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64#L567true assume !(0 != activate_threads_~tmp___2~0#1); 93#L567-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304#L489true assume !(1 == ~M_E~0); 224#L489-2true assume !(1 == ~T1_E~0); 150#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L499-1true assume !(1 == ~T3_E~0); 124#L504-1true assume !(1 == ~E_M~0); 263#L509-1true assume !(1 == ~E_1~0); 52#L514-1true assume !(1 == ~E_2~0); 178#L519-1true assume !(1 == ~E_3~0); 57#L524-1true assume { :end_inline_reset_delta_events } true; 38#L690-2true [2021-12-15 17:20:24,784 INFO L793 eck$LassoCheckResult]: Loop: 38#L690-2true assume !false; 53#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22#L416true assume false; 321#L431true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 210#L297-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 195#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 9#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 255#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 191#L451-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 36#L456-3true assume 0 == ~E_M~0;~E_M~0 := 1; 73#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 154#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 258#L471-3true assume !(0 == ~E_3~0); 66#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106#L220-15true assume !(1 == ~m_pc~0); 160#L220-17true is_master_triggered_~__retres1~0#1 := 0; 207#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28#L232-5true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 219#L543-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 131#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L239-15true assume 1 == ~t1_pc~0; 268#L240-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 281#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 331#L251-5true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26#L551-15true assume !(0 != activate_threads_~tmp___0~0#1); 316#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315#L258-15true assume 1 == ~t2_pc~0; 153#L259-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 279#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122#L270-5true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 332#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 228#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 300#L277-15true assume 1 == ~t3_pc~0; 72#L278-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 325#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242#L289-5true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270#L567-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34#L567-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 174#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 220#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 298#L499-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 107#L504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 16#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 296#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 165#L519-3true assume !(1 == ~E_3~0); 46#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 54#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 58#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 333#L355-1true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 151#L709true assume !(0 == start_simulation_~tmp~3#1); 8#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 56#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 113#L355-2true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 55#L664true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 155#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 142#L672true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 86#L722true assume !(0 != start_simulation_~tmp___0~1#1); 38#L690-2true [2021-12-15 17:20:24,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2021-12-15 17:20:24,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222144462] [2021-12-15 17:20:24,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,892 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,892 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222144462] [2021-12-15 17:20:24,892 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1222144462] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,893 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,893 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:24,894 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535780659] [2021-12-15 17:20:24,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,897 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:24,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:24,898 INFO L85 PathProgramCache]: Analyzing trace with hash 1938644724, now seen corresponding path program 1 times [2021-12-15 17:20:24,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:24,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701491425] [2021-12-15 17:20:24,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:24,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:24,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:24,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:24,917 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:24,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701491425] [2021-12-15 17:20:24,918 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701491425] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:24,918 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:24,918 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:24,918 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377733927] [2021-12-15 17:20:24,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:24,919 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:24,920 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:24,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:24,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:24,970 INFO L87 Difference]: Start difference. First operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,017 INFO L93 Difference]: Finished difference Result 329 states and 491 transitions. [2021-12-15 17:20:25,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 491 transitions. [2021-12-15 17:20:25,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-15 17:20:25,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 323 states and 485 transitions. [2021-12-15 17:20:25,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2021-12-15 17:20:25,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2021-12-15 17:20:25,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 485 transitions. [2021-12-15 17:20:25,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,050 INFO L681 BuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2021-12-15 17:20:25,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 485 transitions. [2021-12-15 17:20:25,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2021-12-15 17:20:25,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.501547987616099) internal successors, (485), 322 states have internal predecessors, (485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 485 transitions. [2021-12-15 17:20:25,116 INFO L704 BuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2021-12-15 17:20:25,116 INFO L587 BuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2021-12-15 17:20:25,117 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:25,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 485 transitions. [2021-12-15 17:20:25,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-15 17:20:25,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,131 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,131 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,132 INFO L791 eck$LassoCheckResult]: Stem: 989#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 955#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 795#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 762#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 763#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 869#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 721#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 722#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 888#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 732#L441 assume !(0 == ~M_E~0); 733#L441-2 assume !(0 == ~T1_E~0); 863#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 836#L451-1 assume !(0 == ~T3_E~0); 837#L456-1 assume !(0 == ~E_M~0); 958#L461-1 assume !(0 == ~E_1~0); 959#L466-1 assume !(0 == ~E_2~0); 971#L471-1 assume !(0 == ~E_3~0); 770#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771#L220 assume 1 == ~m_pc~0; 829#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 804#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 799#L543 assume !(0 != activate_threads_~tmp~1#1); 800#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 942#L239 assume !(1 == ~t1_pc~0); 940#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 941#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 974#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 944#L551 assume !(0 != activate_threads_~tmp___0~0#1); 945#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 946#L258 assume 1 == ~t2_pc~0; 947#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 828#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 691#L559 assume !(0 != activate_threads_~tmp___1~0#1); 875#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 876#L277 assume !(1 == ~t3_pc~0); 915#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 746#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 747#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 793#L567 assume !(0 != activate_threads_~tmp___2~0#1); 794#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 833#L489 assume !(1 == ~M_E~0); 957#L489-2 assume !(1 == ~T1_E~0); 902#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 784#L499-1 assume !(1 == ~T3_E~0); 785#L504-1 assume !(1 == ~E_M~0); 870#L509-1 assume !(1 == ~E_1~0); 772#L514-1 assume !(1 == ~E_2~0); 773#L519-1 assume !(1 == ~E_3~0); 780#L524-1 assume { :end_inline_reset_delta_events } true; 744#L690-2 [2021-12-15 17:20:25,133 INFO L793 eck$LassoCheckResult]: Loop: 744#L690-2 assume !false; 745#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674#L416 assume !false; 713#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 809#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 757#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 951#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 952#L369 assume !(0 != eval_~tmp~0#1); 954#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 949#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 936#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 683#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 684#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 930#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 741#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 742#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 808#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 904#L471-3 assume !(0 == ~E_3~0); 797#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 798#L220-15 assume !(1 == ~m_pc~0); 689#L220-17 is_master_triggered_~__retres1~0#1 := 0; 688#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 727#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 728#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 877#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 864#L239-15 assume !(1 == ~t1_pc~0); 865#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 973#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 719#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 720#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 991#L258-15 assume !(1 == ~t2_pc~0); 834#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 835#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 867#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 868#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 960#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961#L277-15 assume !(1 == ~t3_pc~0); 695#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 696#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 967#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 968#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 738#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 723#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 724#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 919#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 956#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 850#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 700#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 701#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 909#L519-3 assume !(1 == ~E_3~0); 760#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 761#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 774#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 781#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 901#L709 assume !(0 == start_simulation_~tmp~3#1); 681#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 682#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 778#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 779#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 776#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 777#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 892#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 826#L722 assume !(0 != start_simulation_~tmp___0~1#1); 744#L690-2 [2021-12-15 17:20:25,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,136 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2021-12-15 17:20:25,153 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106586245] [2021-12-15 17:20:25,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,154 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,226 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106586245] [2021-12-15 17:20:25,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106586245] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,227 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,227 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,230 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848314268] [2021-12-15 17:20:25,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,230 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,231 INFO L85 PathProgramCache]: Analyzing trace with hash -639658428, now seen corresponding path program 1 times [2021-12-15 17:20:25,231 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184366730] [2021-12-15 17:20:25,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,232 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184366730] [2021-12-15 17:20:25,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184366730] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,285 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45765891] [2021-12-15 17:20:25,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,285 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,286 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,286 INFO L87 Difference]: Start difference. First operand 323 states and 485 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,303 INFO L93 Difference]: Finished difference Result 323 states and 484 transitions. [2021-12-15 17:20:25,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 484 transitions. [2021-12-15 17:20:25,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-15 17:20:25,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 484 transitions. [2021-12-15 17:20:25,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2021-12-15 17:20:25,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2021-12-15 17:20:25,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 484 transitions. [2021-12-15 17:20:25,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,310 INFO L681 BuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2021-12-15 17:20:25,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 484 transitions. [2021-12-15 17:20:25,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2021-12-15 17:20:25,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.498452012383901) internal successors, (484), 322 states have internal predecessors, (484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 484 transitions. [2021-12-15 17:20:25,317 INFO L704 BuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2021-12-15 17:20:25,317 INFO L587 BuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2021-12-15 17:20:25,317 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:25,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 484 transitions. [2021-12-15 17:20:25,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-15 17:20:25,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,320 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,320 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,320 INFO L791 eck$LassoCheckResult]: Stem: 1644#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1450#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1417#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1418#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1525#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1376#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1377#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1543#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1389#L441 assume !(0 == ~M_E~0); 1390#L441-2 assume !(0 == ~T1_E~0); 1518#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1491#L451-1 assume !(0 == ~T3_E~0); 1492#L456-1 assume !(0 == ~E_M~0); 1613#L461-1 assume !(0 == ~E_1~0); 1614#L466-1 assume !(0 == ~E_2~0); 1626#L471-1 assume !(0 == ~E_3~0); 1425#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1426#L220 assume 1 == ~m_pc~0; 1486#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1459#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1506#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1454#L543 assume !(0 != activate_threads_~tmp~1#1); 1455#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1597#L239 assume !(1 == ~t1_pc~0); 1595#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1596#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1628#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1599#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1600#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1601#L258 assume 1 == ~t2_pc~0; 1602#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1483#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1345#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1346#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1530#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1531#L277 assume !(1 == ~t3_pc~0); 1569#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1401#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1402#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1448#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1449#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1488#L489 assume !(1 == ~M_E~0); 1612#L489-2 assume !(1 == ~T1_E~0); 1556#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1437#L499-1 assume !(1 == ~T3_E~0); 1438#L504-1 assume !(1 == ~E_M~0); 1524#L509-1 assume !(1 == ~E_1~0); 1427#L514-1 assume !(1 == ~E_2~0); 1428#L519-1 assume !(1 == ~E_3~0); 1435#L524-1 assume { :end_inline_reset_delta_events } true; 1399#L690-2 [2021-12-15 17:20:25,320 INFO L793 eck$LassoCheckResult]: Loop: 1399#L690-2 assume !false; 1400#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1329#L416 assume !false; 1368#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1464#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1411#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1606#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1607#L369 assume !(0 != eval_~tmp~0#1); 1609#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1604#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1589#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1338#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1339#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1585#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1396#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1397#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1463#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1559#L471-3 assume !(0 == ~E_3~0); 1452#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1453#L220-15 assume !(1 == ~m_pc~0); 1344#L220-17 is_master_triggered_~__retres1~0#1 := 0; 1343#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1380#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1381#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1532#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1519#L239-15 assume !(1 == ~t1_pc~0); 1520#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1629#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1639#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1374#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 1375#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1646#L258-15 assume !(1 == ~t2_pc~0); 1489#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1490#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1522#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1523#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1615#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1616#L277-15 assume !(1 == ~t3_pc~0); 1350#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1351#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1622#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1623#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1393#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1378#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1379#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1611#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1505#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1355#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1356#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1564#L519-3 assume !(1 == ~E_3~0); 1415#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1416#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1429#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1436#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1557#L709 assume !(0 == start_simulation_~tmp~3#1); 1336#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1337#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1433#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1434#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1431#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1432#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1547#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1482#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1399#L690-2 [2021-12-15 17:20:25,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2021-12-15 17:20:25,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189895024] [2021-12-15 17:20:25,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189895024] [2021-12-15 17:20:25,348 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189895024] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,349 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,349 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31283161] [2021-12-15 17:20:25,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,349 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,350 INFO L85 PathProgramCache]: Analyzing trace with hash -639658428, now seen corresponding path program 2 times [2021-12-15 17:20:25,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309341019] [2021-12-15 17:20:25,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,350 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,386 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309341019] [2021-12-15 17:20:25,386 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309341019] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,386 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80513717] [2021-12-15 17:20:25,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,387 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,387 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,388 INFO L87 Difference]: Start difference. First operand 323 states and 484 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,415 INFO L93 Difference]: Finished difference Result 323 states and 483 transitions. [2021-12-15 17:20:25,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 483 transitions. [2021-12-15 17:20:25,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-15 17:20:25,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 483 transitions. [2021-12-15 17:20:25,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2021-12-15 17:20:25,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2021-12-15 17:20:25,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 483 transitions. [2021-12-15 17:20:25,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,422 INFO L681 BuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2021-12-15 17:20:25,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 483 transitions. [2021-12-15 17:20:25,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2021-12-15 17:20:25,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.4953560371517027) internal successors, (483), 322 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 483 transitions. [2021-12-15 17:20:25,428 INFO L704 BuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2021-12-15 17:20:25,428 INFO L587 BuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2021-12-15 17:20:25,428 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:25,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 483 transitions. [2021-12-15 17:20:25,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-15 17:20:25,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,431 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,431 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,431 INFO L791 eck$LassoCheckResult]: Stem: 2299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2105#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2072#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2073#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2179#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2029#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2030#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2198#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2042#L441 assume !(0 == ~M_E~0); 2043#L441-2 assume !(0 == ~T1_E~0); 2173#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2146#L451-1 assume !(0 == ~T3_E~0); 2147#L456-1 assume !(0 == ~E_M~0); 2268#L461-1 assume !(0 == ~E_1~0); 2269#L466-1 assume !(0 == ~E_2~0); 2281#L471-1 assume !(0 == ~E_3~0); 2080#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2081#L220 assume 1 == ~m_pc~0; 2139#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2114#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2160#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2109#L543 assume !(0 != activate_threads_~tmp~1#1); 2110#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2252#L239 assume !(1 == ~t1_pc~0); 2250#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2251#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2283#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2254#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2255#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2256#L258 assume 1 == ~t2_pc~0; 2257#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2138#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2000#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2001#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2185#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2186#L277 assume !(1 == ~t3_pc~0); 2224#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2056#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2057#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2103#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2104#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2143#L489 assume !(1 == ~M_E~0); 2267#L489-2 assume !(1 == ~T1_E~0); 2211#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2092#L499-1 assume !(1 == ~T3_E~0); 2093#L504-1 assume !(1 == ~E_M~0); 2180#L509-1 assume !(1 == ~E_1~0); 2082#L514-1 assume !(1 == ~E_2~0); 2083#L519-1 assume !(1 == ~E_3~0); 2090#L524-1 assume { :end_inline_reset_delta_events } true; 2054#L690-2 [2021-12-15 17:20:25,431 INFO L793 eck$LassoCheckResult]: Loop: 2054#L690-2 assume !false; 2055#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1984#L416 assume !false; 2023#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2119#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2066#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2261#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2262#L369 assume !(0 != eval_~tmp~0#1); 2264#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2259#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2244#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1993#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1994#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2240#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2051#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2052#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2118#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2214#L471-3 assume !(0 == ~E_3~0); 2107#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2108#L220-15 assume 1 == ~m_pc~0; 1997#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1998#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2035#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2036#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2187#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2174#L239-15 assume 1 == ~t1_pc~0; 2176#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2284#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2294#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2031#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 2032#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2301#L258-15 assume !(1 == ~t2_pc~0); 2144#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 2145#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2177#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2178#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2270#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2271#L277-15 assume !(1 == ~t3_pc~0); 2005#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2006#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2277#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2278#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2048#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2033#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2034#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2229#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2266#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2161#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2010#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2011#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2219#L519-3 assume !(1 == ~E_3~0); 2070#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2071#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2084#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2091#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2212#L709 assume !(0 == start_simulation_~tmp~3#1); 1991#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1992#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2088#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2089#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2086#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2087#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2202#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2137#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2054#L690-2 [2021-12-15 17:20:25,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,432 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2021-12-15 17:20:25,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379673196] [2021-12-15 17:20:25,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,433 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,463 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,463 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379673196] [2021-12-15 17:20:25,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1379673196] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,463 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,463 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,464 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216200745] [2021-12-15 17:20:25,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,464 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,465 INFO L85 PathProgramCache]: Analyzing trace with hash 1190747650, now seen corresponding path program 1 times [2021-12-15 17:20:25,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328464995] [2021-12-15 17:20:25,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,495 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328464995] [2021-12-15 17:20:25,496 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328464995] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,496 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,496 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,496 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [877131369] [2021-12-15 17:20:25,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,497 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,497 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:25,498 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:25,498 INFO L87 Difference]: Start difference. First operand 323 states and 483 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,543 INFO L93 Difference]: Finished difference Result 561 states and 834 transitions. [2021-12-15 17:20:25,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:25,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 561 states and 834 transitions. [2021-12-15 17:20:25,547 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2021-12-15 17:20:25,549 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 561 states to 561 states and 834 transitions. [2021-12-15 17:20:25,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 561 [2021-12-15 17:20:25,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 561 [2021-12-15 17:20:25,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 561 states and 834 transitions. [2021-12-15 17:20:25,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,551 INFO L681 BuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2021-12-15 17:20:25,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states and 834 transitions. [2021-12-15 17:20:25,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 561. [2021-12-15 17:20:25,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 561 states, 561 states have (on average 1.4866310160427807) internal successors, (834), 560 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 561 states to 561 states and 834 transitions. [2021-12-15 17:20:25,563 INFO L704 BuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2021-12-15 17:20:25,563 INFO L587 BuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2021-12-15 17:20:25,563 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:25,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 561 states and 834 transitions. [2021-12-15 17:20:25,565 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2021-12-15 17:20:25,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,567 INFO L791 eck$LassoCheckResult]: Stem: 3234#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3003#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2970#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2971#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3080#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2926#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2927#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3099#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2940#L441 assume !(0 == ~M_E~0); 2941#L441-2 assume !(0 == ~T1_E~0); 3074#L446-1 assume !(0 == ~T2_E~0); 3045#L451-1 assume !(0 == ~T3_E~0); 3046#L456-1 assume !(0 == ~E_M~0); 3189#L461-1 assume !(0 == ~E_1~0); 3190#L466-1 assume !(0 == ~E_2~0); 3210#L471-1 assume !(0 == ~E_3~0); 2978#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2979#L220 assume 1 == ~m_pc~0; 3038#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3012#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3059#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3007#L543 assume !(0 != activate_threads_~tmp~1#1); 3008#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3164#L239 assume !(1 == ~t1_pc~0); 3162#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3163#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3214#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3168#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3169#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3170#L258 assume 1 == ~t2_pc~0; 3171#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3037#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2896#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2897#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3086#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3087#L277 assume !(1 == ~t3_pc~0); 3127#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2954#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2955#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3001#L567 assume !(0 != activate_threads_~tmp___2~0#1); 3002#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3042#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3186#L489-2 assume !(1 == ~T1_E~0); 3187#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2990#L499-1 assume !(1 == ~T3_E~0); 2991#L504-1 assume !(1 == ~E_M~0); 3081#L509-1 assume !(1 == ~E_1~0); 2980#L514-1 assume !(1 == ~E_2~0); 2981#L519-1 assume !(1 == ~E_3~0); 3137#L524-1 assume { :end_inline_reset_delta_events } true; 3249#L690-2 [2021-12-15 17:20:25,567 INFO L793 eck$LassoCheckResult]: Loop: 3249#L690-2 assume !false; 3248#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2919#L416 assume !false; 2920#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3165#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2964#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3178#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3179#L369 assume !(0 != eval_~tmp~0#1); 3241#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3173#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3174#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3240#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3343#L446-3 assume !(0 == ~T2_E~0); 3342#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3341#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3340#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3339#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3338#L471-3 assume !(0 == ~E_3~0); 3337#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3336#L220-15 assume !(1 == ~m_pc~0); 3334#L220-17 is_master_triggered_~__retres1~0#1 := 0; 3333#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3332#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3331#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3330#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3329#L239-15 assume !(1 == ~t1_pc~0); 3328#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3326#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3325#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3324#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 3323#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3322#L258-15 assume 1 == ~t2_pc~0; 3320#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3319#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3318#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3317#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3316#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3315#L277-15 assume !(1 == ~t3_pc~0); 3313#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3312#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3311#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3310#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3309#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3308#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2931#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3307#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3184#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3306#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3305#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3304#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3303#L519-3 assume !(1 == ~E_3~0); 3302#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3300#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3297#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3296#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3295#L709 assume !(0 == start_simulation_~tmp~3#1); 3136#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3068#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2986#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2987#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2984#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2985#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3103#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3104#L722 assume !(0 != start_simulation_~tmp___0~1#1); 3249#L690-2 [2021-12-15 17:20:25,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,568 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2021-12-15 17:20:25,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533974006] [2021-12-15 17:20:25,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,568 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,589 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533974006] [2021-12-15 17:20:25,589 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533974006] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,589 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:25,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018187069] [2021-12-15 17:20:25,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,590 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1819727935, now seen corresponding path program 1 times [2021-12-15 17:20:25,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857210788] [2021-12-15 17:20:25,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,591 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,617 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,617 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857210788] [2021-12-15 17:20:25,617 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857210788] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,617 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,618 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755706869] [2021-12-15 17:20:25,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,618 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,618 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:25,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:25,619 INFO L87 Difference]: Start difference. First operand 561 states and 834 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,655 INFO L93 Difference]: Finished difference Result 1033 states and 1511 transitions. [2021-12-15 17:20:25,655 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:25,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1033 states and 1511 transitions. [2021-12-15 17:20:25,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 967 [2021-12-15 17:20:25,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1033 states to 1033 states and 1511 transitions. [2021-12-15 17:20:25,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1033 [2021-12-15 17:20:25,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1033 [2021-12-15 17:20:25,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1033 states and 1511 transitions. [2021-12-15 17:20:25,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,686 INFO L681 BuchiCegarLoop]: Abstraction has 1033 states and 1511 transitions. [2021-12-15 17:20:25,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1033 states and 1511 transitions. [2021-12-15 17:20:25,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1033 to 979. [2021-12-15 17:20:25,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4678243105209396) internal successors, (1437), 978 states have internal predecessors, (1437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1437 transitions. [2021-12-15 17:20:25,701 INFO L704 BuchiCegarLoop]: Abstraction has 979 states and 1437 transitions. [2021-12-15 17:20:25,701 INFO L587 BuchiCegarLoop]: Abstraction has 979 states and 1437 transitions. [2021-12-15 17:20:25,701 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:25,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1437 transitions. [2021-12-15 17:20:25,705 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 913 [2021-12-15 17:20:25,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,705 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,706 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,706 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,706 INFO L791 eck$LassoCheckResult]: Stem: 4836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4606#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4573#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4574#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4686#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4530#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4531#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4705#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4542#L441 assume !(0 == ~M_E~0); 4543#L441-2 assume !(0 == ~T1_E~0); 4680#L446-1 assume !(0 == ~T2_E~0); 4648#L451-1 assume !(0 == ~T3_E~0); 4649#L456-1 assume !(0 == ~E_M~0); 4795#L461-1 assume !(0 == ~E_1~0); 4796#L466-1 assume !(0 == ~E_2~0); 4811#L471-1 assume !(0 == ~E_3~0); 4581#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4582#L220 assume !(1 == ~m_pc~0); 4614#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4615#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4665#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4610#L543 assume !(0 != activate_threads_~tmp~1#1); 4611#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4775#L239 assume !(1 == ~t1_pc~0); 4772#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4773#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4814#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4777#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4778#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4779#L258 assume 1 == ~t2_pc~0; 4780#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4641#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4500#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4694#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4695#L277 assume !(1 == ~t3_pc~0); 4741#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4556#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4557#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4604#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4605#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4645#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4835#L489-2 assume !(1 == ~T1_E~0); 5322#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4723#L499-1 assume !(1 == ~T3_E~0); 5321#L504-1 assume !(1 == ~E_M~0); 5320#L509-1 assume !(1 == ~E_1~0); 5319#L514-1 assume !(1 == ~E_2~0); 5318#L519-1 assume !(1 == ~E_3~0); 4591#L524-1 assume { :end_inline_reset_delta_events } true; 4554#L690-2 [2021-12-15 17:20:25,706 INFO L793 eck$LassoCheckResult]: Loop: 4554#L690-2 assume !false; 4555#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4483#L416 assume !false; 4524#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4620#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4568#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5258#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5256#L369 assume !(0 != eval_~tmp~0#1); 4842#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4782#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4783#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5292#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5374#L446-3 assume !(0 == ~T2_E~0); 5373#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5372#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5369#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5367#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5366#L471-3 assume !(0 == ~E_3~0); 5365#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5364#L220-15 assume !(1 == ~m_pc~0); 5363#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5362#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5361#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5360#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5359#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5358#L239-15 assume 1 == ~t1_pc~0; 5356#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5355#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5354#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5353#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 5352#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5351#L258-15 assume 1 == ~t2_pc~0; 5348#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5347#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5346#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5345#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5344#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5343#L277-15 assume !(1 == ~t3_pc~0); 5341#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5340#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5339#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5338#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5337#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5336#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4958#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5335#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4937#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5334#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5333#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5332#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5331#L519-3 assume !(1 == ~E_3~0); 5330#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5328#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5325#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5324#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5323#L709 assume !(0 == start_simulation_~tmp~3#1); 4748#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4673#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4589#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4590#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4585#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4586#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4709#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4639#L722 assume !(0 != start_simulation_~tmp___0~1#1); 4554#L690-2 [2021-12-15 17:20:25,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,707 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2021-12-15 17:20:25,707 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342028306] [2021-12-15 17:20:25,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,708 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,735 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342028306] [2021-12-15 17:20:25,735 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342028306] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,735 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,736 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:25,736 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208605067] [2021-12-15 17:20:25,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,737 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:25,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,740 INFO L85 PathProgramCache]: Analyzing trace with hash -862799552, now seen corresponding path program 1 times [2021-12-15 17:20:25,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173962674] [2021-12-15 17:20:25,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,741 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:25,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:25,787 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:25,787 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173962674] [2021-12-15 17:20:25,787 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [173962674] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:25,787 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:25,787 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:25,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679683210] [2021-12-15 17:20:25,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:25,788 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:25,788 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:25,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:25,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:25,789 INFO L87 Difference]: Start difference. First operand 979 states and 1437 transitions. cyclomatic complexity: 462 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:25,874 INFO L93 Difference]: Finished difference Result 2457 states and 3555 transitions. [2021-12-15 17:20:25,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:25,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2457 states and 3555 transitions. [2021-12-15 17:20:25,891 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2353 [2021-12-15 17:20:25,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2457 states to 2457 states and 3555 transitions. [2021-12-15 17:20:25,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2457 [2021-12-15 17:20:25,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2457 [2021-12-15 17:20:25,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2457 states and 3555 transitions. [2021-12-15 17:20:25,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:25,906 INFO L681 BuchiCegarLoop]: Abstraction has 2457 states and 3555 transitions. [2021-12-15 17:20:25,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2457 states and 3555 transitions. [2021-12-15 17:20:25,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2457 to 2373. [2021-12-15 17:20:25,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2373 states, 2373 states have (on average 1.4542772861356932) internal successors, (3451), 2372 states have internal predecessors, (3451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:25,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2373 states to 2373 states and 3451 transitions. [2021-12-15 17:20:25,941 INFO L704 BuchiCegarLoop]: Abstraction has 2373 states and 3451 transitions. [2021-12-15 17:20:25,941 INFO L587 BuchiCegarLoop]: Abstraction has 2373 states and 3451 transitions. [2021-12-15 17:20:25,941 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:25,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2373 states and 3451 transitions. [2021-12-15 17:20:25,965 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2293 [2021-12-15 17:20:25,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:25,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:25,966 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,966 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:25,967 INFO L791 eck$LassoCheckResult]: Stem: 8296#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 8242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8052#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8018#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8019#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 8143#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7975#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7976#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8162#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7988#L441 assume !(0 == ~M_E~0); 7989#L441-2 assume !(0 == ~T1_E~0); 8138#L446-1 assume !(0 == ~T2_E~0); 8100#L451-1 assume !(0 == ~T3_E~0); 8101#L456-1 assume !(0 == ~E_M~0); 8246#L461-1 assume !(0 == ~E_1~0); 8247#L466-1 assume !(0 == ~E_2~0); 8265#L471-1 assume !(0 == ~E_3~0); 8026#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8027#L220 assume !(1 == ~m_pc~0); 8060#L220-2 is_master_triggered_~__retres1~0#1 := 0; 8061#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8117#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8056#L543 assume !(0 != activate_threads_~tmp~1#1); 8057#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8228#L239 assume !(1 == ~t1_pc~0); 8229#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8244#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8269#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8232#L551 assume !(0 != activate_threads_~tmp___0~0#1); 8233#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8234#L258 assume !(1 == ~t2_pc~0); 8235#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8089#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7947#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7948#L559 assume !(0 != activate_threads_~tmp___1~0#1); 8150#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8151#L277 assume !(1 == ~t3_pc~0); 8201#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8002#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8003#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8050#L567 assume !(0 != activate_threads_~tmp___2~0#1); 8051#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8097#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 8245#L489-2 assume !(1 == ~T1_E~0); 8180#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8039#L499-1 assume !(1 == ~T3_E~0); 8040#L504-1 assume !(1 == ~E_M~0); 8144#L509-1 assume !(1 == ~E_1~0); 9583#L514-1 assume !(1 == ~E_2~0); 9581#L519-1 assume !(1 == ~E_3~0); 9575#L524-1 assume { :end_inline_reset_delta_events } true; 9572#L690-2 [2021-12-15 17:20:25,967 INFO L793 eck$LassoCheckResult]: Loop: 9572#L690-2 assume !false; 9571#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9566#L416 assume !false; 9565#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9542#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9538#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9537#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9536#L369 assume !(0 != eval_~tmp~0#1); 8303#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8236#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8223#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7940#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7941#L446-3 assume !(0 == ~T2_E~0); 9723#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9724#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9717#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9718#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9711#L471-3 assume !(0 == ~E_3~0); 9712#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8118#L220-15 assume !(1 == ~m_pc~0); 8119#L220-17 is_master_triggered_~__retres1~0#1 := 0; 8193#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7981#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7982#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8152#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8139#L239-15 assume !(1 == ~t1_pc~0); 8140#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 8270#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8284#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7977#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 7978#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8300#L258-15 assume !(1 == ~t2_pc~0); 8098#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 8099#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8141#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8142#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8248#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8249#L277-15 assume !(1 == ~t3_pc~0); 7952#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 7953#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8260#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8261#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7994#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7979#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7980#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8206#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8243#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8120#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7956#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7957#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9591#L519-3 assume !(1 == ~E_3~0); 9592#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9186#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9184#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9131#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 9132#L709 assume !(0 == start_simulation_~tmp~3#1); 9603#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9587#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9584#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9582#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 9580#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9579#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9578#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 9576#L722 assume !(0 != start_simulation_~tmp___0~1#1); 9572#L690-2 [2021-12-15 17:20:25,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:25,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2021-12-15 17:20:25,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:25,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749089367] [2021-12-15 17:20:25,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:25,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:25,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,012 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,012 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749089367] [2021-12-15 17:20:26,012 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749089367] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,012 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,012 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:26,012 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330395763] [2021-12-15 17:20:26,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,013 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:26,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,013 INFO L85 PathProgramCache]: Analyzing trace with hash 898681602, now seen corresponding path program 1 times [2021-12-15 17:20:26,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778098498] [2021-12-15 17:20:26,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,014 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1778098498] [2021-12-15 17:20:26,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1778098498] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,054 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,054 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,054 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140013750] [2021-12-15 17:20:26,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,054 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:26,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:26,056 INFO L87 Difference]: Start difference. First operand 2373 states and 3451 transitions. cyclomatic complexity: 1086 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,084 INFO L93 Difference]: Finished difference Result 3466 states and 5042 transitions. [2021-12-15 17:20:26,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:26,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3466 states and 5042 transitions. [2021-12-15 17:20:26,105 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3378 [2021-12-15 17:20:26,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3466 states to 3466 states and 5042 transitions. [2021-12-15 17:20:26,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3466 [2021-12-15 17:20:26,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3466 [2021-12-15 17:20:26,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3466 states and 5042 transitions. [2021-12-15 17:20:26,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,128 INFO L681 BuchiCegarLoop]: Abstraction has 3466 states and 5042 transitions. [2021-12-15 17:20:26,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3466 states and 5042 transitions. [2021-12-15 17:20:26,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3466 to 2413. [2021-12-15 17:20:26,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2413 states, 2413 states have (on average 1.4583506009117282) internal successors, (3519), 2412 states have internal predecessors, (3519), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2413 states to 2413 states and 3519 transitions. [2021-12-15 17:20:26,162 INFO L704 BuchiCegarLoop]: Abstraction has 2413 states and 3519 transitions. [2021-12-15 17:20:26,162 INFO L587 BuchiCegarLoop]: Abstraction has 2413 states and 3519 transitions. [2021-12-15 17:20:26,162 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:26,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2413 states and 3519 transitions. [2021-12-15 17:20:26,172 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2341 [2021-12-15 17:20:26,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,176 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,176 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,176 INFO L791 eck$LassoCheckResult]: Stem: 14129#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 14077#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 13899#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13866#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13867#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 13979#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13823#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13824#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13999#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13836#L441 assume !(0 == ~M_E~0); 13837#L441-2 assume !(0 == ~T1_E~0); 13974#L446-1 assume !(0 == ~T2_E~0); 13945#L451-1 assume !(0 == ~T3_E~0); 13946#L456-1 assume !(0 == ~E_M~0); 14081#L461-1 assume !(0 == ~E_1~0); 14082#L466-1 assume !(0 == ~E_2~0); 14098#L471-1 assume !(0 == ~E_3~0); 13874#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13875#L220 assume !(1 == ~m_pc~0); 13907#L220-2 is_master_triggered_~__retres1~0#1 := 0; 13908#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13960#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13903#L543 assume !(0 != activate_threads_~tmp~1#1); 13904#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14063#L239 assume !(1 == ~t1_pc~0); 14064#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14079#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14101#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14067#L551 assume !(0 != activate_threads_~tmp___0~0#1); 14068#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14069#L258 assume !(1 == ~t2_pc~0); 14070#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13936#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13795#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13796#L559 assume !(0 != activate_threads_~tmp___1~0#1); 13986#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13987#L277 assume !(1 == ~t3_pc~0); 14036#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13850#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13851#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13897#L567 assume !(0 != activate_threads_~tmp___2~0#1); 13898#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13942#L489 assume !(1 == ~M_E~0); 14080#L489-2 assume !(1 == ~T1_E~0); 14017#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13886#L499-1 assume !(1 == ~T3_E~0); 13887#L504-1 assume !(1 == ~E_M~0); 13980#L509-1 assume !(1 == ~E_1~0); 13876#L514-1 assume !(1 == ~E_2~0); 13877#L519-1 assume !(1 == ~E_3~0); 13884#L524-1 assume { :end_inline_reset_delta_events } true; 13848#L690-2 [2021-12-15 17:20:26,178 INFO L793 eck$LassoCheckResult]: Loop: 13848#L690-2 assume !false; 13849#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13779#L416 assume !false; 13817#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13913#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13860#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14073#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14074#L369 assume !(0 != eval_~tmp~0#1); 14076#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16101#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16099#L441-3 assume !(0 == ~M_E~0); 16097#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16096#L446-3 assume !(0 == ~T2_E~0); 16095#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16094#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16093#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16092#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16091#L471-3 assume !(0 == ~E_3~0); 16061#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16060#L220-15 assume !(1 == ~m_pc~0); 16059#L220-17 is_master_triggered_~__retres1~0#1 := 0; 16058#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16056#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16054#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16052#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16050#L239-15 assume !(1 == ~t1_pc~0); 16048#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 16046#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16044#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16042#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 16040#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16038#L258-15 assume !(1 == ~t2_pc~0); 16036#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 16034#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16033#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16032#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16031#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16030#L277-15 assume !(1 == ~t3_pc~0); 16028#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 16027#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16026#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16025#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16024#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15446#L489-3 assume !(1 == ~M_E~0); 14257#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14255#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14253#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14251#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14249#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14247#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14245#L519-3 assume !(1 == ~E_3~0); 14243#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14236#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 14215#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14208#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 14202#L709 assume !(0 == start_simulation_~tmp~3#1); 13786#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13787#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13882#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13883#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 13880#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13881#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14004#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13935#L722 assume !(0 != start_simulation_~tmp___0~1#1); 13848#L690-2 [2021-12-15 17:20:26,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,179 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2021-12-15 17:20:26,179 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815442872] [2021-12-15 17:20:26,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,204 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,205 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815442872] [2021-12-15 17:20:26,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815442872] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,206 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,206 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:26,206 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371204327] [2021-12-15 17:20:26,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,206 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:26,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,207 INFO L85 PathProgramCache]: Analyzing trace with hash -2097564862, now seen corresponding path program 1 times [2021-12-15 17:20:26,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135357826] [2021-12-15 17:20:26,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,248 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,250 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135357826] [2021-12-15 17:20:26,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135357826] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,253 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863207932] [2021-12-15 17:20:26,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,257 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,259 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:26,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:26,261 INFO L87 Difference]: Start difference. First operand 2413 states and 3519 transitions. cyclomatic complexity: 1110 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,316 INFO L93 Difference]: Finished difference Result 3460 states and 5000 transitions. [2021-12-15 17:20:26,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:26,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3460 states and 5000 transitions. [2021-12-15 17:20:26,332 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3378 [2021-12-15 17:20:26,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3460 states to 3460 states and 5000 transitions. [2021-12-15 17:20:26,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3460 [2021-12-15 17:20:26,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3460 [2021-12-15 17:20:26,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3460 states and 5000 transitions. [2021-12-15 17:20:26,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,350 INFO L681 BuchiCegarLoop]: Abstraction has 3460 states and 5000 transitions. [2021-12-15 17:20:26,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3460 states and 5000 transitions. [2021-12-15 17:20:26,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3460 to 2413. [2021-12-15 17:20:26,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2413 states, 2413 states have (on average 1.4479900538748447) internal successors, (3494), 2412 states have internal predecessors, (3494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2413 states to 2413 states and 3494 transitions. [2021-12-15 17:20:26,380 INFO L704 BuchiCegarLoop]: Abstraction has 2413 states and 3494 transitions. [2021-12-15 17:20:26,380 INFO L587 BuchiCegarLoop]: Abstraction has 2413 states and 3494 transitions. [2021-12-15 17:20:26,380 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:26,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2413 states and 3494 transitions. [2021-12-15 17:20:26,385 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2341 [2021-12-15 17:20:26,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,386 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,386 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,387 INFO L791 eck$LassoCheckResult]: Stem: 20030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 19968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 19786#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19751#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19752#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 19867#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19709#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19710#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19889#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19722#L441 assume !(0 == ~M_E~0); 19723#L441-2 assume !(0 == ~T1_E~0); 19862#L446-1 assume !(0 == ~T2_E~0); 19829#L451-1 assume !(0 == ~T3_E~0); 19830#L456-1 assume !(0 == ~E_M~0); 19972#L461-1 assume !(0 == ~E_1~0); 19973#L466-1 assume !(0 == ~E_2~0); 19992#L471-1 assume !(0 == ~E_3~0); 19759#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19760#L220 assume !(1 == ~m_pc~0); 19794#L220-2 is_master_triggered_~__retres1~0#1 := 0; 19795#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19848#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19792#L543 assume !(0 != activate_threads_~tmp~1#1); 19793#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19952#L239 assume !(1 == ~t1_pc~0); 19953#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19970#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19998#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19957#L551 assume !(0 != activate_threads_~tmp___0~0#1); 19958#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19959#L258 assume !(1 == ~t2_pc~0); 19960#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19820#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19680#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19681#L559 assume !(0 != activate_threads_~tmp___1~0#1); 19876#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19877#L277 assume !(1 == ~t3_pc~0); 19926#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19735#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19736#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19784#L567 assume !(0 != activate_threads_~tmp___2~0#1); 19785#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19826#L489 assume !(1 == ~M_E~0); 19971#L489-2 assume !(1 == ~T1_E~0); 19905#L494-1 assume !(1 == ~T2_E~0); 19775#L499-1 assume !(1 == ~T3_E~0); 19776#L504-1 assume !(1 == ~E_M~0); 19868#L509-1 assume !(1 == ~E_1~0); 19762#L514-1 assume !(1 == ~E_2~0); 19763#L519-1 assume !(1 == ~E_3~0); 19770#L524-1 assume { :end_inline_reset_delta_events } true; 19771#L690-2 [2021-12-15 17:20:26,387 INFO L793 eck$LassoCheckResult]: Loop: 19771#L690-2 assume !false; 21754#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21747#L416 assume !false; 21743#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21732#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21725#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21720#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21714#L369 assume !(0 != eval_~tmp~0#1); 21711#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21707#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21703#L441-3 assume !(0 == ~M_E~0); 21699#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21538#L446-3 assume !(0 == ~T2_E~0); 21535#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21511#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21507#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21299#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21297#L471-3 assume !(0 == ~E_3~0); 21296#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21295#L220-15 assume !(1 == ~m_pc~0); 21294#L220-17 is_master_triggered_~__retres1~0#1 := 0; 21293#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21292#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21290#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21288#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21286#L239-15 assume !(1 == ~t1_pc~0); 21284#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 21282#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21280#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21278#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 21276#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21274#L258-15 assume !(1 == ~t2_pc~0); 21272#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21270#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21268#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21266#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21264#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21262#L277-15 assume !(1 == ~t3_pc~0); 21259#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 21257#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21254#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21253#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21252#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21251#L489-3 assume !(1 == ~M_E~0); 20910#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21248#L494-3 assume !(1 == ~T2_E~0); 21246#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21244#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21242#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21240#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21238#L519-3 assume !(1 == ~E_3~0); 21235#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20135#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20115#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20109#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 20102#L709 assume !(0 == start_simulation_~tmp~3#1); 20103#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21774#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21771#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21770#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 21769#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21767#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21765#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 21764#L722 assume !(0 != start_simulation_~tmp___0~1#1); 19771#L690-2 [2021-12-15 17:20:26,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2021-12-15 17:20:26,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490059552] [2021-12-15 17:20:26,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,388 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,393 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,411 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,412 INFO L85 PathProgramCache]: Analyzing trace with hash 508458692, now seen corresponding path program 1 times [2021-12-15 17:20:26,412 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691558055] [2021-12-15 17:20:26,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,412 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691558055] [2021-12-15 17:20:26,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691558055] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,438 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,438 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,438 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549656088] [2021-12-15 17:20:26,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,438 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,438 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:26,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:26,439 INFO L87 Difference]: Start difference. First operand 2413 states and 3494 transitions. cyclomatic complexity: 1085 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,509 INFO L93 Difference]: Finished difference Result 4192 states and 5963 transitions. [2021-12-15 17:20:26,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:26,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4192 states and 5963 transitions. [2021-12-15 17:20:26,522 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4100 [2021-12-15 17:20:26,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4192 states to 4192 states and 5963 transitions. [2021-12-15 17:20:26,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4192 [2021-12-15 17:20:26,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4192 [2021-12-15 17:20:26,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4192 states and 5963 transitions. [2021-12-15 17:20:26,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,565 INFO L681 BuchiCegarLoop]: Abstraction has 4192 states and 5963 transitions. [2021-12-15 17:20:26,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4192 states and 5963 transitions. [2021-12-15 17:20:26,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4192 to 2449. [2021-12-15 17:20:26,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2449 states, 2449 states have (on average 1.4414046549612087) internal successors, (3530), 2448 states have internal predecessors, (3530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2449 states to 2449 states and 3530 transitions. [2021-12-15 17:20:26,595 INFO L704 BuchiCegarLoop]: Abstraction has 2449 states and 3530 transitions. [2021-12-15 17:20:26,595 INFO L587 BuchiCegarLoop]: Abstraction has 2449 states and 3530 transitions. [2021-12-15 17:20:26,595 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:26,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2449 states and 3530 transitions. [2021-12-15 17:20:26,600 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2377 [2021-12-15 17:20:26,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,601 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,601 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,601 INFO L791 eck$LassoCheckResult]: Stem: 26663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26409#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26374#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26375#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 26496#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26331#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26332#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26517#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26344#L441 assume !(0 == ~M_E~0); 26345#L441-2 assume !(0 == ~T1_E~0); 26491#L446-1 assume !(0 == ~T2_E~0); 26455#L451-1 assume !(0 == ~T3_E~0); 26456#L456-1 assume !(0 == ~E_M~0); 26605#L461-1 assume !(0 == ~E_1~0); 26606#L466-1 assume !(0 == ~E_2~0); 26621#L471-1 assume !(0 == ~E_3~0); 26382#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26383#L220 assume !(1 == ~m_pc~0); 26417#L220-2 is_master_triggered_~__retres1~0#1 := 0; 26418#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26475#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26415#L543 assume !(0 != activate_threads_~tmp~1#1); 26416#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26584#L239 assume !(1 == ~t1_pc~0); 26585#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26603#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26630#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26588#L551 assume !(0 != activate_threads_~tmp___0~0#1); 26589#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26590#L258 assume !(1 == ~t2_pc~0); 26591#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26446#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26301#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26302#L559 assume !(0 != activate_threads_~tmp___1~0#1); 26505#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26506#L277 assume !(1 == ~t3_pc~0); 26558#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26357#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26358#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26407#L567 assume !(0 != activate_threads_~tmp___2~0#1); 26408#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26452#L489 assume !(1 == ~M_E~0); 26604#L489-2 assume !(1 == ~T1_E~0); 26537#L494-1 assume !(1 == ~T2_E~0); 26396#L499-1 assume !(1 == ~T3_E~0); 26397#L504-1 assume !(1 == ~E_M~0); 26497#L509-1 assume !(1 == ~E_1~0); 26384#L514-1 assume !(1 == ~E_2~0); 26385#L519-1 assume !(1 == ~E_3~0); 26393#L524-1 assume { :end_inline_reset_delta_events } true; 26394#L690-2 [2021-12-15 17:20:26,602 INFO L793 eck$LassoCheckResult]: Loop: 26394#L690-2 assume !false; 28620#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28616#L416 assume !false; 28475#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28473#L332 assume !(0 == ~m_st~0); 28474#L336 assume !(0 == ~t1_st~0); 28472#L340 assume !(0 == ~t2_st~0); 28469#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 28468#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28467#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27863#L369 assume !(0 != eval_~tmp~0#1); 27864#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26592#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26593#L441-3 assume !(0 == ~M_E~0); 28518#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26623#L446-3 assume !(0 == ~T2_E~0); 26624#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26353#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26354#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26542#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26543#L471-3 assume !(0 == ~E_3~0); 26410#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26411#L220-15 assume !(1 == ~m_pc~0); 26472#L220-17 is_master_triggered_~__retres1~0#1 := 0; 28516#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28515#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28514#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26503#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26504#L239-15 assume !(1 == ~t1_pc~0); 26628#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 26629#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26650#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26329#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 26330#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26667#L258-15 assume !(1 == ~t2_pc~0); 26668#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 26648#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26494#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26495#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26607#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26608#L277-15 assume !(1 == ~t3_pc~0); 26306#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 26307#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28506#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26640#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26641#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26333#L489-3 assume !(1 == ~M_E~0); 26334#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26601#L494-3 assume !(1 == ~T2_E~0); 26602#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26473#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26474#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26656#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26657#L519-3 assume !(1 == ~E_3~0); 26372#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26373#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28650#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28647#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 28644#L709 assume !(0 == start_simulation_~tmp~3#1); 28642#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28640#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28635#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28633#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 28631#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28629#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28627#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 28623#L722 assume !(0 != start_simulation_~tmp___0~1#1); 26394#L690-2 [2021-12-15 17:20:26,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2021-12-15 17:20:26,602 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,602 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1041503411] [2021-12-15 17:20:26,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,603 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,607 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,616 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,616 INFO L85 PathProgramCache]: Analyzing trace with hash -2116089398, now seen corresponding path program 1 times [2021-12-15 17:20:26,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494061432] [2021-12-15 17:20:26,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,617 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:26,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:26,637 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:26,637 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494061432] [2021-12-15 17:20:26,637 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494061432] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:26,638 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:26,638 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:26,638 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598224132] [2021-12-15 17:20:26,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:26,638 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:26,638 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:26,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:26,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:26,639 INFO L87 Difference]: Start difference. First operand 2449 states and 3530 transitions. cyclomatic complexity: 1085 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:26,727 INFO L93 Difference]: Finished difference Result 7852 states and 11195 transitions. [2021-12-15 17:20:26,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:26,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7852 states and 11195 transitions. [2021-12-15 17:20:26,752 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7720 [2021-12-15 17:20:26,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7852 states to 7852 states and 11195 transitions. [2021-12-15 17:20:26,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7852 [2021-12-15 17:20:26,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7852 [2021-12-15 17:20:26,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7852 states and 11195 transitions. [2021-12-15 17:20:26,848 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:26,848 INFO L681 BuchiCegarLoop]: Abstraction has 7852 states and 11195 transitions. [2021-12-15 17:20:26,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7852 states and 11195 transitions. [2021-12-15 17:20:26,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7852 to 2485. [2021-12-15 17:20:26,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2485 states, 2485 states have (on average 1.435010060362173) internal successors, (3566), 2484 states have internal predecessors, (3566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:26,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2485 states to 2485 states and 3566 transitions. [2021-12-15 17:20:26,905 INFO L704 BuchiCegarLoop]: Abstraction has 2485 states and 3566 transitions. [2021-12-15 17:20:26,905 INFO L587 BuchiCegarLoop]: Abstraction has 2485 states and 3566 transitions. [2021-12-15 17:20:26,906 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:26,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2485 states and 3566 transitions. [2021-12-15 17:20:26,912 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2413 [2021-12-15 17:20:26,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:26,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:26,913 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,914 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:26,914 INFO L791 eck$LassoCheckResult]: Stem: 36963#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 36903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 36726#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36692#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36693#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 36804#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36649#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36650#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36823#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36662#L441 assume !(0 == ~M_E~0); 36663#L441-2 assume !(0 == ~T1_E~0); 36799#L446-1 assume !(0 == ~T2_E~0); 36768#L451-1 assume !(0 == ~T3_E~0); 36769#L456-1 assume !(0 == ~E_M~0); 36908#L461-1 assume !(0 == ~E_1~0); 36909#L466-1 assume !(0 == ~E_2~0); 36927#L471-1 assume !(0 == ~E_3~0); 36700#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36701#L220 assume !(1 == ~m_pc~0); 36734#L220-2 is_master_triggered_~__retres1~0#1 := 0; 36735#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36785#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36732#L543 assume !(0 != activate_threads_~tmp~1#1); 36733#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36889#L239 assume !(1 == ~t1_pc~0); 36890#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36905#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36933#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36894#L551 assume !(0 != activate_threads_~tmp___0~0#1); 36895#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36896#L258 assume !(1 == ~t2_pc~0); 36897#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36759#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36619#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36620#L559 assume !(0 != activate_threads_~tmp___1~0#1); 36811#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36812#L277 assume !(1 == ~t3_pc~0); 36863#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36675#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36676#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36724#L567 assume !(0 != activate_threads_~tmp___2~0#1); 36725#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36765#L489 assume !(1 == ~M_E~0); 36906#L489-2 assume !(1 == ~T1_E~0); 36841#L494-1 assume !(1 == ~T2_E~0); 36715#L499-1 assume !(1 == ~T3_E~0); 36716#L504-1 assume !(1 == ~E_M~0); 36805#L509-1 assume !(1 == ~E_1~0); 36702#L514-1 assume !(1 == ~E_2~0); 36703#L519-1 assume !(1 == ~E_3~0); 36710#L524-1 assume { :end_inline_reset_delta_events } true; 36711#L690-2 [2021-12-15 17:20:26,914 INFO L793 eck$LassoCheckResult]: Loop: 36711#L690-2 assume !false; 37943#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37938#L416 assume !false; 37937#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37935#L332 assume !(0 == ~m_st~0); 37936#L336 assume !(0 == ~t1_st~0); 37932#L340 assume !(0 == ~t2_st~0); 37933#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 37934#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37926#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37927#L369 assume !(0 != eval_~tmp~0#1); 36971#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36898#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36884#L441-3 assume !(0 == ~M_E~0); 36612#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36613#L446-3 assume !(0 == ~T2_E~0); 36879#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36880#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36739#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36740#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36846#L471-3 assume !(0 == ~E_3~0); 36728#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36729#L220-15 assume !(1 == ~m_pc~0); 36784#L220-17 is_master_triggered_~__retres1~0#1 := 0; 36852#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36653#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36654#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36810#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36800#L239-15 assume !(1 == ~t1_pc~0); 36801#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 38014#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38012#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38010#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 38008#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38006#L258-15 assume !(1 == ~t2_pc~0); 38004#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 38002#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38000#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37998#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37996#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37994#L277-15 assume !(1 == ~t3_pc~0); 37991#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 37988#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37986#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37984#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37982#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37980#L489-3 assume !(1 == ~M_E~0); 37977#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37976#L494-3 assume !(1 == ~T2_E~0); 37975#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37974#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37973#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37972#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37971#L519-3 assume !(1 == ~E_3~0); 37970#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37968#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37964#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37962#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 37958#L709 assume !(0 == start_simulation_~tmp~3#1); 37957#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37955#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37952#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37950#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 37948#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37946#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37945#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 37944#L722 assume !(0 != start_simulation_~tmp___0~1#1); 36711#L690-2 [2021-12-15 17:20:26,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2021-12-15 17:20:26,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401723272] [2021-12-15 17:20:26,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,922 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:26,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:26,932 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:26,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:26,933 INFO L85 PathProgramCache]: Analyzing trace with hash -2116148980, now seen corresponding path program 1 times [2021-12-15 17:20:26,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:26,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459664655] [2021-12-15 17:20:26,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:26,934 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:26,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:27,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:27,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:27,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459664655] [2021-12-15 17:20:27,003 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459664655] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:27,003 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:27,003 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:27,003 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302999160] [2021-12-15 17:20:27,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:27,003 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:27,003 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:27,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:27,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:27,004 INFO L87 Difference]: Start difference. First operand 2485 states and 3566 transitions. cyclomatic complexity: 1085 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:27,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:27,128 INFO L93 Difference]: Finished difference Result 4924 states and 7015 transitions. [2021-12-15 17:20:27,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:27,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4924 states and 7015 transitions. [2021-12-15 17:20:27,143 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4844 [2021-12-15 17:20:27,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4924 states to 4924 states and 7015 transitions. [2021-12-15 17:20:27,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4924 [2021-12-15 17:20:27,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4924 [2021-12-15 17:20:27,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4924 states and 7015 transitions. [2021-12-15 17:20:27,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:27,173 INFO L681 BuchiCegarLoop]: Abstraction has 4924 states and 7015 transitions. [2021-12-15 17:20:27,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4924 states and 7015 transitions. [2021-12-15 17:20:27,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4924 to 2566. [2021-12-15 17:20:27,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2566 states, 2566 states have (on average 1.4127045985970381) internal successors, (3625), 2565 states have internal predecessors, (3625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:27,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2566 states to 2566 states and 3625 transitions. [2021-12-15 17:20:27,209 INFO L704 BuchiCegarLoop]: Abstraction has 2566 states and 3625 transitions. [2021-12-15 17:20:27,210 INFO L587 BuchiCegarLoop]: Abstraction has 2566 states and 3625 transitions. [2021-12-15 17:20:27,210 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:27,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2566 states and 3625 transitions. [2021-12-15 17:20:27,246 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2494 [2021-12-15 17:20:27,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:27,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:27,247 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,247 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,247 INFO L791 eck$LassoCheckResult]: Stem: 44415#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 44342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 44148#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44113#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44114#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 44233#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44070#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44071#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44254#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44083#L441 assume !(0 == ~M_E~0); 44084#L441-2 assume !(0 == ~T1_E~0); 44227#L446-1 assume !(0 == ~T2_E~0); 44192#L451-1 assume !(0 == ~T3_E~0); 44193#L456-1 assume !(0 == ~E_M~0); 44349#L461-1 assume !(0 == ~E_1~0); 44350#L466-1 assume !(0 == ~E_2~0); 44370#L471-1 assume !(0 == ~E_3~0); 44121#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44122#L220 assume !(1 == ~m_pc~0); 44156#L220-2 is_master_triggered_~__retres1~0#1 := 0; 44157#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44212#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 44154#L543 assume !(0 != activate_threads_~tmp~1#1); 44155#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44327#L239 assume !(1 == ~t1_pc~0); 44328#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44346#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44382#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44332#L551 assume !(0 != activate_threads_~tmp___0~0#1); 44333#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44334#L258 assume !(1 == ~t2_pc~0); 44335#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44185#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44041#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44042#L559 assume !(0 != activate_threads_~tmp___1~0#1); 44240#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44241#L277 assume !(1 == ~t3_pc~0); 44299#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44096#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44097#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44146#L567 assume !(0 != activate_threads_~tmp___2~0#1); 44147#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44189#L489 assume !(1 == ~M_E~0); 44347#L489-2 assume !(1 == ~T1_E~0); 44275#L494-1 assume !(1 == ~T2_E~0); 44137#L499-1 assume !(1 == ~T3_E~0); 44138#L504-1 assume !(1 == ~E_M~0); 44234#L509-1 assume !(1 == ~E_1~0); 44123#L514-1 assume !(1 == ~E_2~0); 44124#L519-1 assume !(1 == ~E_3~0); 44132#L524-1 assume { :end_inline_reset_delta_events } true; 44133#L690-2 [2021-12-15 17:20:27,247 INFO L793 eck$LassoCheckResult]: Loop: 44133#L690-2 assume !false; 45333#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45319#L416 assume !false; 45314#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45308#L332 assume !(0 == ~m_st~0); 45309#L336 assume !(0 == ~t1_st~0); 45305#L340 assume !(0 == ~t2_st~0); 45306#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 45307#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 44986#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44987#L369 assume !(0 != eval_~tmp~0#1); 46391#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46390#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46389#L441-3 assume !(0 == ~M_E~0); 46388#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46387#L446-3 assume !(0 == ~T2_E~0); 46386#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46385#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46384#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46383#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46382#L471-3 assume !(0 == ~E_3~0); 44149#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44150#L220-15 assume !(1 == ~m_pc~0); 44211#L220-17 is_master_triggered_~__retres1~0#1 := 0; 45492#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45490#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45488#L543-15 assume !(0 != activate_threads_~tmp~1#1); 45486#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45484#L239-15 assume !(1 == ~t1_pc~0); 45482#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 45480#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45478#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45476#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 45474#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45471#L258-15 assume !(1 == ~t2_pc~0); 45467#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 45463#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45459#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45455#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45451#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45447#L277-15 assume !(1 == ~t3_pc~0); 45442#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 45438#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45434#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45430#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45425#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45421#L489-3 assume !(1 == ~M_E~0); 45407#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45413#L494-3 assume !(1 == ~T2_E~0); 45351#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45345#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45343#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45341#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45338#L519-3 assume !(1 == ~E_3~0); 45336#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45322#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 45315#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 45310#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 45156#L709 assume !(0 == start_simulation_~tmp~3#1); 45157#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45349#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 45344#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 45342#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 45340#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45337#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45335#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 45334#L722 assume !(0 != start_simulation_~tmp___0~1#1); 44133#L690-2 [2021-12-15 17:20:27,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,248 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2021-12-15 17:20:27,248 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503037139] [2021-12-15 17:20:27,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,265 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:27,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,286 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:27,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,287 INFO L85 PathProgramCache]: Analyzing trace with hash -1692502258, now seen corresponding path program 1 times [2021-12-15 17:20:27,287 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60693639] [2021-12-15 17:20:27,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:27,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:27,316 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:27,316 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60693639] [2021-12-15 17:20:27,316 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60693639] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:27,316 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:27,316 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:27,316 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695243135] [2021-12-15 17:20:27,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:27,317 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:27,317 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:27,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:27,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:27,317 INFO L87 Difference]: Start difference. First operand 2566 states and 3625 transitions. cyclomatic complexity: 1063 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:27,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:27,345 INFO L93 Difference]: Finished difference Result 3876 states and 5379 transitions. [2021-12-15 17:20:27,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:27,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3876 states and 5379 transitions. [2021-12-15 17:20:27,366 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3802 [2021-12-15 17:20:27,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3876 states to 3876 states and 5379 transitions. [2021-12-15 17:20:27,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3876 [2021-12-15 17:20:27,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3876 [2021-12-15 17:20:27,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3876 states and 5379 transitions. [2021-12-15 17:20:27,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:27,396 INFO L681 BuchiCegarLoop]: Abstraction has 3876 states and 5379 transitions. [2021-12-15 17:20:27,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3876 states and 5379 transitions. [2021-12-15 17:20:27,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3876 to 3744. [2021-12-15 17:20:27,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3744 states, 3744 states have (on average 1.390224358974359) internal successors, (5205), 3743 states have internal predecessors, (5205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:27,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3744 states to 3744 states and 5205 transitions. [2021-12-15 17:20:27,496 INFO L704 BuchiCegarLoop]: Abstraction has 3744 states and 5205 transitions. [2021-12-15 17:20:27,496 INFO L587 BuchiCegarLoop]: Abstraction has 3744 states and 5205 transitions. [2021-12-15 17:20:27,496 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:27,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3744 states and 5205 transitions. [2021-12-15 17:20:27,504 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3670 [2021-12-15 17:20:27,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:27,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:27,514 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,514 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:27,514 INFO L791 eck$LassoCheckResult]: Stem: 50852#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 50791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 50597#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50563#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50564#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 50684#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50520#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50521#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50705#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50533#L441 assume !(0 == ~M_E~0); 50534#L441-2 assume !(0 == ~T1_E~0); 50677#L446-1 assume !(0 == ~T2_E~0); 50640#L451-1 assume !(0 == ~T3_E~0); 50641#L456-1 assume !(0 == ~E_M~0); 50795#L461-1 assume !(0 == ~E_1~0); 50796#L466-1 assume !(0 == ~E_2~0); 50817#L471-1 assume !(0 == ~E_3~0); 50571#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50572#L220 assume !(1 == ~m_pc~0); 50605#L220-2 is_master_triggered_~__retres1~0#1 := 0; 50606#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50658#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50603#L543 assume !(0 != activate_threads_~tmp~1#1); 50604#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50776#L239 assume !(1 == ~t1_pc~0); 50777#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50793#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50822#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50782#L551 assume !(0 != activate_threads_~tmp___0~0#1); 50783#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50784#L258 assume !(1 == ~t2_pc~0); 50785#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50631#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50489#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50490#L559 assume !(0 != activate_threads_~tmp___1~0#1); 50693#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50694#L277 assume !(1 == ~t3_pc~0); 50743#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50545#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50546#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50595#L567 assume !(0 != activate_threads_~tmp___2~0#1); 50596#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50637#L489 assume !(1 == ~M_E~0); 50794#L489-2 assume !(1 == ~T1_E~0); 50722#L494-1 assume !(1 == ~T2_E~0); 50584#L499-1 assume !(1 == ~T3_E~0); 50585#L504-1 assume !(1 == ~E_M~0); 50685#L509-1 assume !(1 == ~E_1~0); 50573#L514-1 assume !(1 == ~E_2~0); 50574#L519-1 assume !(1 == ~E_3~0); 50580#L524-1 assume { :end_inline_reset_delta_events } true; 50581#L690-2 assume !false; 51812#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51806#L416 [2021-12-15 17:20:27,514 INFO L793 eck$LassoCheckResult]: Loop: 51806#L416 assume !false; 51803#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 51800#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 51797#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 51791#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 51788#L369 assume 0 != eval_~tmp~0#1; 51784#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 51771#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 51772#L374 assume !(0 == ~t1_st~0); 51735#L388 assume !(0 == ~t2_st~0); 51811#L402 assume !(0 == ~t3_st~0); 51806#L416 [2021-12-15 17:20:27,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,515 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2021-12-15 17:20:27,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849901744] [2021-12-15 17:20:27,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,520 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:27,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,544 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:27,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,544 INFO L85 PathProgramCache]: Analyzing trace with hash 258292880, now seen corresponding path program 1 times [2021-12-15 17:20:27,544 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702227418] [2021-12-15 17:20:27,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,544 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,547 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:27,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:27,549 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:27,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:27,550 INFO L85 PathProgramCache]: Analyzing trace with hash 1139971210, now seen corresponding path program 1 times [2021-12-15 17:20:27,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:27,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393370815] [2021-12-15 17:20:27,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:27,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:27,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:27,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:27,588 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:27,588 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393370815] [2021-12-15 17:20:27,588 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393370815] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:27,588 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:27,588 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:27,588 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772486365] [2021-12-15 17:20:27,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:27,649 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:27,652 INFO L158 Benchmark]: Toolchain (without parser) took 4154.40ms. Allocated memory was 90.2MB in the beginning and 234.9MB in the end (delta: 144.7MB). Free memory was 56.4MB in the beginning and 100.0MB in the end (delta: -43.6MB). Peak memory consumption was 101.5MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,652 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 90.2MB. Free memory was 62.8MB in the beginning and 62.8MB in the end (delta: 18.9kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:27,653 INFO L158 Benchmark]: CACSL2BoogieTranslator took 346.09ms. Allocated memory was 90.2MB in the beginning and 111.1MB in the end (delta: 21.0MB). Free memory was 56.2MB in the beginning and 85.1MB in the end (delta: -28.9MB). Peak memory consumption was 9.8MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,653 INFO L158 Benchmark]: Boogie Procedure Inliner took 69.23ms. Allocated memory is still 111.1MB. Free memory was 85.1MB in the beginning and 81.7MB in the end (delta: 3.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,653 INFO L158 Benchmark]: Boogie Preprocessor took 64.73ms. Allocated memory is still 111.1MB. Free memory was 81.7MB in the beginning and 78.4MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,653 INFO L158 Benchmark]: RCFGBuilder took 695.13ms. Allocated memory is still 111.1MB. Free memory was 78.4MB in the beginning and 76.8MB in the end (delta: 1.6MB). Peak memory consumption was 25.4MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,653 INFO L158 Benchmark]: BuchiAutomizer took 2973.67ms. Allocated memory was 111.1MB in the beginning and 234.9MB in the end (delta: 123.7MB). Free memory was 76.8MB in the beginning and 100.0MB in the end (delta: -23.2MB). Peak memory consumption was 99.9MB. Max. memory is 16.1GB. [2021-12-15 17:20:27,654 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 90.2MB. Free memory was 62.8MB in the beginning and 62.8MB in the end (delta: 18.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 346.09ms. Allocated memory was 90.2MB in the beginning and 111.1MB in the end (delta: 21.0MB). Free memory was 56.2MB in the beginning and 85.1MB in the end (delta: -28.9MB). Peak memory consumption was 9.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 69.23ms. Allocated memory is still 111.1MB. Free memory was 85.1MB in the beginning and 81.7MB in the end (delta: 3.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 64.73ms. Allocated memory is still 111.1MB. Free memory was 81.7MB in the beginning and 78.4MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 695.13ms. Allocated memory is still 111.1MB. Free memory was 78.4MB in the beginning and 76.8MB in the end (delta: 1.6MB). Peak memory consumption was 25.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 2973.67ms. Allocated memory was 111.1MB in the beginning and 234.9MB in the end (delta: 123.7MB). Free memory was 76.8MB in the beginning and 100.0MB in the end (delta: -23.2MB). Peak memory consumption was 99.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:27,679 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable