./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:26,111 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:26,113 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:26,160 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:26,161 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:26,162 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:26,163 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:26,164 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:26,166 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:26,167 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:26,167 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:26,168 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:26,169 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:26,170 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:26,171 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:26,172 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:26,173 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:26,173 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:26,175 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:26,177 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:26,178 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:26,179 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:26,180 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:26,181 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:26,183 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:26,184 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:26,184 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:26,185 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:26,185 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:26,186 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:26,186 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:26,187 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:26,187 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:26,188 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:26,189 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:26,189 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:26,190 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:26,190 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:26,190 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:26,191 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:26,192 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:26,193 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:26,211 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:26,211 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:26,211 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:26,212 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:26,213 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:26,213 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:26,213 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:26,213 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:26,214 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:26,214 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:26,214 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:26,214 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:26,215 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:26,215 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:26,215 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:26,215 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:26,216 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:26,216 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:26,216 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:26,216 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:26,217 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:26,217 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:26,217 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:26,217 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:26,217 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:26,218 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:26,218 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:26,218 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:26,218 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:26,218 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:26,219 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:26,219 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:26,219 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:26,220 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2021-12-15 17:20:26,416 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:26,435 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:26,439 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:26,439 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:26,440 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:26,441 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-12-15 17:20:26,495 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6629cb52d/d9b6abe0d61849df9cfbac5e3d1834d1/FLAGe144c425b [2021-12-15 17:20:26,883 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:26,883 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-12-15 17:20:26,892 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6629cb52d/d9b6abe0d61849df9cfbac5e3d1834d1/FLAGe144c425b [2021-12-15 17:20:27,293 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6629cb52d/d9b6abe0d61849df9cfbac5e3d1834d1 [2021-12-15 17:20:27,295 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:27,296 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:27,298 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:27,298 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:27,301 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:27,302 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,302 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@649cf74c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27, skipping insertion in model container [2021-12-15 17:20:27,303 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,311 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:27,350 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:27,476 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[671,684] [2021-12-15 17:20:27,531 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:27,539 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:27,548 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[671,684] [2021-12-15 17:20:27,578 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:27,592 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:27,592 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27 WrapperNode [2021-12-15 17:20:27,593 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:27,593 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:27,594 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:27,594 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:27,600 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,623 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,692 INFO L137 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 94, statements flattened = 1341 [2021-12-15 17:20:27,693 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:27,693 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:27,693 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:27,694 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:27,710 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,710 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,719 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,720 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,739 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,761 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,776 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,785 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:27,786 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:27,786 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:27,787 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:27,787 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,796 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:27,803 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:27,813 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:27,835 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:27,849 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:27,849 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:27,850 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:27,853 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:27,920 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:27,922 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:28,795 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:28,813 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:28,814 INFO L301 CfgBuilder]: Removed 8 assume(true) statements. [2021-12-15 17:20:28,817 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:28 BoogieIcfgContainer [2021-12-15 17:20:28,817 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:28,819 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:28,819 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:28,822 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:28,822 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:28,823 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:27" (1/3) ... [2021-12-15 17:20:28,824 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1959638a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:28, skipping insertion in model container [2021-12-15 17:20:28,824 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:28,824 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (2/3) ... [2021-12-15 17:20:28,825 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1959638a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:28, skipping insertion in model container [2021-12-15 17:20:28,825 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:28,825 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:28" (3/3) ... [2021-12-15 17:20:28,826 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2021-12-15 17:20:28,871 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:28,871 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:28,871 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:28,871 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:28,871 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:28,871 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:28,871 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:28,871 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:28,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 469 [2021-12-15 17:20:28,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:28,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:28,971 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,971 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,971 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:28,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 469 [2021-12-15 17:20:28,992 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:28,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:28,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,999 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,011 INFO L791 eck$LassoCheckResult]: Stem: 544#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 465#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 213#L891true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14#L407true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 547#L414true assume !(1 == ~m_i~0);~m_st~0 := 2; 223#L414-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 415#L419-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 414#L424-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 204#L429-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 407#L434-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 468#L439-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 202#L599true assume 0 == ~M_E~0;~M_E~0 := 1; 359#L599-2true assume !(0 == ~T1_E~0); 16#L604-1true assume !(0 == ~T2_E~0); 11#L609-1true assume !(0 == ~T3_E~0); 85#L614-1true assume !(0 == ~T4_E~0); 155#L619-1true assume !(0 == ~T5_E~0); 228#L624-1true assume !(0 == ~E_M~0); 505#L629-1true assume !(0 == ~E_1~0); 52#L634-1true assume 0 == ~E_2~0;~E_2~0 := 1; 326#L639-1true assume !(0 == ~E_3~0); 400#L644-1true assume !(0 == ~E_4~0); 349#L649-1true assume !(0 == ~E_5~0); 35#L654-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90#L292true assume !(1 == ~m_pc~0); 183#L292-2true is_master_triggered_~__retres1~0#1 := 0; 263#L303true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 524#L304true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 484#L743true assume !(0 != activate_threads_~tmp~1#1); 69#L743-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 325#L311true assume 1 == ~t1_pc~0; 139#L312true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 233#L322true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3#L323true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25#L751true assume !(0 != activate_threads_~tmp___0~0#1); 430#L751-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 328#L330true assume 1 == ~t2_pc~0; 158#L331true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 91#L341true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30#L342true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 459#L759true assume !(0 != activate_threads_~tmp___1~0#1); 469#L759-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86#L349true assume !(1 == ~t3_pc~0); 509#L349-2true is_transmit3_triggered_~__retres1~3#1 := 0; 296#L360true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220#L361true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 531#L767true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 450#L767-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 532#L368true assume 1 == ~t4_pc~0; 461#L369true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 390#L379true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215#L380true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 440#L775true assume !(0 != activate_threads_~tmp___3~0#1); 17#L775-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 474#L387true assume !(1 == ~t5_pc~0); 244#L387-2true is_transmit5_triggered_~__retres1~5#1 := 0; 541#L398true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67#L399true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75#L783true assume !(0 != activate_threads_~tmp___4~0#1); 121#L783-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 179#L667true assume !(1 == ~M_E~0); 334#L667-2true assume !(1 == ~T1_E~0); 339#L672-1true assume !(1 == ~T2_E~0); 147#L677-1true assume !(1 == ~T3_E~0); 308#L682-1true assume !(1 == ~T4_E~0); 402#L687-1true assume !(1 == ~T5_E~0); 470#L692-1true assume !(1 == ~E_M~0); 295#L697-1true assume 1 == ~E_1~0;~E_1~0 := 2; 523#L702-1true assume !(1 == ~E_2~0); 348#L707-1true assume !(1 == ~E_3~0); 216#L712-1true assume !(1 == ~E_4~0); 333#L717-1true assume !(1 == ~E_5~0); 317#L722-1true assume { :end_inline_reset_delta_events } true; 22#L928-2true [2021-12-15 17:20:29,014 INFO L793 eck$LassoCheckResult]: Loop: 22#L928-2true assume !false; 219#L929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40#L574true assume !true; 160#L589true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96#L407-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 260#L599-3true assume 0 == ~M_E~0;~M_E~0 := 1; 307#L599-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 190#L604-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 513#L609-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 248#L614-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 26#L619-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 258#L624-3true assume !(0 == ~E_M~0); 304#L629-3true assume 0 == ~E_1~0;~E_1~0 := 1; 398#L634-3true assume 0 == ~E_2~0;~E_2~0 := 1; 318#L639-3true assume 0 == ~E_3~0;~E_3~0 := 1; 453#L644-3true assume 0 == ~E_4~0;~E_4~0 := 1; 516#L649-3true assume 0 == ~E_5~0;~E_5~0 := 1; 196#L654-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294#L292-21true assume !(1 == ~m_pc~0); 124#L292-23true is_master_triggered_~__retres1~0#1 := 0; 60#L303-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363#L304-7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 432#L743-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 186#L743-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L311-21true assume 1 == ~t1_pc~0; 543#L312-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38#L322-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201#L323-7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 466#L751-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89#L751-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 283#L330-21true assume 1 == ~t2_pc~0; 478#L331-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 255#L341-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109#L342-7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274#L759-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65#L759-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 212#L349-21true assume !(1 == ~t3_pc~0); 366#L349-23true is_transmit3_triggered_~__retres1~3#1 := 0; 387#L360-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 483#L361-7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 321#L767-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 457#L767-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100#L368-21true assume 1 == ~t4_pc~0; 46#L369-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 384#L379-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7#L380-7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 360#L775-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13#L775-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41#L387-21true assume 1 == ~t5_pc~0; 243#L388-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 336#L398-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10#L399-7true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 394#L783-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62#L783-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185#L667-3true assume !(1 == ~M_E~0); 54#L667-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 330#L672-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 88#L677-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 549#L682-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 379#L687-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 113#L692-3true assume 1 == ~E_M~0;~E_M~0 := 2; 495#L697-3true assume 1 == ~E_1~0;~E_1~0 := 2; 167#L702-3true assume !(1 == ~E_2~0); 264#L707-3true assume 1 == ~E_3~0;~E_3~0 := 2; 292#L712-3true assume 1 == ~E_4~0;~E_4~0 := 2; 59#L717-3true assume 1 == ~E_5~0;~E_5~0 := 2; 287#L722-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 456#L452-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 389#L484-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 504#L485-1true start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 192#L947true assume !(0 == start_simulation_~tmp~3#1); 525#L947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 195#L452-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 322#L484-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 429#L485-2true stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 376#L902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 332#L909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 293#L910true start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 280#L960true assume !(0 != start_simulation_~tmp___0~1#1); 22#L928-2true [2021-12-15 17:20:29,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,021 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2021-12-15 17:20:29,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345707124] [2021-12-15 17:20:29,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,034 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,221 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345707124] [2021-12-15 17:20:29,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345707124] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268883848] [2021-12-15 17:20:29,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,228 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,229 INFO L85 PathProgramCache]: Analyzing trace with hash -1256885446, now seen corresponding path program 1 times [2021-12-15 17:20:29,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618394366] [2021-12-15 17:20:29,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,230 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,253 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,253 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618394366] [2021-12-15 17:20:29,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618394366] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,254 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,254 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:29,254 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485634790] [2021-12-15 17:20:29,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,255 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,256 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,286 INFO L87 Difference]: Start difference. First operand has 552 states, 551 states have (on average 1.528130671506352) internal successors, (842), 551 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,341 INFO L93 Difference]: Finished difference Result 551 states and 823 transitions. [2021-12-15 17:20:29,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 823 transitions. [2021-12-15 17:20:29,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 546 states and 818 transitions. [2021-12-15 17:20:29,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2021-12-15 17:20:29,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2021-12-15 17:20:29,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 818 transitions. [2021-12-15 17:20:29,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,365 INFO L681 BuchiCegarLoop]: Abstraction has 546 states and 818 transitions. [2021-12-15 17:20:29,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 818 transitions. [2021-12-15 17:20:29,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2021-12-15 17:20:29,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4981684981684982) internal successors, (818), 545 states have internal predecessors, (818), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 818 transitions. [2021-12-15 17:20:29,410 INFO L704 BuchiCegarLoop]: Abstraction has 546 states and 818 transitions. [2021-12-15 17:20:29,410 INFO L587 BuchiCegarLoop]: Abstraction has 546 states and 818 transitions. [2021-12-15 17:20:29,410 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:29,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 818 transitions. [2021-12-15 17:20:29,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,416 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,416 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,416 INFO L791 eck$LassoCheckResult]: Stem: 1657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1477#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1133#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1134#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1489#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1490#L419-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1628#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1467#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1468#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1624#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1465#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 1466#L599-2 assume !(0 == ~T1_E~0); 1137#L604-1 assume !(0 == ~T2_E~0); 1126#L609-1 assume !(0 == ~T3_E~0); 1127#L614-1 assume !(0 == ~T4_E~0); 1286#L619-1 assume !(0 == ~T5_E~0); 1405#L624-1 assume !(0 == ~E_M~0); 1494#L629-1 assume !(0 == ~E_1~0); 1214#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1215#L639-1 assume !(0 == ~E_3~0); 1586#L644-1 assume !(0 == ~E_4~0); 1598#L649-1 assume !(0 == ~E_5~0); 1177#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1178#L292 assume !(1 == ~m_pc~0); 1296#L292-2 is_master_triggered_~__retres1~0#1 := 0; 1437#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1535#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1650#L743 assume !(0 != activate_threads_~tmp~1#1); 1251#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1252#L311 assume 1 == ~t1_pc~0; 1374#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1375#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1112#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1113#L751 assume !(0 != activate_threads_~tmp___0~0#1); 1153#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1587#L330 assume 1 == ~t2_pc~0; 1407#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1298#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1165#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1166#L759 assume !(0 != activate_threads_~tmp___1~0#1); 1645#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1287#L349 assume !(1 == ~t3_pc~0); 1288#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1332#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1485#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1486#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1641#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1642#L368 assume 1 == ~t4_pc~0; 1646#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1363#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1478#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1479#L775 assume !(0 != activate_threads_~tmp___3~0#1); 1138#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1139#L387 assume !(1 == ~t5_pc~0); 1510#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1511#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1247#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1248#L783 assume !(0 != activate_threads_~tmp___4~0#1); 1264#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1351#L667 assume !(1 == ~M_E~0); 1431#L667-2 assume !(1 == ~T1_E~0); 1591#L672-1 assume !(1 == ~T2_E~0); 1390#L677-1 assume !(1 == ~T3_E~0); 1391#L682-1 assume !(1 == ~T4_E~0); 1567#L687-1 assume !(1 == ~T5_E~0); 1621#L692-1 assume !(1 == ~E_M~0); 1558#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1559#L702-1 assume !(1 == ~E_2~0); 1597#L707-1 assume !(1 == ~E_3~0); 1480#L712-1 assume !(1 == ~E_4~0); 1481#L717-1 assume !(1 == ~E_5~0); 1577#L722-1 assume { :end_inline_reset_delta_events } true; 1148#L928-2 [2021-12-15 17:20:29,417 INFO L793 eck$LassoCheckResult]: Loop: 1148#L928-2 assume !false; 1149#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1188#L574 assume !false; 1189#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1640#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1338#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1302#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1182#L499 assume !(0 != eval_~tmp~0#1); 1183#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1306#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1307#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1533#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1447#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1448#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1517#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1154#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1155#L624-3 assume !(0 == ~E_M~0); 1529#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1565#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1578#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1579#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1643#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1457#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1458#L292-21 assume 1 == ~m_pc~0; 1536#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1233#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1234#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1605#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1440#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1441#L311-21 assume 1 == ~t1_pc~0; 1620#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1184#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1185#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1461#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1294#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1295#L330-21 assume 1 == ~t2_pc~0; 1549#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1525#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1327#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1328#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1243#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1244#L349-21 assume !(1 == ~t3_pc~0); 1475#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 1607#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1616#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1581#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1582#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1312#L368-21 assume 1 == ~t4_pc~0; 1202#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1203#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1118#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1119#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1131#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1132#L387-21 assume 1 == ~t5_pc~0; 1190#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1509#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1124#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1125#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1235#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1236#L667-3 assume !(1 == ~M_E~0); 1221#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1222#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1292#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1293#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1614#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1333#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1334#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1414#L702-3 assume !(1 == ~E_2~0); 1415#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1534#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1227#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1228#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1553#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1160#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1618#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1450#L947 assume !(0 == start_simulation_~tmp~3#1); 1451#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1454#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1418#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1583#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 1613#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1589#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1555#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1545#L960 assume !(0 != start_simulation_~tmp___0~1#1); 1148#L928-2 [2021-12-15 17:20:29,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2021-12-15 17:20:29,418 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,418 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379128020] [2021-12-15 17:20:29,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,468 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379128020] [2021-12-15 17:20:29,469 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [379128020] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,469 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,469 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707000456] [2021-12-15 17:20:29,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,470 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,471 INFO L85 PathProgramCache]: Analyzing trace with hash 354999345, now seen corresponding path program 1 times [2021-12-15 17:20:29,471 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039763863] [2021-12-15 17:20:29,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,472 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,541 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039763863] [2021-12-15 17:20:29,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039763863] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,541 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,542 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,542 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868443852] [2021-12-15 17:20:29,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,542 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,542 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,543 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,543 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,543 INFO L87 Difference]: Start difference. First operand 546 states and 818 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,579 INFO L93 Difference]: Finished difference Result 546 states and 817 transitions. [2021-12-15 17:20:29,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 817 transitions. [2021-12-15 17:20:29,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 817 transitions. [2021-12-15 17:20:29,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2021-12-15 17:20:29,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2021-12-15 17:20:29,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 817 transitions. [2021-12-15 17:20:29,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,596 INFO L681 BuchiCegarLoop]: Abstraction has 546 states and 817 transitions. [2021-12-15 17:20:29,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 817 transitions. [2021-12-15 17:20:29,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2021-12-15 17:20:29,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4963369963369964) internal successors, (817), 545 states have internal predecessors, (817), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 817 transitions. [2021-12-15 17:20:29,620 INFO L704 BuchiCegarLoop]: Abstraction has 546 states and 817 transitions. [2021-12-15 17:20:29,620 INFO L587 BuchiCegarLoop]: Abstraction has 546 states and 817 transitions. [2021-12-15 17:20:29,620 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:29,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 817 transitions. [2021-12-15 17:20:29,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,631 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,631 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,632 INFO L791 eck$LassoCheckResult]: Stem: 2756#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2747#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2576#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2232#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2233#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2588#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2589#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2727#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2566#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2567#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2723#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2564#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 2565#L599-2 assume !(0 == ~T1_E~0); 2236#L604-1 assume !(0 == ~T2_E~0); 2225#L609-1 assume !(0 == ~T3_E~0); 2226#L614-1 assume !(0 == ~T4_E~0); 2385#L619-1 assume !(0 == ~T5_E~0); 2504#L624-1 assume !(0 == ~E_M~0); 2593#L629-1 assume !(0 == ~E_1~0); 2313#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2314#L639-1 assume !(0 == ~E_3~0); 2685#L644-1 assume !(0 == ~E_4~0); 2698#L649-1 assume !(0 == ~E_5~0); 2276#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2277#L292 assume !(1 == ~m_pc~0); 2395#L292-2 is_master_triggered_~__retres1~0#1 := 0; 2536#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2634#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2749#L743 assume !(0 != activate_threads_~tmp~1#1); 2350#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2351#L311 assume 1 == ~t1_pc~0; 2473#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2474#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2211#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2212#L751 assume !(0 != activate_threads_~tmp___0~0#1); 2252#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2686#L330 assume 1 == ~t2_pc~0; 2506#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2397#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2264#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2265#L759 assume !(0 != activate_threads_~tmp___1~0#1); 2744#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2386#L349 assume !(1 == ~t3_pc~0); 2387#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2433#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2584#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2585#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2740#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2741#L368 assume 1 == ~t4_pc~0; 2745#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2464#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2577#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2578#L775 assume !(0 != activate_threads_~tmp___3~0#1); 2237#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2238#L387 assume !(1 == ~t5_pc~0); 2609#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2610#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2348#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2349#L783 assume !(0 != activate_threads_~tmp___4~0#1); 2363#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2450#L667 assume !(1 == ~M_E~0); 2530#L667-2 assume !(1 == ~T1_E~0); 2690#L672-1 assume !(1 == ~T2_E~0); 2489#L677-1 assume !(1 == ~T3_E~0); 2490#L682-1 assume !(1 == ~T4_E~0); 2666#L687-1 assume !(1 == ~T5_E~0); 2720#L692-1 assume !(1 == ~E_M~0); 2657#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2658#L702-1 assume !(1 == ~E_2~0); 2696#L707-1 assume !(1 == ~E_3~0); 2579#L712-1 assume !(1 == ~E_4~0); 2580#L717-1 assume !(1 == ~E_5~0); 2676#L722-1 assume { :end_inline_reset_delta_events } true; 2247#L928-2 [2021-12-15 17:20:29,633 INFO L793 eck$LassoCheckResult]: Loop: 2247#L928-2 assume !false; 2248#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2287#L574 assume !false; 2288#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2739#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2437#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2401#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2281#L499 assume !(0 != eval_~tmp~0#1); 2282#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2406#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2407#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2632#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2546#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2547#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2616#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2253#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2254#L624-3 assume !(0 == ~E_M~0); 2628#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2664#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2677#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2678#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2742#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2556#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2557#L292-21 assume !(1 == ~m_pc~0); 2453#L292-23 is_master_triggered_~__retres1~0#1 := 0; 2332#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2333#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2704#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2539#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2540#L311-21 assume !(1 == ~t1_pc~0); 2467#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 2283#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2284#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2560#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2393#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2394#L330-21 assume 1 == ~t2_pc~0; 2648#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2624#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2426#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2427#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2344#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2345#L349-21 assume !(1 == ~t3_pc~0); 2574#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2706#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2715#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2680#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2681#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2411#L368-21 assume 1 == ~t4_pc~0; 2301#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2302#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2217#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2218#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2227#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2228#L387-21 assume 1 == ~t5_pc~0; 2289#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2607#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2221#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2222#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2334#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2335#L667-3 assume !(1 == ~M_E~0); 2315#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2316#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2391#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2392#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2713#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2431#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2432#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2513#L702-3 assume !(1 == ~E_2~0); 2514#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2633#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2328#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2329#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2652#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2259#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2717#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2549#L947 assume !(0 == start_simulation_~tmp~3#1); 2550#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2553#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2517#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2682#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 2712#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2688#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2654#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2644#L960 assume !(0 != start_simulation_~tmp___0~1#1); 2247#L928-2 [2021-12-15 17:20:29,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,636 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2021-12-15 17:20:29,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262614968] [2021-12-15 17:20:29,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,637 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,700 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262614968] [2021-12-15 17:20:29,700 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262614968] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,700 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,700 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,701 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405165702] [2021-12-15 17:20:29,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,702 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,702 INFO L85 PathProgramCache]: Analyzing trace with hash 275402867, now seen corresponding path program 1 times [2021-12-15 17:20:29,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863038265] [2021-12-15 17:20:29,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,704 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,780 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,780 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863038265] [2021-12-15 17:20:29,781 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [863038265] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,781 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,781 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,781 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922745426] [2021-12-15 17:20:29,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,782 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,783 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,784 INFO L87 Difference]: Start difference. First operand 546 states and 817 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,797 INFO L93 Difference]: Finished difference Result 546 states and 816 transitions. [2021-12-15 17:20:29,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 816 transitions. [2021-12-15 17:20:29,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 816 transitions. [2021-12-15 17:20:29,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2021-12-15 17:20:29,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2021-12-15 17:20:29,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 816 transitions. [2021-12-15 17:20:29,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,806 INFO L681 BuchiCegarLoop]: Abstraction has 546 states and 816 transitions. [2021-12-15 17:20:29,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 816 transitions. [2021-12-15 17:20:29,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2021-12-15 17:20:29,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4945054945054945) internal successors, (816), 545 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 816 transitions. [2021-12-15 17:20:29,816 INFO L704 BuchiCegarLoop]: Abstraction has 546 states and 816 transitions. [2021-12-15 17:20:29,816 INFO L587 BuchiCegarLoop]: Abstraction has 546 states and 816 transitions. [2021-12-15 17:20:29,816 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:29,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 816 transitions. [2021-12-15 17:20:29,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,821 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,821 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,822 INFO L791 eck$LassoCheckResult]: Stem: 3855#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3675#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3331#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3332#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 3687#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3688#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3826#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3667#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3668#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3822#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3663#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 3664#L599-2 assume !(0 == ~T1_E~0); 3335#L604-1 assume !(0 == ~T2_E~0); 3324#L609-1 assume !(0 == ~T3_E~0); 3325#L614-1 assume !(0 == ~T4_E~0); 3484#L619-1 assume !(0 == ~T5_E~0); 3603#L624-1 assume !(0 == ~E_M~0); 3692#L629-1 assume !(0 == ~E_1~0); 3412#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3413#L639-1 assume !(0 == ~E_3~0); 3784#L644-1 assume !(0 == ~E_4~0); 3797#L649-1 assume !(0 == ~E_5~0); 3375#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3376#L292 assume !(1 == ~m_pc~0); 3494#L292-2 is_master_triggered_~__retres1~0#1 := 0; 3635#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3733#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3848#L743 assume !(0 != activate_threads_~tmp~1#1); 3449#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3450#L311 assume 1 == ~t1_pc~0; 3572#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3310#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3311#L751 assume !(0 != activate_threads_~tmp___0~0#1); 3351#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3785#L330 assume 1 == ~t2_pc~0; 3605#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3496#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3365#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3366#L759 assume !(0 != activate_threads_~tmp___1~0#1); 3843#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3485#L349 assume !(1 == ~t3_pc~0); 3486#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3532#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3683#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3684#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3839#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3840#L368 assume 1 == ~t4_pc~0; 3844#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3563#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3676#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3677#L775 assume !(0 != activate_threads_~tmp___3~0#1); 3336#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3337#L387 assume !(1 == ~t5_pc~0); 3708#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3709#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3447#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3448#L783 assume !(0 != activate_threads_~tmp___4~0#1); 3465#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3551#L667 assume !(1 == ~M_E~0); 3629#L667-2 assume !(1 == ~T1_E~0); 3789#L672-1 assume !(1 == ~T2_E~0); 3588#L677-1 assume !(1 == ~T3_E~0); 3589#L682-1 assume !(1 == ~T4_E~0); 3765#L687-1 assume !(1 == ~T5_E~0); 3819#L692-1 assume !(1 == ~E_M~0); 3756#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3757#L702-1 assume !(1 == ~E_2~0); 3795#L707-1 assume !(1 == ~E_3~0); 3678#L712-1 assume !(1 == ~E_4~0); 3679#L717-1 assume !(1 == ~E_5~0); 3775#L722-1 assume { :end_inline_reset_delta_events } true; 3346#L928-2 [2021-12-15 17:20:29,823 INFO L793 eck$LassoCheckResult]: Loop: 3346#L928-2 assume !false; 3347#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3386#L574 assume !false; 3387#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3838#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3536#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3500#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3380#L499 assume !(0 != eval_~tmp~0#1); 3381#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3505#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3506#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3731#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3645#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3646#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3716#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3352#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3353#L624-3 assume !(0 == ~E_M~0); 3727#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3763#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3776#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3777#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3841#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3655#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3656#L292-21 assume !(1 == ~m_pc~0); 3552#L292-23 is_master_triggered_~__retres1~0#1 := 0; 3431#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3432#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3803#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3638#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3639#L311-21 assume 1 == ~t1_pc~0; 3818#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3382#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3383#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3659#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3492#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3493#L330-21 assume 1 == ~t2_pc~0; 3744#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3723#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3525#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3526#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3438#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3439#L349-21 assume !(1 == ~t3_pc~0); 3673#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3805#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3814#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3779#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3780#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3510#L368-21 assume 1 == ~t4_pc~0; 3400#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3401#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3316#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3317#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3329#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3330#L387-21 assume 1 == ~t5_pc~0; 3388#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3706#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3320#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3321#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3433#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3434#L667-3 assume !(1 == ~M_E~0); 3414#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3415#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3490#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3491#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3812#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3530#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3531#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3612#L702-3 assume !(1 == ~E_2~0); 3613#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3732#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3427#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3428#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3751#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3358#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3816#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3648#L947 assume !(0 == start_simulation_~tmp~3#1); 3649#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3652#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3616#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3781#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 3811#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3787#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3755#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3743#L960 assume !(0 != start_simulation_~tmp___0~1#1); 3346#L928-2 [2021-12-15 17:20:29,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,824 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2021-12-15 17:20:29,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946150152] [2021-12-15 17:20:29,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,880 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946150152] [2021-12-15 17:20:29,880 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [946150152] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,881 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,881 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,881 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129478543] [2021-12-15 17:20:29,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,882 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1383531506, now seen corresponding path program 1 times [2021-12-15 17:20:29,882 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908296776] [2021-12-15 17:20:29,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,883 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,939 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908296776] [2021-12-15 17:20:29,940 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908296776] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,940 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,941 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,941 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028962375] [2021-12-15 17:20:29,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,941 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,942 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,943 INFO L87 Difference]: Start difference. First operand 546 states and 816 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,955 INFO L93 Difference]: Finished difference Result 546 states and 815 transitions. [2021-12-15 17:20:29,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 815 transitions. [2021-12-15 17:20:29,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,962 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 815 transitions. [2021-12-15 17:20:29,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2021-12-15 17:20:29,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2021-12-15 17:20:29,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 815 transitions. [2021-12-15 17:20:29,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,964 INFO L681 BuchiCegarLoop]: Abstraction has 546 states and 815 transitions. [2021-12-15 17:20:29,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 815 transitions. [2021-12-15 17:20:29,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2021-12-15 17:20:29,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4926739926739927) internal successors, (815), 545 states have internal predecessors, (815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 815 transitions. [2021-12-15 17:20:29,974 INFO L704 BuchiCegarLoop]: Abstraction has 546 states and 815 transitions. [2021-12-15 17:20:29,974 INFO L587 BuchiCegarLoop]: Abstraction has 546 states and 815 transitions. [2021-12-15 17:20:29,974 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:29,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 815 transitions. [2021-12-15 17:20:29,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:29,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,983 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,984 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,984 INFO L791 eck$LassoCheckResult]: Stem: 4954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4774#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4430#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4431#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 4786#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4787#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4925#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4766#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4767#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4921#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4762#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 4763#L599-2 assume !(0 == ~T1_E~0); 4434#L604-1 assume !(0 == ~T2_E~0); 4423#L609-1 assume !(0 == ~T3_E~0); 4424#L614-1 assume !(0 == ~T4_E~0); 4583#L619-1 assume !(0 == ~T5_E~0); 4702#L624-1 assume !(0 == ~E_M~0); 4791#L629-1 assume !(0 == ~E_1~0); 4511#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4512#L639-1 assume !(0 == ~E_3~0); 4883#L644-1 assume !(0 == ~E_4~0); 4896#L649-1 assume !(0 == ~E_5~0); 4474#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4475#L292 assume !(1 == ~m_pc~0); 4593#L292-2 is_master_triggered_~__retres1~0#1 := 0; 4734#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4832#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4947#L743 assume !(0 != activate_threads_~tmp~1#1); 4548#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4549#L311 assume 1 == ~t1_pc~0; 4671#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4672#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4409#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4410#L751 assume !(0 != activate_threads_~tmp___0~0#1); 4450#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4884#L330 assume 1 == ~t2_pc~0; 4704#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4595#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4464#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4465#L759 assume !(0 != activate_threads_~tmp___1~0#1); 4942#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4584#L349 assume !(1 == ~t3_pc~0); 4585#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4631#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4782#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4783#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4938#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4939#L368 assume 1 == ~t4_pc~0; 4943#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4662#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4775#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4776#L775 assume !(0 != activate_threads_~tmp___3~0#1); 4435#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4436#L387 assume !(1 == ~t5_pc~0); 4807#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4808#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4546#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4547#L783 assume !(0 != activate_threads_~tmp___4~0#1); 4564#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4650#L667 assume !(1 == ~M_E~0); 4728#L667-2 assume !(1 == ~T1_E~0); 4888#L672-1 assume !(1 == ~T2_E~0); 4687#L677-1 assume !(1 == ~T3_E~0); 4688#L682-1 assume !(1 == ~T4_E~0); 4864#L687-1 assume !(1 == ~T5_E~0); 4918#L692-1 assume !(1 == ~E_M~0); 4855#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4856#L702-1 assume !(1 == ~E_2~0); 4894#L707-1 assume !(1 == ~E_3~0); 4777#L712-1 assume !(1 == ~E_4~0); 4778#L717-1 assume !(1 == ~E_5~0); 4874#L722-1 assume { :end_inline_reset_delta_events } true; 4445#L928-2 [2021-12-15 17:20:29,984 INFO L793 eck$LassoCheckResult]: Loop: 4445#L928-2 assume !false; 4446#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4485#L574 assume !false; 4486#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4937#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4635#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4599#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4479#L499 assume !(0 != eval_~tmp~0#1); 4480#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4604#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4605#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4830#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4744#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4745#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4815#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4451#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4452#L624-3 assume !(0 == ~E_M~0); 4826#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4862#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4875#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4876#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4940#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4754#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4755#L292-21 assume 1 == ~m_pc~0; 4833#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4530#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4531#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4902#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4737#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4738#L311-21 assume 1 == ~t1_pc~0; 4917#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4481#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4482#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4758#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4591#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4592#L330-21 assume 1 == ~t2_pc~0; 4844#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4822#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4624#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4625#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4537#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4538#L349-21 assume !(1 == ~t3_pc~0); 4772#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 4904#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4913#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4878#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4879#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4609#L368-21 assume 1 == ~t4_pc~0; 4499#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4500#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4415#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4416#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4428#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4429#L387-21 assume 1 == ~t5_pc~0; 4487#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4805#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4419#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4420#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4532#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4533#L667-3 assume !(1 == ~M_E~0); 4516#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4517#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4589#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4590#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4911#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4629#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4630#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4711#L702-3 assume !(1 == ~E_2~0); 4712#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4831#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4526#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4527#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4850#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4457#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4915#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4747#L947 assume !(0 == start_simulation_~tmp~3#1); 4748#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4751#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4716#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4880#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 4910#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4886#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4854#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4842#L960 assume !(0 != start_simulation_~tmp___0~1#1); 4445#L928-2 [2021-12-15 17:20:29,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,985 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2021-12-15 17:20:29,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707702599] [2021-12-15 17:20:29,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,986 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,030 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,030 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707702599] [2021-12-15 17:20:30,031 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707702599] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,031 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,031 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,031 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868529694] [2021-12-15 17:20:30,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,032 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,032 INFO L85 PathProgramCache]: Analyzing trace with hash 354999345, now seen corresponding path program 2 times [2021-12-15 17:20:30,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566212227] [2021-12-15 17:20:30,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,076 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566212227] [2021-12-15 17:20:30,077 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1566212227] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,077 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,077 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,077 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537854459] [2021-12-15 17:20:30,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,078 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,078 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:30,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:30,079 INFO L87 Difference]: Start difference. First operand 546 states and 815 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,089 INFO L93 Difference]: Finished difference Result 546 states and 814 transitions. [2021-12-15 17:20:30,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:30,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 814 transitions. [2021-12-15 17:20:30,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:30,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 814 transitions. [2021-12-15 17:20:30,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2021-12-15 17:20:30,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2021-12-15 17:20:30,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 814 transitions. [2021-12-15 17:20:30,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,099 INFO L681 BuchiCegarLoop]: Abstraction has 546 states and 814 transitions. [2021-12-15 17:20:30,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 814 transitions. [2021-12-15 17:20:30,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 546. [2021-12-15 17:20:30,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 546 states, 546 states have (on average 1.4908424908424909) internal successors, (814), 545 states have internal predecessors, (814), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 546 states and 814 transitions. [2021-12-15 17:20:30,107 INFO L704 BuchiCegarLoop]: Abstraction has 546 states and 814 transitions. [2021-12-15 17:20:30,107 INFO L587 BuchiCegarLoop]: Abstraction has 546 states and 814 transitions. [2021-12-15 17:20:30,107 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:30,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 546 states and 814 transitions. [2021-12-15 17:20:30,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 467 [2021-12-15 17:20:30,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,113 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,113 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,114 INFO L791 eck$LassoCheckResult]: Stem: 6053#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5873#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5529#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5530#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 5885#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5886#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6024#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5865#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5866#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6020#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5861#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 5862#L599-2 assume !(0 == ~T1_E~0); 5533#L604-1 assume !(0 == ~T2_E~0); 5522#L609-1 assume !(0 == ~T3_E~0); 5523#L614-1 assume !(0 == ~T4_E~0); 5682#L619-1 assume !(0 == ~T5_E~0); 5801#L624-1 assume !(0 == ~E_M~0); 5890#L629-1 assume !(0 == ~E_1~0); 5610#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5611#L639-1 assume !(0 == ~E_3~0); 5982#L644-1 assume !(0 == ~E_4~0); 5995#L649-1 assume !(0 == ~E_5~0); 5573#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5574#L292 assume !(1 == ~m_pc~0); 5692#L292-2 is_master_triggered_~__retres1~0#1 := 0; 5833#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5931#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6046#L743 assume !(0 != activate_threads_~tmp~1#1); 5647#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5648#L311 assume 1 == ~t1_pc~0; 5770#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5771#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5508#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5509#L751 assume !(0 != activate_threads_~tmp___0~0#1); 5549#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5983#L330 assume 1 == ~t2_pc~0; 5803#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5695#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5563#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5564#L759 assume !(0 != activate_threads_~tmp___1~0#1); 6041#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5683#L349 assume !(1 == ~t3_pc~0); 5684#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5730#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5881#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5882#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6037#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6038#L368 assume 1 == ~t4_pc~0; 6042#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5763#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5874#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5875#L775 assume !(0 != activate_threads_~tmp___3~0#1); 5534#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5535#L387 assume !(1 == ~t5_pc~0); 5906#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5907#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5645#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5646#L783 assume !(0 != activate_threads_~tmp___4~0#1); 5663#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5749#L667 assume !(1 == ~M_E~0); 5827#L667-2 assume !(1 == ~T1_E~0); 5987#L672-1 assume !(1 == ~T2_E~0); 5786#L677-1 assume !(1 == ~T3_E~0); 5787#L682-1 assume !(1 == ~T4_E~0); 5963#L687-1 assume !(1 == ~T5_E~0); 6017#L692-1 assume !(1 == ~E_M~0); 5954#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5955#L702-1 assume !(1 == ~E_2~0); 5993#L707-1 assume !(1 == ~E_3~0); 5876#L712-1 assume !(1 == ~E_4~0); 5877#L717-1 assume !(1 == ~E_5~0); 5973#L722-1 assume { :end_inline_reset_delta_events } true; 5544#L928-2 [2021-12-15 17:20:30,114 INFO L793 eck$LassoCheckResult]: Loop: 5544#L928-2 assume !false; 5545#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5584#L574 assume !false; 5585#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6036#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5734#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5698#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5578#L499 assume !(0 != eval_~tmp~0#1); 5579#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5703#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5704#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5929#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5844#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5845#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5914#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5550#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5551#L624-3 assume !(0 == ~E_M~0); 5925#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5961#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5974#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5975#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6039#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5853#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5854#L292-21 assume !(1 == ~m_pc~0); 5750#L292-23 is_master_triggered_~__retres1~0#1 := 0; 5629#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5630#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6001#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5836#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5837#L311-21 assume 1 == ~t1_pc~0; 6016#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5580#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5581#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5857#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5690#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5691#L330-21 assume 1 == ~t2_pc~0; 5943#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5921#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5723#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5724#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5636#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5637#L349-21 assume 1 == ~t3_pc~0; 5872#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6003#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6012#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5977#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5978#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5708#L368-21 assume !(1 == ~t4_pc~0); 5600#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5599#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5514#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5515#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5527#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5528#L387-21 assume 1 == ~t5_pc~0; 5586#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5904#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5520#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5521#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5631#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5632#L667-3 assume !(1 == ~M_E~0); 5615#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5616#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5688#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5689#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6010#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5728#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5729#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5810#L702-3 assume !(1 == ~E_2~0); 5811#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5930#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5625#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5626#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5949#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5556#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6014#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5846#L947 assume !(0 == start_simulation_~tmp~3#1); 5847#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5850#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5815#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5979#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 6009#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5985#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5953#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5941#L960 assume !(0 != start_simulation_~tmp___0~1#1); 5544#L928-2 [2021-12-15 17:20:30,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,118 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2021-12-15 17:20:30,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,118 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063271464] [2021-12-15 17:20:30,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,119 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,148 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063271464] [2021-12-15 17:20:30,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063271464] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,148 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,149 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:30,149 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498179108] [2021-12-15 17:20:30,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,150 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,152 INFO L85 PathProgramCache]: Analyzing trace with hash 610261170, now seen corresponding path program 1 times [2021-12-15 17:20:30,152 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266942774] [2021-12-15 17:20:30,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,155 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,188 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266942774] [2021-12-15 17:20:30,192 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266942774] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,192 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,192 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,192 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266161151] [2021-12-15 17:20:30,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,193 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,193 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:30,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:30,194 INFO L87 Difference]: Start difference. First operand 546 states and 814 transitions. cyclomatic complexity: 269 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,222 INFO L93 Difference]: Finished difference Result 969 states and 1439 transitions. [2021-12-15 17:20:30,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:30,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 969 states and 1439 transitions. [2021-12-15 17:20:30,228 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2021-12-15 17:20:30,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 969 states to 969 states and 1439 transitions. [2021-12-15 17:20:30,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 969 [2021-12-15 17:20:30,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 969 [2021-12-15 17:20:30,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 969 states and 1439 transitions. [2021-12-15 17:20:30,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,234 INFO L681 BuchiCegarLoop]: Abstraction has 969 states and 1439 transitions. [2021-12-15 17:20:30,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 969 states and 1439 transitions. [2021-12-15 17:20:30,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 969 to 969. [2021-12-15 17:20:30,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.4850361197110422) internal successors, (1439), 968 states have internal predecessors, (1439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1439 transitions. [2021-12-15 17:20:30,275 INFO L704 BuchiCegarLoop]: Abstraction has 969 states and 1439 transitions. [2021-12-15 17:20:30,275 INFO L587 BuchiCegarLoop]: Abstraction has 969 states and 1439 transitions. [2021-12-15 17:20:30,275 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:30,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1439 transitions. [2021-12-15 17:20:30,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2021-12-15 17:20:30,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,280 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,280 INFO L791 eck$LassoCheckResult]: Stem: 7605#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7400#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7051#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7052#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 7412#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7413#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7563#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7392#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7393#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7560#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7388#L599 assume !(0 == ~M_E~0); 7389#L599-2 assume !(0 == ~T1_E~0); 7055#L604-1 assume !(0 == ~T2_E~0); 7044#L609-1 assume !(0 == ~T3_E~0); 7045#L614-1 assume !(0 == ~T4_E~0); 7205#L619-1 assume !(0 == ~T5_E~0); 7324#L624-1 assume !(0 == ~E_M~0); 7418#L629-1 assume !(0 == ~E_1~0); 7133#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7134#L639-1 assume !(0 == ~E_3~0); 7513#L644-1 assume !(0 == ~E_4~0); 7527#L649-1 assume !(0 == ~E_5~0); 7095#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7096#L292 assume !(1 == ~m_pc~0); 7215#L292-2 is_master_triggered_~__retres1~0#1 := 0; 7359#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7459#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7592#L743 assume !(0 != activate_threads_~tmp~1#1); 7170#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7171#L311 assume 1 == ~t1_pc~0; 7293#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7294#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7030#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7031#L751 assume !(0 != activate_threads_~tmp___0~0#1); 7071#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7515#L330 assume 1 == ~t2_pc~0; 7326#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7218#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7085#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7086#L759 assume !(0 != activate_threads_~tmp___1~0#1); 7586#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7206#L349 assume !(1 == ~t3_pc~0); 7207#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7253#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7408#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7409#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7582#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7583#L368 assume 1 == ~t4_pc~0; 7587#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7286#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7401#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7402#L775 assume !(0 != activate_threads_~tmp___3~0#1); 7056#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7057#L387 assume !(1 == ~t5_pc~0); 7434#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7435#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7168#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7169#L783 assume !(0 != activate_threads_~tmp___4~0#1); 7186#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7272#L667 assume !(1 == ~M_E~0); 7353#L667-2 assume !(1 == ~T1_E~0); 7520#L672-1 assume !(1 == ~T2_E~0); 7309#L677-1 assume !(1 == ~T3_E~0); 7310#L682-1 assume !(1 == ~T4_E~0); 7492#L687-1 assume !(1 == ~T5_E~0); 7554#L692-1 assume !(1 == ~E_M~0); 7482#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7483#L702-1 assume !(1 == ~E_2~0); 7525#L707-1 assume !(1 == ~E_3~0); 7403#L712-1 assume !(1 == ~E_4~0); 7404#L717-1 assume !(1 == ~E_5~0); 7503#L722-1 assume { :end_inline_reset_delta_events } true; 7504#L928-2 [2021-12-15 17:20:30,280 INFO L793 eck$LassoCheckResult]: Loop: 7504#L928-2 assume !false; 7620#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7619#L574 assume !false; 7618#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7614#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7562#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7221#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7100#L499 assume !(0 != eval_~tmp~0#1); 7102#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7224#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7225#L599-3 assume !(0 == ~M_E~0); 7456#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7889#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7888#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7886#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7883#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7881#L624-3 assume !(0 == ~E_M~0); 7880#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7879#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7877#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7875#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7873#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7870#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7868#L292-21 assume 1 == ~m_pc~0; 7865#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7863#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7861#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7859#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7856#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7854#L311-21 assume !(1 == ~t1_pc~0); 7851#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 7849#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7847#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7845#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7842#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7840#L330-21 assume 1 == ~t2_pc~0; 7837#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7835#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7833#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7831#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7828#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7826#L349-21 assume 1 == ~t3_pc~0; 7824#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7821#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7819#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7817#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7814#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7812#L368-21 assume 1 == ~t4_pc~0; 7721#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7719#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7717#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7715#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7713#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7712#L387-21 assume !(1 == ~t5_pc~0); 7710#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7709#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7706#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7704#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7702#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7701#L667-3 assume !(1 == ~M_E~0); 7362#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7516#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7211#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7212#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7546#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7251#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7252#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7335#L702-3 assume !(1 == ~E_2~0); 7336#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7458#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7148#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7149#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7477#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7078#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7551#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7373#L947 assume !(0 == start_simulation_~tmp~3#1); 7374#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7378#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7340#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7510#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 7544#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7545#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7633#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7627#L960 assume !(0 != start_simulation_~tmp___0~1#1); 7504#L928-2 [2021-12-15 17:20:30,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,281 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2021-12-15 17:20:30,281 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,281 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285184899] [2021-12-15 17:20:30,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,282 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285184899] [2021-12-15 17:20:30,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285184899] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,305 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,305 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,305 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1656816129] [2021-12-15 17:20:30,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,306 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,306 INFO L85 PathProgramCache]: Analyzing trace with hash 759059568, now seen corresponding path program 1 times [2021-12-15 17:20:30,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716344426] [2021-12-15 17:20:30,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,332 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,332 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716344426] [2021-12-15 17:20:30,332 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716344426] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,332 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,332 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,333 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897022007] [2021-12-15 17:20:30,333 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,333 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,333 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,334 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:30,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:30,334 INFO L87 Difference]: Start difference. First operand 969 states and 1439 transitions. cyclomatic complexity: 471 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,420 INFO L93 Difference]: Finished difference Result 1341 states and 1985 transitions. [2021-12-15 17:20:30,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:30,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1341 states and 1985 transitions. [2021-12-15 17:20:30,429 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1257 [2021-12-15 17:20:30,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1341 states to 1341 states and 1985 transitions. [2021-12-15 17:20:30,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1341 [2021-12-15 17:20:30,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1341 [2021-12-15 17:20:30,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1341 states and 1985 transitions. [2021-12-15 17:20:30,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,438 INFO L681 BuchiCegarLoop]: Abstraction has 1341 states and 1985 transitions. [2021-12-15 17:20:30,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1341 states and 1985 transitions. [2021-12-15 17:20:30,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1341 to 969. [2021-12-15 17:20:30,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 969 states, 969 states have (on average 1.4819401444788443) internal successors, (1436), 968 states have internal predecessors, (1436), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 969 states to 969 states and 1436 transitions. [2021-12-15 17:20:30,455 INFO L704 BuchiCegarLoop]: Abstraction has 969 states and 1436 transitions. [2021-12-15 17:20:30,456 INFO L587 BuchiCegarLoop]: Abstraction has 969 states and 1436 transitions. [2021-12-15 17:20:30,456 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:30,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 969 states and 1436 transitions. [2021-12-15 17:20:30,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2021-12-15 17:20:30,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,461 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,461 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,461 INFO L791 eck$LassoCheckResult]: Stem: 9926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9733#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9371#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9372#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 9745#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9746#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9888#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9720#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9721#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9886#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9716#L599 assume !(0 == ~M_E~0); 9717#L599-2 assume !(0 == ~T1_E~0); 9375#L604-1 assume !(0 == ~T2_E~0); 9364#L609-1 assume !(0 == ~T3_E~0); 9365#L614-1 assume !(0 == ~T4_E~0); 9526#L619-1 assume !(0 == ~T5_E~0); 9651#L624-1 assume !(0 == ~E_M~0); 9750#L629-1 assume !(0 == ~E_1~0); 9452#L634-1 assume !(0 == ~E_2~0); 9453#L639-1 assume !(0 == ~E_3~0); 9843#L644-1 assume !(0 == ~E_4~0); 9857#L649-1 assume !(0 == ~E_5~0); 9415#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9416#L292 assume !(1 == ~m_pc~0); 9536#L292-2 is_master_triggered_~__retres1~0#1 := 0; 9687#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9792#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9911#L743 assume !(0 != activate_threads_~tmp~1#1); 9489#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9490#L311 assume 1 == ~t1_pc~0; 9620#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9621#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9350#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9351#L751 assume !(0 != activate_threads_~tmp___0~0#1); 9391#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9845#L330 assume 1 == ~t2_pc~0; 9653#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9540#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9405#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9406#L759 assume !(0 != activate_threads_~tmp___1~0#1); 9905#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9527#L349 assume !(1 == ~t3_pc~0); 9528#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9575#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9741#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9742#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9901#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9902#L368 assume 1 == ~t4_pc~0; 9906#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9611#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9734#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9735#L775 assume !(0 != activate_threads_~tmp___3~0#1); 9376#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9377#L387 assume !(1 == ~t5_pc~0); 9767#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9768#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9487#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9488#L783 assume !(0 != activate_threads_~tmp___4~0#1); 9505#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9594#L667 assume !(1 == ~M_E~0); 9681#L667-2 assume !(1 == ~T1_E~0); 9849#L672-1 assume !(1 == ~T2_E~0); 9636#L677-1 assume !(1 == ~T3_E~0); 9637#L682-1 assume !(1 == ~T4_E~0); 9824#L687-1 assume !(1 == ~T5_E~0); 9880#L692-1 assume !(1 == ~E_M~0); 9815#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9816#L702-1 assume !(1 == ~E_2~0); 9855#L707-1 assume !(1 == ~E_3~0); 9736#L712-1 assume !(1 == ~E_4~0); 9737#L717-1 assume !(1 == ~E_5~0); 9834#L722-1 assume { :end_inline_reset_delta_events } true; 9386#L928-2 [2021-12-15 17:20:30,462 INFO L793 eck$LassoCheckResult]: Loop: 9386#L928-2 assume !false; 9387#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9426#L574 assume !false; 9427#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9900#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9579#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9545#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9420#L499 assume !(0 != eval_~tmp~0#1); 9421#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9548#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9549#L599-3 assume !(0 == ~M_E~0); 9790#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9698#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9699#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9774#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9392#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9393#L624-3 assume !(0 == ~E_M~0); 9786#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9822#L634-3 assume !(0 == ~E_2~0); 9835#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9836#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9903#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9707#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9708#L292-21 assume 1 == ~m_pc~0; 9793#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9471#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9472#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9863#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9690#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9691#L311-21 assume 1 == ~t1_pc~0; 9878#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9422#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9423#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9712#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9534#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9535#L330-21 assume 1 == ~t2_pc~0; 9804#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9782#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9568#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9569#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9481#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9482#L349-21 assume !(1 == ~t3_pc~0); 9729#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 9865#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9874#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9838#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9839#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9553#L368-21 assume 1 == ~t4_pc~0; 9440#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9441#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9356#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9357#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9369#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9370#L387-21 assume 1 == ~t5_pc~0; 9428#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9766#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9362#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9363#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9473#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9474#L667-3 assume !(1 == ~M_E~0); 9457#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9458#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9532#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9533#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9872#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9573#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9574#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9663#L702-3 assume !(1 == ~E_2~0); 9664#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9791#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9467#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9468#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9810#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9398#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9876#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9700#L947 assume !(0 == start_simulation_~tmp~3#1); 9701#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9704#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9668#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9840#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 9871#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9847#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9814#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9802#L960 assume !(0 != start_simulation_~tmp___0~1#1); 9386#L928-2 [2021-12-15 17:20:30,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,462 INFO L85 PathProgramCache]: Analyzing trace with hash -1945891710, now seen corresponding path program 1 times [2021-12-15 17:20:30,463 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009549371] [2021-12-15 17:20:30,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,463 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009549371] [2021-12-15 17:20:30,488 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009549371] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,489 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,489 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:30,489 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413242850] [2021-12-15 17:20:30,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,490 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,490 INFO L85 PathProgramCache]: Analyzing trace with hash 510254765, now seen corresponding path program 1 times [2021-12-15 17:20:30,491 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579006933] [2021-12-15 17:20:30,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,497 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,520 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579006933] [2021-12-15 17:20:30,521 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579006933] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,522 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,522 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,523 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699662438] [2021-12-15 17:20:30,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,523 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,524 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:30,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:30,524 INFO L87 Difference]: Start difference. First operand 969 states and 1436 transitions. cyclomatic complexity: 468 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,571 INFO L93 Difference]: Finished difference Result 1753 states and 2579 transitions. [2021-12-15 17:20:30,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:30,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1753 states and 2579 transitions. [2021-12-15 17:20:30,582 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2021-12-15 17:20:30,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1753 states to 1753 states and 2579 transitions. [2021-12-15 17:20:30,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1753 [2021-12-15 17:20:30,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1753 [2021-12-15 17:20:30,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1753 states and 2579 transitions. [2021-12-15 17:20:30,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,597 INFO L681 BuchiCegarLoop]: Abstraction has 1753 states and 2579 transitions. [2021-12-15 17:20:30,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1753 states and 2579 transitions. [2021-12-15 17:20:30,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1753 to 1749. [2021-12-15 17:20:30,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1749 states, 1749 states have (on average 1.4722698684962836) internal successors, (2575), 1748 states have internal predecessors, (2575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1749 states to 1749 states and 2575 transitions. [2021-12-15 17:20:30,647 INFO L704 BuchiCegarLoop]: Abstraction has 1749 states and 2575 transitions. [2021-12-15 17:20:30,647 INFO L587 BuchiCegarLoop]: Abstraction has 1749 states and 2575 transitions. [2021-12-15 17:20:30,647 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:30,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1749 states and 2575 transitions. [2021-12-15 17:20:30,653 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1669 [2021-12-15 17:20:30,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,655 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,655 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,655 INFO L791 eck$LassoCheckResult]: Stem: 12682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12447#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12100#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12101#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 12459#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12460#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12632#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12437#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12438#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12625#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12432#L599 assume !(0 == ~M_E~0); 12433#L599-2 assume !(0 == ~T1_E~0); 12104#L604-1 assume !(0 == ~T2_E~0); 12093#L609-1 assume !(0 == ~T3_E~0); 12094#L614-1 assume !(0 == ~T4_E~0); 12255#L619-1 assume !(0 == ~T5_E~0); 12373#L624-1 assume !(0 == ~E_M~0); 12465#L629-1 assume !(0 == ~E_1~0); 12182#L634-1 assume !(0 == ~E_2~0); 12183#L639-1 assume !(0 == ~E_3~0); 12566#L644-1 assume !(0 == ~E_4~0); 12582#L649-1 assume !(0 == ~E_5~0); 12144#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12145#L292 assume !(1 == ~m_pc~0); 12265#L292-2 is_master_triggered_~__retres1~0#1 := 0; 12406#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12508#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12664#L743 assume !(0 != activate_threads_~tmp~1#1); 12220#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12221#L311 assume !(1 == ~t1_pc~0); 12565#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12472#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12079#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12080#L751 assume !(0 != activate_threads_~tmp___0~0#1); 12120#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12568#L330 assume 1 == ~t2_pc~0; 12375#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12267#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12132#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12133#L759 assume !(0 != activate_threads_~tmp___1~0#1); 12655#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12256#L349 assume !(1 == ~t3_pc~0); 12257#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12301#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12455#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12456#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12651#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12652#L368 assume 1 == ~t4_pc~0; 12656#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12333#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12448#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12449#L775 assume !(0 != activate_threads_~tmp___3~0#1); 12105#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12106#L387 assume !(1 == ~t5_pc~0); 12484#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12485#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12216#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12217#L783 assume !(0 != activate_threads_~tmp___4~0#1); 12233#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12320#L667 assume !(1 == ~M_E~0); 12400#L667-2 assume !(1 == ~T1_E~0); 12572#L672-1 assume !(1 == ~T2_E~0); 12358#L677-1 assume !(1 == ~T3_E~0); 12359#L682-1 assume !(1 == ~T4_E~0); 12546#L687-1 assume !(1 == ~T5_E~0); 12620#L692-1 assume !(1 == ~E_M~0); 12535#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12536#L702-1 assume !(1 == ~E_2~0); 12581#L707-1 assume !(1 == ~E_3~0); 12450#L712-1 assume !(1 == ~E_4~0); 12451#L717-1 assume !(1 == ~E_5~0); 12556#L722-1 assume { :end_inline_reset_delta_events } true; 12115#L928-2 [2021-12-15 17:20:30,655 INFO L793 eck$LassoCheckResult]: Loop: 12115#L928-2 assume !false; 12116#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12156#L574 assume !false; 12157#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12982#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12979#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12271#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12149#L499 assume !(0 != eval_~tmp~0#1); 12150#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12975#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12973#L599-3 assume !(0 == ~M_E~0); 12969#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12970#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12964#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12965#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12958#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12959#L624-3 assume !(0 == ~E_M~0); 12949#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12950#L634-3 assume !(0 == ~E_2~0); 12943#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12944#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12937#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12938#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12931#L292-21 assume !(1 == ~m_pc~0); 12929#L292-23 is_master_triggered_~__retres1~0#1 := 0; 12928#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12913#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12914#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12890#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12618#L311-21 assume !(1 == ~t1_pc~0); 12619#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 13322#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13320#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13317#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13312#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13305#L330-21 assume 1 == ~t2_pc~0; 13301#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13299#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13297#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13291#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13288#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13286#L349-21 assume !(1 == ~t3_pc~0); 13282#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 13276#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13273#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13270#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13267#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13264#L368-21 assume 1 == ~t4_pc~0; 13260#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13257#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13253#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13250#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13248#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13244#L387-21 assume !(1 == ~t5_pc~0); 13240#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 13238#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13236#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13234#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13232#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13228#L667-3 assume !(1 == ~M_E~0); 13226#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13224#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13222#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13220#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13218#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13216#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13214#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13212#L702-3 assume !(1 == ~E_2~0); 13210#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13208#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13207#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13206#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13146#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13138#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13135#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 13133#L947 assume !(0 == start_simulation_~tmp~3#1); 13130#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12909#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12902#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12897#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 12606#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12571#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12534#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12520#L960 assume !(0 != start_simulation_~tmp___0~1#1); 12115#L928-2 [2021-12-15 17:20:30,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,656 INFO L85 PathProgramCache]: Analyzing trace with hash -47361405, now seen corresponding path program 1 times [2021-12-15 17:20:30,656 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,656 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213430000] [2021-12-15 17:20:30,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,657 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,681 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213430000] [2021-12-15 17:20:30,682 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213430000] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,682 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,682 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,682 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043784708] [2021-12-15 17:20:30,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,683 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1340812688, now seen corresponding path program 1 times [2021-12-15 17:20:30,683 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307225754] [2021-12-15 17:20:30,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,704 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307225754] [2021-12-15 17:20:30,704 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307225754] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,705 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,705 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,705 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340300114] [2021-12-15 17:20:30,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,705 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,706 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:30,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:30,706 INFO L87 Difference]: Start difference. First operand 1749 states and 2575 transitions. cyclomatic complexity: 828 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,828 INFO L93 Difference]: Finished difference Result 4011 states and 5848 transitions. [2021-12-15 17:20:30,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:30,829 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4011 states and 5848 transitions. [2021-12-15 17:20:30,851 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3916 [2021-12-15 17:20:30,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4011 states to 4011 states and 5848 transitions. [2021-12-15 17:20:30,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4011 [2021-12-15 17:20:30,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4011 [2021-12-15 17:20:30,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4011 states and 5848 transitions. [2021-12-15 17:20:30,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,877 INFO L681 BuchiCegarLoop]: Abstraction has 4011 states and 5848 transitions. [2021-12-15 17:20:30,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4011 states and 5848 transitions. [2021-12-15 17:20:30,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4011 to 3209. [2021-12-15 17:20:30,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3209 states, 3209 states have (on average 1.464942349641633) internal successors, (4701), 3208 states have internal predecessors, (4701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3209 states to 3209 states and 4701 transitions. [2021-12-15 17:20:30,965 INFO L704 BuchiCegarLoop]: Abstraction has 3209 states and 4701 transitions. [2021-12-15 17:20:30,965 INFO L587 BuchiCegarLoop]: Abstraction has 3209 states and 4701 transitions. [2021-12-15 17:20:30,965 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:30,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3209 states and 4701 transitions. [2021-12-15 17:20:30,976 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3128 [2021-12-15 17:20:30,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,979 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,979 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,979 INFO L791 eck$LassoCheckResult]: Stem: 18483#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 18441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 18222#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17870#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17871#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 18236#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18237#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18412#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18211#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18212#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18410#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18204#L599 assume !(0 == ~M_E~0); 18205#L599-2 assume !(0 == ~T1_E~0); 17874#L604-1 assume !(0 == ~T2_E~0); 17863#L609-1 assume !(0 == ~T3_E~0); 17864#L614-1 assume !(0 == ~T4_E~0); 18022#L619-1 assume !(0 == ~T5_E~0); 18142#L624-1 assume !(0 == ~E_M~0); 18243#L629-1 assume !(0 == ~E_1~0); 17951#L634-1 assume !(0 == ~E_2~0); 17952#L639-1 assume !(0 == ~E_3~0); 18357#L644-1 assume !(0 == ~E_4~0); 18374#L649-1 assume !(0 == ~E_5~0); 17914#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17915#L292 assume !(1 == ~m_pc~0); 18032#L292-2 is_master_triggered_~__retres1~0#1 := 0; 18177#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18293#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18447#L743 assume !(0 != activate_threads_~tmp~1#1); 17989#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17990#L311 assume !(1 == ~t1_pc~0); 18356#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18250#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17849#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17850#L751 assume !(0 != activate_threads_~tmp___0~0#1); 17890#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18359#L330 assume !(1 == ~t2_pc~0); 18314#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18035#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17904#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17905#L759 assume !(0 != activate_threads_~tmp___1~0#1); 18437#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18023#L349 assume !(1 == ~t3_pc~0); 18024#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18070#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18230#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18231#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18432#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18433#L368 assume 1 == ~t4_pc~0; 18438#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18105#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18223#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18224#L775 assume !(0 != activate_threads_~tmp___3~0#1); 17875#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17876#L387 assume !(1 == ~t5_pc~0); 18265#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18266#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17987#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17988#L783 assume !(0 != activate_threads_~tmp___4~0#1); 18004#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18088#L667 assume !(1 == ~M_E~0); 18171#L667-2 assume !(1 == ~T1_E~0); 18365#L672-1 assume !(1 == ~T2_E~0); 18127#L677-1 assume !(1 == ~T3_E~0); 18128#L682-1 assume !(1 == ~T4_E~0); 18332#L687-1 assume !(1 == ~T5_E~0); 18403#L692-1 assume !(1 == ~E_M~0); 18322#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18323#L702-1 assume !(1 == ~E_2~0); 18372#L707-1 assume !(1 == ~E_3~0); 18225#L712-1 assume !(1 == ~E_4~0); 18226#L717-1 assume !(1 == ~E_5~0); 18347#L722-1 assume { :end_inline_reset_delta_events } true; 17885#L928-2 [2021-12-15 17:20:30,980 INFO L793 eck$LassoCheckResult]: Loop: 17885#L928-2 assume !false; 17886#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17925#L574 assume !false; 17926#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18428#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18074#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18038#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17919#L499 assume !(0 != eval_~tmp~0#1); 17920#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21057#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18289#L599-3 assume !(0 == ~M_E~0); 18290#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18187#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18188#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18272#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17891#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17892#L624-3 assume !(0 == ~E_M~0); 18286#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18330#L634-3 assume !(0 == ~E_2~0); 18348#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18349#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18434#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18467#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21035#L292-21 assume 1 == ~m_pc~0; 18294#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17971#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17972#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18381#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18181#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18182#L311-21 assume !(1 == ~t1_pc~0); 18106#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 17921#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17922#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18203#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21013#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21011#L330-21 assume !(1 == ~t2_pc~0); 19684#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 18281#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18282#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18301#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17981#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17982#L349-21 assume !(1 == ~t3_pc~0); 18219#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 21006#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21005#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21004#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21003#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21002#L368-21 assume 1 == ~t4_pc~0; 21000#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20999#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20998#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20997#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20996#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20995#L387-21 assume !(1 == ~t5_pc~0); 20993#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 20992#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20991#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20969#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20968#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20967#L667-3 assume !(1 == ~M_E~0); 18180#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18360#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18028#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18029#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18392#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18393#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20892#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20891#L702-3 assume !(1 == ~E_2~0); 20890#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20889#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20888#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20887#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 20885#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18398#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18399#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18190#L947 assume !(0 == start_simulation_~tmp~3#1); 18191#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18196#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18157#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18353#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 18391#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18363#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18319#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 18304#L960 assume !(0 != start_simulation_~tmp___0~1#1); 17885#L928-2 [2021-12-15 17:20:30,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,980 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2021-12-15 17:20:30,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533639191] [2021-12-15 17:20:30,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533639191] [2021-12-15 17:20:31,021 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533639191] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,021 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,021 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:31,021 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384251315] [2021-12-15 17:20:31,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,022 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:31,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,023 INFO L85 PathProgramCache]: Analyzing trace with hash -901141520, now seen corresponding path program 1 times [2021-12-15 17:20:31,023 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245097760] [2021-12-15 17:20:31,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245097760] [2021-12-15 17:20:31,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245097760] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,056 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:31,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178321770] [2021-12-15 17:20:31,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,057 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,057 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:31,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:31,058 INFO L87 Difference]: Start difference. First operand 3209 states and 4701 transitions. cyclomatic complexity: 1494 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,210 INFO L93 Difference]: Finished difference Result 8020 states and 11774 transitions. [2021-12-15 17:20:31,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:31,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8020 states and 11774 transitions. [2021-12-15 17:20:31,274 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7872 [2021-12-15 17:20:31,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8020 states to 8020 states and 11774 transitions. [2021-12-15 17:20:31,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8020 [2021-12-15 17:20:31,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8020 [2021-12-15 17:20:31,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8020 states and 11774 transitions. [2021-12-15 17:20:31,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:31,344 INFO L681 BuchiCegarLoop]: Abstraction has 8020 states and 11774 transitions. [2021-12-15 17:20:31,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8020 states and 11774 transitions. [2021-12-15 17:20:31,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8020 to 3368. [2021-12-15 17:20:31,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3368 states, 3368 states have (on average 1.4429928741092637) internal successors, (4860), 3367 states have internal predecessors, (4860), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3368 states to 3368 states and 4860 transitions. [2021-12-15 17:20:31,422 INFO L704 BuchiCegarLoop]: Abstraction has 3368 states and 4860 transitions. [2021-12-15 17:20:31,422 INFO L587 BuchiCegarLoop]: Abstraction has 3368 states and 4860 transitions. [2021-12-15 17:20:31,422 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:31,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3368 states and 4860 transitions. [2021-12-15 17:20:31,430 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3284 [2021-12-15 17:20:31,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,432 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,432 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,432 INFO L791 eck$LassoCheckResult]: Stem: 29754#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 29706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 29472#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29114#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29115#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 29485#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29486#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29672#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29459#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29460#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29666#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29454#L599 assume !(0 == ~M_E~0); 29455#L599-2 assume !(0 == ~T1_E~0); 29118#L604-1 assume !(0 == ~T2_E~0); 29107#L609-1 assume !(0 == ~T3_E~0); 29108#L614-1 assume !(0 == ~T4_E~0); 29268#L619-1 assume !(0 == ~T5_E~0); 29390#L624-1 assume !(0 == ~E_M~0); 29493#L629-1 assume !(0 == ~E_1~0); 29196#L634-1 assume !(0 == ~E_2~0); 29197#L639-1 assume !(0 == ~E_3~0); 29612#L644-1 assume !(0 == ~E_4~0); 29629#L649-1 assume !(0 == ~E_5~0); 29158#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29159#L292 assume !(1 == ~m_pc~0); 29278#L292-2 is_master_triggered_~__retres1~0#1 := 0; 29425#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29541#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29717#L743 assume !(0 != activate_threads_~tmp~1#1); 29234#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29235#L311 assume !(1 == ~t1_pc~0); 29611#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29500#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29093#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29094#L751 assume !(0 != activate_threads_~tmp___0~0#1); 29134#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29614#L330 assume !(1 == ~t2_pc~0); 29568#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29280#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29146#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29147#L759 assume !(0 != activate_threads_~tmp___1~0#1); 29702#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29269#L349 assume !(1 == ~t3_pc~0); 29270#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29576#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29577#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29746#L767 assume !(0 != activate_threads_~tmp___2~0#1); 29694#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29695#L368 assume 1 == ~t4_pc~0; 29703#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29349#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29474#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29475#L775 assume !(0 != activate_threads_~tmp___3~0#1); 29119#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29120#L387 assume !(1 == ~t5_pc~0); 29513#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29514#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29230#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29231#L783 assume !(0 != activate_threads_~tmp___4~0#1); 29247#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29332#L667 assume !(1 == ~M_E~0); 29419#L667-2 assume !(1 == ~T1_E~0); 29619#L672-1 assume !(1 == ~T2_E~0); 29375#L677-1 assume !(1 == ~T3_E~0); 29376#L682-1 assume !(1 == ~T4_E~0); 29589#L687-1 assume !(1 == ~T5_E~0); 29660#L692-1 assume !(1 == ~E_M~0); 29574#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 29575#L702-1 assume !(1 == ~E_2~0); 29628#L707-1 assume !(1 == ~E_3~0); 29476#L712-1 assume !(1 == ~E_4~0); 29477#L717-1 assume !(1 == ~E_5~0); 29601#L722-1 assume { :end_inline_reset_delta_events } true; 29602#L928-2 [2021-12-15 17:20:31,432 INFO L793 eck$LassoCheckResult]: Loop: 29602#L928-2 assume !false; 30832#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30830#L574 assume !false; 30828#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30817#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30813#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30811#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30809#L499 assume !(0 != eval_~tmp~0#1); 30810#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32223#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32192#L599-3 assume !(0 == ~M_E~0); 32191#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32190#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29738#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29521#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29135#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29136#L624-3 assume !(0 == ~E_M~0); 29535#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29585#L634-3 assume !(0 == ~E_2~0); 29603#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29604#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29697#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29447#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29448#L292-21 assume 1 == ~m_pc~0; 29543#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29213#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29214#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29638#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29430#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29431#L311-21 assume !(1 == ~t1_pc~0); 29354#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 29165#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29166#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29453#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29276#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29277#L330-21 assume !(1 == ~t2_pc~0); 29563#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 30154#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30153#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30152#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30151#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30150#L349-21 assume 1 == ~t3_pc~0; 30148#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30146#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30144#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30142#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30126#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30124#L368-21 assume 1 == ~t4_pc~0; 30121#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30118#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30116#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30114#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30112#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30110#L387-21 assume !(1 == ~t5_pc~0); 30107#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 30104#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30102#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30100#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30098#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30092#L667-3 assume !(1 == ~M_E~0); 30012#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30010#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30008#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30006#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30004#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30002#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30000#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29998#L702-3 assume !(1 == ~E_2~0); 29995#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29996#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31012#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31011#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30992#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30986#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30983#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 30981#L947 assume !(0 == start_simulation_~tmp~3#1); 30978#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30971#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30965#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30963#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 30961#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30959#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30958#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 30954#L960 assume !(0 != start_simulation_~tmp___0~1#1); 29602#L928-2 [2021-12-15 17:20:31,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,433 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2021-12-15 17:20:31,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772598117] [2021-12-15 17:20:31,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,455 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772598117] [2021-12-15 17:20:31,455 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772598117] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,455 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,455 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:31,456 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213503430] [2021-12-15 17:20:31,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,456 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:31,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,457 INFO L85 PathProgramCache]: Analyzing trace with hash 1495295471, now seen corresponding path program 1 times [2021-12-15 17:20:31,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627854678] [2021-12-15 17:20:31,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,489 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627854678] [2021-12-15 17:20:31,490 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627854678] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,490 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,490 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:31,490 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027053725] [2021-12-15 17:20:31,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,491 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,491 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:31,492 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:31,492 INFO L87 Difference]: Start difference. First operand 3368 states and 4860 transitions. cyclomatic complexity: 1494 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,552 INFO L93 Difference]: Finished difference Result 6235 states and 8957 transitions. [2021-12-15 17:20:31,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:31,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6235 states and 8957 transitions. [2021-12-15 17:20:31,576 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6132 [2021-12-15 17:20:31,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6235 states to 6235 states and 8957 transitions. [2021-12-15 17:20:31,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6235 [2021-12-15 17:20:31,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6235 [2021-12-15 17:20:31,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6235 states and 8957 transitions. [2021-12-15 17:20:31,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:31,617 INFO L681 BuchiCegarLoop]: Abstraction has 6235 states and 8957 transitions. [2021-12-15 17:20:31,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6235 states and 8957 transitions. [2021-12-15 17:20:31,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6235 to 6219. [2021-12-15 17:20:31,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6219 states, 6219 states have (on average 1.437690947097604) internal successors, (8941), 6218 states have internal predecessors, (8941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6219 states to 6219 states and 8941 transitions. [2021-12-15 17:20:31,784 INFO L704 BuchiCegarLoop]: Abstraction has 6219 states and 8941 transitions. [2021-12-15 17:20:31,784 INFO L587 BuchiCegarLoop]: Abstraction has 6219 states and 8941 transitions. [2021-12-15 17:20:31,784 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:31,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6219 states and 8941 transitions. [2021-12-15 17:20:31,801 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6116 [2021-12-15 17:20:31,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,802 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,802 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,803 INFO L791 eck$LassoCheckResult]: Stem: 39336#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 39297#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 39078#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38726#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38727#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 39090#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39091#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39269#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39069#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39070#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39265#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39065#L599 assume !(0 == ~M_E~0); 39066#L599-2 assume !(0 == ~T1_E~0); 38730#L604-1 assume !(0 == ~T2_E~0); 38719#L609-1 assume !(0 == ~T3_E~0); 38720#L614-1 assume !(0 == ~T4_E~0); 38878#L619-1 assume !(0 == ~T5_E~0); 39000#L624-1 assume !(0 == ~E_M~0); 39097#L629-1 assume !(0 == ~E_1~0); 38807#L634-1 assume !(0 == ~E_2~0); 38808#L639-1 assume !(0 == ~E_3~0); 39208#L644-1 assume !(0 == ~E_4~0); 39224#L649-1 assume !(0 == ~E_5~0); 38770#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38771#L292 assume !(1 == ~m_pc~0); 38888#L292-2 is_master_triggered_~__retres1~0#1 := 0; 39032#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39143#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39307#L743 assume !(0 != activate_threads_~tmp~1#1); 38844#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38845#L311 assume !(1 == ~t1_pc~0); 39207#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39103#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38705#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38706#L751 assume !(0 != activate_threads_~tmp___0~0#1); 38746#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39210#L330 assume !(1 == ~t2_pc~0); 39165#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38891#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38760#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38761#L759 assume !(0 != activate_threads_~tmp___1~0#1); 39293#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38879#L349 assume !(1 == ~t3_pc~0); 38880#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39173#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39174#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39331#L767 assume !(0 != activate_threads_~tmp___2~0#1); 39287#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39288#L368 assume !(1 == ~t4_pc~0); 38963#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 38964#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39079#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39080#L775 assume !(0 != activate_threads_~tmp___3~0#1); 38731#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38732#L387 assume !(1 == ~t5_pc~0); 39117#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39118#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38842#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38843#L783 assume !(0 != activate_threads_~tmp___4~0#1); 38860#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38946#L667 assume !(1 == ~M_E~0); 39027#L667-2 assume !(1 == ~T1_E~0); 39215#L672-1 assume !(1 == ~T2_E~0); 38985#L677-1 assume !(1 == ~T3_E~0); 38986#L682-1 assume !(1 == ~T4_E~0); 39183#L687-1 assume !(1 == ~T5_E~0); 39259#L692-1 assume !(1 == ~E_M~0); 39171#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 39172#L702-1 assume !(1 == ~E_2~0); 39222#L707-1 assume !(1 == ~E_3~0); 39081#L712-1 assume !(1 == ~E_4~0); 39082#L717-1 assume !(1 == ~E_5~0); 39197#L722-1 assume { :end_inline_reset_delta_events } true; 39198#L928-2 [2021-12-15 17:20:31,803 INFO L793 eck$LassoCheckResult]: Loop: 39198#L928-2 assume !false; 42960#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42959#L574 assume !false; 42912#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42903#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42899#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42897#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42894#L499 assume !(0 != eval_~tmp~0#1); 42895#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44789#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44788#L599-3 assume !(0 == ~M_E~0); 44787#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44786#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44785#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44784#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44783#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44782#L624-3 assume !(0 == ~E_M~0); 44781#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44780#L634-3 assume !(0 == ~E_2~0); 39199#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39200#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39325#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39326#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44779#L292-21 assume 1 == ~m_pc~0; 44777#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 38824#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38825#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39278#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39036#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39037#L311-21 assume !(1 == ~t1_pc~0); 38965#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 38777#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38778#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39061#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39296#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39160#L330-21 assume !(1 == ~t2_pc~0); 39161#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 39132#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38920#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38921#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44404#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44403#L349-21 assume !(1 == ~t3_pc~0); 44401#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 44399#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44397#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44396#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 44394#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44393#L368-21 assume !(1 == ~t4_pc~0); 44391#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 44388#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44386#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44384#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44382#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44380#L387-21 assume !(1 == ~t5_pc~0); 44376#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 44374#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44372#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44370#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40369#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40363#L667-3 assume !(1 == ~M_E~0); 40364#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44776#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44775#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44774#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44773#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44772#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44771#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44770#L702-3 assume !(1 == ~E_2~0); 44769#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44768#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44767#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44766#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 44488#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40328#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40314#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 40315#L947 assume !(0 == start_simulation_~tmp~3#1); 41198#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 43038#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 43032#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 43031#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 43030#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43028#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43026#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 43024#L960 assume !(0 != start_simulation_~tmp___0~1#1); 39198#L928-2 [2021-12-15 17:20:31,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,803 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2021-12-15 17:20:31,804 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63957697] [2021-12-15 17:20:31,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,804 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63957697] [2021-12-15 17:20:31,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63957697] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,839 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,839 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:31,840 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176500958] [2021-12-15 17:20:31,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,840 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:31,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1621248717, now seen corresponding path program 1 times [2021-12-15 17:20:31,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210953605] [2021-12-15 17:20:31,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,867 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210953605] [2021-12-15 17:20:31,868 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210953605] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,868 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,868 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:31,868 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784825850] [2021-12-15 17:20:31,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,869 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,869 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:31,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:31,870 INFO L87 Difference]: Start difference. First operand 6219 states and 8941 transitions. cyclomatic complexity: 2726 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,915 INFO L93 Difference]: Finished difference Result 6219 states and 8847 transitions. [2021-12-15 17:20:31,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:31,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6219 states and 8847 transitions. [2021-12-15 17:20:31,935 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6116 [2021-12-15 17:20:31,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6219 states to 6219 states and 8847 transitions. [2021-12-15 17:20:31,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6219 [2021-12-15 17:20:31,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6219 [2021-12-15 17:20:31,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6219 states and 8847 transitions. [2021-12-15 17:20:32,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,000 INFO L681 BuchiCegarLoop]: Abstraction has 6219 states and 8847 transitions. [2021-12-15 17:20:32,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6219 states and 8847 transitions. [2021-12-15 17:20:32,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6219 to 6219. [2021-12-15 17:20:32,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6219 states, 6219 states have (on average 1.422575976845152) internal successors, (8847), 6218 states have internal predecessors, (8847), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6219 states to 6219 states and 8847 transitions. [2021-12-15 17:20:32,110 INFO L704 BuchiCegarLoop]: Abstraction has 6219 states and 8847 transitions. [2021-12-15 17:20:32,110 INFO L587 BuchiCegarLoop]: Abstraction has 6219 states and 8847 transitions. [2021-12-15 17:20:32,110 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:32,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6219 states and 8847 transitions. [2021-12-15 17:20:32,125 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6116 [2021-12-15 17:20:32,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,127 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,127 INFO L791 eck$LassoCheckResult]: Stem: 51782#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 51740#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 51519#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51173#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51174#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 51532#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51533#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51717#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51510#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51511#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51711#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51503#L599 assume !(0 == ~M_E~0); 51504#L599-2 assume !(0 == ~T1_E~0); 51177#L604-1 assume !(0 == ~T2_E~0); 51166#L609-1 assume !(0 == ~T3_E~0); 51167#L614-1 assume !(0 == ~T4_E~0); 51322#L619-1 assume !(0 == ~T5_E~0); 51442#L624-1 assume !(0 == ~E_M~0); 51539#L629-1 assume !(0 == ~E_1~0); 51255#L634-1 assume !(0 == ~E_2~0); 51256#L639-1 assume !(0 == ~E_3~0); 51656#L644-1 assume !(0 == ~E_4~0); 51674#L649-1 assume !(0 == ~E_5~0); 51217#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51218#L292 assume !(1 == ~m_pc~0); 51332#L292-2 is_master_triggered_~__retres1~0#1 := 0; 51473#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51584#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51746#L743 assume !(0 != activate_threads_~tmp~1#1); 51291#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51292#L311 assume !(1 == ~t1_pc~0); 51655#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51545#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51152#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51153#L751 assume !(0 != activate_threads_~tmp___0~0#1); 51193#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51658#L330 assume !(1 == ~t2_pc~0); 51610#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51335#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51207#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51208#L759 assume !(0 != activate_threads_~tmp___1~0#1); 51737#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51323#L349 assume !(1 == ~t3_pc~0); 51324#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51618#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51619#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 51775#L767 assume !(0 != activate_threads_~tmp___2~0#1); 51733#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51734#L368 assume !(1 == ~t4_pc~0); 51404#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51405#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51520#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51521#L775 assume !(0 != activate_threads_~tmp___3~0#1); 51178#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51179#L387 assume !(1 == ~t5_pc~0); 51557#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 51558#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51289#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51290#L783 assume !(0 != activate_threads_~tmp___4~0#1); 51306#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51388#L667 assume !(1 == ~M_E~0); 51468#L667-2 assume !(1 == ~T1_E~0); 51663#L672-1 assume !(1 == ~T2_E~0); 51427#L677-1 assume !(1 == ~T3_E~0); 51428#L682-1 assume !(1 == ~T4_E~0); 51630#L687-1 assume !(1 == ~T5_E~0); 51706#L692-1 assume !(1 == ~E_M~0); 51616#L697-1 assume !(1 == ~E_1~0); 51617#L702-1 assume !(1 == ~E_2~0); 51671#L707-1 assume !(1 == ~E_3~0); 51522#L712-1 assume !(1 == ~E_4~0); 51523#L717-1 assume !(1 == ~E_5~0); 51644#L722-1 assume { :end_inline_reset_delta_events } true; 51645#L928-2 [2021-12-15 17:20:32,127 INFO L793 eck$LassoCheckResult]: Loop: 51645#L928-2 assume !false; 53463#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53460#L574 assume !false; 53458#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53449#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53445#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53443#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 53439#L499 assume !(0 != eval_~tmp~0#1); 53440#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55739#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55736#L599-3 assume !(0 == ~M_E~0); 55733#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55730#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55727#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55724#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55721#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55718#L624-3 assume !(0 == ~E_M~0); 55714#L629-3 assume !(0 == ~E_1~0); 55711#L634-3 assume !(0 == ~E_2~0); 55708#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55703#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55696#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55486#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55483#L292-21 assume 1 == ~m_pc~0; 55480#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 55478#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55476#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55474#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55472#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55470#L311-21 assume !(1 == ~t1_pc~0); 55468#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 54872#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54871#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54869#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54867#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53682#L330-21 assume !(1 == ~t2_pc~0); 53680#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 53679#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53677#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53675#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53673#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53668#L349-21 assume !(1 == ~t3_pc~0); 53666#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 53665#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53661#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53659#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 53656#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53654#L368-21 assume !(1 == ~t4_pc~0); 53651#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 53649#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53647#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53645#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53643#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53641#L387-21 assume !(1 == ~t5_pc~0); 53638#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 53636#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53634#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53631#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53629#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53621#L667-3 assume !(1 == ~M_E~0); 53619#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53617#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53615#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53613#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53609#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53607#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53605#L697-3 assume !(1 == ~E_1~0); 53603#L702-3 assume !(1 == ~E_2~0); 53600#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53598#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53596#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53594#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53589#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53583#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53581#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 53577#L947 assume !(0 == start_simulation_~tmp~3#1); 53574#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53569#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53563#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53562#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 53561#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53560#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53559#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 53558#L960 assume !(0 != start_simulation_~tmp___0~1#1); 51645#L928-2 [2021-12-15 17:20:32,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2021-12-15 17:20:32,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130375709] [2021-12-15 17:20:32,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,152 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:32,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,196 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:32,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,198 INFO L85 PathProgramCache]: Analyzing trace with hash -536579853, now seen corresponding path program 1 times [2021-12-15 17:20:32,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744684669] [2021-12-15 17:20:32,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,264 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744684669] [2021-12-15 17:20:32,264 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744684669] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,265 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:32,265 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422759276] [2021-12-15 17:20:32,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,265 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,266 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:32,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:32,267 INFO L87 Difference]: Start difference. First operand 6219 states and 8847 transitions. cyclomatic complexity: 2632 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,376 INFO L93 Difference]: Finished difference Result 11119 states and 15583 transitions. [2021-12-15 17:20:32,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:32,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11119 states and 15583 transitions. [2021-12-15 17:20:32,418 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10992 [2021-12-15 17:20:32,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11119 states to 11119 states and 15583 transitions. [2021-12-15 17:20:32,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11119 [2021-12-15 17:20:32,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11119 [2021-12-15 17:20:32,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11119 states and 15583 transitions. [2021-12-15 17:20:32,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,500 INFO L681 BuchiCegarLoop]: Abstraction has 11119 states and 15583 transitions. [2021-12-15 17:20:32,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11119 states and 15583 transitions. [2021-12-15 17:20:32,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11119 to 6267. [2021-12-15 17:20:32,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6267 states, 6267 states have (on average 1.4193393968405936) internal successors, (8895), 6266 states have internal predecessors, (8895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6267 states to 6267 states and 8895 transitions. [2021-12-15 17:20:32,597 INFO L704 BuchiCegarLoop]: Abstraction has 6267 states and 8895 transitions. [2021-12-15 17:20:32,598 INFO L587 BuchiCegarLoop]: Abstraction has 6267 states and 8895 transitions. [2021-12-15 17:20:32,598 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:32,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6267 states and 8895 transitions. [2021-12-15 17:20:32,611 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6164 [2021-12-15 17:20:32,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,613 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,613 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,613 INFO L791 eck$LassoCheckResult]: Stem: 69157#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 69115#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 68877#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68527#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68528#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 68889#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68890#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69083#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68866#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68867#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69076#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68859#L599 assume !(0 == ~M_E~0); 68860#L599-2 assume !(0 == ~T1_E~0); 68531#L604-1 assume !(0 == ~T2_E~0); 68520#L609-1 assume !(0 == ~T3_E~0); 68521#L614-1 assume !(0 == ~T4_E~0); 68675#L619-1 assume !(0 == ~T5_E~0); 68795#L624-1 assume !(0 == ~E_M~0); 68896#L629-1 assume !(0 == ~E_1~0); 68608#L634-1 assume !(0 == ~E_2~0); 68609#L639-1 assume !(0 == ~E_3~0); 69017#L644-1 assume !(0 == ~E_4~0); 69037#L649-1 assume !(0 == ~E_5~0); 68571#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68572#L292 assume !(1 == ~m_pc~0); 68685#L292-2 is_master_triggered_~__retres1~0#1 := 0; 68826#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68944#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69127#L743 assume !(0 != activate_threads_~tmp~1#1); 68644#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68645#L311 assume !(1 == ~t1_pc~0); 69016#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68902#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68506#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68507#L751 assume !(0 != activate_threads_~tmp___0~0#1); 68547#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69019#L330 assume !(1 == ~t2_pc~0); 68966#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68688#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68561#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68562#L759 assume !(0 != activate_threads_~tmp___1~0#1); 69111#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68676#L349 assume !(1 == ~t3_pc~0); 68677#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68980#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68981#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69152#L767 assume !(0 != activate_threads_~tmp___2~0#1); 69104#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69105#L368 assume !(1 == ~t4_pc~0); 68757#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68758#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68878#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68879#L775 assume !(0 != activate_threads_~tmp___3~0#1); 68532#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68533#L387 assume !(1 == ~t5_pc~0); 68915#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68916#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68642#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68643#L783 assume !(0 != activate_threads_~tmp___4~0#1); 68659#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68741#L667 assume !(1 == ~M_E~0); 68821#L667-2 assume !(1 == ~T1_E~0); 69027#L672-1 assume !(1 == ~T2_E~0); 68780#L677-1 assume !(1 == ~T3_E~0); 68781#L682-1 assume !(1 == ~T4_E~0); 68994#L687-1 assume !(1 == ~T5_E~0); 69073#L692-1 assume !(1 == ~E_M~0); 68978#L697-1 assume !(1 == ~E_1~0); 68979#L702-1 assume !(1 == ~E_2~0); 69035#L707-1 assume !(1 == ~E_3~0); 68880#L712-1 assume !(1 == ~E_4~0); 68881#L717-1 assume !(1 == ~E_5~0); 69006#L722-1 assume { :end_inline_reset_delta_events } true; 69007#L928-2 [2021-12-15 17:20:32,614 INFO L793 eck$LassoCheckResult]: Loop: 69007#L928-2 assume !false; 73719#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73465#L574 assume !false; 73370#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 73365#L452 assume !(0 == ~m_st~0); 73366#L456 assume !(0 == ~t1_st~0); 73368#L460 assume !(0 == ~t2_st~0); 73363#L464 assume !(0 == ~t3_st~0); 73364#L468 assume !(0 == ~t4_st~0); 73367#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 73369#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 71352#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 71353#L499 assume !(0 != eval_~tmp~0#1); 73350#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73348#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73346#L599-3 assume !(0 == ~M_E~0); 73344#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 73342#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73340#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73338#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 73336#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 73334#L624-3 assume !(0 == ~E_M~0); 73332#L629-3 assume !(0 == ~E_1~0); 73330#L634-3 assume !(0 == ~E_2~0); 73328#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73326#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 73324#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 73322#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73320#L292-21 assume !(1 == ~m_pc~0); 73317#L292-23 is_master_triggered_~__retres1~0#1 := 0; 73314#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73312#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 73310#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73308#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73306#L311-21 assume !(1 == ~t1_pc~0); 73304#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 73302#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73300#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 73298#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73296#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73294#L330-21 assume !(1 == ~t2_pc~0); 73293#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 73292#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73291#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 73290#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73289#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73288#L349-21 assume !(1 == ~t3_pc~0); 73287#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 73285#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73283#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73281#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 73279#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73278#L368-21 assume !(1 == ~t4_pc~0); 73277#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 73276#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73275#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73274#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73273#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73272#L387-21 assume 1 == ~t5_pc~0; 73271#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73269#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73268#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73267#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 73266#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73265#L667-3 assume !(1 == ~M_E~0); 73055#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73264#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73263#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73262#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73261#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73260#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 73259#L697-3 assume !(1 == ~E_1~0); 73258#L702-3 assume !(1 == ~E_2~0); 73257#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73256#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73255#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73254#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 73252#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 73246#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 73245#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 73243#L947 assume !(0 == start_simulation_~tmp~3#1); 73244#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 73856#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 73845#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 73839#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 73828#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73819#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73813#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 73806#L960 assume !(0 != start_simulation_~tmp___0~1#1); 69007#L928-2 [2021-12-15 17:20:32,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2021-12-15 17:20:32,615 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432534575] [2021-12-15 17:20:32,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,615 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,623 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:32,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,645 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:32,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,645 INFO L85 PathProgramCache]: Analyzing trace with hash -2140652226, now seen corresponding path program 1 times [2021-12-15 17:20:32,646 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434630093] [2021-12-15 17:20:32,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,696 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434630093] [2021-12-15 17:20:32,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434630093] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,696 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,697 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:32,697 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010881306] [2021-12-15 17:20:32,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,697 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,698 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:32,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:32,698 INFO L87 Difference]: Start difference. First operand 6267 states and 8895 transitions. cyclomatic complexity: 2632 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,894 INFO L93 Difference]: Finished difference Result 17880 states and 25162 transitions. [2021-12-15 17:20:32,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:32,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17880 states and 25162 transitions. [2021-12-15 17:20:33,047 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 17628 [2021-12-15 17:20:33,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17880 states to 17880 states and 25162 transitions. [2021-12-15 17:20:33,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17880 [2021-12-15 17:20:33,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17880 [2021-12-15 17:20:33,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17880 states and 25162 transitions. [2021-12-15 17:20:33,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,117 INFO L681 BuchiCegarLoop]: Abstraction has 17880 states and 25162 transitions. [2021-12-15 17:20:33,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17880 states and 25162 transitions. [2021-12-15 17:20:33,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17880 to 6558. [2021-12-15 17:20:33,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6558 states, 6558 states have (on average 1.4007319304666057) internal successors, (9186), 6557 states have internal predecessors, (9186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6558 states to 6558 states and 9186 transitions. [2021-12-15 17:20:33,248 INFO L704 BuchiCegarLoop]: Abstraction has 6558 states and 9186 transitions. [2021-12-15 17:20:33,248 INFO L587 BuchiCegarLoop]: Abstraction has 6558 states and 9186 transitions. [2021-12-15 17:20:33,249 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:33,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6558 states and 9186 transitions. [2021-12-15 17:20:33,261 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6452 [2021-12-15 17:20:33,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,263 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,263 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,263 INFO L791 eck$LassoCheckResult]: Stem: 93366#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 93319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 93045#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92687#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92688#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 93058#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93059#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93280#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93031#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93032#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 93272#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93026#L599 assume !(0 == ~M_E~0); 93027#L599-2 assume !(0 == ~T1_E~0); 92691#L604-1 assume !(0 == ~T2_E~0); 92680#L609-1 assume !(0 == ~T3_E~0); 92681#L614-1 assume !(0 == ~T4_E~0); 92837#L619-1 assume !(0 == ~T5_E~0); 92965#L624-1 assume !(0 == ~E_M~0); 93066#L629-1 assume !(0 == ~E_1~0); 92768#L634-1 assume !(0 == ~E_2~0); 92769#L639-1 assume !(0 == ~E_3~0); 93195#L644-1 assume !(0 == ~E_4~0); 93214#L649-1 assume !(0 == ~E_5~0); 92731#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92732#L292 assume !(1 == ~m_pc~0); 92847#L292-2 is_master_triggered_~__retres1~0#1 := 0; 92997#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93114#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 93327#L743 assume !(0 != activate_threads_~tmp~1#1); 92804#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92805#L311 assume !(1 == ~t1_pc~0); 93194#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93071#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92666#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92667#L751 assume !(0 != activate_threads_~tmp___0~0#1); 92707#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93196#L330 assume !(1 == ~t2_pc~0); 93141#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92849#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92719#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92720#L759 assume !(0 != activate_threads_~tmp___1~0#1); 93315#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92838#L349 assume !(1 == ~t3_pc~0); 92839#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 93155#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93156#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 93361#L767 assume !(0 != activate_threads_~tmp___2~0#1); 93310#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93311#L368 assume !(1 == ~t4_pc~0); 92922#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 92923#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93047#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 93048#L775 assume !(0 != activate_threads_~tmp___3~0#1); 92692#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92693#L387 assume !(1 == ~t5_pc~0); 93085#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 93086#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 92800#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 92801#L783 assume !(0 != activate_threads_~tmp___4~0#1); 92817#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92905#L667 assume !(1 == ~M_E~0); 92992#L667-2 assume !(1 == ~T1_E~0); 93203#L672-1 assume !(1 == ~T2_E~0); 92950#L677-1 assume !(1 == ~T3_E~0); 92951#L682-1 assume !(1 == ~T4_E~0); 93165#L687-1 assume !(1 == ~T5_E~0); 93267#L692-1 assume !(1 == ~E_M~0); 93153#L697-1 assume !(1 == ~E_1~0); 93154#L702-1 assume !(1 == ~E_2~0); 93213#L707-1 assume !(1 == ~E_3~0); 93049#L712-1 assume !(1 == ~E_4~0); 93050#L717-1 assume !(1 == ~E_5~0); 93180#L722-1 assume { :end_inline_reset_delta_events } true; 93181#L928-2 [2021-12-15 17:20:33,264 INFO L793 eck$LassoCheckResult]: Loop: 93181#L928-2 assume !false; 98177#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98175#L574 assume !false; 98173#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 98167#L452 assume !(0 == ~m_st~0); 98168#L456 assume !(0 == ~t1_st~0); 98170#L460 assume !(0 == ~t2_st~0); 98165#L464 assume !(0 == ~t3_st~0); 98166#L468 assume !(0 == ~t4_st~0); 98169#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 98171#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 95969#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 95970#L499 assume !(0 != eval_~tmp~0#1); 98160#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98158#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98156#L599-3 assume !(0 == ~M_E~0); 98154#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98152#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98150#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 98148#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98146#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 98144#L624-3 assume !(0 == ~E_M~0); 98142#L629-3 assume !(0 == ~E_1~0); 98140#L634-3 assume !(0 == ~E_2~0); 98138#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98136#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98134#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 98123#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98122#L292-21 assume !(1 == ~m_pc~0); 98121#L292-23 is_master_triggered_~__retres1~0#1 := 0; 98119#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98117#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 98115#L743-21 assume !(0 != activate_threads_~tmp~1#1); 98112#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98110#L311-21 assume !(1 == ~t1_pc~0); 98108#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 98106#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98104#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 98102#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 98100#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98098#L330-21 assume !(1 == ~t2_pc~0); 96965#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 98096#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98094#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98092#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98090#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98088#L349-21 assume !(1 == ~t3_pc~0); 98085#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 98081#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98077#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98073#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 98070#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98068#L368-21 assume !(1 == ~t4_pc~0); 98066#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 98064#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98062#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98060#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 98058#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98056#L387-21 assume 1 == ~t5_pc~0; 98053#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 98050#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98048#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98046#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98044#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98040#L667-3 assume !(1 == ~M_E~0); 98041#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98350#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98024#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98016#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98010#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98011#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98338#L697-3 assume !(1 == ~E_1~0); 98337#L702-3 assume !(1 == ~E_2~0); 97996#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97997#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97972#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97973#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 97966#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 97962#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 97953#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 97954#L947 assume !(0 == start_simulation_~tmp~3#1); 98244#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 98229#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 98220#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 98212#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 98203#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98199#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98193#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 98187#L960 assume !(0 != start_simulation_~tmp___0~1#1); 93181#L928-2 [2021-12-15 17:20:33,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2021-12-15 17:20:33,264 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139649398] [2021-12-15 17:20:33,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,279 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:33,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,304 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:33,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,305 INFO L85 PathProgramCache]: Analyzing trace with hash -879734976, now seen corresponding path program 1 times [2021-12-15 17:20:33,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253214129] [2021-12-15 17:20:33,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,329 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [253214129] [2021-12-15 17:20:33,329 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [253214129] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,329 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,329 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,330 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439833543] [2021-12-15 17:20:33,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,330 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,330 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:33,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:33,331 INFO L87 Difference]: Start difference. First operand 6558 states and 9186 transitions. cyclomatic complexity: 2632 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,451 INFO L93 Difference]: Finished difference Result 12106 states and 16714 transitions. [2021-12-15 17:20:33,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:33,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12106 states and 16714 transitions. [2021-12-15 17:20:33,494 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11976 [2021-12-15 17:20:33,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12106 states to 12106 states and 16714 transitions. [2021-12-15 17:20:33,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12106 [2021-12-15 17:20:33,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12106 [2021-12-15 17:20:33,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12106 states and 16714 transitions. [2021-12-15 17:20:33,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,548 INFO L681 BuchiCegarLoop]: Abstraction has 12106 states and 16714 transitions. [2021-12-15 17:20:33,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12106 states and 16714 transitions. [2021-12-15 17:20:33,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12106 to 11490. [2021-12-15 17:20:33,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11490 states, 11490 states have (on average 1.3843342036553525) internal successors, (15906), 11489 states have internal predecessors, (15906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11490 states to 11490 states and 15906 transitions. [2021-12-15 17:20:33,674 INFO L704 BuchiCegarLoop]: Abstraction has 11490 states and 15906 transitions. [2021-12-15 17:20:33,674 INFO L587 BuchiCegarLoop]: Abstraction has 11490 states and 15906 transitions. [2021-12-15 17:20:33,674 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:33,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11490 states and 15906 transitions. [2021-12-15 17:20:33,698 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11360 [2021-12-15 17:20:33,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,700 INFO L791 eck$LassoCheckResult]: Stem: 111970#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 111936#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 111701#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111357#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111358#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 111715#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111716#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111907#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111690#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111691#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111899#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111685#L599 assume !(0 == ~M_E~0); 111686#L599-2 assume !(0 == ~T1_E~0); 111361#L604-1 assume !(0 == ~T2_E~0); 111350#L609-1 assume !(0 == ~T3_E~0); 111351#L614-1 assume !(0 == ~T4_E~0); 111504#L619-1 assume !(0 == ~T5_E~0); 111626#L624-1 assume !(0 == ~E_M~0); 111723#L629-1 assume !(0 == ~E_1~0); 111436#L634-1 assume !(0 == ~E_2~0); 111437#L639-1 assume !(0 == ~E_3~0); 111841#L644-1 assume !(0 == ~E_4~0); 111857#L649-1 assume !(0 == ~E_5~0); 111401#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111402#L292 assume !(1 == ~m_pc~0); 111514#L292-2 is_master_triggered_~__retres1~0#1 := 0; 111657#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111961#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 111943#L743 assume !(0 != activate_threads_~tmp~1#1); 111472#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111473#L311 assume !(1 == ~t1_pc~0); 111840#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111728#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111336#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 111337#L751 assume !(0 != activate_threads_~tmp___0~0#1); 111377#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111842#L330 assume !(1 == ~t2_pc~0); 111795#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 111516#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111389#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 111390#L759 assume !(0 != activate_threads_~tmp___1~0#1); 111934#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111505#L349 assume !(1 == ~t3_pc~0); 111506#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111804#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111805#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 111964#L767 assume !(0 != activate_threads_~tmp___2~0#1); 111927#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111928#L368 assume !(1 == ~t4_pc~0); 111585#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111586#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111703#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 111704#L775 assume !(0 != activate_threads_~tmp___3~0#1); 111362#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111363#L387 assume !(1 == ~t5_pc~0); 111744#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 111745#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111468#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 111469#L783 assume !(0 != activate_threads_~tmp___4~0#1); 111485#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111571#L667 assume !(1 == ~M_E~0); 111652#L667-2 assume !(1 == ~T1_E~0); 111848#L672-1 assume !(1 == ~T2_E~0); 111611#L677-1 assume !(1 == ~T3_E~0); 111612#L682-1 assume !(1 == ~T4_E~0); 111816#L687-1 assume !(1 == ~T5_E~0); 111896#L692-1 assume !(1 == ~E_M~0); 111802#L697-1 assume !(1 == ~E_1~0); 111803#L702-1 assume !(1 == ~E_2~0); 111856#L707-1 assume !(1 == ~E_3~0); 111705#L712-1 assume !(1 == ~E_4~0); 111706#L717-1 assume !(1 == ~E_5~0); 111828#L722-1 assume { :end_inline_reset_delta_events } true; 111829#L928-2 [2021-12-15 17:20:33,701 INFO L793 eck$LassoCheckResult]: Loop: 111829#L928-2 assume !false; 115779#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115775#L574 assume !false; 115776#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 116593#L452 assume !(0 == ~m_st~0); 114891#L456 assume !(0 == ~t1_st~0); 114889#L460 assume !(0 == ~t2_st~0); 114887#L464 assume !(0 == ~t3_st~0); 114885#L468 assume !(0 == ~t4_st~0); 114880#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 114878#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 114876#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 114873#L499 assume !(0 != eval_~tmp~0#1); 114870#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114868#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 114866#L599-3 assume !(0 == ~M_E~0); 114864#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 114862#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 114860#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 114858#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 114856#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 114854#L624-3 assume !(0 == ~E_M~0); 114851#L629-3 assume !(0 == ~E_1~0); 114849#L634-3 assume !(0 == ~E_2~0); 114847#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 114845#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 114843#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 114841#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114840#L292-21 assume 1 == ~m_pc~0; 114837#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 114834#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114833#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 114830#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 114828#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114827#L311-21 assume !(1 == ~t1_pc~0); 114825#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 114823#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114821#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114818#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 114816#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114814#L330-21 assume !(1 == ~t2_pc~0); 112836#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 114743#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114735#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 114731#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 114727#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114722#L349-21 assume !(1 == ~t3_pc~0); 114717#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 114710#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114704#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 114697#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 114691#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114685#L368-21 assume !(1 == ~t4_pc~0); 114681#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 114677#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114674#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 114671#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114668#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114667#L387-21 assume !(1 == ~t5_pc~0); 114665#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 114664#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114662#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 114661#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 114660#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114616#L667-3 assume !(1 == ~M_E~0); 114614#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 114612#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114610#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 114608#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 114606#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 114604#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 114602#L697-3 assume !(1 == ~E_1~0); 114600#L702-3 assume !(1 == ~E_2~0); 114597#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 114595#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 114569#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 114564#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 114557#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 114553#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 114551#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 114548#L947 assume !(0 == start_simulation_~tmp~3#1); 114549#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 117085#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 117083#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 117080#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 117078#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117076#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117074#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 117071#L960 assume !(0 != start_simulation_~tmp___0~1#1); 111829#L928-2 [2021-12-15 17:20:33,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2021-12-15 17:20:33,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95143129] [2021-12-15 17:20:33,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,702 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,709 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:33,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,728 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:33,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,728 INFO L85 PathProgramCache]: Analyzing trace with hash -645688066, now seen corresponding path program 1 times [2021-12-15 17:20:33,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128665389] [2021-12-15 17:20:33,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,729 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128665389] [2021-12-15 17:20:33,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128665389] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,771 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,771 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:33,771 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076230320] [2021-12-15 17:20:33,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,772 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,772 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:33,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:33,773 INFO L87 Difference]: Start difference. First operand 11490 states and 15906 transitions. cyclomatic complexity: 4420 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,964 INFO L93 Difference]: Finished difference Result 13538 states and 18617 transitions. [2021-12-15 17:20:33,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:33,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13538 states and 18617 transitions. [2021-12-15 17:20:34,011 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13392 [2021-12-15 17:20:34,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13538 states to 13538 states and 18617 transitions. [2021-12-15 17:20:34,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13538 [2021-12-15 17:20:34,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13538 [2021-12-15 17:20:34,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13538 states and 18617 transitions. [2021-12-15 17:20:34,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,068 INFO L681 BuchiCegarLoop]: Abstraction has 13538 states and 18617 transitions. [2021-12-15 17:20:34,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13538 states and 18617 transitions. [2021-12-15 17:20:34,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13538 to 11514. [2021-12-15 17:20:34,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11514 states, 11514 states have (on average 1.3688553065832898) internal successors, (15761), 11513 states have internal predecessors, (15761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11514 states to 11514 states and 15761 transitions. [2021-12-15 17:20:34,221 INFO L704 BuchiCegarLoop]: Abstraction has 11514 states and 15761 transitions. [2021-12-15 17:20:34,221 INFO L587 BuchiCegarLoop]: Abstraction has 11514 states and 15761 transitions. [2021-12-15 17:20:34,221 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:34,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11514 states and 15761 transitions. [2021-12-15 17:20:34,290 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11384 [2021-12-15 17:20:34,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,292 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,292 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,293 INFO L791 eck$LassoCheckResult]: Stem: 137094#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 137049#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 136766#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 136399#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 136400#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 136779#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 136780#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137005#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 136753#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 136754#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 137001#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 136746#L599 assume !(0 == ~M_E~0); 136747#L599-2 assume !(0 == ~T1_E~0); 136403#L604-1 assume !(0 == ~T2_E~0); 136392#L609-1 assume !(0 == ~T3_E~0); 136393#L614-1 assume !(0 == ~T4_E~0); 136549#L619-1 assume !(0 == ~T5_E~0); 136679#L624-1 assume !(0 == ~E_M~0); 136786#L629-1 assume !(0 == ~E_1~0); 136481#L634-1 assume !(0 == ~E_2~0); 136482#L639-1 assume !(0 == ~E_3~0); 136916#L644-1 assume !(0 == ~E_4~0); 136939#L649-1 assume !(0 == ~E_5~0); 136444#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136445#L292 assume !(1 == ~m_pc~0); 136559#L292-2 is_master_triggered_~__retres1~0#1 := 0; 136716#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137084#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137056#L743 assume !(0 != activate_threads_~tmp~1#1); 136517#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136518#L311 assume !(1 == ~t1_pc~0); 136915#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 136793#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136378#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 136379#L751 assume !(0 != activate_threads_~tmp___0~0#1); 136420#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136919#L330 assume !(1 == ~t2_pc~0); 136867#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 136563#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136434#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 136435#L759 assume !(0 != activate_threads_~tmp___1~0#1); 137044#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136550#L349 assume !(1 == ~t3_pc~0); 136551#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 137077#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136775#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 136776#L767 assume !(0 != activate_threads_~tmp___2~0#1); 137033#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137034#L368 assume !(1 == ~t4_pc~0); 136638#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 136639#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136767#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 136768#L775 assume !(0 != activate_threads_~tmp___3~0#1); 136404#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136405#L387 assume !(1 == ~t5_pc~0); 136809#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 136810#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136515#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 136516#L783 assume !(0 != activate_threads_~tmp___4~0#1); 136533#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136620#L667 assume !(1 == ~M_E~0); 136711#L667-2 assume !(1 == ~T1_E~0); 136927#L672-1 assume !(1 == ~T2_E~0); 136662#L677-1 assume !(1 == ~T3_E~0); 136663#L682-1 assume !(1 == ~T4_E~0); 136887#L687-1 assume !(1 == ~T5_E~0); 136994#L692-1 assume !(1 == ~E_M~0); 136875#L697-1 assume !(1 == ~E_1~0); 136876#L702-1 assume !(1 == ~E_2~0); 136937#L707-1 assume !(1 == ~E_3~0); 136769#L712-1 assume !(1 == ~E_4~0); 136770#L717-1 assume !(1 == ~E_5~0); 136902#L722-1 assume { :end_inline_reset_delta_events } true; 136903#L928-2 [2021-12-15 17:20:34,293 INFO L793 eck$LassoCheckResult]: Loop: 136903#L928-2 assume !false; 141293#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141294#L574 assume !false; 141065#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 141066#L452 assume !(0 == ~m_st~0); 140988#L456 assume !(0 == ~t1_st~0); 140984#L460 assume !(0 == ~t2_st~0); 140978#L464 assume !(0 == ~t3_st~0); 140974#L468 assume !(0 == ~t4_st~0); 140970#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 140966#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 140962#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 140956#L499 assume !(0 != eval_~tmp~0#1); 140952#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 140948#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 140943#L599-3 assume !(0 == ~M_E~0); 140938#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 140933#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 140928#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 140924#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 140920#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 140913#L624-3 assume !(0 == ~E_M~0); 140909#L629-3 assume !(0 == ~E_1~0); 140905#L634-3 assume !(0 == ~E_2~0); 140900#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 140895#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 140890#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 140889#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140887#L292-21 assume 1 == ~m_pc~0; 140884#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 140882#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 140880#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 140877#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 140874#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140872#L311-21 assume !(1 == ~t1_pc~0); 140870#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 140867#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 140865#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 140863#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 140861#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 140859#L330-21 assume !(1 == ~t2_pc~0); 140810#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 140856#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 140854#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 140852#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 140850#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 140848#L349-21 assume !(1 == ~t3_pc~0); 140846#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 140901#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 140896#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 140838#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 140835#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 140832#L368-21 assume !(1 == ~t4_pc~0); 140830#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 140828#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 140826#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 140824#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 140822#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140820#L387-21 assume 1 == ~t5_pc~0; 140818#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 140815#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 140813#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 140811#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 140808#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140807#L667-3 assume !(1 == ~M_E~0); 140078#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 140803#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 140794#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 140790#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 140786#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 140780#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 140771#L697-3 assume !(1 == ~E_1~0); 140762#L702-3 assume !(1 == ~E_2~0); 140754#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 140745#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 140739#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 140735#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 140729#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 140724#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 140716#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 140708#L947 assume !(0 == start_simulation_~tmp~3#1); 140709#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 141504#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 141503#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 141500#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 141498#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 141496#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 141494#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 141414#L960 assume !(0 != start_simulation_~tmp___0~1#1); 136903#L928-2 [2021-12-15 17:20:34,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,294 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2021-12-15 17:20:34,295 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76165218] [2021-12-15 17:20:34,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,295 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:34,302 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:34,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:34,325 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:34,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,327 INFO L85 PathProgramCache]: Analyzing trace with hash -902803201, now seen corresponding path program 1 times [2021-12-15 17:20:34,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904093445] [2021-12-15 17:20:34,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,378 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904093445] [2021-12-15 17:20:34,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904093445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:34,379 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930474680] [2021-12-15 17:20:34,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,379 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,379 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:34,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:34,380 INFO L87 Difference]: Start difference. First operand 11514 states and 15761 transitions. cyclomatic complexity: 4251 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,576 INFO L93 Difference]: Finished difference Result 21466 states and 29356 transitions. [2021-12-15 17:20:34,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:34,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21466 states and 29356 transitions. [2021-12-15 17:20:34,675 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21288 [2021-12-15 17:20:34,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21466 states to 21466 states and 29356 transitions. [2021-12-15 17:20:34,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21466 [2021-12-15 17:20:34,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21466 [2021-12-15 17:20:34,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21466 states and 29356 transitions. [2021-12-15 17:20:34,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,779 INFO L681 BuchiCegarLoop]: Abstraction has 21466 states and 29356 transitions. [2021-12-15 17:20:34,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21466 states and 29356 transitions. [2021-12-15 17:20:34,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21466 to 11802. [2021-12-15 17:20:34,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11802 states, 11802 states have (on average 1.3529910184714455) internal successors, (15968), 11801 states have internal predecessors, (15968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11802 states to 11802 states and 15968 transitions. [2021-12-15 17:20:34,966 INFO L704 BuchiCegarLoop]: Abstraction has 11802 states and 15968 transitions. [2021-12-15 17:20:34,966 INFO L587 BuchiCegarLoop]: Abstraction has 11802 states and 15968 transitions. [2021-12-15 17:20:34,966 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:20:34,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11802 states and 15968 transitions. [2021-12-15 17:20:35,001 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11672 [2021-12-15 17:20:35,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,003 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,003 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,003 INFO L791 eck$LassoCheckResult]: Stem: 170028#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 169986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 169744#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169393#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169394#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 169756#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 169757#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 169951#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 169734#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169735#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169943#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 169727#L599 assume !(0 == ~M_E~0); 169728#L599-2 assume !(0 == ~T1_E~0); 169397#L604-1 assume !(0 == ~T2_E~0); 169386#L609-1 assume !(0 == ~T3_E~0); 169387#L614-1 assume !(0 == ~T4_E~0); 169541#L619-1 assume !(0 == ~T5_E~0); 169661#L624-1 assume !(0 == ~E_M~0); 169764#L629-1 assume !(0 == ~E_1~0); 169474#L634-1 assume !(0 == ~E_2~0); 169475#L639-1 assume !(0 == ~E_3~0); 169884#L644-1 assume !(0 == ~E_4~0); 169901#L649-1 assume !(0 == ~E_5~0); 169437#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169438#L292 assume !(1 == ~m_pc~0); 169551#L292-2 is_master_triggered_~__retres1~0#1 := 0; 169696#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170020#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 169996#L743 assume !(0 != activate_threads_~tmp~1#1); 169510#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169511#L311 assume !(1 == ~t1_pc~0); 169883#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169769#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169372#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 169373#L751 assume !(0 != activate_threads_~tmp___0~0#1); 169413#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169885#L330 assume !(1 == ~t2_pc~0); 169836#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 169554#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169427#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 169428#L759 assume !(0 != activate_threads_~tmp___1~0#1); 169984#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169542#L349 assume !(1 == ~t3_pc~0); 169543#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 170016#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169752#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 169753#L767 assume !(0 != activate_threads_~tmp___2~0#1); 169977#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169978#L368 assume !(1 == ~t4_pc~0); 169624#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 169625#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169745#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 169746#L775 assume !(0 != activate_threads_~tmp___3~0#1); 169398#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169399#L387 assume !(1 == ~t5_pc~0); 169782#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 169783#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169508#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 169509#L783 assume !(0 != activate_threads_~tmp___4~0#1); 169525#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169607#L667 assume !(1 == ~M_E~0); 169690#L667-2 assume !(1 == ~T1_E~0); 169890#L672-1 assume !(1 == ~T2_E~0); 169646#L677-1 assume !(1 == ~T3_E~0); 169647#L682-1 assume !(1 == ~T4_E~0); 169855#L687-1 assume !(1 == ~T5_E~0); 169939#L692-1 assume !(1 == ~E_M~0); 169842#L697-1 assume !(1 == ~E_1~0); 169843#L702-1 assume !(1 == ~E_2~0); 169899#L707-1 assume !(1 == ~E_3~0); 169747#L712-1 assume !(1 == ~E_4~0); 169748#L717-1 assume !(1 == ~E_5~0); 169868#L722-1 assume { :end_inline_reset_delta_events } true; 169869#L928-2 [2021-12-15 17:20:35,004 INFO L793 eck$LassoCheckResult]: Loop: 169869#L928-2 assume !false; 171830#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 173809#L574 assume !false; 173808#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 173806#L452 assume !(0 == ~m_st~0); 173807#L456 assume !(0 == ~t1_st~0); 175096#L460 assume !(0 == ~t2_st~0); 175093#L464 assume !(0 == ~t3_st~0); 175094#L468 assume !(0 == ~t4_st~0); 175095#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 175097#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 175004#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 175005#L499 assume !(0 != eval_~tmp~0#1); 178185#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 178184#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 178183#L599-3 assume !(0 == ~M_E~0); 178182#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 178181#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 178180#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 178179#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 178178#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 178177#L624-3 assume !(0 == ~E_M~0); 178176#L629-3 assume !(0 == ~E_1~0); 178175#L634-3 assume !(0 == ~E_2~0); 178174#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 178173#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 178172#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 178171#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178170#L292-21 assume 1 == ~m_pc~0; 178168#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 178167#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178166#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 178164#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 178163#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178162#L311-21 assume !(1 == ~t1_pc~0); 178161#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 178160#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178159#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 178158#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 178157#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172676#L330-21 assume !(1 == ~t2_pc~0); 172675#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 172674#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172673#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 172672#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 172671#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172670#L349-21 assume 1 == ~t3_pc~0; 172668#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 172666#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172664#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 172662#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 172661#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172660#L368-21 assume !(1 == ~t4_pc~0); 172659#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 172658#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172657#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 172656#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172655#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172654#L387-21 assume !(1 == ~t5_pc~0); 172652#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 172651#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172650#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172649#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 172648#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172604#L667-3 assume !(1 == ~M_E~0); 172601#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 171990#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 171883#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 171881#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 171879#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 171877#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 171875#L697-3 assume !(1 == ~E_1~0); 171873#L702-3 assume !(1 == ~E_2~0); 171871#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 171869#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 171867#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 171865#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 171862#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 171860#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 171859#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 171857#L947 assume !(0 == start_simulation_~tmp~3#1); 171854#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 171851#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 171849#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 171846#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 171843#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 171839#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 171836#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 171833#L960 assume !(0 != start_simulation_~tmp___0~1#1); 169869#L928-2 [2021-12-15 17:20:35,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2021-12-15 17:20:35,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510706763] [2021-12-15 17:20:35,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,013 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:35,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,037 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:35,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,038 INFO L85 PathProgramCache]: Analyzing trace with hash -1833950977, now seen corresponding path program 1 times [2021-12-15 17:20:35,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594385977] [2021-12-15 17:20:35,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,038 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,144 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,145 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594385977] [2021-12-15 17:20:35,145 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [594385977] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,145 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,145 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:35,145 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351862582] [2021-12-15 17:20:35,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,145 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,145 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:35,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:35,146 INFO L87 Difference]: Start difference. First operand 11802 states and 15968 transitions. cyclomatic complexity: 4170 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,346 INFO L93 Difference]: Finished difference Result 20322 states and 27599 transitions. [2021-12-15 17:20:35,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:35,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20322 states and 27599 transitions. [2021-12-15 17:20:35,433 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 20176 [2021-12-15 17:20:35,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20322 states to 20322 states and 27599 transitions. [2021-12-15 17:20:35,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20322 [2021-12-15 17:20:35,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20322 [2021-12-15 17:20:35,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20322 states and 27599 transitions. [2021-12-15 17:20:35,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,527 INFO L681 BuchiCegarLoop]: Abstraction has 20322 states and 27599 transitions. [2021-12-15 17:20:35,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20322 states and 27599 transitions. [2021-12-15 17:20:35,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20322 to 12090. [2021-12-15 17:20:35,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12090 states, 12090 states have (on average 1.337882547559967) internal successors, (16175), 12089 states have internal predecessors, (16175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12090 states to 12090 states and 16175 transitions. [2021-12-15 17:20:35,678 INFO L704 BuchiCegarLoop]: Abstraction has 12090 states and 16175 transitions. [2021-12-15 17:20:35,678 INFO L587 BuchiCegarLoop]: Abstraction has 12090 states and 16175 transitions. [2021-12-15 17:20:35,678 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:20:35,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12090 states and 16175 transitions. [2021-12-15 17:20:35,706 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11960 [2021-12-15 17:20:35,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,708 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,708 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,708 INFO L791 eck$LassoCheckResult]: Stem: 202186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 202140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 201887#L891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201531#L407 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 201532#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 201899#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 201900#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 202100#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 201878#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 201879#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 202091#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201871#L599 assume !(0 == ~M_E~0); 201872#L599-2 assume !(0 == ~T1_E~0); 201535#L604-1 assume !(0 == ~T2_E~0); 201524#L609-1 assume !(0 == ~T3_E~0); 201525#L614-1 assume !(0 == ~T4_E~0); 201680#L619-1 assume !(0 == ~T5_E~0); 201809#L624-1 assume !(0 == ~E_M~0); 201906#L629-1 assume !(0 == ~E_1~0); 201612#L634-1 assume !(0 == ~E_2~0); 201613#L639-1 assume !(0 == ~E_3~0); 202028#L644-1 assume !(0 == ~E_4~0); 202044#L649-1 assume !(0 == ~E_5~0); 201575#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 201576#L292 assume !(1 == ~m_pc~0); 201690#L292-2 is_master_triggered_~__retres1~0#1 := 0; 201842#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 202179#L304 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 202150#L743 assume !(0 != activate_threads_~tmp~1#1); 201648#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201649#L311 assume !(1 == ~t1_pc~0); 202026#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 201915#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201510#L323 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 201511#L751 assume !(0 != activate_threads_~tmp___0~0#1); 201551#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 202029#L330 assume !(1 == ~t2_pc~0); 201983#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 201692#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 201565#L342 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 201566#L759 assume !(0 != activate_threads_~tmp___1~0#1); 202134#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 201681#L349 assume !(1 == ~t3_pc~0); 201682#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 202172#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 201895#L361 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 201896#L767 assume !(0 != activate_threads_~tmp___2~0#1); 202127#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 202128#L368 assume !(1 == ~t4_pc~0); 201770#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 201771#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 201888#L380 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 201889#L775 assume !(0 != activate_threads_~tmp___3~0#1); 201536#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 201537#L387 assume !(1 == ~t5_pc~0); 201931#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 201932#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 201646#L399 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 201647#L783 assume !(0 != activate_threads_~tmp___4~0#1); 201663#L783-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201749#L667 assume !(1 == ~M_E~0); 201837#L667-2 assume !(1 == ~T1_E~0); 202034#L672-1 assume !(1 == ~T2_E~0); 201794#L677-1 assume !(1 == ~T3_E~0); 201795#L682-1 assume !(1 == ~T4_E~0); 202003#L687-1 assume !(1 == ~T5_E~0); 202087#L692-1 assume !(1 == ~E_M~0); 201989#L697-1 assume !(1 == ~E_1~0); 201990#L702-1 assume !(1 == ~E_2~0); 202042#L707-1 assume !(1 == ~E_3~0); 201890#L712-1 assume !(1 == ~E_4~0); 201891#L717-1 assume !(1 == ~E_5~0); 202016#L722-1 assume { :end_inline_reset_delta_events } true; 202017#L928-2 [2021-12-15 17:20:35,708 INFO L793 eck$LassoCheckResult]: Loop: 202017#L928-2 assume !false; 206725#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 206724#L574 assume !false; 206722#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 206720#L452 assume !(0 == ~m_st~0); 205887#L456 assume !(0 == ~t1_st~0); 205885#L460 assume !(0 == ~t2_st~0); 205881#L464 assume !(0 == ~t3_st~0); 205879#L468 assume !(0 == ~t4_st~0); 205876#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 205874#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 205871#L485 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 205868#L499 assume !(0 != eval_~tmp~0#1); 205866#L589 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 205864#L407-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 205862#L599-3 assume !(0 == ~M_E~0); 205860#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 205858#L604-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 205856#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 205854#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 205851#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 205849#L624-3 assume !(0 == ~E_M~0); 205847#L629-3 assume !(0 == ~E_1~0); 205845#L634-3 assume !(0 == ~E_2~0); 205843#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 205841#L644-3 assume 0 == ~E_4~0;~E_4~0 := 1; 205840#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 205838#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205835#L292-21 assume 1 == ~m_pc~0; 205833#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 205831#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 205829#L304-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 205827#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 205825#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205823#L311-21 assume !(1 == ~t1_pc~0); 205821#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 205818#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 205816#L323-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 205814#L751-21 assume !(0 != activate_threads_~tmp___0~0#1); 205812#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 204523#L330-21 assume !(1 == ~t2_pc~0); 204521#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 204519#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204517#L342-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 204515#L759-21 assume !(0 != activate_threads_~tmp___1~0#1); 204513#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 204508#L349-21 assume !(1 == ~t3_pc~0); 204506#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 204503#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 204501#L361-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 204499#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 204496#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 204494#L368-21 assume !(1 == ~t4_pc~0); 204492#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 204491#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 204489#L380-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 204487#L775-21 assume !(0 != activate_threads_~tmp___3~0#1); 204484#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204482#L387-21 assume 1 == ~t5_pc~0; 204479#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 204476#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 204473#L399-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204471#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 204469#L783-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 204466#L667-3 assume !(1 == ~M_E~0); 204046#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 204463#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 204462#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 204461#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 204459#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 204457#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 204456#L697-3 assume !(1 == ~E_1~0); 204455#L702-3 assume !(1 == ~E_2~0); 204453#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 204451#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 204448#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 204446#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 204443#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 204440#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 204438#L485-1 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 204435#L947 assume !(0 == start_simulation_~tmp~3#1); 204436#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 206806#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 206803#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 206802#L485-2 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 206801#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 206800#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 206798#L910 start_simulation_#t~ret20#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 206797#L960 assume !(0 != start_simulation_~tmp___0~1#1); 202017#L928-2 [2021-12-15 17:20:35,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2021-12-15 17:20:35,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421598585] [2021-12-15 17:20:35,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,710 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,718 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:35,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,732 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:35,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,732 INFO L85 PathProgramCache]: Analyzing trace with hash -81703421, now seen corresponding path program 1 times [2021-12-15 17:20:35,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482212012] [2021-12-15 17:20:35,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,740 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:35,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,755 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:35,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,756 INFO L85 PathProgramCache]: Analyzing trace with hash 1816612415, now seen corresponding path program 1 times [2021-12-15 17:20:35,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066519520] [2021-12-15 17:20:35,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,757 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,785 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066519520] [2021-12-15 17:20:35,785 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066519520] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,785 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,785 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,785 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143358254] [2021-12-15 17:20:35,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,069 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:37,073 INFO L158 Benchmark]: Toolchain (without parser) took 9775.47ms. Allocated memory was 94.4MB in the beginning and 931.1MB in the end (delta: 836.8MB). Free memory was 62.8MB in the beginning and 407.5MB in the end (delta: -344.7MB). Peak memory consumption was 493.1MB. Max. memory is 16.1GB. [2021-12-15 17:20:37,073 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 94.4MB. Free memory was 51.2MB in the beginning and 51.1MB in the end (delta: 84.1kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:37,073 INFO L158 Benchmark]: CACSL2BoogieTranslator took 294.54ms. Allocated memory is still 94.4MB. Free memory was 62.6MB in the beginning and 66.2MB in the end (delta: -3.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-15 17:20:37,074 INFO L158 Benchmark]: Boogie Procedure Inliner took 99.32ms. Allocated memory is still 94.4MB. Free memory was 66.2MB in the beginning and 61.2MB in the end (delta: 5.0MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-15 17:20:37,074 INFO L158 Benchmark]: Boogie Preprocessor took 92.20ms. Allocated memory is still 94.4MB. Free memory was 61.2MB in the beginning and 56.7MB in the end (delta: 4.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:37,074 INFO L158 Benchmark]: RCFGBuilder took 1030.66ms. Allocated memory was 94.4MB in the beginning and 125.8MB in the end (delta: 31.5MB). Free memory was 56.7MB in the beginning and 95.4MB in the end (delta: -38.7MB). Peak memory consumption was 26.9MB. Max. memory is 16.1GB. [2021-12-15 17:20:37,075 INFO L158 Benchmark]: BuchiAutomizer took 8252.59ms. Allocated memory was 125.8MB in the beginning and 931.1MB in the end (delta: 805.3MB). Free memory was 95.4MB in the beginning and 407.5MB in the end (delta: -312.1MB). Peak memory consumption was 492.9MB. Max. memory is 16.1GB. [2021-12-15 17:20:37,076 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 94.4MB. Free memory was 51.2MB in the beginning and 51.1MB in the end (delta: 84.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 294.54ms. Allocated memory is still 94.4MB. Free memory was 62.6MB in the beginning and 66.2MB in the end (delta: -3.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 99.32ms. Allocated memory is still 94.4MB. Free memory was 66.2MB in the beginning and 61.2MB in the end (delta: 5.0MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 92.20ms. Allocated memory is still 94.4MB. Free memory was 61.2MB in the beginning and 56.7MB in the end (delta: 4.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1030.66ms. Allocated memory was 94.4MB in the beginning and 125.8MB in the end (delta: 31.5MB). Free memory was 56.7MB in the beginning and 95.4MB in the end (delta: -38.7MB). Peak memory consumption was 26.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 8252.59ms. Allocated memory was 125.8MB in the beginning and 931.1MB in the end (delta: 805.3MB). Free memory was 95.4MB in the beginning and 407.5MB in the end (delta: -312.1MB). Peak memory consumption was 492.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:37,106 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable