./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:25,967 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:26,016 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:26,036 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:26,038 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:26,040 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:26,042 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:26,046 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:26,047 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:26,052 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:26,052 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:26,053 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:26,053 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:26,055 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:26,056 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:26,058 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:26,063 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:26,064 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:26,068 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:26,072 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:26,073 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:26,074 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:26,075 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:26,076 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:26,081 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:26,082 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:26,082 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:26,083 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:26,084 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:26,084 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:26,085 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:26,085 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:26,086 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:26,087 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:26,088 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:26,088 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:26,089 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:26,089 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:26,089 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:26,089 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:26,090 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:26,091 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:26,111 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:26,112 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:26,113 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:26,113 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:26,114 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:26,114 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:26,114 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:26,114 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:26,114 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:26,115 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:26,115 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:26,115 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:26,116 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:26,116 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:26,116 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:26,116 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:26,116 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:26,116 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:26,116 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:26,116 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:26,117 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:26,117 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:26,117 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:26,117 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:26,118 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:26,118 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:26,118 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:26,119 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:26,119 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:26,119 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:26,119 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:26,119 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:26,120 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:26,120 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2021-12-15 17:20:26,324 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:26,342 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:26,344 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:26,344 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:26,345 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:26,346 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-12-15 17:20:26,389 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/669ae43d8/f15b64f966ab40d7804362717369e9a9/FLAGbf7639ceb [2021-12-15 17:20:26,789 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:26,792 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-12-15 17:20:26,807 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/669ae43d8/f15b64f966ab40d7804362717369e9a9/FLAGbf7639ceb [2021-12-15 17:20:26,819 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/669ae43d8/f15b64f966ab40d7804362717369e9a9 [2021-12-15 17:20:26,822 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:26,823 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:26,826 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:26,826 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:26,828 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:26,829 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:26" (1/1) ... [2021-12-15 17:20:26,830 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6dd0d140 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:26, skipping insertion in model container [2021-12-15 17:20:26,830 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:26" (1/1) ... [2021-12-15 17:20:26,835 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:26,871 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:27,026 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2021-12-15 17:20:27,093 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:27,107 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:27,115 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2021-12-15 17:20:27,157 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:27,177 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:27,177 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27 WrapperNode [2021-12-15 17:20:27,177 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:27,179 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:27,179 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:27,179 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:27,184 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,204 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,233 INFO L137 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1353 [2021-12-15 17:20:27,233 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:27,234 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:27,234 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:27,234 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:27,243 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,250 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,253 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,257 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,267 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,295 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,297 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,300 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:27,301 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:27,301 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:27,301 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:27,304 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (1/1) ... [2021-12-15 17:20:27,308 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:27,317 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:27,354 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:27,385 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:27,401 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:27,402 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:27,402 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:27,405 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:27,470 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:27,471 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:28,204 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:28,213 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:28,213 INFO L301 CfgBuilder]: Removed 8 assume(true) statements. [2021-12-15 17:20:28,216 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:28 BoogieIcfgContainer [2021-12-15 17:20:28,216 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:28,217 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:28,217 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:28,220 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:28,221 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:28,221 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:26" (1/3) ... [2021-12-15 17:20:28,221 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4abc3510 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:28, skipping insertion in model container [2021-12-15 17:20:28,222 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:28,222 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:27" (2/3) ... [2021-12-15 17:20:28,222 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4abc3510 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:28, skipping insertion in model container [2021-12-15 17:20:28,222 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:28,222 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:28" (3/3) ... [2021-12-15 17:20:28,223 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2021-12-15 17:20:28,248 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:28,248 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:28,248 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:28,248 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:28,248 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:28,248 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:28,248 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:28,249 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:28,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2021-12-15 17:20:28,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:28,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:28,303 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,303 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,304 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:28,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2021-12-15 17:20:28,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:28,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:28,319 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,319 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,324 INFO L791 eck$LassoCheckResult]: Stem: 541#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 467#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 250#L903true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7#L419true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 262#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 319#L426-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 149#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 313#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 135#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 502#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 354#L451-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 378#L611-2true assume !(0 == ~T1_E~0); 372#L616-1true assume !(0 == ~T2_E~0); 385#L621-1true assume !(0 == ~T3_E~0); 68#L626-1true assume !(0 == ~T4_E~0); 344#L631-1true assume !(0 == ~T5_E~0); 174#L636-1true assume !(0 == ~E_M~0); 89#L641-1true assume !(0 == ~E_1~0); 185#L646-1true assume 0 == ~E_2~0;~E_2~0 := 1; 492#L651-1true assume !(0 == ~E_3~0); 443#L656-1true assume !(0 == ~E_4~0); 352#L661-1true assume !(0 == ~E_5~0); 402#L666-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 524#L304true assume !(1 == ~m_pc~0); 99#L304-2true is_master_triggered_~__retres1~0#1 := 0; 56#L315true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 539#L316true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29#L755true assume !(0 != activate_threads_~tmp~1#1); 547#L755-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8#L323true assume 1 == ~t1_pc~0; 299#L324true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39#L334true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 311#L335true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 493#L763true assume !(0 != activate_threads_~tmp___0~0#1); 504#L763-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41#L342true assume 1 == ~t2_pc~0; 521#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103#L353true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 483#L354true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 526#L771true assume !(0 != activate_threads_~tmp___1~0#1); 345#L771-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234#L361true assume !(1 == ~t3_pc~0); 252#L361-2true is_transmit3_triggered_~__retres1~3#1 := 0; 460#L372true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127#L373true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 434#L779true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47#L779-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232#L380true assume 1 == ~t4_pc~0; 79#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 366#L391true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 472#L392true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 269#L787true assume !(0 != activate_threads_~tmp___3~0#1); 519#L787-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80#L399true assume !(1 == ~t5_pc~0); 155#L399-2true is_transmit5_triggered_~__retres1~5#1 := 0; 381#L410true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 482#L411true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 150#L795true assume !(0 != activate_threads_~tmp___4~0#1); 454#L795-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 527#L679true assume !(1 == ~M_E~0); 203#L679-2true assume !(1 == ~T1_E~0); 110#L684-1true assume !(1 == ~T2_E~0); 241#L689-1true assume !(1 == ~T3_E~0); 536#L694-1true assume !(1 == ~T4_E~0); 240#L699-1true assume !(1 == ~T5_E~0); 353#L704-1true assume !(1 == ~E_M~0); 221#L709-1true assume 1 == ~E_1~0;~E_1~0 := 2; 177#L714-1true assume !(1 == ~E_2~0); 336#L719-1true assume !(1 == ~E_3~0); 478#L724-1true assume !(1 == ~E_4~0); 62#L729-1true assume !(1 == ~E_5~0); 463#L734-1true assume { :end_inline_reset_delta_events } true; 326#L940-2true [2021-12-15 17:20:28,326 INFO L793 eck$LassoCheckResult]: Loop: 326#L940-2true assume !false; 396#L941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 108#L586true assume !true; 485#L601true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 416#L419-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 295#L611-3true assume 0 == ~M_E~0;~M_E~0 := 1; 63#L611-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 307#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 60#L621-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 32#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 556#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 33#L636-3true assume !(0 == ~E_M~0); 69#L641-3true assume 0 == ~E_1~0;~E_1~0 := 1; 237#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 75#L651-3true assume 0 == ~E_3~0;~E_3~0 := 1; 213#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 494#L661-3true assume 0 == ~E_5~0;~E_5~0 := 1; 506#L666-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152#L304-21true assume !(1 == ~m_pc~0); 77#L304-23true is_master_triggered_~__retres1~0#1 := 0; 265#L315-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 507#L316-7true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 195#L755-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 215#L755-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 490#L323-21true assume !(1 == ~t1_pc~0); 361#L323-23true is_transmit1_triggered_~__retres1~1#1 := 0; 403#L334-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 312#L335-7true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 397#L763-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 421#L763-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 553#L342-21true assume 1 == ~t2_pc~0; 27#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 257#L353-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 391#L354-7true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 347#L771-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81#L771-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 473#L361-21true assume !(1 == ~t3_pc~0); 456#L361-23true is_transmit3_triggered_~__retres1~3#1 := 0; 477#L372-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 368#L373-7true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175#L779-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31#L779-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 515#L380-21true assume 1 == ~t4_pc~0; 431#L381-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95#L391-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 321#L392-7true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 335#L787-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 271#L787-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140#L399-21true assume 1 == ~t5_pc~0; 123#L400-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 283#L410-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 419#L411-7true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 499#L795-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 448#L795-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28#L679-3true assume 1 == ~M_E~0;~M_E~0 := 2; 182#L679-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 224#L684-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 3#L689-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 165#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 22#L699-3true assume !(1 == ~T5_E~0); 297#L704-3true assume 1 == ~E_M~0;~E_M~0 := 2; 395#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 288#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 159#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 21#L724-3true assume 1 == ~E_4~0;~E_4~0 := 2; 275#L729-3true assume 1 == ~E_5~0;~E_5~0 := 2; 316#L734-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 38#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 214#L496-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 45#L497-1true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 249#L959true assume !(0 == start_simulation_~tmp~3#1); 514#L959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 179#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 376#L496-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 457#L497-2true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 363#L914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121#L921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 543#L922true start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 298#L972true assume !(0 != start_simulation_~tmp___0~1#1); 326#L940-2true [2021-12-15 17:20:28,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:28,330 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2021-12-15 17:20:28,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:28,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658008238] [2021-12-15 17:20:28,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:28,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:28,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:28,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:28,502 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:28,502 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658008238] [2021-12-15 17:20:28,502 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658008238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:28,502 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:28,503 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:28,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116197100] [2021-12-15 17:20:28,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:28,506 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:28,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:28,507 INFO L85 PathProgramCache]: Analyzing trace with hash 874088918, now seen corresponding path program 1 times [2021-12-15 17:20:28,507 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:28,507 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033342433] [2021-12-15 17:20:28,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:28,508 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:28,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:28,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:28,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:28,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033342433] [2021-12-15 17:20:28,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2033342433] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:28,539 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:28,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:28,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137813516] [2021-12-15 17:20:28,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:28,592 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:28,593 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:28,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:28,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:28,620 INFO L87 Difference]: Start difference. First operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:28,669 INFO L93 Difference]: Finished difference Result 557 states and 833 transitions. [2021-12-15 17:20:28,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:28,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 833 transitions. [2021-12-15 17:20:28,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:28,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 551 states and 827 transitions. [2021-12-15 17:20:28,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2021-12-15 17:20:28,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2021-12-15 17:20:28,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 827 transitions. [2021-12-15 17:20:28,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:28,703 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 827 transitions. [2021-12-15 17:20:28,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 827 transitions. [2021-12-15 17:20:28,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2021-12-15 17:20:28,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.5009074410163339) internal successors, (827), 550 states have internal predecessors, (827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 827 transitions. [2021-12-15 17:20:28,751 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 827 transitions. [2021-12-15 17:20:28,752 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 827 transitions. [2021-12-15 17:20:28,752 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:28,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 827 transitions. [2021-12-15 17:20:28,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:28,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:28,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:28,761 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,761 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,761 INFO L791 eck$LassoCheckResult]: Stem: 1675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1665#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1540#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1135#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1136#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1548#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1403#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1404#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1381#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1382#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1611#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1485#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1486#L611-2 assume !(0 == ~T1_E~0); 1622#L616-1 assume !(0 == ~T2_E~0); 1623#L621-1 assume !(0 == ~T3_E~0); 1257#L626-1 assume !(0 == ~T4_E~0); 1258#L631-1 assume !(0 == ~T5_E~0); 1443#L636-1 assume !(0 == ~E_M~0); 1301#L641-1 assume !(0 == ~E_1~0); 1302#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1460#L651-1 assume !(0 == ~E_3~0); 1655#L656-1 assume !(0 == ~E_4~0); 1609#L661-1 assume !(0 == ~E_5~0); 1610#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1635#L304 assume !(1 == ~m_pc~0); 1319#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1233#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1234#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1179#L755 assume !(0 != activate_threads_~tmp~1#1); 1180#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1137#L323 assume 1 == ~t1_pc~0; 1138#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1202#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1203#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1583#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1671#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1205#L342 assume 1 == ~t2_pc~0; 1206#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1324#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1325#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1667#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1605#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1520#L361 assume !(1 == ~t3_pc~0); 1521#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1541#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1366#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1367#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1220#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1221#L380 assume 1 == ~t4_pc~0; 1278#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1279#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1616#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1552#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1553#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1281#L399 assume !(1 == ~t5_pc~0); 1282#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1415#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1625#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1405#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1406#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1661#L679 assume !(1 == ~M_E~0); 1483#L679-2 assume !(1 == ~T1_E~0); 1337#L684-1 assume !(1 == ~T2_E~0); 1338#L689-1 assume !(1 == ~T3_E~0); 1529#L694-1 assume !(1 == ~T4_E~0); 1527#L699-1 assume !(1 == ~T5_E~0); 1528#L704-1 assume !(1 == ~E_M~0); 1506#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1450#L714-1 assume !(1 == ~E_2~0); 1451#L719-1 assume !(1 == ~E_3~0); 1601#L724-1 assume !(1 == ~E_4~0); 1243#L729-1 assume !(1 == ~E_5~0); 1244#L734-1 assume { :end_inline_reset_delta_events } true; 1573#L940-2 [2021-12-15 17:20:28,763 INFO L793 eck$LassoCheckResult]: Loop: 1573#L940-2 assume !false; 1593#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1333#L586 assume !false; 1334#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1659#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1524#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1525#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1515#L511 assume !(0 != eval_~tmp~0#1); 1516#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1644#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1570#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1245#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1246#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1241#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1186#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1187#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1188#L636-3 assume !(0 == ~E_M~0); 1189#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1259#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1269#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1270#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1500#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1672#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1410#L304-21 assume 1 == ~m_pc~0; 1411#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1274#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1549#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1473#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1474#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1501#L323-21 assume 1 == ~t1_pc~0; 1150#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1152#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1584#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1585#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1634#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1648#L342-21 assume 1 == ~t2_pc~0; 1174#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1175#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1545#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1606#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1284#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1285#L361-21 assume 1 == ~t3_pc~0; 1666#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1663#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1617#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1446#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1184#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1185#L380-21 assume !(1 == ~t4_pc~0); 1251#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 1252#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1311#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1589#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1555#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1391#L399-21 assume !(1 == ~t5_pc~0); 1255#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1256#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1565#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1646#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1658#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1177#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1178#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1456#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1125#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1126#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1164#L699-3 assume !(1 == ~T5_E~0); 1165#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1571#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1567#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1416#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1162#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1163#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1560#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1197#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1198#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1212#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1213#L959 assume !(0 == start_simulation_~tmp~3#1); 1539#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1447#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1448#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1624#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1614#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1357#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1358#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1572#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1573#L940-2 [2021-12-15 17:20:28,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:28,764 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2021-12-15 17:20:28,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:28,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402889028] [2021-12-15 17:20:28,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:28,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:28,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:28,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:28,802 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:28,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402889028] [2021-12-15 17:20:28,803 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [402889028] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:28,803 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:28,803 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:28,803 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505949430] [2021-12-15 17:20:28,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:28,804 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:28,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:28,804 INFO L85 PathProgramCache]: Analyzing trace with hash 602778604, now seen corresponding path program 1 times [2021-12-15 17:20:28,804 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:28,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646910259] [2021-12-15 17:20:28,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:28,805 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:28,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:28,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:28,868 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:28,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646910259] [2021-12-15 17:20:28,868 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646910259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:28,868 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:28,868 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:28,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236531340] [2021-12-15 17:20:28,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:28,869 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:28,869 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:28,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:28,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:28,870 INFO L87 Difference]: Start difference. First operand 551 states and 827 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:28,880 INFO L93 Difference]: Finished difference Result 551 states and 826 transitions. [2021-12-15 17:20:28,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:28,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 826 transitions. [2021-12-15 17:20:28,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:28,886 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 826 transitions. [2021-12-15 17:20:28,886 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2021-12-15 17:20:28,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2021-12-15 17:20:28,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 826 transitions. [2021-12-15 17:20:28,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:28,888 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 826 transitions. [2021-12-15 17:20:28,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 826 transitions. [2021-12-15 17:20:28,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2021-12-15 17:20:28,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4990925589836661) internal successors, (826), 550 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:28,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 826 transitions. [2021-12-15 17:20:28,900 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 826 transitions. [2021-12-15 17:20:28,900 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 826 transitions. [2021-12-15 17:20:28,900 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:28,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 826 transitions. [2021-12-15 17:20:28,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:28,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:28,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:28,903 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,903 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:28,904 INFO L791 eck$LassoCheckResult]: Stem: 2784#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2649#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2244#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2245#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2657#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2512#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2513#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2490#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2491#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2720#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2594#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2595#L611-2 assume !(0 == ~T1_E~0); 2731#L616-1 assume !(0 == ~T2_E~0); 2732#L621-1 assume !(0 == ~T3_E~0); 2366#L626-1 assume !(0 == ~T4_E~0); 2367#L631-1 assume !(0 == ~T5_E~0); 2555#L636-1 assume !(0 == ~E_M~0); 2410#L641-1 assume !(0 == ~E_1~0); 2411#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2569#L651-1 assume !(0 == ~E_3~0); 2764#L656-1 assume !(0 == ~E_4~0); 2718#L661-1 assume !(0 == ~E_5~0); 2719#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2744#L304 assume !(1 == ~m_pc~0); 2428#L304-2 is_master_triggered_~__retres1~0#1 := 0; 2342#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2343#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2290#L755 assume !(0 != activate_threads_~tmp~1#1); 2291#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2246#L323 assume 1 == ~t1_pc~0; 2247#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2311#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2312#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2692#L763 assume !(0 != activate_threads_~tmp___0~0#1); 2780#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2318#L342 assume 1 == ~t2_pc~0; 2319#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2433#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2434#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2776#L771 assume !(0 != activate_threads_~tmp___1~0#1); 2714#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2629#L361 assume !(1 == ~t3_pc~0); 2630#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2650#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2475#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2476#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2329#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2330#L380 assume 1 == ~t4_pc~0; 2387#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2388#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2725#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2662#L787 assume !(0 != activate_threads_~tmp___3~0#1); 2663#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2390#L399 assume !(1 == ~t5_pc~0); 2391#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2524#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2734#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2514#L795 assume !(0 != activate_threads_~tmp___4~0#1); 2515#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2770#L679 assume !(1 == ~M_E~0); 2592#L679-2 assume !(1 == ~T1_E~0); 2446#L684-1 assume !(1 == ~T2_E~0); 2447#L689-1 assume !(1 == ~T3_E~0); 2638#L694-1 assume !(1 == ~T4_E~0); 2636#L699-1 assume !(1 == ~T5_E~0); 2637#L704-1 assume !(1 == ~E_M~0); 2615#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2559#L714-1 assume !(1 == ~E_2~0); 2560#L719-1 assume !(1 == ~E_3~0); 2710#L724-1 assume !(1 == ~E_4~0); 2352#L729-1 assume !(1 == ~E_5~0); 2353#L734-1 assume { :end_inline_reset_delta_events } true; 2682#L940-2 [2021-12-15 17:20:28,904 INFO L793 eck$LassoCheckResult]: Loop: 2682#L940-2 assume !false; 2702#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2444#L586 assume !false; 2445#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2768#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2633#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2634#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2624#L511 assume !(0 != eval_~tmp~0#1); 2625#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2753#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2679#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2354#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2355#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2351#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2295#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2296#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2297#L636-3 assume !(0 == ~E_M~0); 2298#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2368#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2378#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2379#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2609#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2781#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2519#L304-21 assume 1 == ~m_pc~0; 2520#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2383#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2658#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2582#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2583#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2610#L323-21 assume 1 == ~t1_pc~0; 2259#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2261#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2693#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2694#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2743#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2757#L342-21 assume 1 == ~t2_pc~0; 2283#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2284#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2654#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2715#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2393#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2394#L361-21 assume !(1 == ~t3_pc~0); 2771#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2772#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2726#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2554#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2288#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2289#L380-21 assume !(1 == ~t4_pc~0); 2358#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 2359#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2420#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2698#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2664#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2500#L399-21 assume 1 == ~t5_pc~0; 2468#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2365#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2674#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2755#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2767#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2286#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2287#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2565#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2234#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2235#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2273#L699-3 assume !(1 == ~T5_E~0); 2274#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2680#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2676#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2526#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2271#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2272#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2669#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2306#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2307#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2321#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2322#L959 assume !(0 == start_simulation_~tmp~3#1); 2648#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2556#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2557#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2733#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2723#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2466#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2467#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2681#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2682#L940-2 [2021-12-15 17:20:28,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:28,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2021-12-15 17:20:28,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:28,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499328907] [2021-12-15 17:20:28,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:28,905 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:28,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:28,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:28,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:28,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499328907] [2021-12-15 17:20:28,961 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1499328907] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:28,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:28,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:28,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866873384] [2021-12-15 17:20:28,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:28,962 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:28,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:28,963 INFO L85 PathProgramCache]: Analyzing trace with hash -22187412, now seen corresponding path program 1 times [2021-12-15 17:20:28,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:28,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619175640] [2021-12-15 17:20:28,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:28,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:28,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619175640] [2021-12-15 17:20:29,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619175640] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,017 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,017 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549304460] [2021-12-15 17:20:29,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,017 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,018 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,018 INFO L87 Difference]: Start difference. First operand 551 states and 826 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,030 INFO L93 Difference]: Finished difference Result 551 states and 825 transitions. [2021-12-15 17:20:29,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 825 transitions. [2021-12-15 17:20:29,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:29,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 825 transitions. [2021-12-15 17:20:29,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2021-12-15 17:20:29,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2021-12-15 17:20:29,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 825 transitions. [2021-12-15 17:20:29,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,037 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 825 transitions. [2021-12-15 17:20:29,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 825 transitions. [2021-12-15 17:20:29,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2021-12-15 17:20:29,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4972776769509981) internal successors, (825), 550 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 825 transitions. [2021-12-15 17:20:29,045 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 825 transitions. [2021-12-15 17:20:29,045 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 825 transitions. [2021-12-15 17:20:29,045 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:29,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 825 transitions. [2021-12-15 17:20:29,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:29,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,048 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,048 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,049 INFO L791 eck$LassoCheckResult]: Stem: 3893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3758#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3353#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3354#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3766#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3621#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3622#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3599#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3829#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3703#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3704#L611-2 assume !(0 == ~T1_E~0); 3840#L616-1 assume !(0 == ~T2_E~0); 3841#L621-1 assume !(0 == ~T3_E~0); 3475#L626-1 assume !(0 == ~T4_E~0); 3476#L631-1 assume !(0 == ~T5_E~0); 3664#L636-1 assume !(0 == ~E_M~0); 3519#L641-1 assume !(0 == ~E_1~0); 3520#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3678#L651-1 assume !(0 == ~E_3~0); 3873#L656-1 assume !(0 == ~E_4~0); 3827#L661-1 assume !(0 == ~E_5~0); 3828#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3853#L304 assume !(1 == ~m_pc~0); 3539#L304-2 is_master_triggered_~__retres1~0#1 := 0; 3451#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3452#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3399#L755 assume !(0 != activate_threads_~tmp~1#1); 3400#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3355#L323 assume 1 == ~t1_pc~0; 3356#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3420#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3421#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3803#L763 assume !(0 != activate_threads_~tmp___0~0#1); 3889#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3427#L342 assume 1 == ~t2_pc~0; 3428#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3542#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3543#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3885#L771 assume !(0 != activate_threads_~tmp___1~0#1); 3823#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3738#L361 assume !(1 == ~t3_pc~0); 3739#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3759#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3584#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3585#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3438#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3439#L380 assume 1 == ~t4_pc~0; 3496#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3497#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3834#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3771#L787 assume !(0 != activate_threads_~tmp___3~0#1); 3772#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3499#L399 assume !(1 == ~t5_pc~0); 3500#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3633#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3843#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3623#L795 assume !(0 != activate_threads_~tmp___4~0#1); 3624#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3879#L679 assume !(1 == ~M_E~0); 3701#L679-2 assume !(1 == ~T1_E~0); 3555#L684-1 assume !(1 == ~T2_E~0); 3556#L689-1 assume !(1 == ~T3_E~0); 3747#L694-1 assume !(1 == ~T4_E~0); 3745#L699-1 assume !(1 == ~T5_E~0); 3746#L704-1 assume !(1 == ~E_M~0); 3724#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3668#L714-1 assume !(1 == ~E_2~0); 3669#L719-1 assume !(1 == ~E_3~0); 3819#L724-1 assume !(1 == ~E_4~0); 3461#L729-1 assume !(1 == ~E_5~0); 3462#L734-1 assume { :end_inline_reset_delta_events } true; 3791#L940-2 [2021-12-15 17:20:29,049 INFO L793 eck$LassoCheckResult]: Loop: 3791#L940-2 assume !false; 3811#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3553#L586 assume !false; 3554#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3877#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3742#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3743#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3733#L511 assume !(0 != eval_~tmp~0#1); 3734#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3862#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3788#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3463#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3464#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3460#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3404#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3405#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3406#L636-3 assume !(0 == ~E_M~0); 3407#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3477#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3487#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3488#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3718#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3890#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3628#L304-21 assume !(1 == ~m_pc~0); 3491#L304-23 is_master_triggered_~__retres1~0#1 := 0; 3492#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3768#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3691#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3692#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3719#L323-21 assume 1 == ~t1_pc~0; 3368#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3370#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3801#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3802#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3852#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3866#L342-21 assume 1 == ~t2_pc~0; 3392#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3393#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3763#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3824#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3502#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3503#L361-21 assume !(1 == ~t3_pc~0); 3880#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3881#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3835#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3663#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3397#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3398#L380-21 assume !(1 == ~t4_pc~0); 3467#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 3468#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3529#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3807#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3773#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3609#L399-21 assume !(1 == ~t5_pc~0); 3473#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3474#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3783#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3864#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3876#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3395#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3396#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3674#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3343#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3344#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3382#L699-3 assume !(1 == ~T5_E~0); 3383#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3789#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3785#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3635#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3380#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3381#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3778#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3415#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3416#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3430#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3431#L959 assume !(0 == start_simulation_~tmp~3#1); 3757#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3665#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3666#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3842#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3832#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3575#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3576#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3790#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3791#L940-2 [2021-12-15 17:20:29,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,051 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2021-12-15 17:20:29,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811823182] [2021-12-15 17:20:29,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,091 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811823182] [2021-12-15 17:20:29,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811823182] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,092 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,092 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,092 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726163443] [2021-12-15 17:20:29,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,092 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,093 INFO L85 PathProgramCache]: Analyzing trace with hash -765126226, now seen corresponding path program 1 times [2021-12-15 17:20:29,093 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,093 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290191568] [2021-12-15 17:20:29,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,094 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,140 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,140 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290191568] [2021-12-15 17:20:29,141 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290191568] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,141 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,141 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,141 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024209212] [2021-12-15 17:20:29,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,141 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,142 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,142 INFO L87 Difference]: Start difference. First operand 551 states and 825 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,151 INFO L93 Difference]: Finished difference Result 551 states and 824 transitions. [2021-12-15 17:20:29,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 824 transitions. [2021-12-15 17:20:29,154 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:29,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 824 transitions. [2021-12-15 17:20:29,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2021-12-15 17:20:29,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2021-12-15 17:20:29,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 824 transitions. [2021-12-15 17:20:29,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,157 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 824 transitions. [2021-12-15 17:20:29,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 824 transitions. [2021-12-15 17:20:29,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2021-12-15 17:20:29,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4954627949183303) internal successors, (824), 550 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 824 transitions. [2021-12-15 17:20:29,175 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 824 transitions. [2021-12-15 17:20:29,175 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 824 transitions. [2021-12-15 17:20:29,175 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:29,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 824 transitions. [2021-12-15 17:20:29,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:29,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,179 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,179 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,179 INFO L791 eck$LassoCheckResult]: Stem: 5002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4867#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4464#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4465#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 4875#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4730#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4731#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4708#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4709#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4938#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4812#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 4813#L611-2 assume !(0 == ~T1_E~0); 4949#L616-1 assume !(0 == ~T2_E~0); 4950#L621-1 assume !(0 == ~T3_E~0); 4584#L626-1 assume !(0 == ~T4_E~0); 4585#L631-1 assume !(0 == ~T5_E~0); 4773#L636-1 assume !(0 == ~E_M~0); 4628#L641-1 assume !(0 == ~E_1~0); 4629#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4787#L651-1 assume !(0 == ~E_3~0); 4982#L656-1 assume !(0 == ~E_4~0); 4936#L661-1 assume !(0 == ~E_5~0); 4937#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4962#L304 assume !(1 == ~m_pc~0); 4648#L304-2 is_master_triggered_~__retres1~0#1 := 0; 4560#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4561#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4508#L755 assume !(0 != activate_threads_~tmp~1#1); 4509#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4466#L323 assume 1 == ~t1_pc~0; 4467#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4529#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4530#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4912#L763 assume !(0 != activate_threads_~tmp___0~0#1); 4998#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4536#L342 assume 1 == ~t2_pc~0; 4537#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4651#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4652#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4994#L771 assume !(0 != activate_threads_~tmp___1~0#1); 4932#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4847#L361 assume !(1 == ~t3_pc~0); 4848#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4868#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4693#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4694#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4547#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4548#L380 assume 1 == ~t4_pc~0; 4605#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4606#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4943#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4880#L787 assume !(0 != activate_threads_~tmp___3~0#1); 4881#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4608#L399 assume !(1 == ~t5_pc~0); 4609#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4742#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4952#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4732#L795 assume !(0 != activate_threads_~tmp___4~0#1); 4733#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4988#L679 assume !(1 == ~M_E~0); 4811#L679-2 assume !(1 == ~T1_E~0); 4664#L684-1 assume !(1 == ~T2_E~0); 4665#L689-1 assume !(1 == ~T3_E~0); 4856#L694-1 assume !(1 == ~T4_E~0); 4854#L699-1 assume !(1 == ~T5_E~0); 4855#L704-1 assume !(1 == ~E_M~0); 4833#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4778#L714-1 assume !(1 == ~E_2~0); 4779#L719-1 assume !(1 == ~E_3~0); 4928#L724-1 assume !(1 == ~E_4~0); 4570#L729-1 assume !(1 == ~E_5~0); 4571#L734-1 assume { :end_inline_reset_delta_events } true; 4900#L940-2 [2021-12-15 17:20:29,179 INFO L793 eck$LassoCheckResult]: Loop: 4900#L940-2 assume !false; 4920#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4662#L586 assume !false; 4663#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4986#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4851#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4852#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4843#L511 assume !(0 != eval_~tmp~0#1); 4844#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4971#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4897#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4572#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4573#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4569#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4513#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4514#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4515#L636-3 assume !(0 == ~E_M~0); 4516#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4586#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4596#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4597#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4827#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4999#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4737#L304-21 assume 1 == ~m_pc~0; 4738#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4601#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4876#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4800#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4801#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4828#L323-21 assume 1 == ~t1_pc~0; 4477#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4479#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4910#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4911#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4961#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4975#L342-21 assume 1 == ~t2_pc~0; 4501#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4502#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4872#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4933#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4611#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4612#L361-21 assume 1 == ~t3_pc~0; 4993#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4990#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4944#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4772#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4506#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4507#L380-21 assume !(1 == ~t4_pc~0); 4578#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4579#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4638#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4916#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4882#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4718#L399-21 assume !(1 == ~t5_pc~0); 4582#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4583#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4892#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4973#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4985#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4504#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4505#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4783#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4452#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4453#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4491#L699-3 assume !(1 == ~T5_E~0); 4492#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4898#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4894#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4744#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4489#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4490#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4887#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4526#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4527#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4541#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4542#L959 assume !(0 == start_simulation_~tmp~3#1); 4866#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4775#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4776#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4951#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4941#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4684#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4685#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4899#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4900#L940-2 [2021-12-15 17:20:29,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,180 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2021-12-15 17:20:29,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454623360] [2021-12-15 17:20:29,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,225 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,225 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454623360] [2021-12-15 17:20:29,225 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454623360] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,226 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,226 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,226 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639885806] [2021-12-15 17:20:29,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,226 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,226 INFO L85 PathProgramCache]: Analyzing trace with hash 602778604, now seen corresponding path program 2 times [2021-12-15 17:20:29,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338069898] [2021-12-15 17:20:29,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,227 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,249 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338069898] [2021-12-15 17:20:29,249 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338069898] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,249 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,249 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427542361] [2021-12-15 17:20:29,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,250 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,250 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,250 INFO L87 Difference]: Start difference. First operand 551 states and 824 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,258 INFO L93 Difference]: Finished difference Result 551 states and 823 transitions. [2021-12-15 17:20:29,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 823 transitions. [2021-12-15 17:20:29,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:29,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 823 transitions. [2021-12-15 17:20:29,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2021-12-15 17:20:29,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2021-12-15 17:20:29,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 823 transitions. [2021-12-15 17:20:29,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,266 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 823 transitions. [2021-12-15 17:20:29,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 823 transitions. [2021-12-15 17:20:29,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2021-12-15 17:20:29,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4936479128856623) internal successors, (823), 550 states have internal predecessors, (823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 823 transitions. [2021-12-15 17:20:29,273 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 823 transitions. [2021-12-15 17:20:29,273 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 823 transitions. [2021-12-15 17:20:29,273 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:29,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 823 transitions. [2021-12-15 17:20:29,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2021-12-15 17:20:29,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,277 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,277 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,277 INFO L791 eck$LassoCheckResult]: Stem: 6111#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5976#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5573#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5574#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 5984#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5839#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5840#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5817#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5818#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6047#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5921#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5922#L611-2 assume !(0 == ~T1_E~0); 6058#L616-1 assume !(0 == ~T2_E~0); 6059#L621-1 assume !(0 == ~T3_E~0); 5697#L626-1 assume !(0 == ~T4_E~0); 5698#L631-1 assume !(0 == ~T5_E~0); 5882#L636-1 assume !(0 == ~E_M~0); 5739#L641-1 assume !(0 == ~E_1~0); 5740#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5896#L651-1 assume !(0 == ~E_3~0); 6091#L656-1 assume !(0 == ~E_4~0); 6045#L661-1 assume !(0 == ~E_5~0); 6046#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6071#L304 assume !(1 == ~m_pc~0); 5758#L304-2 is_master_triggered_~__retres1~0#1 := 0; 5669#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5670#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5620#L755 assume !(0 != activate_threads_~tmp~1#1); 5621#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5575#L323 assume 1 == ~t1_pc~0; 5576#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5638#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5639#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6021#L763 assume !(0 != activate_threads_~tmp___0~0#1); 6107#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5645#L342 assume 1 == ~t2_pc~0; 5646#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5760#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5761#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6103#L771 assume !(0 != activate_threads_~tmp___1~0#1); 6041#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5956#L361 assume !(1 == ~t3_pc~0); 5957#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5977#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5802#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5803#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5656#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5657#L380 assume 1 == ~t4_pc~0; 5714#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5715#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6052#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5989#L787 assume !(0 != activate_threads_~tmp___3~0#1); 5990#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5717#L399 assume !(1 == ~t5_pc~0); 5718#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5851#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6062#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5841#L795 assume !(0 != activate_threads_~tmp___4~0#1); 5842#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6097#L679 assume !(1 == ~M_E~0); 5920#L679-2 assume !(1 == ~T1_E~0); 5773#L684-1 assume !(1 == ~T2_E~0); 5774#L689-1 assume !(1 == ~T3_E~0); 5965#L694-1 assume !(1 == ~T4_E~0); 5963#L699-1 assume !(1 == ~T5_E~0); 5964#L704-1 assume !(1 == ~E_M~0); 5942#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5887#L714-1 assume !(1 == ~E_2~0); 5888#L719-1 assume !(1 == ~E_3~0); 6037#L724-1 assume !(1 == ~E_4~0); 5679#L729-1 assume !(1 == ~E_5~0); 5680#L734-1 assume { :end_inline_reset_delta_events } true; 6010#L940-2 [2021-12-15 17:20:29,277 INFO L793 eck$LassoCheckResult]: Loop: 6010#L940-2 assume !false; 6029#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5771#L586 assume !false; 5772#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6095#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5960#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5961#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5952#L511 assume !(0 != eval_~tmp~0#1); 5953#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6080#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6006#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5681#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5682#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5677#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5622#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5623#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5624#L636-3 assume !(0 == ~E_M~0); 5625#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5691#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5705#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5706#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5936#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6108#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5846#L304-21 assume 1 == ~m_pc~0; 5847#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5710#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5985#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5909#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5910#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5937#L323-21 assume 1 == ~t1_pc~0; 5586#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5588#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6019#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6020#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6070#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6084#L342-21 assume 1 == ~t2_pc~0; 5610#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5611#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5981#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6042#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5720#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5721#L361-21 assume !(1 == ~t3_pc~0); 6098#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6099#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6053#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5881#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5618#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5619#L380-21 assume !(1 == ~t4_pc~0); 5687#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5688#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5747#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6025#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5991#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5827#L399-21 assume 1 == ~t5_pc~0; 5796#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5696#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6001#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6083#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6094#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5613#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5614#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5892#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5561#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5562#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5600#L699-3 assume !(1 == ~T5_E~0); 5601#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6008#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6003#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5855#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5598#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5599#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5996#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5635#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5636#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5650#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5651#L959 assume !(0 == start_simulation_~tmp~3#1); 5975#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5884#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5885#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6060#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6050#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5793#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5794#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6009#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6010#L940-2 [2021-12-15 17:20:29,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,278 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2021-12-15 17:20:29,278 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182620019] [2021-12-15 17:20:29,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182620019] [2021-12-15 17:20:29,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [182620019] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,305 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,305 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:29,306 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700799832] [2021-12-15 17:20:29,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,306 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,308 INFO L85 PathProgramCache]: Analyzing trace with hash -22187412, now seen corresponding path program 2 times [2021-12-15 17:20:29,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612581648] [2021-12-15 17:20:29,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,311 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612581648] [2021-12-15 17:20:29,352 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612581648] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,352 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,352 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,352 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839141937] [2021-12-15 17:20:29,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,352 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,352 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,353 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,353 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,353 INFO L87 Difference]: Start difference. First operand 551 states and 823 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,378 INFO L93 Difference]: Finished difference Result 979 states and 1457 transitions. [2021-12-15 17:20:29,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 979 states and 1457 transitions. [2021-12-15 17:20:29,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2021-12-15 17:20:29,387 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 979 states to 979 states and 1457 transitions. [2021-12-15 17:20:29,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 979 [2021-12-15 17:20:29,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 979 [2021-12-15 17:20:29,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 979 states and 1457 transitions. [2021-12-15 17:20:29,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,388 INFO L681 BuchiCegarLoop]: Abstraction has 979 states and 1457 transitions. [2021-12-15 17:20:29,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 979 states and 1457 transitions. [2021-12-15 17:20:29,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 979 to 979. [2021-12-15 17:20:29,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4882533197139938) internal successors, (1457), 978 states have internal predecessors, (1457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1457 transitions. [2021-12-15 17:20:29,404 INFO L704 BuchiCegarLoop]: Abstraction has 979 states and 1457 transitions. [2021-12-15 17:20:29,404 INFO L587 BuchiCegarLoop]: Abstraction has 979 states and 1457 transitions. [2021-12-15 17:20:29,404 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:29,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1457 transitions. [2021-12-15 17:20:29,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2021-12-15 17:20:29,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,409 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,409 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,410 INFO L791 eck$LassoCheckResult]: Stem: 7706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7526#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7113#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7114#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7536#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7380#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7381#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7356#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7357#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7612#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7468#L611 assume !(0 == ~M_E~0); 7469#L611-2 assume !(0 == ~T1_E~0); 7624#L616-1 assume !(0 == ~T2_E~0); 7625#L621-1 assume !(0 == ~T3_E~0); 7235#L626-1 assume !(0 == ~T4_E~0); 7236#L631-1 assume !(0 == ~T5_E~0); 7427#L636-1 assume !(0 == ~E_M~0); 7277#L641-1 assume !(0 == ~E_1~0); 7278#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7442#L651-1 assume !(0 == ~E_3~0); 7674#L656-1 assume !(0 == ~E_4~0); 7610#L661-1 assume !(0 == ~E_5~0); 7611#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7643#L304 assume !(1 == ~m_pc~0); 7294#L304-2 is_master_triggered_~__retres1~0#1 := 0; 7206#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7207#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7152#L755 assume !(0 != activate_threads_~tmp~1#1); 7153#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7106#L323 assume 1 == ~t1_pc~0; 7107#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7175#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7176#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7579#L763 assume !(0 != activate_threads_~tmp___0~0#1); 7695#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7178#L342 assume 1 == ~t2_pc~0; 7179#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7299#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7300#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7689#L771 assume !(0 != activate_threads_~tmp___1~0#1); 7606#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7506#L361 assume !(1 == ~t3_pc~0); 7507#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7527#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7341#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7342#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7191#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7192#L380 assume 1 == ~t4_pc~0; 7252#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7253#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7617#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7540#L787 assume !(0 != activate_threads_~tmp___3~0#1); 7541#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7255#L399 assume !(1 == ~t5_pc~0); 7256#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7393#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7628#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7382#L795 assume !(0 != activate_threads_~tmp___4~0#1); 7383#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7680#L679 assume !(1 == ~M_E~0); 7466#L679-2 assume !(1 == ~T1_E~0); 7312#L684-1 assume !(1 == ~T2_E~0); 7313#L689-1 assume !(1 == ~T3_E~0); 7515#L694-1 assume !(1 == ~T4_E~0); 7513#L699-1 assume !(1 == ~T5_E~0); 7514#L704-1 assume !(1 == ~E_M~0); 7491#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7428#L714-1 assume !(1 == ~E_2~0); 7429#L719-1 assume !(1 == ~E_3~0); 7602#L724-1 assume !(1 == ~E_4~0); 7217#L729-1 assume !(1 == ~E_5~0); 7218#L734-1 assume { :end_inline_reset_delta_events } true; 7567#L940-2 [2021-12-15 17:20:29,410 INFO L793 eck$LassoCheckResult]: Loop: 7567#L940-2 assume !false; 7591#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7308#L586 assume !false; 7309#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7678#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7593#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7742#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7740#L511 assume !(0 != eval_~tmp~0#1); 7739#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7738#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7563#L611-3 assume !(0 == ~M_E~0); 7219#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7220#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7576#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7735#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7734#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7733#L636-3 assume !(0 == ~E_M~0); 7732#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7731#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7730#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7729#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7728#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7727#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7726#L304-21 assume 1 == ~m_pc~0; 7703#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7248#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7537#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7698#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7485#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7486#L323-21 assume !(1 == ~t1_pc~0); 7692#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 7644#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7645#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7639#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7640#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7722#L342-21 assume 1 == ~t2_pc~0; 7720#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7531#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7532#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7607#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7258#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7259#L361-21 assume !(1 == ~t3_pc~0); 7681#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7682#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7619#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7425#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7426#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7714#L380-21 assume 1 == ~t4_pc~0; 7671#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7226#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7586#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7587#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7713#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7712#L399-21 assume !(1 == ~t5_pc~0); 7233#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7234#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7661#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7662#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7677#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7150#L679-3 assume !(1 == ~M_E~0); 7151#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8047#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7098#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7099#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7137#L699-3 assume !(1 == ~T5_E~0); 7138#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7565#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7560#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7398#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7135#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7136#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7549#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7583#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7484#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7187#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7188#L959 assume !(0 == start_simulation_~tmp~3#1); 7525#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7431#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7432#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7774#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7772#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7771#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7770#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7566#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7567#L940-2 [2021-12-15 17:20:29,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2021-12-15 17:20:29,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636758030] [2021-12-15 17:20:29,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,411 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,429 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636758030] [2021-12-15 17:20:29,430 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636758030] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,430 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,430 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,430 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045252209] [2021-12-15 17:20:29,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,430 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,430 INFO L85 PathProgramCache]: Analyzing trace with hash 1295691757, now seen corresponding path program 1 times [2021-12-15 17:20:29,430 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416333333] [2021-12-15 17:20:29,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,431 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,453 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416333333] [2021-12-15 17:20:29,453 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416333333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,453 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,453 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,453 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765094166] [2021-12-15 17:20:29,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,453 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:29,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:29,454 INFO L87 Difference]: Start difference. First operand 979 states and 1457 transitions. cyclomatic complexity: 479 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,528 INFO L93 Difference]: Finished difference Result 1356 states and 2012 transitions. [2021-12-15 17:20:29,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:29,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1356 states and 2012 transitions. [2021-12-15 17:20:29,536 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1272 [2021-12-15 17:20:29,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1356 states to 1356 states and 2012 transitions. [2021-12-15 17:20:29,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1356 [2021-12-15 17:20:29,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1356 [2021-12-15 17:20:29,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1356 states and 2012 transitions. [2021-12-15 17:20:29,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,543 INFO L681 BuchiCegarLoop]: Abstraction has 1356 states and 2012 transitions. [2021-12-15 17:20:29,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1356 states and 2012 transitions. [2021-12-15 17:20:29,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1356 to 979. [2021-12-15 17:20:29,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4851889683350357) internal successors, (1454), 978 states have internal predecessors, (1454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1454 transitions. [2021-12-15 17:20:29,581 INFO L704 BuchiCegarLoop]: Abstraction has 979 states and 1454 transitions. [2021-12-15 17:20:29,581 INFO L587 BuchiCegarLoop]: Abstraction has 979 states and 1454 transitions. [2021-12-15 17:20:29,581 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:29,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1454 transitions. [2021-12-15 17:20:29,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2021-12-15 17:20:29,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,585 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,585 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,585 INFO L791 eck$LassoCheckResult]: Stem: 10038#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 10021#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9872#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9455#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9456#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 9882#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9725#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9726#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9701#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9702#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9949#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9811#L611 assume !(0 == ~M_E~0); 9812#L611-2 assume !(0 == ~T1_E~0); 9966#L616-1 assume !(0 == ~T2_E~0); 9967#L621-1 assume !(0 == ~T3_E~0); 9579#L626-1 assume !(0 == ~T4_E~0); 9580#L631-1 assume !(0 == ~T5_E~0); 9769#L636-1 assume !(0 == ~E_M~0); 9622#L641-1 assume !(0 == ~E_1~0); 9623#L646-1 assume !(0 == ~E_2~0); 9785#L651-1 assume !(0 == ~E_3~0); 10008#L656-1 assume !(0 == ~E_4~0); 9947#L661-1 assume !(0 == ~E_5~0); 9948#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9981#L304 assume !(1 == ~m_pc~0); 9641#L304-2 is_master_triggered_~__retres1~0#1 := 0; 9551#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9552#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9502#L755 assume !(0 != activate_threads_~tmp~1#1); 9503#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9457#L323 assume 1 == ~t1_pc~0; 9458#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9520#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9521#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9923#L763 assume !(0 != activate_threads_~tmp___0~0#1); 10027#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9527#L342 assume 1 == ~t2_pc~0; 9528#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9643#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9644#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10023#L771 assume !(0 != activate_threads_~tmp___1~0#1); 9943#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9850#L361 assume !(1 == ~t3_pc~0); 9851#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9873#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9686#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9687#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9538#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9539#L380 assume 1 == ~t4_pc~0; 9597#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9598#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9958#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9887#L787 assume !(0 != activate_threads_~tmp___3~0#1); 9888#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9600#L399 assume !(1 == ~t5_pc~0); 9601#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9737#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9970#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9727#L795 assume !(0 != activate_threads_~tmp___4~0#1); 9728#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10017#L679 assume !(1 == ~M_E~0); 9810#L679-2 assume !(1 == ~T1_E~0); 9657#L684-1 assume !(1 == ~T2_E~0); 9658#L689-1 assume !(1 == ~T3_E~0); 9859#L694-1 assume !(1 == ~T4_E~0); 9857#L699-1 assume !(1 == ~T5_E~0); 9858#L704-1 assume !(1 == ~E_M~0); 9836#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9776#L714-1 assume !(1 == ~E_2~0); 9777#L719-1 assume !(1 == ~E_3~0); 9939#L724-1 assume !(1 == ~E_4~0); 9561#L729-1 assume !(1 == ~E_5~0); 9562#L734-1 assume { :end_inline_reset_delta_events } true; 9912#L940-2 [2021-12-15 17:20:29,588 INFO L793 eck$LassoCheckResult]: Loop: 9912#L940-2 assume !false; 9931#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9655#L586 assume !false; 9656#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10012#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9854#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9855#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9846#L511 assume !(0 != eval_~tmp~0#1); 9847#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9991#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9907#L611-3 assume !(0 == ~M_E~0); 9563#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9564#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9559#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9504#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9505#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9506#L636-3 assume !(0 == ~E_M~0); 9507#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9573#L646-3 assume !(0 == ~E_2~0); 9588#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9589#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9827#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10028#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9732#L304-21 assume 1 == ~m_pc~0; 9733#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9593#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9883#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9799#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9800#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9828#L323-21 assume 1 == ~t1_pc~0; 9468#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9470#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9921#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9922#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9980#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9997#L342-21 assume 1 == ~t2_pc~0; 9492#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9493#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9877#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9944#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9603#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9604#L361-21 assume !(1 == ~t3_pc~0); 10018#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 10019#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9959#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9768#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9500#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9501#L380-21 assume !(1 == ~t4_pc~0); 9569#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 9570#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9630#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9927#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9889#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9711#L399-21 assume 1 == ~t5_pc~0; 9680#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9578#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9900#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9994#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10011#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9495#L679-3 assume !(1 == ~M_E~0); 9496#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9781#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9443#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9444#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9482#L699-3 assume !(1 == ~T5_E~0); 9483#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9910#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9902#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9741#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9480#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9481#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9895#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9517#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9518#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9532#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9533#L959 assume !(0 == start_simulation_~tmp~3#1); 9871#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9773#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9774#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9968#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9955#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9677#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9678#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9911#L972 assume !(0 != start_simulation_~tmp___0~1#1); 9912#L940-2 [2021-12-15 17:20:29,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,589 INFO L85 PathProgramCache]: Analyzing trace with hash -1945891710, now seen corresponding path program 1 times [2021-12-15 17:20:29,589 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392396974] [2021-12-15 17:20:29,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,589 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,605 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,606 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [392396974] [2021-12-15 17:20:29,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [392396974] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,607 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,607 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:29,607 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822581803] [2021-12-15 17:20:29,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,607 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,608 INFO L85 PathProgramCache]: Analyzing trace with hash 273616618, now seen corresponding path program 1 times [2021-12-15 17:20:29,608 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,611 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966822748] [2021-12-15 17:20:29,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,613 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,640 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966822748] [2021-12-15 17:20:29,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1966822748] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,643 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,643 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969611414] [2021-12-15 17:20:29,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,644 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,644 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:29,645 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:29,645 INFO L87 Difference]: Start difference. First operand 979 states and 1454 transitions. cyclomatic complexity: 476 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,686 INFO L93 Difference]: Finished difference Result 1773 states and 2615 transitions. [2021-12-15 17:20:29,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:29,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1773 states and 2615 transitions. [2021-12-15 17:20:29,700 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1693 [2021-12-15 17:20:29,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1773 states to 1773 states and 2615 transitions. [2021-12-15 17:20:29,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1773 [2021-12-15 17:20:29,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1773 [2021-12-15 17:20:29,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1773 states and 2615 transitions. [2021-12-15 17:20:29,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,710 INFO L681 BuchiCegarLoop]: Abstraction has 1773 states and 2615 transitions. [2021-12-15 17:20:29,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1773 states and 2615 transitions. [2021-12-15 17:20:29,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1773 to 1769. [2021-12-15 17:20:29,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1769 states, 1769 states have (on average 1.475975127190503) internal successors, (2611), 1768 states have internal predecessors, (2611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1769 states to 1769 states and 2611 transitions. [2021-12-15 17:20:29,732 INFO L704 BuchiCegarLoop]: Abstraction has 1769 states and 2611 transitions. [2021-12-15 17:20:29,732 INFO L587 BuchiCegarLoop]: Abstraction has 1769 states and 2611 transitions. [2021-12-15 17:20:29,732 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:29,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1769 states and 2611 transitions. [2021-12-15 17:20:29,738 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1689 [2021-12-15 17:20:29,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:29,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:29,739 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,739 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:29,740 INFO L791 eck$LassoCheckResult]: Stem: 12789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12621#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12210#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12211#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 12629#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12481#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12482#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12458#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12459#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12701#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12565#L611 assume !(0 == ~M_E~0); 12566#L611-2 assume !(0 == ~T1_E~0); 12715#L616-1 assume !(0 == ~T2_E~0); 12716#L621-1 assume !(0 == ~T3_E~0); 12332#L626-1 assume !(0 == ~T4_E~0); 12333#L631-1 assume !(0 == ~T5_E~0); 12521#L636-1 assume !(0 == ~E_M~0); 12378#L641-1 assume !(0 == ~E_1~0); 12379#L646-1 assume !(0 == ~E_2~0); 12538#L651-1 assume !(0 == ~E_3~0); 12754#L656-1 assume !(0 == ~E_4~0); 12699#L661-1 assume !(0 == ~E_5~0); 12700#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12730#L304 assume !(1 == ~m_pc~0); 12396#L304-2 is_master_triggered_~__retres1~0#1 := 0; 12310#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12311#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12255#L755 assume !(0 != activate_threads_~tmp~1#1); 12256#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12212#L323 assume !(1 == ~t1_pc~0); 12213#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12278#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12279#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12668#L763 assume !(0 != activate_threads_~tmp___0~0#1); 12779#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12281#L342 assume 1 == ~t2_pc~0; 12282#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12401#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12402#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12770#L771 assume !(0 != activate_threads_~tmp___1~0#1); 12695#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12600#L361 assume !(1 == ~t3_pc~0); 12601#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12622#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12443#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12444#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12294#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12295#L380 assume 1 == ~t4_pc~0; 12355#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12356#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12707#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12633#L787 assume !(0 != activate_threads_~tmp___3~0#1); 12634#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12358#L399 assume !(1 == ~t5_pc~0); 12359#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12493#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12719#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12483#L795 assume !(0 != activate_threads_~tmp___4~0#1); 12484#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12760#L679 assume !(1 == ~M_E~0); 12563#L679-2 assume !(1 == ~T1_E~0); 12414#L684-1 assume !(1 == ~T2_E~0); 12415#L689-1 assume !(1 == ~T3_E~0); 12609#L694-1 assume !(1 == ~T4_E~0); 12607#L699-1 assume !(1 == ~T5_E~0); 12608#L704-1 assume !(1 == ~E_M~0); 12586#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12525#L714-1 assume !(1 == ~E_2~0); 12526#L719-1 assume !(1 == ~E_3~0); 12688#L724-1 assume !(1 == ~E_4~0); 12320#L729-1 assume !(1 == ~E_5~0); 12321#L734-1 assume { :end_inline_reset_delta_events } true; 12764#L940-2 [2021-12-15 17:20:29,740 INFO L793 eck$LassoCheckResult]: Loop: 12764#L940-2 assume !false; 12896#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12890#L586 assume !false; 12885#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12857#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12848#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12838#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12831#L511 assume !(0 != eval_~tmp~0#1); 12832#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13683#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13682#L611-3 assume !(0 == ~M_E~0); 13681#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13680#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13679#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13678#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13677#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13676#L636-3 assume !(0 == ~E_M~0); 13675#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13674#L646-3 assume !(0 == ~E_2~0); 13673#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13672#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13671#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13670#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13669#L304-21 assume 1 == ~m_pc~0; 13667#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13666#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13665#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12550#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12551#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12581#L323-21 assume !(1 == ~t1_pc~0); 12704#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12705#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12669#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12670#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12729#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12745#L342-21 assume 1 == ~t2_pc~0; 12250#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12251#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12626#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12696#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12361#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12362#L361-21 assume 1 == ~t3_pc~0; 12768#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12762#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12709#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12524#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12260#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12261#L380-21 assume !(1 == ~t4_pc~0); 12328#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 12329#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12388#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12674#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12637#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12467#L399-21 assume !(1 == ~t5_pc~0); 12338#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 12339#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12647#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12744#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12757#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12253#L679-3 assume !(1 == ~M_E~0); 12254#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12534#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12202#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12203#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12240#L699-3 assume !(1 == ~T5_E~0); 12241#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12657#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12651#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12497#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12238#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12239#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12642#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12275#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12276#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12290#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12291#L959 assume !(0 == start_simulation_~tmp~3#1); 12619#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12785#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12914#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12912#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12910#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12908#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12907#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12905#L972 assume !(0 != start_simulation_~tmp___0~1#1); 12764#L940-2 [2021-12-15 17:20:29,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,740 INFO L85 PathProgramCache]: Analyzing trace with hash -47361405, now seen corresponding path program 1 times [2021-12-15 17:20:29,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055278070] [2021-12-15 17:20:29,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,741 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,761 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,761 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055278070] [2021-12-15 17:20:29,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2055278070] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888413809] [2021-12-15 17:20:29,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,762 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:29,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:29,763 INFO L85 PathProgramCache]: Analyzing trace with hash -209546005, now seen corresponding path program 1 times [2021-12-15 17:20:29,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:29,763 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187014434] [2021-12-15 17:20:29,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:29,763 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:29,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:29,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:29,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:29,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187014434] [2021-12-15 17:20:29,785 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187014434] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:29,785 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:29,785 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:29,785 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350485184] [2021-12-15 17:20:29,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:29,786 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:29,786 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:29,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:29,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:29,786 INFO L87 Difference]: Start difference. First operand 1769 states and 2611 transitions. cyclomatic complexity: 844 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:29,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:29,892 INFO L93 Difference]: Finished difference Result 4061 states and 5938 transitions. [2021-12-15 17:20:29,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:29,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4061 states and 5938 transitions. [2021-12-15 17:20:29,947 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3966 [2021-12-15 17:20:29,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4061 states to 4061 states and 5938 transitions. [2021-12-15 17:20:29,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4061 [2021-12-15 17:20:29,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4061 [2021-12-15 17:20:29,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4061 states and 5938 transitions. [2021-12-15 17:20:29,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:29,987 INFO L681 BuchiCegarLoop]: Abstraction has 4061 states and 5938 transitions. [2021-12-15 17:20:29,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4061 states and 5938 transitions. [2021-12-15 17:20:30,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4061 to 3249. [2021-12-15 17:20:30,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3249 states, 3249 states have (on average 1.469067405355494) internal successors, (4773), 3248 states have internal predecessors, (4773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3249 states to 3249 states and 4773 transitions. [2021-12-15 17:20:30,113 INFO L704 BuchiCegarLoop]: Abstraction has 3249 states and 4773 transitions. [2021-12-15 17:20:30,113 INFO L587 BuchiCegarLoop]: Abstraction has 3249 states and 4773 transitions. [2021-12-15 17:20:30,113 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:30,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3249 states and 4773 transitions. [2021-12-15 17:20:30,120 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3168 [2021-12-15 17:20:30,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,121 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,121 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,121 INFO L791 eck$LassoCheckResult]: Stem: 18672#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 18644#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 18479#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18052#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18053#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 18490#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18328#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18329#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18306#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18307#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18568#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18416#L611 assume !(0 == ~M_E~0); 18417#L611-2 assume !(0 == ~T1_E~0); 18587#L616-1 assume !(0 == ~T2_E~0); 18588#L621-1 assume !(0 == ~T3_E~0); 18177#L626-1 assume !(0 == ~T4_E~0); 18178#L631-1 assume !(0 == ~T5_E~0); 18371#L636-1 assume !(0 == ~E_M~0); 18220#L641-1 assume !(0 == ~E_1~0); 18221#L646-1 assume !(0 == ~E_2~0); 18386#L651-1 assume !(0 == ~E_3~0); 18632#L656-1 assume !(0 == ~E_4~0); 18566#L661-1 assume !(0 == ~E_5~0); 18567#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18605#L304 assume !(1 == ~m_pc~0); 18239#L304-2 is_master_triggered_~__retres1~0#1 := 0; 18149#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18150#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18100#L755 assume !(0 != activate_threads_~tmp~1#1); 18101#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18054#L323 assume !(1 == ~t1_pc~0); 18055#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18118#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18119#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18537#L763 assume !(0 != activate_threads_~tmp___0~0#1); 18652#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18125#L342 assume !(1 == ~t2_pc~0); 18126#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18241#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18242#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18648#L771 assume !(0 != activate_threads_~tmp___1~0#1); 18562#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18457#L361 assume !(1 == ~t3_pc~0); 18458#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18480#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18289#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18290#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18135#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18136#L380 assume 1 == ~t4_pc~0; 18195#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18196#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18578#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18495#L787 assume !(0 != activate_threads_~tmp___3~0#1); 18496#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18198#L399 assume !(1 == ~t5_pc~0); 18199#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18340#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18593#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18330#L795 assume !(0 != activate_threads_~tmp___4~0#1); 18331#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18640#L679 assume !(1 == ~M_E~0); 18415#L679-2 assume !(1 == ~T1_E~0); 18256#L684-1 assume !(1 == ~T2_E~0); 18257#L689-1 assume !(1 == ~T3_E~0); 18466#L694-1 assume !(1 == ~T4_E~0); 18464#L699-1 assume !(1 == ~T5_E~0); 18465#L704-1 assume !(1 == ~E_M~0); 18443#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18374#L714-1 assume !(1 == ~E_2~0); 18375#L719-1 assume !(1 == ~E_3~0); 18557#L724-1 assume !(1 == ~E_4~0); 18159#L729-1 assume !(1 == ~E_5~0); 18160#L734-1 assume { :end_inline_reset_delta_events } true; 18519#L940-2 [2021-12-15 17:20:30,121 INFO L793 eck$LassoCheckResult]: Loop: 18519#L940-2 assume !false; 18547#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18252#L586 assume !false; 18253#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18636#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18461#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18462#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18453#L511 assume !(0 != eval_~tmp~0#1); 18454#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18615#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18517#L611-3 assume !(0 == ~M_E~0); 18161#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18162#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18157#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18102#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18103#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18104#L636-3 assume !(0 == ~E_M~0); 18105#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18174#L646-3 assume !(0 == ~E_2~0); 18186#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18187#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18433#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18653#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18335#L304-21 assume 1 == ~m_pc~0; 18336#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18191#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18491#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18399#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18400#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18434#L323-21 assume !(1 == ~t1_pc~0); 18573#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 18574#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18535#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18536#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18603#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18621#L342-21 assume !(1 == ~t2_pc~0); 18656#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 18484#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18485#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18563#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18201#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18202#L361-21 assume !(1 == ~t3_pc~0); 18641#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 18642#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18580#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18370#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18098#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18099#L380-21 assume 1 == ~t4_pc~0; 18630#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18168#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18228#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18543#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18497#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18315#L399-21 assume 1 == ~t5_pc~0; 18281#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18176#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18507#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18618#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18635#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18093#L679-3 assume !(1 == ~M_E~0); 18094#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18382#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18042#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18043#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18080#L699-3 assume !(1 == ~T5_E~0); 18081#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18522#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18512#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18344#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18078#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18079#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18502#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18115#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18116#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18129#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 18130#L959 assume !(0 == start_simulation_~tmp~3#1); 18478#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18376#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18377#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18589#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 18576#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18278#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18279#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 18518#L972 assume !(0 != start_simulation_~tmp___0~1#1); 18519#L940-2 [2021-12-15 17:20:30,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2021-12-15 17:20:30,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623791079] [2021-12-15 17:20:30,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,149 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623791079] [2021-12-15 17:20:30,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623791079] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,149 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,149 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:30,149 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070314212] [2021-12-15 17:20:30,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,149 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,149 INFO L85 PathProgramCache]: Analyzing trace with hash -491568661, now seen corresponding path program 1 times [2021-12-15 17:20:30,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968102988] [2021-12-15 17:20:30,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968102988] [2021-12-15 17:20:30,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968102988] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,165 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,165 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,166 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988175842] [2021-12-15 17:20:30,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,166 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,166 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:30,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:30,166 INFO L87 Difference]: Start difference. First operand 3249 states and 4773 transitions. cyclomatic complexity: 1526 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,292 INFO L93 Difference]: Finished difference Result 8140 states and 11990 transitions. [2021-12-15 17:20:30,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:30,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8140 states and 11990 transitions. [2021-12-15 17:20:30,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7992 [2021-12-15 17:20:30,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8140 states to 8140 states and 11990 transitions. [2021-12-15 17:20:30,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8140 [2021-12-15 17:20:30,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8140 [2021-12-15 17:20:30,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8140 states and 11990 transitions. [2021-12-15 17:20:30,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,366 INFO L681 BuchiCegarLoop]: Abstraction has 8140 states and 11990 transitions. [2021-12-15 17:20:30,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8140 states and 11990 transitions. [2021-12-15 17:20:30,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8140 to 3408. [2021-12-15 17:20:30,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3408 states, 3408 states have (on average 1.4471830985915493) internal successors, (4932), 3407 states have internal predecessors, (4932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3408 states to 3408 states and 4932 transitions. [2021-12-15 17:20:30,465 INFO L704 BuchiCegarLoop]: Abstraction has 3408 states and 4932 transitions. [2021-12-15 17:20:30,466 INFO L587 BuchiCegarLoop]: Abstraction has 3408 states and 4932 transitions. [2021-12-15 17:20:30,466 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:30,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3408 states and 4932 transitions. [2021-12-15 17:20:30,474 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3324 [2021-12-15 17:20:30,474 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,474 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,475 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,475 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,475 INFO L791 eck$LassoCheckResult]: Stem: 30210#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 30150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 29904#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29452#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29453#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 29921#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29738#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29739#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29713#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29714#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30021#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29832#L611 assume !(0 == ~M_E~0); 29833#L611-2 assume !(0 == ~T1_E~0); 30043#L616-1 assume !(0 == ~T2_E~0); 30044#L621-1 assume !(0 == ~T3_E~0); 29574#L626-1 assume !(0 == ~T4_E~0); 29575#L631-1 assume !(0 == ~T5_E~0); 29781#L636-1 assume !(0 == ~E_M~0); 29622#L641-1 assume !(0 == ~E_1~0); 29623#L646-1 assume !(0 == ~E_2~0); 29802#L651-1 assume !(0 == ~E_3~0); 30125#L656-1 assume !(0 == ~E_4~0); 30019#L661-1 assume !(0 == ~E_5~0); 30020#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30077#L304 assume !(1 == ~m_pc~0); 29641#L304-2 is_master_triggered_~__retres1~0#1 := 0; 29552#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29553#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29497#L755 assume !(0 != activate_threads_~tmp~1#1); 29498#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29454#L323 assume !(1 == ~t1_pc~0); 29455#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29520#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29521#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29973#L763 assume !(0 != activate_threads_~tmp___0~0#1); 30177#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29524#L342 assume !(1 == ~t2_pc~0); 29525#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29648#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29649#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30164#L771 assume !(0 != activate_threads_~tmp___1~0#1); 30010#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29874#L361 assume !(1 == ~t3_pc~0); 29875#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29907#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30143#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30117#L779 assume !(0 != activate_threads_~tmp___2~0#1); 29536#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29537#L380 assume 1 == ~t4_pc~0; 29598#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29599#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30033#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29927#L787 assume !(0 != activate_threads_~tmp___3~0#1); 29928#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29601#L399 assume !(1 == ~t5_pc~0); 29602#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29752#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30050#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29740#L795 assume !(0 != activate_threads_~tmp___4~0#1); 29741#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30137#L679 assume !(1 == ~M_E~0); 29830#L679-2 assume !(1 == ~T1_E~0); 29662#L684-1 assume !(1 == ~T2_E~0); 29663#L689-1 assume !(1 == ~T3_E~0); 29887#L694-1 assume !(1 == ~T4_E~0); 29885#L699-1 assume !(1 == ~T5_E~0); 29886#L704-1 assume !(1 == ~E_M~0); 29858#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 29786#L714-1 assume !(1 == ~E_2~0); 29787#L719-1 assume !(1 == ~E_3~0); 30000#L724-1 assume !(1 == ~E_4~0); 29562#L729-1 assume !(1 == ~E_5~0); 29563#L734-1 assume { :end_inline_reset_delta_events } true; 30148#L940-2 [2021-12-15 17:20:30,475 INFO L793 eck$LassoCheckResult]: Loop: 30148#L940-2 assume !false; 30838#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30827#L586 assume !false; 30807#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30803#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30800#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30799#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30738#L511 assume !(0 != eval_~tmp~0#1); 30739#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31554#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31552#L611-3 assume !(0 == ~M_E~0); 31550#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31548#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31538#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31528#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31512#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31504#L636-3 assume !(0 == ~E_M~0); 31499#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31495#L646-3 assume !(0 == ~E_2~0); 31486#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31482#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31478#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31459#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31458#L304-21 assume 1 == ~m_pc~0; 31456#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31455#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31454#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31453#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31452#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31451#L323-21 assume !(1 == ~t1_pc~0); 31450#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 31449#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31448#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31447#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31446#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31445#L342-21 assume !(1 == ~t2_pc~0); 30430#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 31444#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31443#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31442#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31441#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31440#L361-21 assume 1 == ~t3_pc~0; 31438#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31436#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31434#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31432#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31429#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31426#L380-21 assume 1 == ~t4_pc~0; 31421#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31415#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31411#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31395#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31391#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31387#L399-21 assume !(1 == ~t5_pc~0); 31381#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 31376#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31372#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31368#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31365#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31362#L679-3 assume !(1 == ~M_E~0); 31357#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31328#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31325#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31322#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31316#L699-3 assume !(1 == ~T5_E~0); 31307#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31303#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31272#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31268#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31264#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31260#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31230#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31165#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31157#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31154#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 30905#L959 assume !(0 == start_simulation_~tmp~3#1); 30900#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30895#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30890#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30889#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 30888#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30884#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30882#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 30880#L972 assume !(0 != start_simulation_~tmp___0~1#1); 30148#L940-2 [2021-12-15 17:20:30,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,476 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2021-12-15 17:20:30,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,476 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186245651] [2021-12-15 17:20:30,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,476 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,495 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186245651] [2021-12-15 17:20:30,495 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186245651] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,495 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,495 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:30,495 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856993581] [2021-12-15 17:20:30,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,495 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,495 INFO L85 PathProgramCache]: Analyzing trace with hash 133397355, now seen corresponding path program 1 times [2021-12-15 17:20:30,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972525643] [2021-12-15 17:20:30,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,513 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,513 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972525643] [2021-12-15 17:20:30,513 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972525643] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,513 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,514 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,514 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743737551] [2021-12-15 17:20:30,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,514 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,514 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:30,514 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:30,514 INFO L87 Difference]: Start difference. First operand 3408 states and 4932 transitions. cyclomatic complexity: 1526 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,565 INFO L93 Difference]: Finished difference Result 6315 states and 9101 transitions. [2021-12-15 17:20:30,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:30,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6315 states and 9101 transitions. [2021-12-15 17:20:30,588 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6212 [2021-12-15 17:20:30,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6315 states to 6315 states and 9101 transitions. [2021-12-15 17:20:30,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6315 [2021-12-15 17:20:30,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6315 [2021-12-15 17:20:30,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6315 states and 9101 transitions. [2021-12-15 17:20:30,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,625 INFO L681 BuchiCegarLoop]: Abstraction has 6315 states and 9101 transitions. [2021-12-15 17:20:30,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6315 states and 9101 transitions. [2021-12-15 17:20:30,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6315 to 6299. [2021-12-15 17:20:30,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6299 states, 6299 states have (on average 1.4422924273694238) internal successors, (9085), 6298 states have internal predecessors, (9085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6299 states to 6299 states and 9085 transitions. [2021-12-15 17:20:30,716 INFO L704 BuchiCegarLoop]: Abstraction has 6299 states and 9085 transitions. [2021-12-15 17:20:30,716 INFO L587 BuchiCegarLoop]: Abstraction has 6299 states and 9085 transitions. [2021-12-15 17:20:30,716 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:30,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6299 states and 9085 transitions. [2021-12-15 17:20:30,733 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6196 [2021-12-15 17:20:30,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:30,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:30,735 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,735 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:30,738 INFO L791 eck$LassoCheckResult]: Stem: 39786#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 39762#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 39601#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39182#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39183#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 39615#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39453#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39454#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39433#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39434#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39690#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39538#L611 assume !(0 == ~M_E~0); 39539#L611-2 assume !(0 == ~T1_E~0); 39704#L616-1 assume !(0 == ~T2_E~0); 39705#L621-1 assume !(0 == ~T3_E~0); 39303#L626-1 assume !(0 == ~T4_E~0); 39304#L631-1 assume !(0 == ~T5_E~0); 39492#L636-1 assume !(0 == ~E_M~0); 39348#L641-1 assume !(0 == ~E_1~0); 39349#L646-1 assume !(0 == ~E_2~0); 39512#L651-1 assume !(0 == ~E_3~0); 39749#L656-1 assume !(0 == ~E_4~0); 39688#L661-1 assume !(0 == ~E_5~0); 39689#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39721#L304 assume !(1 == ~m_pc~0); 39366#L304-2 is_master_triggered_~__retres1~0#1 := 0; 39281#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39282#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39227#L755 assume !(0 != activate_threads_~tmp~1#1); 39228#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39184#L323 assume !(1 == ~t1_pc~0); 39185#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39249#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39250#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39660#L763 assume !(0 != activate_threads_~tmp___0~0#1); 39774#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39253#L342 assume !(1 == ~t2_pc~0); 39254#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39373#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39374#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39766#L771 assume !(0 != activate_threads_~tmp___1~0#1); 39684#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39579#L361 assume !(1 == ~t3_pc~0); 39580#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39603#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39417#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39418#L779 assume !(0 != activate_threads_~tmp___2~0#1); 39265#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39266#L380 assume !(1 == ~t4_pc~0); 39576#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39695#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39696#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39620#L787 assume !(0 != activate_threads_~tmp___3~0#1); 39621#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39326#L399 assume !(1 == ~t5_pc~0); 39327#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39465#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39707#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39455#L795 assume !(0 != activate_threads_~tmp___4~0#1); 39456#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39755#L679 assume !(1 == ~M_E~0); 39536#L679-2 assume !(1 == ~T1_E~0); 39386#L684-1 assume !(1 == ~T2_E~0); 39387#L689-1 assume !(1 == ~T3_E~0); 39589#L694-1 assume !(1 == ~T4_E~0); 39587#L699-1 assume !(1 == ~T5_E~0); 39588#L704-1 assume !(1 == ~E_M~0); 39563#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 39496#L714-1 assume !(1 == ~E_2~0); 39497#L719-1 assume !(1 == ~E_3~0); 39679#L724-1 assume !(1 == ~E_4~0); 39291#L729-1 assume !(1 == ~E_5~0); 39292#L734-1 assume { :end_inline_reset_delta_events } true; 39760#L940-2 [2021-12-15 17:20:30,738 INFO L793 eck$LassoCheckResult]: Loop: 39760#L940-2 assume !false; 42105#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42100#L586 assume !false; 42096#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 41999#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 41992#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 41986#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41979#L511 assume !(0 != eval_~tmp~0#1); 41980#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42638#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42637#L611-3 assume !(0 == ~M_E~0); 42636#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42635#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42634#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42633#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42632#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42631#L636-3 assume !(0 == ~E_M~0); 42630#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42629#L646-3 assume !(0 == ~E_2~0); 42628#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42627#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42626#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42625#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42624#L304-21 assume 1 == ~m_pc~0; 42622#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 42621#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42620#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42619#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42618#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42617#L323-21 assume !(1 == ~t1_pc~0); 42616#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 42615#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42614#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42613#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42612#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42611#L342-21 assume !(1 == ~t2_pc~0); 42102#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 42610#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42608#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42605#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42603#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42601#L361-21 assume 1 == ~t3_pc~0; 42598#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42595#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42592#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42589#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42587#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42585#L380-21 assume !(1 == ~t4_pc~0); 42583#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 42581#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42579#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42576#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42572#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42566#L399-21 assume !(1 == ~t5_pc~0); 42561#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 42323#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42320#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42318#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42316#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42314#L679-3 assume !(1 == ~M_E~0); 41692#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42309#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42307#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42305#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42303#L699-3 assume !(1 == ~T5_E~0); 42300#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 42298#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42296#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42294#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42292#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42290#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42288#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42281#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42275#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42273#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 42271#L959 assume !(0 == start_simulation_~tmp~3#1); 42269#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 42147#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 42138#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42133#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 42128#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42123#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42117#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 42113#L972 assume !(0 != start_simulation_~tmp___0~1#1); 39760#L940-2 [2021-12-15 17:20:30,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,739 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2021-12-15 17:20:30,739 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671334116] [2021-12-15 17:20:30,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,739 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,764 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,764 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671334116] [2021-12-15 17:20:30,764 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671334116] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,765 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:30,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531243982] [2021-12-15 17:20:30,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,767 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:30,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:30,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1258657324, now seen corresponding path program 1 times [2021-12-15 17:20:30,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:30,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542822936] [2021-12-15 17:20:30,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:30,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:30,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:30,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:30,786 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:30,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542822936] [2021-12-15 17:20:30,786 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542822936] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:30,786 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:30,787 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:30,787 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964382724] [2021-12-15 17:20:30,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:30,787 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:30,787 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:30,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:30,787 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:30,788 INFO L87 Difference]: Start difference. First operand 6299 states and 9085 transitions. cyclomatic complexity: 2790 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:30,827 INFO L93 Difference]: Finished difference Result 6299 states and 8991 transitions. [2021-12-15 17:20:30,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:30,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6299 states and 8991 transitions. [2021-12-15 17:20:30,847 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6196 [2021-12-15 17:20:30,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6299 states to 6299 states and 8991 transitions. [2021-12-15 17:20:30,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6299 [2021-12-15 17:20:30,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6299 [2021-12-15 17:20:30,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6299 states and 8991 transitions. [2021-12-15 17:20:30,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:30,871 INFO L681 BuchiCegarLoop]: Abstraction has 6299 states and 8991 transitions. [2021-12-15 17:20:30,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6299 states and 8991 transitions. [2021-12-15 17:20:30,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6299 to 6299. [2021-12-15 17:20:30,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6299 states, 6299 states have (on average 1.4273694237180505) internal successors, (8991), 6298 states have internal predecessors, (8991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:30,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6299 states to 6299 states and 8991 transitions. [2021-12-15 17:20:30,996 INFO L704 BuchiCegarLoop]: Abstraction has 6299 states and 8991 transitions. [2021-12-15 17:20:30,996 INFO L587 BuchiCegarLoop]: Abstraction has 6299 states and 8991 transitions. [2021-12-15 17:20:30,996 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:30,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6299 states and 8991 transitions. [2021-12-15 17:20:31,010 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6196 [2021-12-15 17:20:31,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,011 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,011 INFO L791 eck$LassoCheckResult]: Stem: 52405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 52379#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 52202#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51789#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51790#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 52213#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52056#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52057#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52035#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52036#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52295#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52145#L611 assume !(0 == ~M_E~0); 52146#L611-2 assume !(0 == ~T1_E~0); 52314#L616-1 assume !(0 == ~T2_E~0); 52315#L621-1 assume !(0 == ~T3_E~0); 51913#L626-1 assume !(0 == ~T4_E~0); 51914#L631-1 assume !(0 == ~T5_E~0); 52100#L636-1 assume !(0 == ~E_M~0); 51952#L641-1 assume !(0 == ~E_1~0); 51953#L646-1 assume !(0 == ~E_2~0); 52117#L651-1 assume !(0 == ~E_3~0); 52363#L656-1 assume !(0 == ~E_4~0); 52293#L661-1 assume !(0 == ~E_5~0); 52294#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52332#L304 assume !(1 == ~m_pc~0); 51972#L304-2 is_master_triggered_~__retres1~0#1 := 0; 51885#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51886#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51836#L755 assume !(0 != activate_threads_~tmp~1#1); 51837#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51791#L323 assume !(1 == ~t1_pc~0); 51792#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51853#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51854#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52260#L763 assume !(0 != activate_threads_~tmp___0~0#1); 52394#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51861#L342 assume !(1 == ~t2_pc~0); 51862#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51974#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51975#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 52385#L771 assume !(0 != activate_threads_~tmp___1~0#1); 52289#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52181#L361 assume !(1 == ~t3_pc~0); 52182#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52203#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52019#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52020#L779 assume !(0 != activate_threads_~tmp___2~0#1); 51871#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51872#L380 assume !(1 == ~t4_pc~0); 52178#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 52303#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52304#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52219#L787 assume !(0 != activate_threads_~tmp___3~0#1); 52220#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51930#L399 assume !(1 == ~t5_pc~0); 51931#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52068#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52320#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52058#L795 assume !(0 != activate_threads_~tmp___4~0#1); 52059#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52370#L679 assume !(1 == ~M_E~0); 52144#L679-2 assume !(1 == ~T1_E~0); 51987#L684-1 assume !(1 == ~T2_E~0); 51988#L689-1 assume !(1 == ~T3_E~0); 52190#L694-1 assume !(1 == ~T4_E~0); 52188#L699-1 assume !(1 == ~T5_E~0); 52189#L704-1 assume !(1 == ~E_M~0); 52166#L709-1 assume !(1 == ~E_1~0); 52106#L714-1 assume !(1 == ~E_2~0); 52107#L719-1 assume !(1 == ~E_3~0); 52280#L724-1 assume !(1 == ~E_4~0); 51895#L729-1 assume !(1 == ~E_5~0); 51896#L734-1 assume { :end_inline_reset_delta_events } true; 52377#L940-2 [2021-12-15 17:20:31,012 INFO L793 eck$LassoCheckResult]: Loop: 52377#L940-2 assume !false; 54794#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54787#L586 assume !false; 54781#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54773#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54766#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54762#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54756#L511 assume !(0 != eval_~tmp~0#1); 54757#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55758#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55756#L611-3 assume !(0 == ~M_E~0); 55754#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55752#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55750#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55749#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55745#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55743#L636-3 assume !(0 == ~E_M~0); 55741#L641-3 assume !(0 == ~E_1~0); 55739#L646-3 assume !(0 == ~E_2~0); 55736#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55734#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55732#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55729#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55727#L304-21 assume 1 == ~m_pc~0; 55724#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 55722#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55720#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55718#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55717#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55716#L323-21 assume !(1 == ~t1_pc~0); 55715#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 55713#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55712#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55711#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55709#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55436#L342-21 assume !(1 == ~t2_pc~0); 54290#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 55418#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55406#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54362#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54355#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54350#L361-21 assume !(1 == ~t3_pc~0); 54347#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 54345#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54343#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54341#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 54338#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54336#L380-21 assume !(1 == ~t4_pc~0); 54334#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 54332#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54330#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54328#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54326#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54324#L399-21 assume !(1 == ~t5_pc~0); 54321#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 54319#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54317#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54315#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54313#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54310#L679-3 assume !(1 == ~M_E~0); 54017#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54307#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54305#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54303#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54301#L699-3 assume !(1 == ~T5_E~0); 54299#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54297#L709-3 assume !(1 == ~E_1~0); 54295#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54293#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54291#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54288#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54287#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54281#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54275#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54273#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 54271#L959 assume !(0 == start_simulation_~tmp~3#1); 54272#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54854#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54843#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54838#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 54832#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54823#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54815#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 54809#L972 assume !(0 != start_simulation_~tmp___0~1#1); 52377#L940-2 [2021-12-15 17:20:31,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,012 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2021-12-15 17:20:31,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534488117] [2021-12-15 17:20:31,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,013 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:31,021 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:31,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:31,053 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:31,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1898477969, now seen corresponding path program 1 times [2021-12-15 17:20:31,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,055 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124739881] [2021-12-15 17:20:31,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,055 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,073 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,073 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124739881] [2021-12-15 17:20:31,073 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124739881] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,073 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,073 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:31,074 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292708118] [2021-12-15 17:20:31,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,074 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,074 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,074 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:31,074 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:31,075 INFO L87 Difference]: Start difference. First operand 6299 states and 8991 transitions. cyclomatic complexity: 2696 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,107 INFO L93 Difference]: Finished difference Result 7258 states and 10338 transitions. [2021-12-15 17:20:31,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:31,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7258 states and 10338 transitions. [2021-12-15 17:20:31,132 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7100 [2021-12-15 17:20:31,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7258 states to 7258 states and 10338 transitions. [2021-12-15 17:20:31,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7258 [2021-12-15 17:20:31,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7258 [2021-12-15 17:20:31,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7258 states and 10338 transitions. [2021-12-15 17:20:31,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:31,156 INFO L681 BuchiCegarLoop]: Abstraction has 7258 states and 10338 transitions. [2021-12-15 17:20:31,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7258 states and 10338 transitions. [2021-12-15 17:20:31,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7258 to 7258. [2021-12-15 17:20:31,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7258 states, 7258 states have (on average 1.4243593276384678) internal successors, (10338), 7257 states have internal predecessors, (10338), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7258 states to 7258 states and 10338 transitions. [2021-12-15 17:20:31,228 INFO L704 BuchiCegarLoop]: Abstraction has 7258 states and 10338 transitions. [2021-12-15 17:20:31,228 INFO L587 BuchiCegarLoop]: Abstraction has 7258 states and 10338 transitions. [2021-12-15 17:20:31,228 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:31,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7258 states and 10338 transitions. [2021-12-15 17:20:31,244 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7100 [2021-12-15 17:20:31,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,246 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,246 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,246 INFO L791 eck$LassoCheckResult]: Stem: 65982#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 65943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 65773#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65350#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65351#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 65784#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65620#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65621#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65599#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65600#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65864#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65711#L611 assume !(0 == ~M_E~0); 65712#L611-2 assume !(0 == ~T1_E~0); 65881#L616-1 assume !(0 == ~T2_E~0); 65882#L621-1 assume !(0 == ~T3_E~0); 65470#L626-1 assume !(0 == ~T4_E~0); 65471#L631-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65854#L636-1 assume !(0 == ~E_M~0); 65514#L641-1 assume !(0 == ~E_1~0); 65515#L646-1 assume !(0 == ~E_2~0); 65955#L651-1 assume !(0 == ~E_3~0); 65956#L656-1 assume !(0 == ~E_4~0); 65862#L661-1 assume !(0 == ~E_5~0); 65863#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65972#L304 assume !(1 == ~m_pc~0); 65973#L304-2 is_master_triggered_~__retres1~0#1 := 0; 65448#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65449#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65394#L755 assume !(0 != activate_threads_~tmp~1#1); 65395#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65352#L323 assume !(1 == ~t1_pc~0); 65353#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65416#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65417#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65957#L763 assume !(0 != activate_threads_~tmp___0~0#1); 65958#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65420#L342 assume !(1 == ~t2_pc~0); 65421#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65539#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65540#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 65948#L771 assume !(0 != activate_threads_~tmp___1~0#1); 65855#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65751#L361 assume !(1 == ~t3_pc~0); 65752#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 65775#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65583#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 65584#L779 assume !(0 != activate_threads_~tmp___2~0#1); 65924#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66005#L380 assume !(1 == ~t4_pc~0); 65978#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65871#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65872#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65788#L787 assume !(0 != activate_threads_~tmp___3~0#1); 65789#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65970#L399 assume !(1 == ~t5_pc~0); 65632#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 65633#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65885#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65622#L795 assume !(0 != activate_threads_~tmp___4~0#1); 65623#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65936#L679 assume !(1 == ~M_E~0); 65996#L679-2 assume !(1 == ~T1_E~0); 65995#L684-1 assume !(1 == ~T2_E~0); 65760#L689-1 assume !(1 == ~T3_E~0); 65761#L694-1 assume !(1 == ~T4_E~0); 65758#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65759#L704-1 assume !(1 == ~E_M~0); 65733#L709-1 assume !(1 == ~E_1~0); 65667#L714-1 assume !(1 == ~E_2~0); 65668#L719-1 assume !(1 == ~E_3~0); 65848#L724-1 assume !(1 == ~E_4~0); 65458#L729-1 assume !(1 == ~E_5~0); 65459#L734-1 assume { :end_inline_reset_delta_events } true; 65941#L940-2 [2021-12-15 17:20:31,246 INFO L793 eck$LassoCheckResult]: Loop: 65941#L940-2 assume !false; 69627#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69618#L586 assume !false; 69611#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 67848#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 67844#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 67842#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 67838#L511 assume !(0 != eval_~tmp~0#1); 67839#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69030#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69028#L611-3 assume !(0 == ~M_E~0); 69026#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69024#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69021#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69019#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69016#L631-3 assume !(0 == ~T5_E~0); 69014#L636-3 assume !(0 == ~E_M~0); 69012#L641-3 assume !(0 == ~E_1~0); 69010#L646-3 assume !(0 == ~E_2~0); 69009#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69008#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69007#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69006#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69005#L304-21 assume !(1 == ~m_pc~0); 69003#L304-23 is_master_triggered_~__retres1~0#1 := 0; 69001#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69000#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68999#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68998#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68997#L323-21 assume !(1 == ~t1_pc~0); 68996#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 68995#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68993#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68992#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68991#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68990#L342-21 assume !(1 == ~t2_pc~0); 67918#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 68989#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68988#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68986#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68985#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68984#L361-21 assume !(1 == ~t3_pc~0); 68983#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 70181#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70171#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68975#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 68972#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68970#L380-21 assume !(1 == ~t4_pc~0); 68968#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 68965#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68963#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68961#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68959#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68957#L399-21 assume 1 == ~t5_pc~0; 68955#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68952#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68950#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68948#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 68945#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68943#L679-3 assume !(1 == ~M_E~0); 68725#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68940#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68938#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68936#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68927#L699-3 assume !(1 == ~T5_E~0); 68925#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68923#L709-3 assume !(1 == ~E_1~0); 68920#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68918#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68916#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68914#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68912#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 68907#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 68899#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 68897#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 68894#L959 assume !(0 == start_simulation_~tmp~3#1); 68895#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 69659#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 69653#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 69649#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 69647#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69645#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69644#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 69643#L972 assume !(0 != start_simulation_~tmp___0~1#1); 65941#L940-2 [2021-12-15 17:20:31,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,247 INFO L85 PathProgramCache]: Analyzing trace with hash 549210245, now seen corresponding path program 1 times [2021-12-15 17:20:31,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673155279] [2021-12-15 17:20:31,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,299 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,299 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673155279] [2021-12-15 17:20:31,300 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673155279] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,300 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,300 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:31,300 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339164572] [2021-12-15 17:20:31,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,301 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:31,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,301 INFO L85 PathProgramCache]: Analyzing trace with hash 408898993, now seen corresponding path program 1 times [2021-12-15 17:20:31,302 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260927683] [2021-12-15 17:20:31,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,302 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,326 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260927683] [2021-12-15 17:20:31,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260927683] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,326 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,327 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:31,327 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762877977] [2021-12-15 17:20:31,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,327 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,327 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:31,328 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:31,328 INFO L87 Difference]: Start difference. First operand 7258 states and 10338 transitions. cyclomatic complexity: 3084 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,384 INFO L93 Difference]: Finished difference Result 9138 states and 12990 transitions. [2021-12-15 17:20:31,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:31,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9138 states and 12990 transitions. [2021-12-15 17:20:31,415 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9016 [2021-12-15 17:20:31,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9138 states to 9138 states and 12990 transitions. [2021-12-15 17:20:31,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9138 [2021-12-15 17:20:31,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9138 [2021-12-15 17:20:31,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9138 states and 12990 transitions. [2021-12-15 17:20:31,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:31,451 INFO L681 BuchiCegarLoop]: Abstraction has 9138 states and 12990 transitions. [2021-12-15 17:20:31,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9138 states and 12990 transitions. [2021-12-15 17:20:31,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9138 to 6299. [2021-12-15 17:20:31,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6299 states, 6299 states have (on average 1.4246705826321637) internal successors, (8974), 6298 states have internal predecessors, (8974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6299 states to 6299 states and 8974 transitions. [2021-12-15 17:20:31,531 INFO L704 BuchiCegarLoop]: Abstraction has 6299 states and 8974 transitions. [2021-12-15 17:20:31,531 INFO L587 BuchiCegarLoop]: Abstraction has 6299 states and 8974 transitions. [2021-12-15 17:20:31,532 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:31,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6299 states and 8974 transitions. [2021-12-15 17:20:31,544 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6196 [2021-12-15 17:20:31,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,545 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,545 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,546 INFO L791 eck$LassoCheckResult]: Stem: 82374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 82340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 82181#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81758#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81759#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 82193#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82032#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82033#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82010#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82011#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82267#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82120#L611 assume !(0 == ~M_E~0); 82121#L611-2 assume !(0 == ~T1_E~0); 82283#L616-1 assume !(0 == ~T2_E~0); 82284#L621-1 assume !(0 == ~T3_E~0); 81880#L626-1 assume !(0 == ~T4_E~0); 81881#L631-1 assume !(0 == ~T5_E~0); 82072#L636-1 assume !(0 == ~E_M~0); 81926#L641-1 assume !(0 == ~E_1~0); 81927#L646-1 assume !(0 == ~E_2~0); 82092#L651-1 assume !(0 == ~E_3~0); 82328#L656-1 assume !(0 == ~E_4~0); 82265#L661-1 assume !(0 == ~E_5~0); 82266#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82300#L304 assume !(1 == ~m_pc~0); 81944#L304-2 is_master_triggered_~__retres1~0#1 := 0; 81857#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81858#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81802#L755 assume !(0 != activate_threads_~tmp~1#1); 81803#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81760#L323 assume !(1 == ~t1_pc~0); 81761#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81825#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81826#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82235#L763 assume !(0 != activate_threads_~tmp___0~0#1); 82357#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81829#L342 assume !(1 == ~t2_pc~0); 81830#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81949#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81950#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82350#L771 assume !(0 != activate_threads_~tmp___1~0#1); 82261#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82159#L361 assume !(1 == ~t3_pc~0); 82160#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82183#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81995#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81996#L779 assume !(0 != activate_threads_~tmp___2~0#1); 81841#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81842#L380 assume !(1 == ~t4_pc~0); 82156#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82272#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82273#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82196#L787 assume !(0 != activate_threads_~tmp___3~0#1); 82197#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81904#L399 assume !(1 == ~t5_pc~0); 81905#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 82044#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82287#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82034#L795 assume !(0 != activate_threads_~tmp___4~0#1); 82035#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82335#L679 assume !(1 == ~M_E~0); 82116#L679-2 assume !(1 == ~T1_E~0); 81962#L684-1 assume !(1 == ~T2_E~0); 81963#L689-1 assume !(1 == ~T3_E~0); 82169#L694-1 assume !(1 == ~T4_E~0); 82167#L699-1 assume !(1 == ~T5_E~0); 82168#L704-1 assume !(1 == ~E_M~0); 82144#L709-1 assume !(1 == ~E_1~0); 82077#L714-1 assume !(1 == ~E_2~0); 82078#L719-1 assume !(1 == ~E_3~0); 82257#L724-1 assume !(1 == ~E_4~0); 81868#L729-1 assume !(1 == ~E_5~0); 81869#L734-1 assume { :end_inline_reset_delta_events } true; 82338#L940-2 [2021-12-15 17:20:31,546 INFO L793 eck$LassoCheckResult]: Loop: 82338#L940-2 assume !false; 85271#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85267#L586 assume !false; 85265#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 85256#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 85251#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 84696#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 84692#L511 assume !(0 != eval_~tmp~0#1); 84693#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87972#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87971#L611-3 assume !(0 == ~M_E~0); 87970#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87969#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87968#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87966#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87964#L631-3 assume !(0 == ~T5_E~0); 87963#L636-3 assume !(0 == ~E_M~0); 87962#L641-3 assume !(0 == ~E_1~0); 87961#L646-3 assume !(0 == ~E_2~0); 87960#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87959#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87958#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87957#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87956#L304-21 assume !(1 == ~m_pc~0); 87955#L304-23 is_master_triggered_~__retres1~0#1 := 0; 87953#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87952#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87951#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87949#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87947#L323-21 assume !(1 == ~t1_pc~0); 87945#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 82301#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82236#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82237#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82297#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82317#L342-21 assume !(1 == ~t2_pc~0); 82359#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 82189#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82190#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82262#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81907#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81908#L361-21 assume 1 == ~t3_pc~0; 86097#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86093#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86088#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86083#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86079#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86075#L380-21 assume !(1 == ~t4_pc~0); 86071#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 86066#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86061#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86056#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86040#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86038#L399-21 assume 1 == ~t5_pc~0; 86031#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 86020#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86015#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 86010#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 86004#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85998#L679-3 assume !(1 == ~M_E~0); 84151#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85991#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85988#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85984#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85978#L699-3 assume !(1 == ~T5_E~0); 85975#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85971#L709-3 assume !(1 == ~E_1~0); 85967#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 85964#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85960#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85917#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85914#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 84648#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 84598#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 84569#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 83855#L959 assume !(0 == start_simulation_~tmp~3#1); 83856#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 86028#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 86019#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 86014#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 86009#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86003#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 85997#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 85994#L972 assume !(0 != start_simulation_~tmp___0~1#1); 82338#L940-2 [2021-12-15 17:20:31,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,546 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2021-12-15 17:20:31,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738686353] [2021-12-15 17:20:31,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,547 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:31,554 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:31,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:31,574 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:31,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,575 INFO L85 PathProgramCache]: Analyzing trace with hash 355735854, now seen corresponding path program 1 times [2021-12-15 17:20:31,575 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363381715] [2021-12-15 17:20:31,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,575 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,596 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,596 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363381715] [2021-12-15 17:20:31,596 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363381715] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,596 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,596 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:31,596 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154942752] [2021-12-15 17:20:31,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,596 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,597 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:31,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:31,597 INFO L87 Difference]: Start difference. First operand 6299 states and 8974 transitions. cyclomatic complexity: 2679 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,710 INFO L93 Difference]: Finished difference Result 11279 states and 15854 transitions. [2021-12-15 17:20:31,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:31,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11279 states and 15854 transitions. [2021-12-15 17:20:31,755 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11152 [2021-12-15 17:20:31,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11279 states to 11279 states and 15854 transitions. [2021-12-15 17:20:31,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11279 [2021-12-15 17:20:31,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11279 [2021-12-15 17:20:31,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11279 states and 15854 transitions. [2021-12-15 17:20:31,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:31,799 INFO L681 BuchiCegarLoop]: Abstraction has 11279 states and 15854 transitions. [2021-12-15 17:20:31,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11279 states and 15854 transitions. [2021-12-15 17:20:31,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11279 to 6347. [2021-12-15 17:20:31,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6347 states, 6347 states have (on average 1.421458956987553) internal successors, (9022), 6346 states have internal predecessors, (9022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6347 states to 6347 states and 9022 transitions. [2021-12-15 17:20:31,876 INFO L704 BuchiCegarLoop]: Abstraction has 6347 states and 9022 transitions. [2021-12-15 17:20:31,876 INFO L587 BuchiCegarLoop]: Abstraction has 6347 states and 9022 transitions. [2021-12-15 17:20:31,876 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:31,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6347 states and 9022 transitions. [2021-12-15 17:20:31,887 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6244 [2021-12-15 17:20:31,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,889 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,889 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,889 INFO L791 eck$LassoCheckResult]: Stem: 100001#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 99970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 99775#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 99352#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 99353#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 99788#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99625#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99626#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99602#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 99603#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 99881#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99717#L611 assume !(0 == ~M_E~0); 99718#L611-2 assume !(0 == ~T1_E~0); 99897#L616-1 assume !(0 == ~T2_E~0); 99898#L621-1 assume !(0 == ~T3_E~0); 99474#L626-1 assume !(0 == ~T4_E~0); 99475#L631-1 assume !(0 == ~T5_E~0); 99670#L636-1 assume !(0 == ~E_M~0); 99517#L641-1 assume !(0 == ~E_1~0); 99518#L646-1 assume !(0 == ~E_2~0); 99690#L651-1 assume !(0 == ~E_3~0); 99959#L656-1 assume !(0 == ~E_4~0); 99879#L661-1 assume !(0 == ~E_5~0); 99880#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99920#L304 assume !(1 == ~m_pc~0); 99538#L304-2 is_master_triggered_~__retres1~0#1 := 0; 99449#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99450#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 99398#L755 assume !(0 != activate_threads_~tmp~1#1); 99399#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99354#L323 assume !(1 == ~t1_pc~0); 99355#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 99418#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99419#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 99840#L763 assume !(0 != activate_threads_~tmp___0~0#1); 99985#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99425#L342 assume !(1 == ~t2_pc~0); 99426#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 99541#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99542#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 99979#L771 assume !(0 != activate_threads_~tmp___1~0#1); 99874#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99755#L361 assume !(1 == ~t3_pc~0); 99756#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 99778#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99587#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 99588#L779 assume !(0 != activate_threads_~tmp___2~0#1); 99434#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99435#L380 assume !(1 == ~t4_pc~0); 99752#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 99888#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99889#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 99793#L787 assume !(0 != activate_threads_~tmp___3~0#1); 99794#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99495#L399 assume !(1 == ~t5_pc~0); 99496#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 99637#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99901#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99627#L795 assume !(0 != activate_threads_~tmp___4~0#1); 99628#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99966#L679 assume !(1 == ~M_E~0); 99715#L679-2 assume !(1 == ~T1_E~0); 99554#L684-1 assume !(1 == ~T2_E~0); 99555#L689-1 assume !(1 == ~T3_E~0); 99764#L694-1 assume !(1 == ~T4_E~0); 99762#L699-1 assume !(1 == ~T5_E~0); 99763#L704-1 assume !(1 == ~E_M~0); 99739#L709-1 assume !(1 == ~E_1~0); 99674#L714-1 assume !(1 == ~E_2~0); 99675#L719-1 assume !(1 == ~E_3~0); 99869#L724-1 assume !(1 == ~E_4~0); 99460#L729-1 assume !(1 == ~E_5~0); 99461#L734-1 assume { :end_inline_reset_delta_events } true; 99828#L940-2 [2021-12-15 17:20:31,889 INFO L793 eck$LassoCheckResult]: Loop: 99828#L940-2 assume !false; 99854#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99645#L586 assume !false; 100278#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 100274#L464 assume !(0 == ~m_st~0); 100270#L468 assume !(0 == ~t1_st~0); 100266#L472 assume !(0 == ~t2_st~0); 100262#L476 assume !(0 == ~t3_st~0); 100258#L480 assume !(0 == ~t4_st~0); 100252#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 100244#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 100245#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 100218#L511 assume !(0 != eval_~tmp~0#1); 100214#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100215#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100207#L611-3 assume !(0 == ~M_E~0); 100201#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100202#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 100195#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100196#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100187#L631-3 assume !(0 == ~T5_E~0); 100188#L636-3 assume !(0 == ~E_M~0); 100179#L641-3 assume !(0 == ~E_1~0); 100180#L646-3 assume !(0 == ~E_2~0); 100171#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100172#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100163#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100164#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100149#L304-21 assume !(1 == ~m_pc~0); 100151#L304-23 is_master_triggered_~__retres1~0#1 := 0; 100135#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100136#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 100123#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100124#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99983#L323-21 assume !(1 == ~t1_pc~0); 99885#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 99886#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99841#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 99842#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99940#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99941#L342-21 assume !(1 == ~t2_pc~0); 99987#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 99988#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99908#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 99909#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99498#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99499#L361-21 assume 1 == ~t3_pc~0; 99992#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 99993#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105312#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105313#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99396#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99397#L380-21 assume !(1 == ~t4_pc~0); 99466#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 99467#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99848#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 99849#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99795#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99796#L399-21 assume !(1 == ~t5_pc~0); 99472#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 99473#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99937#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99938#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 99962#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99963#L679-3 assume !(1 == ~M_E~0); 99684#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 99685#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99344#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99345#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99381#L699-3 assume !(1 == ~T5_E~0); 99382#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 99913#L709-3 assume !(1 == ~E_1~0); 99914#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 99639#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 99640#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99802#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 99803#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 99413#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 99414#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 99427#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 99428#L959 assume !(0 == start_simulation_~tmp~3#1); 99774#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 99678#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 99679#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 99899#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 99887#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99576#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99577#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 99827#L972 assume !(0 != start_simulation_~tmp___0~1#1); 99828#L940-2 [2021-12-15 17:20:31,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,890 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2021-12-15 17:20:31,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730449944] [2021-12-15 17:20:31,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:31,896 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:31,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:31,908 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:31,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,909 INFO L85 PathProgramCache]: Analyzing trace with hash -1524843334, now seen corresponding path program 1 times [2021-12-15 17:20:31,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876185670] [2021-12-15 17:20:31,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,909 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876185670] [2021-12-15 17:20:31,949 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876185670] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,949 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,949 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:31,949 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537568044] [2021-12-15 17:20:31,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,950 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,950 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:31,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:31,950 INFO L87 Difference]: Start difference. First operand 6347 states and 9022 transitions. cyclomatic complexity: 2679 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,148 INFO L93 Difference]: Finished difference Result 18120 states and 25545 transitions. [2021-12-15 17:20:32,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:32,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18120 states and 25545 transitions. [2021-12-15 17:20:32,225 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 17868 [2021-12-15 17:20:32,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18120 states to 18120 states and 25545 transitions. [2021-12-15 17:20:32,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18120 [2021-12-15 17:20:32,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18120 [2021-12-15 17:20:32,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18120 states and 25545 transitions. [2021-12-15 17:20:32,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,310 INFO L681 BuchiCegarLoop]: Abstraction has 18120 states and 25545 transitions. [2021-12-15 17:20:32,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18120 states and 25545 transitions. [2021-12-15 17:20:32,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18120 to 6638. [2021-12-15 17:20:32,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6638 states, 6638 states have (on average 1.4029828261524555) internal successors, (9313), 6637 states have internal predecessors, (9313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6638 states to 6638 states and 9313 transitions. [2021-12-15 17:20:32,428 INFO L704 BuchiCegarLoop]: Abstraction has 6638 states and 9313 transitions. [2021-12-15 17:20:32,428 INFO L587 BuchiCegarLoop]: Abstraction has 6638 states and 9313 transitions. [2021-12-15 17:20:32,428 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:32,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6638 states and 9313 transitions. [2021-12-15 17:20:32,442 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6532 [2021-12-15 17:20:32,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,444 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,444 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,444 INFO L791 eck$LassoCheckResult]: Stem: 124498#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 124458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 124260#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123832#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123833#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 124272#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124108#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124109#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124084#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124085#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124365#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124195#L611 assume !(0 == ~M_E~0); 124196#L611-2 assume !(0 == ~T1_E~0); 124380#L616-1 assume !(0 == ~T2_E~0); 124381#L621-1 assume !(0 == ~T3_E~0); 123952#L626-1 assume !(0 == ~T4_E~0); 123953#L631-1 assume !(0 == ~T5_E~0); 124149#L636-1 assume !(0 == ~E_M~0); 123997#L641-1 assume !(0 == ~E_1~0); 123998#L646-1 assume !(0 == ~E_2~0); 124169#L651-1 assume !(0 == ~E_3~0); 124440#L656-1 assume !(0 == ~E_4~0); 124363#L661-1 assume !(0 == ~E_5~0); 124364#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124403#L304 assume !(1 == ~m_pc~0); 124016#L304-2 is_master_triggered_~__retres1~0#1 := 0; 123930#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123931#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123876#L755 assume !(0 != activate_threads_~tmp~1#1); 123877#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123834#L323 assume !(1 == ~t1_pc~0); 123835#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123898#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123899#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 124323#L763 assume !(0 != activate_threads_~tmp___0~0#1); 124471#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123902#L342 assume !(1 == ~t2_pc~0); 123903#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124023#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124024#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 124463#L771 assume !(0 != activate_threads_~tmp___1~0#1); 124358#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124234#L361 assume !(1 == ~t3_pc~0); 124235#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 124262#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124453#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 124436#L779 assume !(0 != activate_threads_~tmp___2~0#1); 123914#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123915#L380 assume !(1 == ~t4_pc~0); 124231#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124372#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124373#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124277#L787 assume !(0 != activate_threads_~tmp___3~0#1); 124278#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123977#L399 assume !(1 == ~t5_pc~0); 123978#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 124122#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124385#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124110#L795 assume !(0 != activate_threads_~tmp___4~0#1); 124111#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124449#L679 assume !(1 == ~M_E~0); 124193#L679-2 assume !(1 == ~T1_E~0); 124037#L684-1 assume !(1 == ~T2_E~0); 124038#L689-1 assume !(1 == ~T3_E~0); 124245#L694-1 assume !(1 == ~T4_E~0); 124243#L699-1 assume !(1 == ~T5_E~0); 124244#L704-1 assume !(1 == ~E_M~0); 124218#L709-1 assume !(1 == ~E_1~0); 124153#L714-1 assume !(1 == ~E_2~0); 124154#L719-1 assume !(1 == ~E_3~0); 124349#L724-1 assume !(1 == ~E_4~0); 123940#L729-1 assume !(1 == ~E_5~0); 123941#L734-1 assume { :end_inline_reset_delta_events } true; 124455#L940-2 [2021-12-15 17:20:32,444 INFO L793 eck$LassoCheckResult]: Loop: 124455#L940-2 assume !false; 127020#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127016#L586 assume !false; 127014#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 127010#L464 assume !(0 == ~m_st~0); 127011#L468 assume !(0 == ~t1_st~0); 127012#L472 assume !(0 == ~t2_st~0); 127008#L476 assume !(0 == ~t3_st~0); 127009#L480 assume !(0 == ~t4_st~0); 127006#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 127003#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 126998#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 126997#L511 assume !(0 != eval_~tmp~0#1); 126996#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 126995#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 126994#L611-3 assume !(0 == ~M_E~0); 126993#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 126992#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 126991#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 126990#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 126989#L631-3 assume !(0 == ~T5_E~0); 126988#L636-3 assume !(0 == ~E_M~0); 126987#L641-3 assume !(0 == ~E_1~0); 126986#L646-3 assume !(0 == ~E_2~0); 126985#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 126984#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 126983#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 126982#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126981#L304-21 assume 1 == ~m_pc~0; 126979#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 126977#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126975#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 126973#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 126972#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126971#L323-21 assume !(1 == ~t1_pc~0); 126970#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 126969#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126968#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126967#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 126966#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126965#L342-21 assume !(1 == ~t2_pc~0); 126428#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 126964#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126963#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 126962#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 126961#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126960#L361-21 assume !(1 == ~t3_pc~0); 126959#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 126957#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126955#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 126953#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 126951#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126950#L380-21 assume !(1 == ~t4_pc~0); 126949#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 126948#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126947#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 126946#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126945#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126944#L399-21 assume 1 == ~t5_pc~0; 126943#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126941#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126940#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 126939#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 126938#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126936#L679-3 assume !(1 == ~M_E~0); 126788#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126933#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126931#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 126929#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126927#L699-3 assume !(1 == ~T5_E~0); 126925#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 126923#L709-3 assume !(1 == ~E_1~0); 126921#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 126919#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 126917#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 126915#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 126913#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 126910#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 126895#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 126893#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 126890#L959 assume !(0 == start_simulation_~tmp~3#1); 126891#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 127059#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 127051#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 127039#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 127035#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 127033#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 127031#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 127030#L972 assume !(0 != start_simulation_~tmp___0~1#1); 124455#L940-2 [2021-12-15 17:20:32,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,445 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2021-12-15 17:20:32,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161705895] [2021-12-15 17:20:32,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,445 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,451 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:32,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,464 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:32,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,465 INFO L85 PathProgramCache]: Analyzing trace with hash -728741381, now seen corresponding path program 1 times [2021-12-15 17:20:32,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535613432] [2021-12-15 17:20:32,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,499 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535613432] [2021-12-15 17:20:32,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535613432] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,499 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:32,499 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199478922] [2021-12-15 17:20:32,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,500 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,500 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:32,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:32,500 INFO L87 Difference]: Start difference. First operand 6638 states and 9313 transitions. cyclomatic complexity: 2679 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,613 INFO L93 Difference]: Finished difference Result 8902 states and 12472 transitions. [2021-12-15 17:20:32,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:32,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8902 states and 12472 transitions. [2021-12-15 17:20:32,642 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8780 [2021-12-15 17:20:32,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8902 states to 8902 states and 12472 transitions. [2021-12-15 17:20:32,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8902 [2021-12-15 17:20:32,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8902 [2021-12-15 17:20:32,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8902 states and 12472 transitions. [2021-12-15 17:20:32,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,672 INFO L681 BuchiCegarLoop]: Abstraction has 8902 states and 12472 transitions. [2021-12-15 17:20:32,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8902 states and 12472 transitions. [2021-12-15 17:20:32,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8902 to 6662. [2021-12-15 17:20:32,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6662 states, 6662 states have (on average 1.3881717202041428) internal successors, (9248), 6661 states have internal predecessors, (9248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6662 states to 6662 states and 9248 transitions. [2021-12-15 17:20:32,766 INFO L704 BuchiCegarLoop]: Abstraction has 6662 states and 9248 transitions. [2021-12-15 17:20:32,766 INFO L587 BuchiCegarLoop]: Abstraction has 6662 states and 9248 transitions. [2021-12-15 17:20:32,766 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:20:32,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6662 states and 9248 transitions. [2021-12-15 17:20:32,779 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6556 [2021-12-15 17:20:32,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,781 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,781 INFO L791 eck$LassoCheckResult]: Stem: 140086#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 140045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 139815#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 139390#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 139391#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 139830#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 139661#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 139662#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 139638#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 139639#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 139940#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 139752#L611 assume !(0 == ~M_E~0); 139753#L611-2 assume !(0 == ~T1_E~0); 139960#L616-1 assume !(0 == ~T2_E~0); 139961#L621-1 assume !(0 == ~T3_E~0); 139513#L626-1 assume !(0 == ~T4_E~0); 139514#L631-1 assume !(0 == ~T5_E~0); 139705#L636-1 assume !(0 == ~E_M~0); 139554#L641-1 assume !(0 == ~E_1~0); 139555#L646-1 assume !(0 == ~E_2~0); 139721#L651-1 assume !(0 == ~E_3~0); 140025#L656-1 assume !(0 == ~E_4~0); 139938#L661-1 assume !(0 == ~E_5~0); 139939#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139986#L304 assume !(1 == ~m_pc~0); 139575#L304-2 is_master_triggered_~__retres1~0#1 := 0; 139576#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 140084#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 139435#L755 assume !(0 != activate_threads_~tmp~1#1); 139436#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139392#L323 assume !(1 == ~t1_pc~0); 139393#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 139452#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139453#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 139896#L763 assume !(0 != activate_threads_~tmp___0~0#1); 140062#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139460#L342 assume !(1 == ~t2_pc~0); 139461#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 139578#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139579#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 140057#L771 assume !(0 != activate_threads_~tmp___1~0#1); 139930#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139790#L361 assume !(1 == ~t3_pc~0); 139791#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 139816#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139623#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 139624#L779 assume !(0 != activate_threads_~tmp___2~0#1); 139470#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139471#L380 assume !(1 == ~t4_pc~0); 139787#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 139950#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139951#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 139838#L787 assume !(0 != activate_threads_~tmp___3~0#1); 139839#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139530#L399 assume !(1 == ~t5_pc~0); 139531#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 139674#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 139969#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 139663#L795 assume !(0 != activate_threads_~tmp___4~0#1); 139664#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140035#L679 assume !(1 == ~M_E~0); 139751#L679-2 assume !(1 == ~T1_E~0); 139592#L684-1 assume !(1 == ~T2_E~0); 139593#L689-1 assume !(1 == ~T3_E~0); 139800#L694-1 assume !(1 == ~T4_E~0); 139798#L699-1 assume !(1 == ~T5_E~0); 139799#L704-1 assume !(1 == ~E_M~0); 139775#L709-1 assume !(1 == ~E_1~0); 139711#L714-1 assume !(1 == ~E_2~0); 139712#L719-1 assume !(1 == ~E_3~0); 139923#L724-1 assume !(1 == ~E_4~0); 139494#L729-1 assume !(1 == ~E_5~0); 139495#L734-1 assume { :end_inline_reset_delta_events } true; 140040#L940-2 [2021-12-15 17:20:32,781 INFO L793 eck$LassoCheckResult]: Loop: 140040#L940-2 assume !false; 143130#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143127#L586 assume !false; 143125#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 143077#L464 assume !(0 == ~m_st~0); 143078#L468 assume !(0 == ~t1_st~0); 143080#L472 assume !(0 == ~t2_st~0); 143075#L476 assume !(0 == ~t3_st~0); 143076#L480 assume !(0 == ~t4_st~0); 143079#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 143081#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 142096#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 142097#L511 assume !(0 != eval_~tmp~0#1); 143766#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 143765#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143764#L611-3 assume !(0 == ~M_E~0); 143763#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 143762#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 143761#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143760#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143759#L631-3 assume !(0 == ~T5_E~0); 143758#L636-3 assume !(0 == ~E_M~0); 143757#L641-3 assume !(0 == ~E_1~0); 143756#L646-3 assume !(0 == ~E_2~0); 143755#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 143754#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 143753#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 140069#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139668#L304-21 assume !(1 == ~m_pc~0); 139525#L304-23 is_master_triggered_~__retres1~0#1 := 0; 139526#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144898#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 139738#L755-21 assume !(0 != activate_threads_~tmp~1#1); 139739#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139769#L323-21 assume !(1 == ~t1_pc~0); 139945#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 139946#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139894#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 139895#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 139983#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 140006#L342-21 assume !(1 == ~t2_pc~0); 140092#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 143689#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143687#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 143684#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 143681#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143678#L361-21 assume 1 == ~t3_pc~0; 143674#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 143671#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143666#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 143661#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 143657#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143653#L380-21 assume !(1 == ~t4_pc~0); 143650#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 143646#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143642#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 143638#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 143634#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143631#L399-21 assume !(1 == ~t5_pc~0); 143627#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 143624#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143619#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 143614#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 143603#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143592#L679-3 assume !(1 == ~M_E~0); 143583#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143575#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 143569#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143564#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143558#L699-3 assume !(1 == ~T5_E~0); 143342#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 143297#L709-3 assume !(1 == ~E_1~0); 143294#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 143289#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 143284#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 143280#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143276#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 143265#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 143255#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 143249#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 143243#L959 assume !(0 == start_simulation_~tmp~3#1); 143239#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 143179#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 143169#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 143164#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 143159#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143154#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143147#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 143142#L972 assume !(0 != start_simulation_~tmp___0~1#1); 140040#L940-2 [2021-12-15 17:20:32,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,782 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2021-12-15 17:20:32,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909635452] [2021-12-15 17:20:32,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,782 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,788 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:32,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:32,799 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:32,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,799 INFO L85 PathProgramCache]: Analyzing trace with hash 2002455102, now seen corresponding path program 1 times [2021-12-15 17:20:32,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643441269] [2021-12-15 17:20:32,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,800 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,816 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643441269] [2021-12-15 17:20:32,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643441269] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,817 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,817 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035650649] [2021-12-15 17:20:32,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,817 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,817 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,818 INFO L87 Difference]: Start difference. First operand 6662 states and 9248 transitions. cyclomatic complexity: 2590 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,876 INFO L93 Difference]: Finished difference Result 12234 states and 16712 transitions. [2021-12-15 17:20:32,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12234 states and 16712 transitions. [2021-12-15 17:20:32,917 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12104 [2021-12-15 17:20:32,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12234 states to 12234 states and 16712 transitions. [2021-12-15 17:20:32,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12234 [2021-12-15 17:20:32,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12234 [2021-12-15 17:20:32,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12234 states and 16712 transitions. [2021-12-15 17:20:32,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,957 INFO L681 BuchiCegarLoop]: Abstraction has 12234 states and 16712 transitions. [2021-12-15 17:20:32,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12234 states and 16712 transitions. [2021-12-15 17:20:33,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12234 to 11594. [2021-12-15 17:20:33,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11594 states, 11594 states have (on average 1.370363981369674) internal successors, (15888), 11593 states have internal predecessors, (15888), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11594 states to 11594 states and 15888 transitions. [2021-12-15 17:20:33,059 INFO L704 BuchiCegarLoop]: Abstraction has 11594 states and 15888 transitions. [2021-12-15 17:20:33,059 INFO L587 BuchiCegarLoop]: Abstraction has 11594 states and 15888 transitions. [2021-12-15 17:20:33,059 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:20:33,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11594 states and 15888 transitions. [2021-12-15 17:20:33,082 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11464 [2021-12-15 17:20:33,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,084 INFO L791 eck$LassoCheckResult]: Stem: 158967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 158925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 158714#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 158292#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 158293#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 158728#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 158560#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158561#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158539#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158540#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 158823#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158648#L611 assume !(0 == ~M_E~0); 158649#L611-2 assume !(0 == ~T1_E~0); 158844#L616-1 assume !(0 == ~T2_E~0); 158845#L621-1 assume !(0 == ~T3_E~0); 158414#L626-1 assume !(0 == ~T4_E~0); 158415#L631-1 assume !(0 == ~T5_E~0); 158604#L636-1 assume !(0 == ~E_M~0); 158452#L641-1 assume !(0 == ~E_1~0); 158453#L646-1 assume !(0 == ~E_2~0); 158619#L651-1 assume !(0 == ~E_3~0); 158909#L656-1 assume !(0 == ~E_4~0); 158821#L661-1 assume !(0 == ~E_5~0); 158822#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158866#L304 assume !(1 == ~m_pc~0); 158473#L304-2 is_master_triggered_~__retres1~0#1 := 0; 158474#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158965#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 158337#L755 assume !(0 != activate_threads_~tmp~1#1); 158338#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158294#L323 assume !(1 == ~t1_pc~0); 158295#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 158353#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 158354#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 158784#L763 assume !(0 != activate_threads_~tmp___0~0#1); 158941#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158361#L342 assume !(1 == ~t2_pc~0); 158362#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 158476#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 158477#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158934#L771 assume !(0 != activate_threads_~tmp___1~0#1); 158813#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158689#L361 assume !(1 == ~t3_pc~0); 158690#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 158715#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 158523#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 158524#L779 assume !(0 != activate_threads_~tmp___2~0#1); 158372#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158373#L380 assume !(1 == ~t4_pc~0); 158686#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 158835#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158836#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158733#L787 assume !(0 != activate_threads_~tmp___3~0#1); 158734#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158430#L399 assume !(1 == ~t5_pc~0); 158431#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 158573#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158850#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 158562#L795 assume !(0 != activate_threads_~tmp___4~0#1); 158563#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158918#L679 assume !(1 == ~M_E~0); 158647#L679-2 assume !(1 == ~T1_E~0); 158490#L684-1 assume !(1 == ~T2_E~0); 158491#L689-1 assume !(1 == ~T3_E~0); 158700#L694-1 assume !(1 == ~T4_E~0); 158698#L699-1 assume !(1 == ~T5_E~0); 158699#L704-1 assume !(1 == ~E_M~0); 158674#L709-1 assume !(1 == ~E_1~0); 158609#L714-1 assume !(1 == ~E_2~0); 158610#L719-1 assume !(1 == ~E_3~0); 158805#L724-1 assume !(1 == ~E_4~0); 158396#L729-1 assume !(1 == ~E_5~0); 158397#L734-1 assume { :end_inline_reset_delta_events } true; 158923#L940-2 [2021-12-15 17:20:33,084 INFO L793 eck$LassoCheckResult]: Loop: 158923#L940-2 assume !false; 162919#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 162915#L586 assume !false; 162913#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 162911#L464 assume !(0 == ~m_st~0); 162674#L468 assume !(0 == ~t1_st~0); 162669#L472 assume !(0 == ~t2_st~0); 162664#L476 assume !(0 == ~t3_st~0); 162659#L480 assume !(0 == ~t4_st~0); 162652#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 162645#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 162635#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 162626#L511 assume !(0 != eval_~tmp~0#1); 162619#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 162613#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 162607#L611-3 assume !(0 == ~M_E~0); 162598#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 162591#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 162584#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 162575#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 162570#L631-3 assume !(0 == ~T5_E~0); 162564#L636-3 assume !(0 == ~E_M~0); 162557#L641-3 assume !(0 == ~E_1~0); 162552#L646-3 assume !(0 == ~E_2~0); 162547#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 162542#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 162535#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 162527#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 162519#L304-21 assume 1 == ~m_pc~0; 162511#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 162505#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 162502#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162497#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 162493#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162491#L323-21 assume !(1 == ~t1_pc~0); 162489#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 162487#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162485#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 162483#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 162481#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162479#L342-21 assume !(1 == ~t2_pc~0); 160954#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 162474#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 162471#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 162468#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 162466#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162464#L361-21 assume !(1 == ~t3_pc~0); 162462#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 162459#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 162456#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 162453#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 162450#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 162448#L380-21 assume !(1 == ~t4_pc~0); 162445#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 162443#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162441#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 162439#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 162437#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 162436#L399-21 assume 1 == ~t5_pc~0; 162434#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 162429#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 162427#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 162425#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 162424#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 162419#L679-3 assume !(1 == ~M_E~0); 161680#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 162416#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 162414#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 162413#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 162411#L699-3 assume !(1 == ~T5_E~0); 162409#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 162407#L709-3 assume !(1 == ~E_1~0); 162404#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 162402#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 162395#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 162393#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 162389#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 162384#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 162381#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 162378#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 162374#L959 assume !(0 == start_simulation_~tmp~3#1); 162375#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 163158#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 163156#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 163152#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 163150#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 163148#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 163147#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 163146#L972 assume !(0 != start_simulation_~tmp___0~1#1); 158923#L940-2 [2021-12-15 17:20:33,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2021-12-15 17:20:33,085 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956238545] [2021-12-15 17:20:33,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,085 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,091 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:33,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,102 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:33,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1537639805, now seen corresponding path program 1 times [2021-12-15 17:20:33,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532800970] [2021-12-15 17:20:33,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,135 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532800970] [2021-12-15 17:20:33,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532800970] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,135 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,136 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:33,136 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716955637] [2021-12-15 17:20:33,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,136 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,136 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:33,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:33,137 INFO L87 Difference]: Start difference. First operand 11594 states and 15888 transitions. cyclomatic complexity: 4298 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,311 INFO L93 Difference]: Finished difference Result 21626 states and 29611 transitions. [2021-12-15 17:20:33,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:33,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21626 states and 29611 transitions. [2021-12-15 17:20:33,463 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 21448 [2021-12-15 17:20:33,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21626 states to 21626 states and 29611 transitions. [2021-12-15 17:20:33,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21626 [2021-12-15 17:20:33,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21626 [2021-12-15 17:20:33,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21626 states and 29611 transitions. [2021-12-15 17:20:33,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,534 INFO L681 BuchiCegarLoop]: Abstraction has 21626 states and 29611 transitions. [2021-12-15 17:20:33,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21626 states and 29611 transitions. [2021-12-15 17:20:33,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21626 to 11882. [2021-12-15 17:20:33,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11882 states, 11882 states have (on average 1.3545699377209224) internal successors, (16095), 11881 states have internal predecessors, (16095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11882 states to 11882 states and 16095 transitions. [2021-12-15 17:20:33,659 INFO L704 BuchiCegarLoop]: Abstraction has 11882 states and 16095 transitions. [2021-12-15 17:20:33,659 INFO L587 BuchiCegarLoop]: Abstraction has 11882 states and 16095 transitions. [2021-12-15 17:20:33,659 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:20:33,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11882 states and 16095 transitions. [2021-12-15 17:20:33,685 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11752 [2021-12-15 17:20:33,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,687 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,687 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,687 INFO L791 eck$LassoCheckResult]: Stem: 192177#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 192144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 191946#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 191522#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 191523#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 191959#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 191792#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 191793#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 191771#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 191772#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 192051#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191882#L611 assume !(0 == ~M_E~0); 191883#L611-2 assume !(0 == ~T1_E~0); 192067#L616-1 assume !(0 == ~T2_E~0); 192068#L621-1 assume !(0 == ~T3_E~0); 191644#L626-1 assume !(0 == ~T4_E~0); 191645#L631-1 assume !(0 == ~T5_E~0); 191832#L636-1 assume !(0 == ~E_M~0); 191687#L641-1 assume !(0 == ~E_1~0); 191688#L646-1 assume !(0 == ~E_2~0); 191851#L651-1 assume !(0 == ~E_3~0); 192127#L656-1 assume !(0 == ~E_4~0); 192049#L661-1 assume !(0 == ~E_5~0); 192050#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192089#L304 assume !(1 == ~m_pc~0); 191705#L304-2 is_master_triggered_~__retres1~0#1 := 0; 191706#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192175#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 191566#L755 assume !(0 != activate_threads_~tmp~1#1); 191567#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191524#L323 assume !(1 == ~t1_pc~0); 191525#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 191587#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191588#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 192011#L763 assume !(0 != activate_threads_~tmp___0~0#1); 192154#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191591#L342 assume !(1 == ~t2_pc~0); 191592#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 191711#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191712#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 192149#L771 assume !(0 != activate_threads_~tmp___1~0#1); 192045#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 191922#L361 assume !(1 == ~t3_pc~0); 191923#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 191948#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191755#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 191756#L779 assume !(0 != activate_threads_~tmp___2~0#1); 191602#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 191603#L380 assume !(1 == ~t4_pc~0); 191919#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 192057#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192058#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 191963#L787 assume !(0 != activate_threads_~tmp___3~0#1); 191964#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 191666#L399 assume !(1 == ~t5_pc~0); 191667#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 191804#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192072#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 191794#L795 assume !(0 != activate_threads_~tmp___4~0#1); 191795#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192136#L679 assume !(1 == ~M_E~0); 191878#L679-2 assume !(1 == ~T1_E~0); 191724#L684-1 assume !(1 == ~T2_E~0); 191725#L689-1 assume !(1 == ~T3_E~0); 191933#L694-1 assume !(1 == ~T4_E~0); 191931#L699-1 assume !(1 == ~T5_E~0); 191932#L704-1 assume !(1 == ~E_M~0); 191907#L709-1 assume !(1 == ~E_1~0); 191836#L714-1 assume !(1 == ~E_2~0); 191837#L719-1 assume !(1 == ~E_3~0); 192039#L724-1 assume !(1 == ~E_4~0); 191632#L729-1 assume !(1 == ~E_5~0); 191633#L734-1 assume { :end_inline_reset_delta_events } true; 192142#L940-2 [2021-12-15 17:20:33,687 INFO L793 eck$LassoCheckResult]: Loop: 192142#L940-2 assume !false; 193075#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193071#L586 assume !false; 193069#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 193065#L464 assume !(0 == ~m_st~0); 193066#L468 assume !(0 == ~t1_st~0); 197287#L472 assume !(0 == ~t2_st~0); 197283#L476 assume !(0 == ~t3_st~0); 197285#L480 assume !(0 == ~t4_st~0); 197286#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 197274#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 197186#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 197187#L511 assume !(0 != eval_~tmp~0#1); 200110#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 200109#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 200108#L611-3 assume !(0 == ~M_E~0); 200107#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 200106#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 200105#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 200104#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 200103#L631-3 assume !(0 == ~T5_E~0); 200102#L636-3 assume !(0 == ~E_M~0); 200101#L641-3 assume !(0 == ~E_1~0); 200100#L646-3 assume !(0 == ~E_2~0); 200099#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 200098#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 200097#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 200096#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 200095#L304-21 assume 1 == ~m_pc~0; 200093#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 200092#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 200091#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 200089#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 200088#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 200087#L323-21 assume !(1 == ~t1_pc~0); 200086#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 200085#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200084#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 200083#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 200082#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193444#L342-21 assume !(1 == ~t2_pc~0); 193442#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 193440#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 193438#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 193436#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 193434#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193432#L361-21 assume !(1 == ~t3_pc~0); 193430#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 193426#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193422#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 193418#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 193414#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193412#L380-21 assume !(1 == ~t4_pc~0); 193410#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 193408#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193406#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 193404#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 193402#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 193400#L399-21 assume 1 == ~t5_pc~0; 193398#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 193394#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 193392#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 193390#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 193388#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 193386#L679-3 assume !(1 == ~M_E~0); 193377#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 193368#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 193349#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 193299#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 193292#L699-3 assume !(1 == ~T5_E~0); 193285#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 193281#L709-3 assume !(1 == ~E_1~0); 193276#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 193271#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 193266#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 193261#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 193138#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 193134#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 193132#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 193130#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 193127#L959 assume !(0 == start_simulation_~tmp~3#1); 193124#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 193119#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 193117#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 193115#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 193114#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 193113#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 193112#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 193108#L972 assume !(0 != start_simulation_~tmp___0~1#1); 192142#L940-2 [2021-12-15 17:20:33,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,688 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2021-12-15 17:20:33,688 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,688 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585102369] [2021-12-15 17:20:33,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,688 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,694 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:33,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:33,705 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:33,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,706 INFO L85 PathProgramCache]: Analyzing trace with hash -1863841153, now seen corresponding path program 1 times [2021-12-15 17:20:33,706 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122259106] [2021-12-15 17:20:33,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,706 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,738 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122259106] [2021-12-15 17:20:33,738 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122259106] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,738 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,738 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:33,738 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624490800] [2021-12-15 17:20:33,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,739 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,739 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:33,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:33,739 INFO L87 Difference]: Start difference. First operand 11882 states and 16095 transitions. cyclomatic complexity: 4217 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,892 INFO L93 Difference]: Finished difference Result 20482 states and 27854 transitions. [2021-12-15 17:20:33,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:33,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20482 states and 27854 transitions. [2021-12-15 17:20:34,055 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 20336 [2021-12-15 17:20:34,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20482 states to 20482 states and 27854 transitions. [2021-12-15 17:20:34,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20482 [2021-12-15 17:20:34,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20482 [2021-12-15 17:20:34,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20482 states and 27854 transitions. [2021-12-15 17:20:34,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,134 INFO L681 BuchiCegarLoop]: Abstraction has 20482 states and 27854 transitions. [2021-12-15 17:20:34,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20482 states and 27854 transitions. [2021-12-15 17:20:34,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20482 to 12170. [2021-12-15 17:20:34,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12170 states, 12170 states have (on average 1.3395234182415776) internal successors, (16302), 12169 states have internal predecessors, (16302), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12170 states to 12170 states and 16302 transitions. [2021-12-15 17:20:34,261 INFO L704 BuchiCegarLoop]: Abstraction has 12170 states and 16302 transitions. [2021-12-15 17:20:34,261 INFO L587 BuchiCegarLoop]: Abstraction has 12170 states and 16302 transitions. [2021-12-15 17:20:34,261 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:20:34,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12170 states and 16302 transitions. [2021-12-15 17:20:34,289 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12040 [2021-12-15 17:20:34,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,290 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,290 INFO L791 eck$LassoCheckResult]: Stem: 224556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 224517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 224331#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223900#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 223901#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 224346#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224172#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224173#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224152#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224153#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224433#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 224264#L611 assume !(0 == ~M_E~0); 224265#L611-2 assume !(0 == ~T1_E~0); 224450#L616-1 assume !(0 == ~T2_E~0); 224451#L621-1 assume !(0 == ~T3_E~0); 224021#L626-1 assume !(0 == ~T4_E~0); 224022#L631-1 assume !(0 == ~T5_E~0); 224214#L636-1 assume !(0 == ~E_M~0); 224065#L641-1 assume !(0 == ~E_1~0); 224066#L646-1 assume !(0 == ~E_2~0); 224234#L651-1 assume !(0 == ~E_3~0); 224501#L656-1 assume !(0 == ~E_4~0); 224431#L661-1 assume !(0 == ~E_5~0); 224432#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224468#L304 assume !(1 == ~m_pc~0); 224085#L304-2 is_master_triggered_~__retres1~0#1 := 0; 224086#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224554#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223944#L755 assume !(0 != activate_threads_~tmp~1#1); 223945#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223902#L323 assume !(1 == ~t1_pc~0); 223903#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223965#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223966#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 224393#L763 assume !(0 != activate_threads_~tmp___0~0#1); 224529#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223969#L342 assume !(1 == ~t2_pc~0); 223970#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224091#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224092#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 224523#L771 assume !(0 != activate_threads_~tmp___1~0#1); 224427#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224305#L361 assume !(1 == ~t3_pc~0); 224306#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 224334#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224136#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 224137#L779 assume !(0 != activate_threads_~tmp___2~0#1); 223980#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223981#L380 assume !(1 == ~t4_pc~0); 224302#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 224442#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224443#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224350#L787 assume !(0 != activate_threads_~tmp___3~0#1); 224351#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224043#L399 assume !(1 == ~t5_pc~0); 224044#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 224184#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224453#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 224174#L795 assume !(0 != activate_threads_~tmp___4~0#1); 224175#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224509#L679 assume !(1 == ~M_E~0); 224261#L679-2 assume !(1 == ~T1_E~0); 224104#L684-1 assume !(1 == ~T2_E~0); 224105#L689-1 assume !(1 == ~T3_E~0); 224317#L694-1 assume !(1 == ~T4_E~0); 224315#L699-1 assume !(1 == ~T5_E~0); 224316#L704-1 assume !(1 == ~E_M~0); 224289#L709-1 assume !(1 == ~E_1~0); 224220#L714-1 assume !(1 == ~E_2~0); 224221#L719-1 assume !(1 == ~E_3~0); 224420#L724-1 assume !(1 == ~E_4~0); 224009#L729-1 assume !(1 == ~E_5~0); 224010#L734-1 assume { :end_inline_reset_delta_events } true; 224513#L940-2 [2021-12-15 17:20:34,291 INFO L793 eck$LassoCheckResult]: Loop: 224513#L940-2 assume !false; 226246#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 226243#L586 assume !false; 226242#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 226240#L464 assume !(0 == ~m_st~0); 226241#L468 assume !(0 == ~t1_st~0); 227052#L472 assume !(0 == ~t2_st~0); 227045#L476 assume !(0 == ~t3_st~0); 227038#L480 assume !(0 == ~t4_st~0); 227030#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 227023#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 226959#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 226954#L511 assume !(0 != eval_~tmp~0#1); 226947#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 226878#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 226847#L611-3 assume !(0 == ~M_E~0); 226840#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 226839#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 226828#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 226808#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 226784#L631-3 assume !(0 == ~T5_E~0); 226780#L636-3 assume !(0 == ~E_M~0); 226778#L641-3 assume !(0 == ~E_1~0); 226776#L646-3 assume !(0 == ~E_2~0); 226775#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 226769#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 226767#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 226765#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 226763#L304-21 assume 1 == ~m_pc~0; 226761#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 226759#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226757#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 226754#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 226751#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226749#L323-21 assume !(1 == ~t1_pc~0); 226747#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 226745#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226743#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 226741#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 226739#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226737#L342-21 assume !(1 == ~t2_pc~0); 225698#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 226734#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 226732#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 226730#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 226728#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 226724#L361-21 assume !(1 == ~t3_pc~0); 226722#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 226720#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226718#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 226714#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 226711#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 226708#L380-21 assume !(1 == ~t4_pc~0); 226706#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 226704#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 226701#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 226699#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 226697#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 226695#L399-21 assume !(1 == ~t5_pc~0); 226691#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 226687#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 226683#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 226678#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 226313#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 226310#L679-3 assume !(1 == ~M_E~0); 226306#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 226304#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 226302#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 226300#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 226296#L699-3 assume !(1 == ~T5_E~0); 226294#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 226292#L709-3 assume !(1 == ~E_1~0); 226290#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 226287#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 226285#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 226283#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 226281#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 226278#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 226276#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 226274#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 226271#L959 assume !(0 == start_simulation_~tmp~3#1); 226268#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 226264#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 226262#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 226260#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 226258#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 226256#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 226255#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 226251#L972 assume !(0 != start_simulation_~tmp___0~1#1); 224513#L940-2 [2021-12-15 17:20:34,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,291 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 8 times [2021-12-15 17:20:34,292 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,292 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667876725] [2021-12-15 17:20:34,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,292 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:34,298 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:34,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:34,308 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:34,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,308 INFO L85 PathProgramCache]: Analyzing trace with hash 587268610, now seen corresponding path program 1 times [2021-12-15 17:20:34,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107431366] [2021-12-15 17:20:34,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,309 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,340 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,340 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107431366] [2021-12-15 17:20:34,340 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107431366] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,341 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,341 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:34,341 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966440200] [2021-12-15 17:20:34,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,341 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,341 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:34,342 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:34,342 INFO L87 Difference]: Start difference. First operand 12170 states and 16302 transitions. cyclomatic complexity: 4136 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,603 INFO L93 Difference]: Finished difference Result 27361 states and 36969 transitions. [2021-12-15 17:20:34,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:34,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27361 states and 36969 transitions. [2021-12-15 17:20:34,714 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27104 [2021-12-15 17:20:34,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27361 states to 27361 states and 36969 transitions. [2021-12-15 17:20:34,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27361 [2021-12-15 17:20:34,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27361 [2021-12-15 17:20:34,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27361 states and 36969 transitions. [2021-12-15 17:20:34,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,822 INFO L681 BuchiCegarLoop]: Abstraction has 27361 states and 36969 transitions. [2021-12-15 17:20:34,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27361 states and 36969 transitions. [2021-12-15 17:20:34,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27361 to 12701. [2021-12-15 17:20:34,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12701 states, 12701 states have (on average 1.3253287142744665) internal successors, (16833), 12700 states have internal predecessors, (16833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12701 states to 12701 states and 16833 transitions. [2021-12-15 17:20:35,016 INFO L704 BuchiCegarLoop]: Abstraction has 12701 states and 16833 transitions. [2021-12-15 17:20:35,016 INFO L587 BuchiCegarLoop]: Abstraction has 12701 states and 16833 transitions. [2021-12-15 17:20:35,016 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:20:35,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12701 states and 16833 transitions. [2021-12-15 17:20:35,048 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12568 [2021-12-15 17:20:35,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,051 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,051 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,051 INFO L791 eck$LassoCheckResult]: Stem: 264132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 264093#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 263878#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 263445#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 263446#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 263892#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 263718#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 263719#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 263696#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 263697#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 263988#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 263812#L611 assume !(0 == ~M_E~0); 263813#L611-2 assume !(0 == ~T1_E~0); 264006#L616-1 assume !(0 == ~T2_E~0); 264007#L621-1 assume !(0 == ~T3_E~0); 263567#L626-1 assume !(0 == ~T4_E~0); 263568#L631-1 assume !(0 == ~T5_E~0); 263761#L636-1 assume !(0 == ~E_M~0); 263608#L641-1 assume !(0 == ~E_1~0); 263609#L646-1 assume !(0 == ~E_2~0); 263780#L651-1 assume !(0 == ~E_3~0); 264071#L656-1 assume !(0 == ~E_4~0); 263986#L661-1 assume !(0 == ~E_5~0); 263987#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264028#L304 assume !(1 == ~m_pc~0); 263628#L304-2 is_master_triggered_~__retres1~0#1 := 0; 263629#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264130#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 263491#L755 assume !(0 != activate_threads_~tmp~1#1); 263492#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 263447#L323 assume !(1 == ~t1_pc~0); 263448#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 263510#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263511#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 263945#L763 assume !(0 != activate_threads_~tmp___0~0#1); 264113#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 263513#L342 assume !(1 == ~t2_pc~0); 263514#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 263634#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 263635#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264104#L771 assume !(0 != activate_threads_~tmp___1~0#1); 263981#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 263851#L361 assume !(1 == ~t3_pc~0); 263852#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 263880#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263680#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263681#L779 assume !(0 != activate_threads_~tmp___2~0#1); 263527#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 263528#L380 assume !(1 == ~t4_pc~0); 263848#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 263997#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263998#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 263899#L787 assume !(0 != activate_threads_~tmp___3~0#1); 263900#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 263587#L399 assume !(1 == ~t5_pc~0); 263588#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 263731#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264013#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 263720#L795 assume !(0 != activate_threads_~tmp___4~0#1); 263721#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264083#L679 assume !(1 == ~M_E~0); 263809#L679-2 assume !(1 == ~T1_E~0); 263647#L684-1 assume !(1 == ~T2_E~0); 263648#L689-1 assume !(1 == ~T3_E~0); 263863#L694-1 assume !(1 == ~T4_E~0); 263861#L699-1 assume !(1 == ~T5_E~0); 263862#L704-1 assume !(1 == ~E_M~0); 263835#L709-1 assume !(1 == ~E_1~0); 263765#L714-1 assume !(1 == ~E_2~0); 263766#L719-1 assume !(1 == ~E_3~0); 263972#L724-1 assume !(1 == ~E_4~0); 263553#L729-1 assume !(1 == ~E_5~0); 263554#L734-1 assume { :end_inline_reset_delta_events } true; 264091#L940-2 [2021-12-15 17:20:35,051 INFO L793 eck$LassoCheckResult]: Loop: 264091#L940-2 assume !false; 265264#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 265245#L586 assume !false; 265246#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 265233#L464 assume !(0 == ~m_st~0); 265235#L468 assume !(0 == ~t1_st~0); 266758#L472 assume !(0 == ~t2_st~0); 266754#L476 assume !(0 == ~t3_st~0); 266750#L480 assume !(0 == ~t4_st~0); 266744#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 266739#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 266734#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 266729#L511 assume !(0 != eval_~tmp~0#1); 266725#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 266720#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 266716#L611-3 assume !(0 == ~M_E~0); 266712#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 266708#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 266615#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 266616#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 266497#L631-3 assume !(0 == ~T5_E~0); 266498#L636-3 assume !(0 == ~E_M~0); 266303#L641-3 assume !(0 == ~E_1~0); 266304#L646-3 assume !(0 == ~E_2~0); 266255#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 266256#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 266229#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 266230#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 266023#L304-21 assume 1 == ~m_pc~0; 266024#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 266015#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 266016#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 266007#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 266008#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265903#L323-21 assume !(1 == ~t1_pc~0); 265904#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 265875#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265876#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 265848#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 265849#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 265818#L342-21 assume !(1 == ~t2_pc~0); 265817#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 265816#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 265815#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 265814#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 265813#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265812#L361-21 assume 1 == ~t3_pc~0; 265810#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 265808#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 265806#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 265804#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 265803#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 265802#L380-21 assume !(1 == ~t4_pc~0); 265801#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 265800#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265799#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 265798#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 265797#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 265796#L399-21 assume 1 == ~t5_pc~0; 265794#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 265792#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 265790#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 265788#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 265756#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 265754#L679-3 assume !(1 == ~M_E~0); 265753#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 267139#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 267138#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 267137#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 267136#L699-3 assume !(1 == ~T5_E~0); 267135#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 267134#L709-3 assume !(1 == ~E_1~0); 267133#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 267132#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 265482#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 265480#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 265477#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 265478#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 267122#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 267120#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 265454#L959 assume !(0 == start_simulation_~tmp~3#1); 265444#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 265445#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 267109#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 267506#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 267505#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267504#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 267503#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 265274#L972 assume !(0 != start_simulation_~tmp___0~1#1); 264091#L940-2 [2021-12-15 17:20:35,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 9 times [2021-12-15 17:20:35,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987813656] [2021-12-15 17:20:35,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,060 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:35,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,072 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:35,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,072 INFO L85 PathProgramCache]: Analyzing trace with hash -1989390850, now seen corresponding path program 1 times [2021-12-15 17:20:35,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650061316] [2021-12-15 17:20:35,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,081 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:35,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:35,099 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:35,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,100 INFO L85 PathProgramCache]: Analyzing trace with hash -91075014, now seen corresponding path program 1 times [2021-12-15 17:20:35,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452182720] [2021-12-15 17:20:35,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,100 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,131 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,131 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452182720] [2021-12-15 17:20:35,131 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452182720] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,131 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,131 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,131 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77334081] [2021-12-15 17:20:35,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,339 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:20:36,342 INFO L158 Benchmark]: Toolchain (without parser) took 9518.29ms. Allocated memory was 117.4MB in the beginning and 1.0GB in the end (delta: 910.2MB). Free memory was 80.7MB in the beginning and 738.5MB in the end (delta: -657.8MB). Peak memory consumption was 557.9MB. Max. memory is 16.1GB. [2021-12-15 17:20:36,342 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 117.4MB. Free memory is still 97.5MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:20:36,343 INFO L158 Benchmark]: CACSL2BoogieTranslator took 351.90ms. Allocated memory is still 117.4MB. Free memory was 80.5MB in the beginning and 88.3MB in the end (delta: -7.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-12-15 17:20:36,343 INFO L158 Benchmark]: Boogie Procedure Inliner took 54.78ms. Allocated memory is still 117.4MB. Free memory was 88.3MB in the beginning and 83.1MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:36,343 INFO L158 Benchmark]: Boogie Preprocessor took 66.59ms. Allocated memory is still 117.4MB. Free memory was 83.1MB in the beginning and 78.5MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:20:36,343 INFO L158 Benchmark]: RCFGBuilder took 915.64ms. Allocated memory is still 117.4MB. Free memory was 78.5MB in the beginning and 74.5MB in the end (delta: 4.0MB). Peak memory consumption was 40.0MB. Max. memory is 16.1GB. [2021-12-15 17:20:36,343 INFO L158 Benchmark]: BuchiAutomizer took 8124.24ms. Allocated memory was 117.4MB in the beginning and 1.0GB in the end (delta: 910.2MB). Free memory was 74.1MB in the beginning and 738.5MB in the end (delta: -664.5MB). Peak memory consumption was 551.7MB. Max. memory is 16.1GB. [2021-12-15 17:20:36,344 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 117.4MB. Free memory is still 97.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 351.90ms. Allocated memory is still 117.4MB. Free memory was 80.5MB in the beginning and 88.3MB in the end (delta: -7.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 54.78ms. Allocated memory is still 117.4MB. Free memory was 88.3MB in the beginning and 83.1MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 66.59ms. Allocated memory is still 117.4MB. Free memory was 83.1MB in the beginning and 78.5MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 915.64ms. Allocated memory is still 117.4MB. Free memory was 78.5MB in the beginning and 74.5MB in the end (delta: 4.0MB). Peak memory consumption was 40.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 8124.24ms. Allocated memory was 117.4MB in the beginning and 1.0GB in the end (delta: 910.2MB). Free memory was 74.1MB in the beginning and 738.5MB in the end (delta: -664.5MB). Peak memory consumption was 551.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:20:36,369 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable