./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:28,226 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:28,228 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:28,277 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:28,278 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:28,280 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:28,281 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:28,283 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:28,285 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:28,288 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:28,288 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:28,289 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:28,290 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:28,291 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:28,293 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:28,295 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:28,296 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:28,297 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:28,298 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:28,303 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:28,304 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:28,304 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:28,305 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:28,306 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:28,311 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:28,311 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:28,311 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:28,312 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:28,313 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:28,313 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:28,313 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:28,314 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:28,315 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:28,316 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:28,317 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:28,317 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:28,317 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:28,318 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:28,318 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:28,319 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:28,319 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:28,320 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:28,346 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:28,346 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:28,347 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:28,347 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:28,348 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:28,348 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:28,348 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:28,348 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:28,348 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:28,349 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:28,349 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:28,349 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:28,349 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:28,350 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:28,350 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:28,350 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:28,350 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:28,350 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:28,350 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:28,350 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:28,351 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:28,351 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:28,351 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:28,351 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:28,351 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:28,351 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:28,352 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:28,352 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:28,352 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:28,352 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:28,352 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:28,352 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:28,353 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:28,353 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2021-12-15 17:20:28,572 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:28,597 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:28,599 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:28,599 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:28,607 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:28,609 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2021-12-15 17:20:28,667 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c71fff23b/951572371ce7498a90153529240b1bb7/FLAG765174a38 [2021-12-15 17:20:29,029 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:29,029 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2021-12-15 17:20:29,041 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c71fff23b/951572371ce7498a90153529240b1bb7/FLAG765174a38 [2021-12-15 17:20:29,400 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c71fff23b/951572371ce7498a90153529240b1bb7 [2021-12-15 17:20:29,403 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:29,404 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:29,407 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:29,407 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:29,409 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:29,409 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,411 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67852c8e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29, skipping insertion in model container [2021-12-15 17:20:29,411 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,415 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:29,452 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:29,599 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2021-12-15 17:20:29,685 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:29,695 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:29,707 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2021-12-15 17:20:29,762 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:29,774 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:29,774 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29 WrapperNode [2021-12-15 17:20:29,774 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:29,775 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:29,775 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:29,776 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:29,781 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,789 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,842 INFO L137 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 134, statements flattened = 1989 [2021-12-15 17:20:29,855 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:29,856 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:29,856 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:29,856 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:29,872 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,872 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,886 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,887 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,902 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,929 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,933 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,953 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:29,954 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:29,954 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:29,954 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:29,955 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (1/1) ... [2021-12-15 17:20:29,972 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:29,979 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:30,005 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:30,009 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:30,038 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:30,038 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:30,038 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:30,039 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:30,150 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:30,155 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:31,061 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:31,069 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:31,070 INFO L301 CfgBuilder]: Removed 10 assume(true) statements. [2021-12-15 17:20:31,072 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:31 BoogieIcfgContainer [2021-12-15 17:20:31,072 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:31,073 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:31,073 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:31,075 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:31,075 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:31,076 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:29" (1/3) ... [2021-12-15 17:20:31,077 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d79fb82 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:31, skipping insertion in model container [2021-12-15 17:20:31,077 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:31,077 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:29" (2/3) ... [2021-12-15 17:20:31,077 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d79fb82 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:31, skipping insertion in model container [2021-12-15 17:20:31,077 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:31,077 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:31" (3/3) ... [2021-12-15 17:20:31,078 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2021-12-15 17:20:31,121 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:31,121 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:31,121 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:31,121 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:31,121 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:31,121 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:31,121 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:31,122 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:31,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2021-12-15 17:20:31,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,194 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,195 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,195 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:31,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2021-12-15 17:20:31,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,209 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,209 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,214 INFO L791 eck$LassoCheckResult]: Stem: 412#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 753#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 307#L1141true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266#L529true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 562#L536true assume !(1 == ~m_i~0);~m_st~0 := 2; 779#L536-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 252#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 150#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 627#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 139#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 578#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 560#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 361#L571-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 649#L769true assume !(0 == ~M_E~0); 378#L769-2true assume !(0 == ~T1_E~0); 403#L774-1true assume !(0 == ~T2_E~0); 666#L779-1true assume !(0 == ~T3_E~0); 540#L784-1true assume !(0 == ~T4_E~0); 358#L789-1true assume !(0 == ~T5_E~0); 458#L794-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 816#L799-1true assume !(0 == ~T7_E~0); 363#L804-1true assume !(0 == ~E_M~0); 394#L809-1true assume !(0 == ~E_1~0); 571#L814-1true assume !(0 == ~E_2~0); 9#L819-1true assume !(0 == ~E_3~0); 186#L824-1true assume !(0 == ~E_4~0); 806#L829-1true assume !(0 == ~E_5~0); 663#L834-1true assume 0 == ~E_6~0;~E_6~0 := 1; 70#L839-1true assume !(0 == ~E_7~0); 464#L844-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 314#L376true assume !(1 == ~m_pc~0); 312#L376-2true is_master_triggered_~__retres1~0#1 := 0; 762#L387true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 626#L388true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46#L955true assume !(0 != activate_threads_~tmp~1#1); 245#L955-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 380#L395true assume 1 == ~t1_pc~0; 61#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 541#L406true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12#L407true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 586#L963true assume !(0 != activate_threads_~tmp___0~0#1); 320#L963-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 826#L414true assume !(1 == ~t2_pc~0); 570#L414-2true is_transmit2_triggered_~__retres1~2#1 := 0; 814#L425true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178#L426true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 568#L971true assume !(0 != activate_threads_~tmp___1~0#1); 680#L971-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 249#L433true assume 1 == ~t3_pc~0; 210#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 692#L444true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228#L445true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 505#L979true assume !(0 != activate_threads_~tmp___2~0#1); 56#L979-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 780#L452true assume !(1 == ~t4_pc~0); 137#L452-2true is_transmit4_triggered_~__retres1~4#1 := 0; 348#L463true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 402#L464true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 688#L987true assume !(0 != activate_threads_~tmp___3~0#1); 155#L987-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 444#L471true assume 1 == ~t5_pc~0; 744#L472true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145#L482true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 395#L483true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 812#L995true assume !(0 != activate_threads_~tmp___4~0#1); 651#L995-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 729#L490true assume 1 == ~t6_pc~0; 609#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 353#L501true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 448#L502true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 355#L1003true assume !(0 != activate_threads_~tmp___5~0#1); 256#L1003-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 233#L509true assume !(1 == ~t7_pc~0); 572#L509-2true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L520true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 685#L521true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 157#L1011true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 690#L1011-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 583#L857true assume !(1 == ~M_E~0); 49#L857-2true assume !(1 == ~T1_E~0); 193#L862-1true assume !(1 == ~T2_E~0); 198#L867-1true assume !(1 == ~T3_E~0); 250#L872-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 422#L877-1true assume !(1 == ~T5_E~0); 608#L882-1true assume !(1 == ~T6_E~0); 736#L887-1true assume !(1 == ~T7_E~0); 479#L892-1true assume !(1 == ~E_M~0); 700#L897-1true assume !(1 == ~E_1~0); 205#L902-1true assume !(1 == ~E_2~0); 495#L907-1true assume !(1 == ~E_3~0); 434#L912-1true assume 1 == ~E_4~0;~E_4~0 := 2; 427#L917-1true assume !(1 == ~E_5~0); 671#L922-1true assume !(1 == ~E_6~0); 788#L927-1true assume !(1 == ~E_7~0); 418#L932-1true assume { :end_inline_reset_delta_events } true; 715#L1178-2true [2021-12-15 17:20:31,216 INFO L793 eck$LassoCheckResult]: Loop: 715#L1178-2true assume !false; 407#L1179true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 227#L744true assume !true; 347#L759true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89#L529-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 647#L769-3true assume 0 == ~M_E~0;~M_E~0 := 1; 247#L769-5true assume !(0 == ~T1_E~0); 385#L774-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 98#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 16#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 829#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 10#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 33#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 161#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 316#L809-3true assume !(0 == ~E_1~0); 31#L814-3true assume 0 == ~E_2~0;~E_2~0 := 1; 550#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 508#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 500#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 194#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 457#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 580#L844-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728#L376-27true assume !(1 == ~m_pc~0); 817#L376-29true is_master_triggered_~__retres1~0#1 := 0; 383#L387-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 485#L388-9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 681#L955-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 822#L955-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 807#L395-27true assume 1 == ~t1_pc~0; 784#L396-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 195#L406-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 517#L407-9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 377#L963-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 253#L963-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 644#L414-27true assume !(1 == ~t2_pc~0); 747#L414-29true is_transmit2_triggered_~__retres1~2#1 := 0; 426#L425-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 659#L426-9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301#L971-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39#L971-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84#L433-27true assume !(1 == ~t3_pc~0); 304#L433-29true is_transmit3_triggered_~__retres1~3#1 := 0; 258#L444-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 795#L445-9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125#L979-27true assume !(0 != activate_threads_~tmp___2~0#1); 754#L979-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 740#L452-27true assume 1 == ~t4_pc~0; 835#L453-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 544#L463-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 674#L464-9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 639#L987-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 650#L987-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35#L471-27true assume 1 == ~t5_pc~0; 483#L472-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 823#L482-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 579#L483-9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 446#L995-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 381#L995-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 313#L490-27true assume 1 == ~t6_pc~0; 229#L491-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 131#L501-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 614#L502-9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 433#L1003-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 709#L1003-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20#L509-27true assume 1 == ~t7_pc~0; 338#L510-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 533#L520-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336#L521-9true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 331#L1011-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 802#L1011-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 344#L857-3true assume 1 == ~M_E~0;~M_E~0 := 2; 375#L857-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 785#L862-3true assume !(1 == ~T2_E~0); 730#L867-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 259#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 337#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 763#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 372#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 109#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 530#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 825#L902-3true assume !(1 == ~E_2~0); 204#L907-3true assume 1 == ~E_3~0;~E_3~0 := 2; 293#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 565#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 262#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 138#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 211#L932-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 60#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 461#L626-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 798#L627-1true start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 241#L1197true assume !(0 == start_simulation_~tmp~3#1); 512#L1197-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 87#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 246#L626-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 36#L627-2true stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 742#L1152true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 526#L1159true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 632#L1160true start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 26#L1210true assume !(0 != start_simulation_~tmp___0~1#1); 715#L1178-2true [2021-12-15 17:20:31,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2021-12-15 17:20:31,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803721059] [2021-12-15 17:20:31,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,361 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,361 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803721059] [2021-12-15 17:20:31,362 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803721059] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,362 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,362 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:31,363 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366739246] [2021-12-15 17:20:31,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,366 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:31,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1867582005, now seen corresponding path program 1 times [2021-12-15 17:20:31,368 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256124500] [2021-12-15 17:20:31,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,368 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,391 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256124500] [2021-12-15 17:20:31,391 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256124500] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,391 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,392 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:31,392 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328341920] [2021-12-15 17:20:31,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,393 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:31,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:31,428 INFO L87 Difference]: Start difference. First operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,591 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2021-12-15 17:20:31,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:31,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2021-12-15 17:20:31,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:31,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 830 states and 1240 transitions. [2021-12-15 17:20:31,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-15 17:20:31,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-15 17:20:31,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1240 transitions. [2021-12-15 17:20:31,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:31,632 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2021-12-15 17:20:31,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1240 transitions. [2021-12-15 17:20:31,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2021-12-15 17:20:31,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1240 transitions. [2021-12-15 17:20:31,695 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2021-12-15 17:20:31,695 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2021-12-15 17:20:31,695 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:31,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1240 transitions. [2021-12-15 17:20:31,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:31,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,701 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,701 INFO L791 eck$LassoCheckResult]: Stem: 2319#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2202#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2152#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2153#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2436#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2135#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1975#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1976#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1957#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1958#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2435#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2260#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2261#L769 assume !(0 == ~M_E~0); 2283#L769-2 assume !(0 == ~T1_E~0); 2284#L774-1 assume !(0 == ~T2_E~0); 2311#L779-1 assume !(0 == ~T3_E~0); 2423#L784-1 assume !(0 == ~T4_E~0); 2256#L789-1 assume !(0 == ~T5_E~0); 2257#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2367#L799-1 assume !(0 == ~T7_E~0); 2263#L804-1 assume !(0 == ~E_M~0); 2264#L809-1 assume !(0 == ~E_1~0); 2304#L814-1 assume !(0 == ~E_2~0); 1693#L819-1 assume !(0 == ~E_3~0); 1694#L824-1 assume !(0 == ~E_4~0); 2045#L829-1 assume !(0 == ~E_5~0); 2482#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1829#L839-1 assume !(0 == ~E_7~0); 1830#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2208#L376 assume !(1 == ~m_pc~0); 2195#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2194#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2465#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1776#L955 assume !(0 != activate_threads_~tmp~1#1); 1777#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2128#L395 assume 1 == ~t1_pc~0; 1806#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1807#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1699#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1700#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2212#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2213#L414 assume !(1 == ~t2_pc~0); 1832#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1833#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2031#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2032#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2439#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2131#L433 assume 1 == ~t3_pc~0; 2076#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1946#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2104#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2105#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1797#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1798#L452 assume !(1 == ~t4_pc~0); 1953#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1954#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2244#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2310#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1986#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1987#L471 assume 1 == ~t5_pc~0; 2355#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1969#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1970#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2305#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2474#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2475#L490 assume 1 == ~t6_pc~0; 2458#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2211#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2251#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2254#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2140#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2109#L509 assume !(1 == ~t7_pc~0); 2110#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1927#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1928#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1991#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1992#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2447#L857 assume !(1 == ~M_E~0); 1783#L857-2 assume !(1 == ~T1_E~0); 1784#L862-1 assume !(1 == ~T2_E~0); 2053#L867-1 assume !(1 == ~T3_E~0); 2058#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2132#L877-1 assume !(1 == ~T5_E~0); 2331#L882-1 assume !(1 == ~T6_E~0); 2457#L887-1 assume !(1 == ~T7_E~0); 2381#L892-1 assume !(1 == ~E_M~0); 2382#L897-1 assume !(1 == ~E_1~0); 2068#L902-1 assume !(1 == ~E_2~0); 2069#L907-1 assume !(1 == ~E_3~0); 2348#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2339#L917-1 assume !(1 == ~E_5~0); 2340#L922-1 assume !(1 == ~E_6~0); 2485#L927-1 assume !(1 == ~E_7~0); 2326#L932-1 assume { :end_inline_reset_delta_events } true; 1732#L1178-2 [2021-12-15 17:20:31,701 INFO L793 eck$LassoCheckResult]: Loop: 1732#L1178-2 assume !false; 2315#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1749#L744 assume !false; 2103#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2176#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1767#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1973#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2427#L641 assume !(0 != eval_~tmp~0#1); 2243#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1867#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1868#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2129#L769-5 assume !(0 == ~T1_E~0); 2130#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1884#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1708#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1709#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1695#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1696#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1747#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2001#L809-3 assume !(0 == ~E_1~0); 1743#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1744#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2403#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2398#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2054#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2055#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2366#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2445#L376-27 assume 1 == ~m_pc~0; 2344#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2290#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2291#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2385#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2488#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2509#L395-27 assume !(1 == ~t1_pc~0); 2148#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2056#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2057#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2282#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2136#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2137#L414-27 assume 1 == ~t2_pc~0; 2472#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2337#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2338#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2197#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1759#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1760#L433-27 assume 1 == ~t3_pc~0; 1856#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2142#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2143#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1930#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1931#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2502#L452-27 assume 1 == ~t4_pc~0; 2503#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2302#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2426#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2468#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2469#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1750#L471-27 assume !(1 == ~t5_pc~0); 1751#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2065#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2444#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2358#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2286#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2207#L490-27 assume 1 == ~t6_pc~0; 2106#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1942#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1943#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2346#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2347#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1717#L509-27 assume !(1 == ~t7_pc~0); 1718#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2108#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2233#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2224#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2225#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2239#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2240#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2280#L862-3 assume !(1 == ~T2_E~0); 2500#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2144#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2145#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2234#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2274#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1904#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1905#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2418#L902-3 assume !(1 == ~E_2~0); 2066#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2067#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2186#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2149#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1955#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1956#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1804#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1707#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2369#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2119#L1197 assume !(0 == start_simulation_~tmp~3#1); 2120#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1863#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1827#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1753#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1754#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2415#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2416#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1731#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1732#L1178-2 [2021-12-15 17:20:31,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,702 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2021-12-15 17:20:31,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10553305] [2021-12-15 17:20:31,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,702 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,769 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10553305] [2021-12-15 17:20:31,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10553305] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,770 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,770 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:31,770 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334606526] [2021-12-15 17:20:31,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,771 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:31,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,771 INFO L85 PathProgramCache]: Analyzing trace with hash -802393431, now seen corresponding path program 1 times [2021-12-15 17:20:31,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643001627] [2021-12-15 17:20:31,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:31,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:31,865 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:31,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643001627] [2021-12-15 17:20:31,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643001627] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:31,866 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:31,866 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:31,866 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144541327] [2021-12-15 17:20:31,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:31,887 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:31,888 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:31,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:31,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:31,889 INFO L87 Difference]: Start difference. First operand 830 states and 1240 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:31,924 INFO L93 Difference]: Finished difference Result 830 states and 1239 transitions. [2021-12-15 17:20:31,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:31,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1239 transitions. [2021-12-15 17:20:31,929 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:31,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1239 transitions. [2021-12-15 17:20:31,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-15 17:20:31,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-15 17:20:31,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1239 transitions. [2021-12-15 17:20:31,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:31,956 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2021-12-15 17:20:31,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1239 transitions. [2021-12-15 17:20:31,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2021-12-15 17:20:31,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:31,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1239 transitions. [2021-12-15 17:20:31,970 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2021-12-15 17:20:31,970 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2021-12-15 17:20:31,970 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:31,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1239 transitions. [2021-12-15 17:20:31,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:31,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:31,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:31,975 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,975 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:31,975 INFO L791 eck$LassoCheckResult]: Stem: 3986#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3869#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3819#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3820#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 4103#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3802#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3642#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3643#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3624#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3625#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4102#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3927#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3928#L769 assume !(0 == ~M_E~0); 3950#L769-2 assume !(0 == ~T1_E~0); 3951#L774-1 assume !(0 == ~T2_E~0); 3978#L779-1 assume !(0 == ~T3_E~0); 4090#L784-1 assume !(0 == ~T4_E~0); 3923#L789-1 assume !(0 == ~T5_E~0); 3924#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4034#L799-1 assume !(0 == ~T7_E~0); 3930#L804-1 assume !(0 == ~E_M~0); 3931#L809-1 assume !(0 == ~E_1~0); 3971#L814-1 assume !(0 == ~E_2~0); 3360#L819-1 assume !(0 == ~E_3~0); 3361#L824-1 assume !(0 == ~E_4~0); 3712#L829-1 assume !(0 == ~E_5~0); 4149#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3496#L839-1 assume !(0 == ~E_7~0); 3497#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3875#L376 assume !(1 == ~m_pc~0); 3862#L376-2 is_master_triggered_~__retres1~0#1 := 0; 3861#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4132#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3443#L955 assume !(0 != activate_threads_~tmp~1#1); 3444#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3795#L395 assume 1 == ~t1_pc~0; 3473#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3474#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3366#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3367#L963 assume !(0 != activate_threads_~tmp___0~0#1); 3879#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3880#L414 assume !(1 == ~t2_pc~0); 3499#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3500#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3698#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3699#L971 assume !(0 != activate_threads_~tmp___1~0#1); 4106#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3798#L433 assume 1 == ~t3_pc~0; 3743#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3613#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3771#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3772#L979 assume !(0 != activate_threads_~tmp___2~0#1); 3464#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3465#L452 assume !(1 == ~t4_pc~0); 3620#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3621#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3911#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3977#L987 assume !(0 != activate_threads_~tmp___3~0#1); 3653#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3654#L471 assume 1 == ~t5_pc~0; 4022#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3636#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3637#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3972#L995 assume !(0 != activate_threads_~tmp___4~0#1); 4141#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4142#L490 assume 1 == ~t6_pc~0; 4125#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3878#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3918#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3921#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 3807#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3776#L509 assume !(1 == ~t7_pc~0); 3777#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3594#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3595#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3658#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3659#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4114#L857 assume !(1 == ~M_E~0); 3450#L857-2 assume !(1 == ~T1_E~0); 3451#L862-1 assume !(1 == ~T2_E~0); 3720#L867-1 assume !(1 == ~T3_E~0); 3725#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3799#L877-1 assume !(1 == ~T5_E~0); 3998#L882-1 assume !(1 == ~T6_E~0); 4124#L887-1 assume !(1 == ~T7_E~0); 4048#L892-1 assume !(1 == ~E_M~0); 4049#L897-1 assume !(1 == ~E_1~0); 3735#L902-1 assume !(1 == ~E_2~0); 3736#L907-1 assume !(1 == ~E_3~0); 4015#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4006#L917-1 assume !(1 == ~E_5~0); 4007#L922-1 assume !(1 == ~E_6~0); 4152#L927-1 assume !(1 == ~E_7~0); 3993#L932-1 assume { :end_inline_reset_delta_events } true; 3399#L1178-2 [2021-12-15 17:20:31,975 INFO L793 eck$LassoCheckResult]: Loop: 3399#L1178-2 assume !false; 3982#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3416#L744 assume !false; 3770#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3843#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3434#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3640#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4094#L641 assume !(0 != eval_~tmp~0#1); 3910#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3534#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3535#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3796#L769-5 assume !(0 == ~T1_E~0); 3797#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3551#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3375#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3376#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3362#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3363#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3414#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3668#L809-3 assume !(0 == ~E_1~0); 3410#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3411#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4070#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4065#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3721#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3722#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4033#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4112#L376-27 assume 1 == ~m_pc~0; 4011#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3957#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3958#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4052#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4155#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4176#L395-27 assume !(1 == ~t1_pc~0); 3815#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 3723#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3724#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3949#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3803#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3804#L414-27 assume 1 == ~t2_pc~0; 4139#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4004#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4005#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3864#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3426#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3427#L433-27 assume !(1 == ~t3_pc~0); 3522#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 3809#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3810#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3597#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 3598#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4169#L452-27 assume !(1 == ~t4_pc~0); 3968#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 3969#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4093#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4135#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4136#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3417#L471-27 assume !(1 == ~t5_pc~0); 3418#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 3732#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4111#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4025#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3953#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3874#L490-27 assume 1 == ~t6_pc~0; 3773#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3609#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3610#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4013#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4014#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3384#L509-27 assume !(1 == ~t7_pc~0); 3385#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 3775#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3900#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3891#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3892#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3906#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3907#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3947#L862-3 assume !(1 == ~T2_E~0); 4167#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3811#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3812#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3901#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3941#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3571#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3572#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4085#L902-3 assume !(1 == ~E_2~0); 3733#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3734#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3853#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3816#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3622#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3623#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3471#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3374#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4036#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3786#L1197 assume !(0 == start_simulation_~tmp~3#1); 3787#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3530#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3494#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3420#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 3421#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4082#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4083#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3398#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 3399#L1178-2 [2021-12-15 17:20:31,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:31,976 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2021-12-15 17:20:31,976 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:31,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948078750] [2021-12-15 17:20:31,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:31,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:31,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,022 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,022 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948078750] [2021-12-15 17:20:32,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948078750] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,023 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,023 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,023 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375939265] [2021-12-15 17:20:32,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,023 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,024 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 1 times [2021-12-15 17:20:32,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731538362] [2021-12-15 17:20:32,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,025 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731538362] [2021-12-15 17:20:32,104 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1731538362] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,105 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,105 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,105 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69746205] [2021-12-15 17:20:32,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,105 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,106 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,106 INFO L87 Difference]: Start difference. First operand 830 states and 1239 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,118 INFO L93 Difference]: Finished difference Result 830 states and 1238 transitions. [2021-12-15 17:20:32,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1238 transitions. [2021-12-15 17:20:32,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1238 transitions. [2021-12-15 17:20:32,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-15 17:20:32,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-15 17:20:32,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1238 transitions. [2021-12-15 17:20:32,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,130 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2021-12-15 17:20:32,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1238 transitions. [2021-12-15 17:20:32,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2021-12-15 17:20:32,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1238 transitions. [2021-12-15 17:20:32,140 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2021-12-15 17:20:32,140 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2021-12-15 17:20:32,140 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:32,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1238 transitions. [2021-12-15 17:20:32,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,146 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,147 INFO L791 eck$LassoCheckResult]: Stem: 5653#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5536#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5486#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5487#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 5770#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5469#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5309#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5310#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5291#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5292#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5769#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5594#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5595#L769 assume !(0 == ~M_E~0); 5617#L769-2 assume !(0 == ~T1_E~0); 5618#L774-1 assume !(0 == ~T2_E~0); 5645#L779-1 assume !(0 == ~T3_E~0); 5757#L784-1 assume !(0 == ~T4_E~0); 5590#L789-1 assume !(0 == ~T5_E~0); 5591#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5701#L799-1 assume !(0 == ~T7_E~0); 5597#L804-1 assume !(0 == ~E_M~0); 5598#L809-1 assume !(0 == ~E_1~0); 5638#L814-1 assume !(0 == ~E_2~0); 5027#L819-1 assume !(0 == ~E_3~0); 5028#L824-1 assume !(0 == ~E_4~0); 5379#L829-1 assume !(0 == ~E_5~0); 5816#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5163#L839-1 assume !(0 == ~E_7~0); 5164#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5542#L376 assume !(1 == ~m_pc~0); 5529#L376-2 is_master_triggered_~__retres1~0#1 := 0; 5528#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5799#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5110#L955 assume !(0 != activate_threads_~tmp~1#1); 5111#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5462#L395 assume 1 == ~t1_pc~0; 5140#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5141#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5033#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5034#L963 assume !(0 != activate_threads_~tmp___0~0#1); 5546#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5547#L414 assume !(1 == ~t2_pc~0); 5166#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5167#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5365#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5366#L971 assume !(0 != activate_threads_~tmp___1~0#1); 5773#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5465#L433 assume 1 == ~t3_pc~0; 5410#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5280#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5438#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5439#L979 assume !(0 != activate_threads_~tmp___2~0#1); 5131#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5132#L452 assume !(1 == ~t4_pc~0); 5287#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5288#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5578#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5644#L987 assume !(0 != activate_threads_~tmp___3~0#1); 5320#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5321#L471 assume 1 == ~t5_pc~0; 5689#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5303#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5304#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5639#L995 assume !(0 != activate_threads_~tmp___4~0#1); 5808#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5809#L490 assume 1 == ~t6_pc~0; 5792#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5545#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5585#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5588#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 5474#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5443#L509 assume !(1 == ~t7_pc~0); 5444#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5261#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5262#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5325#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5326#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5781#L857 assume !(1 == ~M_E~0); 5117#L857-2 assume !(1 == ~T1_E~0); 5118#L862-1 assume !(1 == ~T2_E~0); 5387#L867-1 assume !(1 == ~T3_E~0); 5392#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5466#L877-1 assume !(1 == ~T5_E~0); 5665#L882-1 assume !(1 == ~T6_E~0); 5791#L887-1 assume !(1 == ~T7_E~0); 5715#L892-1 assume !(1 == ~E_M~0); 5716#L897-1 assume !(1 == ~E_1~0); 5402#L902-1 assume !(1 == ~E_2~0); 5403#L907-1 assume !(1 == ~E_3~0); 5682#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5673#L917-1 assume !(1 == ~E_5~0); 5674#L922-1 assume !(1 == ~E_6~0); 5819#L927-1 assume !(1 == ~E_7~0); 5660#L932-1 assume { :end_inline_reset_delta_events } true; 5066#L1178-2 [2021-12-15 17:20:32,148 INFO L793 eck$LassoCheckResult]: Loop: 5066#L1178-2 assume !false; 5649#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5083#L744 assume !false; 5437#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5510#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5101#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5307#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5761#L641 assume !(0 != eval_~tmp~0#1); 5577#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5201#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5202#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5463#L769-5 assume !(0 == ~T1_E~0); 5464#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5218#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5042#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5043#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5029#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5030#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5081#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5335#L809-3 assume !(0 == ~E_1~0); 5077#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5078#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5737#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5732#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5388#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5389#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5700#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5779#L376-27 assume 1 == ~m_pc~0; 5678#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5624#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5625#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5719#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5822#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5843#L395-27 assume !(1 == ~t1_pc~0); 5482#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5390#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5391#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5616#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5470#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5471#L414-27 assume 1 == ~t2_pc~0; 5806#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5671#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5672#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5531#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5093#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5094#L433-27 assume !(1 == ~t3_pc~0); 5189#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 5476#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5477#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5264#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 5265#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5836#L452-27 assume !(1 == ~t4_pc~0); 5635#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5636#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5760#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5802#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5803#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5084#L471-27 assume !(1 == ~t5_pc~0); 5085#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 5399#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5778#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5692#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5620#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5541#L490-27 assume 1 == ~t6_pc~0; 5440#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5276#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5277#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5680#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5681#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5051#L509-27 assume !(1 == ~t7_pc~0); 5052#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5442#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5567#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5558#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5559#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5573#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5574#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5614#L862-3 assume !(1 == ~T2_E~0); 5834#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5478#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5479#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5568#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5608#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5238#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5239#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5752#L902-3 assume !(1 == ~E_2~0); 5400#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5401#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5520#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5483#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5289#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5290#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5138#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5041#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5703#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5453#L1197 assume !(0 == start_simulation_~tmp~3#1); 5454#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5197#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5161#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5087#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 5088#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5749#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5750#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5065#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 5066#L1178-2 [2021-12-15 17:20:32,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,149 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2021-12-15 17:20:32,150 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557076628] [2021-12-15 17:20:32,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,196 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,196 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557076628] [2021-12-15 17:20:32,197 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557076628] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,197 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,198 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,200 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853758623] [2021-12-15 17:20:32,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,200 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,201 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 2 times [2021-12-15 17:20:32,201 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130134127] [2021-12-15 17:20:32,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,261 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130134127] [2021-12-15 17:20:32,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130134127] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,262 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,262 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,262 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873919337] [2021-12-15 17:20:32,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,262 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,262 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,263 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,264 INFO L87 Difference]: Start difference. First operand 830 states and 1238 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,277 INFO L93 Difference]: Finished difference Result 830 states and 1237 transitions. [2021-12-15 17:20:32,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1237 transitions. [2021-12-15 17:20:32,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1237 transitions. [2021-12-15 17:20:32,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-15 17:20:32,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-15 17:20:32,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1237 transitions. [2021-12-15 17:20:32,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,286 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2021-12-15 17:20:32,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1237 transitions. [2021-12-15 17:20:32,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2021-12-15 17:20:32,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1237 transitions. [2021-12-15 17:20:32,296 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2021-12-15 17:20:32,296 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2021-12-15 17:20:32,296 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:32,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1237 transitions. [2021-12-15 17:20:32,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,303 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,303 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,303 INFO L791 eck$LassoCheckResult]: Stem: 7320#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7321#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7203#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7153#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7154#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 7437#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7136#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6976#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6977#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6958#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6959#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7436#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7262#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7263#L769 assume !(0 == ~M_E~0); 7285#L769-2 assume !(0 == ~T1_E~0); 7286#L774-1 assume !(0 == ~T2_E~0); 7312#L779-1 assume !(0 == ~T3_E~0); 7424#L784-1 assume !(0 == ~T4_E~0); 7257#L789-1 assume !(0 == ~T5_E~0); 7258#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7368#L799-1 assume !(0 == ~T7_E~0); 7264#L804-1 assume !(0 == ~E_M~0); 7265#L809-1 assume !(0 == ~E_1~0); 7305#L814-1 assume !(0 == ~E_2~0); 6696#L819-1 assume !(0 == ~E_3~0); 6697#L824-1 assume !(0 == ~E_4~0); 7046#L829-1 assume !(0 == ~E_5~0); 7483#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6830#L839-1 assume !(0 == ~E_7~0); 6831#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7209#L376 assume !(1 == ~m_pc~0); 7199#L376-2 is_master_triggered_~__retres1~0#1 := 0; 7198#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7466#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6779#L955 assume !(0 != activate_threads_~tmp~1#1); 6780#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7129#L395 assume 1 == ~t1_pc~0; 6807#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6808#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6702#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6703#L963 assume !(0 != activate_threads_~tmp___0~0#1); 7214#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7215#L414 assume !(1 == ~t2_pc~0); 6833#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6834#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7032#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7033#L971 assume !(0 != activate_threads_~tmp___1~0#1); 7440#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7132#L433 assume 1 == ~t3_pc~0; 7077#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6949#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7107#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7108#L979 assume !(0 != activate_threads_~tmp___2~0#1); 6798#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6799#L452 assume !(1 == ~t4_pc~0); 6954#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6955#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7246#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7311#L987 assume !(0 != activate_threads_~tmp___3~0#1); 6987#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6988#L471 assume 1 == ~t5_pc~0; 7356#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6970#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6971#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7306#L995 assume !(0 != activate_threads_~tmp___4~0#1); 7475#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7476#L490 assume 1 == ~t6_pc~0; 7460#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7212#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7252#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7255#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 7143#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7110#L509 assume !(1 == ~t7_pc~0); 7111#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6933#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6934#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6992#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6993#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7448#L857 assume !(1 == ~M_E~0); 6784#L857-2 assume !(1 == ~T1_E~0); 6785#L862-1 assume !(1 == ~T2_E~0); 7054#L867-1 assume !(1 == ~T3_E~0); 7059#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7133#L877-1 assume !(1 == ~T5_E~0); 7332#L882-1 assume !(1 == ~T6_E~0); 7458#L887-1 assume !(1 == ~T7_E~0); 7382#L892-1 assume !(1 == ~E_M~0); 7383#L897-1 assume !(1 == ~E_1~0); 7071#L902-1 assume !(1 == ~E_2~0); 7072#L907-1 assume !(1 == ~E_3~0); 7351#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7340#L917-1 assume !(1 == ~E_5~0); 7341#L922-1 assume !(1 == ~E_6~0); 7486#L927-1 assume !(1 == ~E_7~0); 7327#L932-1 assume { :end_inline_reset_delta_events } true; 6733#L1178-2 [2021-12-15 17:20:32,304 INFO L793 eck$LassoCheckResult]: Loop: 6733#L1178-2 assume !false; 7316#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6750#L744 assume !false; 7104#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7178#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6768#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6974#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7430#L641 assume !(0 != eval_~tmp~0#1); 7244#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6868#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6869#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7130#L769-5 assume !(0 == ~T1_E~0); 7131#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6887#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6709#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6710#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6698#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6699#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6748#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7003#L809-3 assume !(0 == ~E_1~0); 6746#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6747#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7405#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7399#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7057#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7058#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7367#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7446#L376-27 assume 1 == ~m_pc~0; 7345#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7291#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7292#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7386#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7489#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7510#L395-27 assume 1 == ~t1_pc~0; 7506#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7055#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7056#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7283#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7137#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7138#L414-27 assume 1 == ~t2_pc~0; 7473#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7338#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7339#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7195#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6760#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6761#L433-27 assume !(1 == ~t3_pc~0); 6856#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 7141#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7142#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6929#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 6930#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7503#L452-27 assume 1 == ~t4_pc~0; 7504#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7303#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7427#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7469#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7470#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6751#L471-27 assume !(1 == ~t5_pc~0); 6752#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 7063#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7445#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7359#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7287#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7208#L490-27 assume 1 == ~t6_pc~0; 7105#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6943#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6944#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7347#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7348#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6718#L509-27 assume 1 == ~t7_pc~0; 6720#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7109#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7234#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7225#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7226#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7240#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7241#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7281#L862-3 assume !(1 == ~T2_E~0); 7501#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7145#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7146#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7235#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7275#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6903#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6904#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7419#L902-3 assume !(1 == ~E_2~0); 7067#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7068#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7187#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7150#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6956#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6957#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6805#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6708#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7370#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7120#L1197 assume !(0 == start_simulation_~tmp~3#1); 7121#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6864#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6828#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6754#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 6755#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7416#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7417#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6732#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 6733#L1178-2 [2021-12-15 17:20:32,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2021-12-15 17:20:32,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184619028] [2021-12-15 17:20:32,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,305 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,342 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184619028] [2021-12-15 17:20:32,342 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184619028] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,342 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,342 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,343 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514122752] [2021-12-15 17:20:32,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,343 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,344 INFO L85 PathProgramCache]: Analyzing trace with hash -929852120, now seen corresponding path program 1 times [2021-12-15 17:20:32,344 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442397235] [2021-12-15 17:20:32,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,386 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442397235] [2021-12-15 17:20:32,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442397235] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,387 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,387 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,387 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178756931] [2021-12-15 17:20:32,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,388 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,388 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,388 INFO L87 Difference]: Start difference. First operand 830 states and 1237 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,400 INFO L93 Difference]: Finished difference Result 830 states and 1236 transitions. [2021-12-15 17:20:32,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1236 transitions. [2021-12-15 17:20:32,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1236 transitions. [2021-12-15 17:20:32,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-15 17:20:32,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-15 17:20:32,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1236 transitions. [2021-12-15 17:20:32,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,410 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2021-12-15 17:20:32,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1236 transitions. [2021-12-15 17:20:32,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2021-12-15 17:20:32,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1236 transitions. [2021-12-15 17:20:32,420 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2021-12-15 17:20:32,420 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2021-12-15 17:20:32,420 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:32,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1236 transitions. [2021-12-15 17:20:32,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,424 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,424 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,424 INFO L791 eck$LassoCheckResult]: Stem: 8987#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8988#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8870#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8820#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8821#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 9104#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8803#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8643#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8644#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8625#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8626#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9103#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8928#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8929#L769 assume !(0 == ~M_E~0); 8951#L769-2 assume !(0 == ~T1_E~0); 8952#L774-1 assume !(0 == ~T2_E~0); 8979#L779-1 assume !(0 == ~T3_E~0); 9091#L784-1 assume !(0 == ~T4_E~0); 8924#L789-1 assume !(0 == ~T5_E~0); 8925#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9035#L799-1 assume !(0 == ~T7_E~0); 8931#L804-1 assume !(0 == ~E_M~0); 8932#L809-1 assume !(0 == ~E_1~0); 8972#L814-1 assume !(0 == ~E_2~0); 8363#L819-1 assume !(0 == ~E_3~0); 8364#L824-1 assume !(0 == ~E_4~0); 8713#L829-1 assume !(0 == ~E_5~0); 9150#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8497#L839-1 assume !(0 == ~E_7~0); 8498#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8876#L376 assume !(1 == ~m_pc~0); 8863#L376-2 is_master_triggered_~__retres1~0#1 := 0; 8862#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9133#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8444#L955 assume !(0 != activate_threads_~tmp~1#1); 8445#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8796#L395 assume 1 == ~t1_pc~0; 8474#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8475#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8367#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8368#L963 assume !(0 != activate_threads_~tmp___0~0#1); 8880#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8881#L414 assume !(1 == ~t2_pc~0); 8500#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8501#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8699#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8700#L971 assume !(0 != activate_threads_~tmp___1~0#1); 9107#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8799#L433 assume 1 == ~t3_pc~0; 8744#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8616#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8774#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8775#L979 assume !(0 != activate_threads_~tmp___2~0#1); 8465#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8466#L452 assume !(1 == ~t4_pc~0); 8621#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8622#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8912#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8978#L987 assume !(0 != activate_threads_~tmp___3~0#1); 8654#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8655#L471 assume 1 == ~t5_pc~0; 9023#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8637#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8638#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8973#L995 assume !(0 != activate_threads_~tmp___4~0#1); 9142#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9143#L490 assume 1 == ~t6_pc~0; 9126#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8879#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8919#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8922#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 8808#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8777#L509 assume !(1 == ~t7_pc~0); 8778#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8597#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8598#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8659#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8660#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9115#L857 assume !(1 == ~M_E~0); 8451#L857-2 assume !(1 == ~T1_E~0); 8452#L862-1 assume !(1 == ~T2_E~0); 8721#L867-1 assume !(1 == ~T3_E~0); 8726#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8800#L877-1 assume !(1 == ~T5_E~0); 8999#L882-1 assume !(1 == ~T6_E~0); 9125#L887-1 assume !(1 == ~T7_E~0); 9049#L892-1 assume !(1 == ~E_M~0); 9050#L897-1 assume !(1 == ~E_1~0); 8736#L902-1 assume !(1 == ~E_2~0); 8737#L907-1 assume !(1 == ~E_3~0); 9018#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9007#L917-1 assume !(1 == ~E_5~0); 9008#L922-1 assume !(1 == ~E_6~0); 9153#L927-1 assume !(1 == ~E_7~0); 8994#L932-1 assume { :end_inline_reset_delta_events } true; 8400#L1178-2 [2021-12-15 17:20:32,424 INFO L793 eck$LassoCheckResult]: Loop: 8400#L1178-2 assume !false; 8983#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8417#L744 assume !false; 8771#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8845#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8435#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8641#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9097#L641 assume !(0 != eval_~tmp~0#1); 8911#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8535#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8536#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8797#L769-5 assume !(0 == ~T1_E~0); 8798#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8552#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8376#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8377#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8365#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8366#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8415#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8670#L809-3 assume !(0 == ~E_1~0); 8411#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8412#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9071#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9066#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8722#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8723#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9034#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9113#L376-27 assume 1 == ~m_pc~0; 9012#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8958#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8959#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9053#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9156#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9177#L395-27 assume !(1 == ~t1_pc~0); 8817#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 8724#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8725#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8950#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8804#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8805#L414-27 assume 1 == ~t2_pc~0; 9140#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9005#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9006#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8865#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8427#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8428#L433-27 assume !(1 == ~t3_pc~0); 8523#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 8810#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8811#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8600#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 8601#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9170#L452-27 assume 1 == ~t4_pc~0; 9171#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8970#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9094#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9136#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9137#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8418#L471-27 assume !(1 == ~t5_pc~0); 8419#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 8733#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9112#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9026#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8954#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8875#L490-27 assume 1 == ~t6_pc~0; 8772#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8610#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8611#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9014#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9015#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8385#L509-27 assume !(1 == ~t7_pc~0); 8386#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8776#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8901#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8892#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8893#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8907#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8908#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8946#L862-3 assume !(1 == ~T2_E~0); 9168#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8812#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8813#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8902#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8941#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8570#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8571#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9086#L902-3 assume !(1 == ~E_2~0); 8734#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8735#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8854#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8816#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8623#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8624#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8472#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8373#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9037#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8786#L1197 assume !(0 == start_simulation_~tmp~3#1); 8787#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8528#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8495#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8421#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 8422#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9083#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9084#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8399#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 8400#L1178-2 [2021-12-15 17:20:32,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,425 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2021-12-15 17:20:32,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983429490] [2021-12-15 17:20:32,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,448 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983429490] [2021-12-15 17:20:32,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983429490] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167444917] [2021-12-15 17:20:32,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,450 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,451 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 1 times [2021-12-15 17:20:32,452 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301334175] [2021-12-15 17:20:32,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,455 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,484 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,484 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301334175] [2021-12-15 17:20:32,486 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301334175] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,486 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,486 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,486 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313051504] [2021-12-15 17:20:32,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,487 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,487 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,488 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,488 INFO L87 Difference]: Start difference. First operand 830 states and 1236 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,500 INFO L93 Difference]: Finished difference Result 830 states and 1235 transitions. [2021-12-15 17:20:32,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1235 transitions. [2021-12-15 17:20:32,504 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1235 transitions. [2021-12-15 17:20:32,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-15 17:20:32,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-15 17:20:32,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1235 transitions. [2021-12-15 17:20:32,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,509 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2021-12-15 17:20:32,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1235 transitions. [2021-12-15 17:20:32,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2021-12-15 17:20:32,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1235 transitions. [2021-12-15 17:20:32,518 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2021-12-15 17:20:32,518 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2021-12-15 17:20:32,518 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:32,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1235 transitions. [2021-12-15 17:20:32,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,522 INFO L791 eck$LassoCheckResult]: Stem: 10654#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10537#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10487#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10488#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 10771#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10470#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10310#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10311#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10292#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10293#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10770#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10595#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10596#L769 assume !(0 == ~M_E~0); 10618#L769-2 assume !(0 == ~T1_E~0); 10619#L774-1 assume !(0 == ~T2_E~0); 10646#L779-1 assume !(0 == ~T3_E~0); 10758#L784-1 assume !(0 == ~T4_E~0); 10591#L789-1 assume !(0 == ~T5_E~0); 10592#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10702#L799-1 assume !(0 == ~T7_E~0); 10598#L804-1 assume !(0 == ~E_M~0); 10599#L809-1 assume !(0 == ~E_1~0); 10639#L814-1 assume !(0 == ~E_2~0); 10028#L819-1 assume !(0 == ~E_3~0); 10029#L824-1 assume !(0 == ~E_4~0); 10380#L829-1 assume !(0 == ~E_5~0); 10817#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10164#L839-1 assume !(0 == ~E_7~0); 10165#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10543#L376 assume !(1 == ~m_pc~0); 10530#L376-2 is_master_triggered_~__retres1~0#1 := 0; 10529#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10800#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10111#L955 assume !(0 != activate_threads_~tmp~1#1); 10112#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10463#L395 assume 1 == ~t1_pc~0; 10141#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10142#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10034#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10035#L963 assume !(0 != activate_threads_~tmp___0~0#1); 10547#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10548#L414 assume !(1 == ~t2_pc~0); 10167#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10168#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10366#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10367#L971 assume !(0 != activate_threads_~tmp___1~0#1); 10774#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10466#L433 assume 1 == ~t3_pc~0; 10411#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10281#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10439#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10440#L979 assume !(0 != activate_threads_~tmp___2~0#1); 10132#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10133#L452 assume !(1 == ~t4_pc~0); 10288#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10289#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10579#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10645#L987 assume !(0 != activate_threads_~tmp___3~0#1); 10321#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10322#L471 assume 1 == ~t5_pc~0; 10690#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10304#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10305#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10640#L995 assume !(0 != activate_threads_~tmp___4~0#1); 10809#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10810#L490 assume 1 == ~t6_pc~0; 10793#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10546#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10586#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10589#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 10475#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10444#L509 assume !(1 == ~t7_pc~0); 10445#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10262#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10263#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10326#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10327#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10782#L857 assume !(1 == ~M_E~0); 10118#L857-2 assume !(1 == ~T1_E~0); 10119#L862-1 assume !(1 == ~T2_E~0); 10388#L867-1 assume !(1 == ~T3_E~0); 10393#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10467#L877-1 assume !(1 == ~T5_E~0); 10666#L882-1 assume !(1 == ~T6_E~0); 10792#L887-1 assume !(1 == ~T7_E~0); 10716#L892-1 assume !(1 == ~E_M~0); 10717#L897-1 assume !(1 == ~E_1~0); 10403#L902-1 assume !(1 == ~E_2~0); 10404#L907-1 assume !(1 == ~E_3~0); 10683#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10674#L917-1 assume !(1 == ~E_5~0); 10675#L922-1 assume !(1 == ~E_6~0); 10820#L927-1 assume !(1 == ~E_7~0); 10661#L932-1 assume { :end_inline_reset_delta_events } true; 10067#L1178-2 [2021-12-15 17:20:32,523 INFO L793 eck$LassoCheckResult]: Loop: 10067#L1178-2 assume !false; 10650#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10084#L744 assume !false; 10438#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10511#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10102#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10308#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10762#L641 assume !(0 != eval_~tmp~0#1); 10578#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10202#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10203#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10464#L769-5 assume !(0 == ~T1_E~0); 10465#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10219#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10043#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10044#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10030#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10031#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10082#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10336#L809-3 assume !(0 == ~E_1~0); 10078#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10079#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10738#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10733#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10389#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10390#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10701#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10780#L376-27 assume 1 == ~m_pc~0; 10679#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10625#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10626#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10720#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10823#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10844#L395-27 assume !(1 == ~t1_pc~0); 10483#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 10391#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10392#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10617#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10471#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10472#L414-27 assume 1 == ~t2_pc~0; 10807#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10672#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10673#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10532#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10094#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10095#L433-27 assume !(1 == ~t3_pc~0); 10190#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10477#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10478#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10265#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 10266#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10837#L452-27 assume 1 == ~t4_pc~0; 10838#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10637#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10761#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10803#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10804#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10085#L471-27 assume !(1 == ~t5_pc~0); 10086#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 10400#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10779#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10693#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10621#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10542#L490-27 assume 1 == ~t6_pc~0; 10441#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10277#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10278#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10681#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10682#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10052#L509-27 assume !(1 == ~t7_pc~0); 10053#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 10443#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10568#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10559#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10560#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10574#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10575#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10615#L862-3 assume !(1 == ~T2_E~0); 10835#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10479#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10480#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10569#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10609#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10239#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10240#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10753#L902-3 assume !(1 == ~E_2~0); 10401#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10402#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10521#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10484#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10290#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10291#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10139#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10042#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10704#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10454#L1197 assume !(0 == start_simulation_~tmp~3#1); 10455#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10198#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10162#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10088#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 10089#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10750#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10751#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10066#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 10067#L1178-2 [2021-12-15 17:20:32,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2021-12-15 17:20:32,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143366909] [2021-12-15 17:20:32,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,541 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143366909] [2021-12-15 17:20:32,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143366909] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,541 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,541 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,542 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905402283] [2021-12-15 17:20:32,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,542 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 2 times [2021-12-15 17:20:32,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868980427] [2021-12-15 17:20:32,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,543 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,564 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868980427] [2021-12-15 17:20:32,564 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868980427] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,564 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,565 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,565 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036958870] [2021-12-15 17:20:32,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,565 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,565 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,566 INFO L87 Difference]: Start difference. First operand 830 states and 1235 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,578 INFO L93 Difference]: Finished difference Result 830 states and 1234 transitions. [2021-12-15 17:20:32,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1234 transitions. [2021-12-15 17:20:32,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1234 transitions. [2021-12-15 17:20:32,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-15 17:20:32,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-15 17:20:32,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1234 transitions. [2021-12-15 17:20:32,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,587 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2021-12-15 17:20:32,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1234 transitions. [2021-12-15 17:20:32,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2021-12-15 17:20:32,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1234 transitions. [2021-12-15 17:20:32,597 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2021-12-15 17:20:32,597 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2021-12-15 17:20:32,597 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:32,597 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1234 transitions. [2021-12-15 17:20:32,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2021-12-15 17:20:32,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,600 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,600 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,601 INFO L791 eck$LassoCheckResult]: Stem: 12321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12204#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12154#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12155#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 12438#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12137#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11977#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11978#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11959#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11960#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12437#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12262#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12263#L769 assume !(0 == ~M_E~0); 12285#L769-2 assume !(0 == ~T1_E~0); 12286#L774-1 assume !(0 == ~T2_E~0); 12313#L779-1 assume !(0 == ~T3_E~0); 12425#L784-1 assume !(0 == ~T4_E~0); 12258#L789-1 assume !(0 == ~T5_E~0); 12259#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12369#L799-1 assume !(0 == ~T7_E~0); 12265#L804-1 assume !(0 == ~E_M~0); 12266#L809-1 assume !(0 == ~E_1~0); 12306#L814-1 assume !(0 == ~E_2~0); 11695#L819-1 assume !(0 == ~E_3~0); 11696#L824-1 assume !(0 == ~E_4~0); 12047#L829-1 assume !(0 == ~E_5~0); 12484#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11831#L839-1 assume !(0 == ~E_7~0); 11832#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12210#L376 assume !(1 == ~m_pc~0); 12197#L376-2 is_master_triggered_~__retres1~0#1 := 0; 12196#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12467#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11778#L955 assume !(0 != activate_threads_~tmp~1#1); 11779#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12130#L395 assume 1 == ~t1_pc~0; 11808#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11809#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11701#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11702#L963 assume !(0 != activate_threads_~tmp___0~0#1); 12214#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12215#L414 assume !(1 == ~t2_pc~0); 11834#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11835#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12033#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12034#L971 assume !(0 != activate_threads_~tmp___1~0#1); 12441#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12133#L433 assume 1 == ~t3_pc~0; 12078#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11948#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12106#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12107#L979 assume !(0 != activate_threads_~tmp___2~0#1); 11799#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11800#L452 assume !(1 == ~t4_pc~0); 11955#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11956#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12246#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12312#L987 assume !(0 != activate_threads_~tmp___3~0#1); 11988#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11989#L471 assume 1 == ~t5_pc~0; 12357#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11971#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11972#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12307#L995 assume !(0 != activate_threads_~tmp___4~0#1); 12476#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12477#L490 assume 1 == ~t6_pc~0; 12460#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12213#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12253#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12256#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 12142#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12111#L509 assume !(1 == ~t7_pc~0); 12112#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11929#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11930#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11993#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11994#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12449#L857 assume !(1 == ~M_E~0); 11785#L857-2 assume !(1 == ~T1_E~0); 11786#L862-1 assume !(1 == ~T2_E~0); 12055#L867-1 assume !(1 == ~T3_E~0); 12060#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12134#L877-1 assume !(1 == ~T5_E~0); 12333#L882-1 assume !(1 == ~T6_E~0); 12459#L887-1 assume !(1 == ~T7_E~0); 12383#L892-1 assume !(1 == ~E_M~0); 12384#L897-1 assume !(1 == ~E_1~0); 12070#L902-1 assume !(1 == ~E_2~0); 12071#L907-1 assume !(1 == ~E_3~0); 12350#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12341#L917-1 assume !(1 == ~E_5~0); 12342#L922-1 assume !(1 == ~E_6~0); 12487#L927-1 assume !(1 == ~E_7~0); 12328#L932-1 assume { :end_inline_reset_delta_events } true; 11734#L1178-2 [2021-12-15 17:20:32,601 INFO L793 eck$LassoCheckResult]: Loop: 11734#L1178-2 assume !false; 12317#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11751#L744 assume !false; 12105#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12178#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11769#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11975#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12429#L641 assume !(0 != eval_~tmp~0#1); 12245#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11869#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11870#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12131#L769-5 assume !(0 == ~T1_E~0); 12132#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11886#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11710#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11711#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11697#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11698#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11749#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12003#L809-3 assume !(0 == ~E_1~0); 11745#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11746#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12405#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12400#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12056#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12057#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12368#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12447#L376-27 assume 1 == ~m_pc~0; 12346#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12292#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12293#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12387#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12490#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12511#L395-27 assume !(1 == ~t1_pc~0); 12150#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 12058#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12059#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12284#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12138#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12139#L414-27 assume 1 == ~t2_pc~0; 12474#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12339#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12340#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12199#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11761#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11762#L433-27 assume !(1 == ~t3_pc~0); 11857#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 12144#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12145#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11932#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 11933#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12504#L452-27 assume 1 == ~t4_pc~0; 12505#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12304#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12428#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12470#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12471#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11752#L471-27 assume !(1 == ~t5_pc~0); 11753#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 12067#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12446#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12360#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12288#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12209#L490-27 assume 1 == ~t6_pc~0; 12108#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11944#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11945#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12348#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12349#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11719#L509-27 assume !(1 == ~t7_pc~0); 11720#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12110#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12235#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12226#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12227#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12241#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12242#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12282#L862-3 assume !(1 == ~T2_E~0); 12502#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12146#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12147#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12236#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12276#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11906#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11907#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12420#L902-3 assume !(1 == ~E_2~0); 12068#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12069#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12188#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12151#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11957#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11958#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11806#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11709#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12371#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12121#L1197 assume !(0 == start_simulation_~tmp~3#1); 12122#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11865#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11829#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11755#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 11756#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12417#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12418#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11733#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 11734#L1178-2 [2021-12-15 17:20:32,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,601 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2021-12-15 17:20:32,601 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,602 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933074287] [2021-12-15 17:20:32,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,602 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,627 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933074287] [2021-12-15 17:20:32,627 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933074287] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,627 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,627 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,628 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680837915] [2021-12-15 17:20:32,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,628 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 3 times [2021-12-15 17:20:32,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145576419] [2021-12-15 17:20:32,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,629 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,650 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145576419] [2021-12-15 17:20:32,650 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145576419] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,650 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,650 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,650 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108153220] [2021-12-15 17:20:32,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,651 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,651 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:32,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:32,651 INFO L87 Difference]: Start difference. First operand 830 states and 1234 transitions. cyclomatic complexity: 405 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,710 INFO L93 Difference]: Finished difference Result 1499 states and 2220 transitions. [2021-12-15 17:20:32,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:32,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1499 states and 2220 transitions. [2021-12-15 17:20:32,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2021-12-15 17:20:32,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1499 states to 1499 states and 2220 transitions. [2021-12-15 17:20:32,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1499 [2021-12-15 17:20:32,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1499 [2021-12-15 17:20:32,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1499 states and 2220 transitions. [2021-12-15 17:20:32,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,725 INFO L681 BuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2021-12-15 17:20:32,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1499 states and 2220 transitions. [2021-12-15 17:20:32,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1499 to 1499. [2021-12-15 17:20:32,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 2220 transitions. [2021-12-15 17:20:32,775 INFO L704 BuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2021-12-15 17:20:32,775 INFO L587 BuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2021-12-15 17:20:32,775 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:32,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1499 states and 2220 transitions. [2021-12-15 17:20:32,779 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2021-12-15 17:20:32,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,780 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,781 INFO L791 eck$LassoCheckResult]: Stem: 14668#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14546#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14496#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14497#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 14794#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14479#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14317#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14318#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14299#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14300#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14793#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14607#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14608#L769 assume !(0 == ~M_E~0); 14630#L769-2 assume !(0 == ~T1_E~0); 14631#L774-1 assume !(0 == ~T2_E~0); 14659#L779-1 assume !(0 == ~T3_E~0); 14779#L784-1 assume !(0 == ~T4_E~0); 14603#L789-1 assume !(0 == ~T5_E~0); 14604#L794-1 assume !(0 == ~T6_E~0); 14720#L799-1 assume !(0 == ~T7_E~0); 14610#L804-1 assume !(0 == ~E_M~0); 14611#L809-1 assume !(0 == ~E_1~0); 14652#L814-1 assume !(0 == ~E_2~0); 14034#L819-1 assume !(0 == ~E_3~0); 14035#L824-1 assume !(0 == ~E_4~0); 14389#L829-1 assume !(0 == ~E_5~0); 14855#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14170#L839-1 assume !(0 == ~E_7~0); 14171#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14552#L376 assume !(1 == ~m_pc~0); 14539#L376-2 is_master_triggered_~__retres1~0#1 := 0; 14538#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14832#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14117#L955 assume !(0 != activate_threads_~tmp~1#1); 14118#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14472#L395 assume 1 == ~t1_pc~0; 14147#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14148#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14040#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14041#L963 assume !(0 != activate_threads_~tmp___0~0#1); 14556#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14557#L414 assume !(1 == ~t2_pc~0); 14173#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14174#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14374#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14375#L971 assume !(0 != activate_threads_~tmp___1~0#1); 14797#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14475#L433 assume 1 == ~t3_pc~0; 14420#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14288#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14448#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14449#L979 assume !(0 != activate_threads_~tmp___2~0#1); 14138#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14139#L452 assume !(1 == ~t4_pc~0); 14295#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14296#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14590#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14658#L987 assume !(0 != activate_threads_~tmp___3~0#1); 14329#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14330#L471 assume 1 == ~t5_pc~0; 14705#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14311#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14312#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14653#L995 assume !(0 != activate_threads_~tmp___4~0#1); 14843#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14844#L490 assume 1 == ~t6_pc~0; 14822#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14555#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14597#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14600#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 14484#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14453#L509 assume !(1 == ~t7_pc~0); 14454#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14268#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14269#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14334#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14335#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14805#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 14806#L857-2 assume !(1 == ~T1_E~0); 14969#L862-1 assume !(1 == ~T2_E~0); 14967#L867-1 assume !(1 == ~T3_E~0); 14965#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14964#L877-1 assume !(1 == ~T5_E~0); 14961#L882-1 assume !(1 == ~T6_E~0); 14820#L887-1 assume !(1 == ~T7_E~0); 14958#L892-1 assume !(1 == ~E_M~0); 14956#L897-1 assume !(1 == ~E_1~0); 14954#L902-1 assume !(1 == ~E_2~0); 14952#L907-1 assume !(1 == ~E_3~0); 14949#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14921#L917-1 assume !(1 == ~E_5~0); 14918#L922-1 assume !(1 == ~E_6~0); 14917#L927-1 assume !(1 == ~E_7~0); 14911#L932-1 assume { :end_inline_reset_delta_events } true; 14905#L1178-2 [2021-12-15 17:20:32,781 INFO L793 eck$LassoCheckResult]: Loop: 14905#L1178-2 assume !false; 14663#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14090#L744 assume !false; 14447#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14520#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14108#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14315#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14783#L641 assume !(0 != eval_~tmp~0#1); 14589#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14208#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14209#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14888#L769-5 assume !(0 == ~T1_E~0); 15492#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15491#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15490#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15489#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15488#L794-3 assume !(0 == ~T6_E~0); 15487#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15486#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15485#L809-3 assume !(0 == ~E_1~0); 15484#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15483#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15482#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15481#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15480#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15479#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15478#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15477#L376-27 assume !(1 == ~m_pc~0); 15475#L376-29 is_master_triggered_~__retres1~0#1 := 0; 15474#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15473#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15472#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15471#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15470#L395-27 assume 1 == ~t1_pc~0; 15468#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15467#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15466#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15465#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15464#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15463#L414-27 assume !(1 == ~t2_pc~0); 15461#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15460#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15459#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15458#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15457#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15456#L433-27 assume 1 == ~t3_pc~0; 15454#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15453#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15452#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15451#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 15450#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15449#L452-27 assume 1 == ~t4_pc~0; 15447#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15446#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15445#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15444#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15443#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15442#L471-27 assume 1 == ~t5_pc~0; 15440#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15439#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15438#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15437#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15436#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15435#L490-27 assume 1 == ~t6_pc~0; 15433#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15432#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15431#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15430#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15429#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15428#L509-27 assume !(1 == ~t7_pc~0); 15426#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 15425#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15424#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15423#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15292#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15291#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14585#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15290#L862-3 assume !(1 == ~T2_E~0); 15278#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14488#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14489#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14579#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14621#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14245#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14246#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14774#L902-3 assume !(1 == ~E_2~0); 14410#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14411#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14530#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14493#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14297#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14298#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14145#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14048#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14722#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 14463#L1197 assume !(0 == start_simulation_~tmp~3#1); 14464#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14204#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14168#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14094#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 14095#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14770#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14771#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 14912#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 14905#L1178-2 [2021-12-15 17:20:32,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,782 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2021-12-15 17:20:32,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702770965] [2021-12-15 17:20:32,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,782 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,800 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702770965] [2021-12-15 17:20:32,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702770965] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,801 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059290672] [2021-12-15 17:20:32,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,801 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,801 INFO L85 PathProgramCache]: Analyzing trace with hash 587005287, now seen corresponding path program 1 times [2021-12-15 17:20:32,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568376913] [2021-12-15 17:20:32,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,802 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,821 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,821 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568376913] [2021-12-15 17:20:32,821 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568376913] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,821 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,821 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,821 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301132045] [2021-12-15 17:20:32,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,822 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,822 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:32,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:32,823 INFO L87 Difference]: Start difference. First operand 1499 states and 2220 transitions. cyclomatic complexity: 723 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,914 INFO L93 Difference]: Finished difference Result 2703 states and 3991 transitions. [2021-12-15 17:20:32,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:32,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2703 states and 3991 transitions. [2021-12-15 17:20:32,928 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2021-12-15 17:20:32,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2703 states to 2703 states and 3991 transitions. [2021-12-15 17:20:32,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2703 [2021-12-15 17:20:32,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2703 [2021-12-15 17:20:32,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2703 states and 3991 transitions. [2021-12-15 17:20:32,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,944 INFO L681 BuchiCegarLoop]: Abstraction has 2703 states and 3991 transitions. [2021-12-15 17:20:32,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2703 states and 3991 transitions. [2021-12-15 17:20:32,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2703 to 2701. [2021-12-15 17:20:32,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2701 states to 2701 states and 3989 transitions. [2021-12-15 17:20:32,979 INFO L704 BuchiCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2021-12-15 17:20:32,979 INFO L587 BuchiCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2021-12-15 17:20:32,979 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:32,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2701 states and 3989 transitions. [2021-12-15 17:20:32,985 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2021-12-15 17:20:32,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,986 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,986 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,986 INFO L791 eck$LassoCheckResult]: Stem: 18893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18894#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 18771#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18715#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18716#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 19026#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18697#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18533#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18534#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18515#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18516#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19025#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18833#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18834#L769 assume !(0 == ~M_E~0); 18857#L769-2 assume !(0 == ~T1_E~0); 18858#L774-1 assume !(0 == ~T2_E~0); 18884#L779-1 assume !(0 == ~T3_E~0); 19013#L784-1 assume !(0 == ~T4_E~0); 18828#L789-1 assume !(0 == ~T5_E~0); 18829#L794-1 assume !(0 == ~T6_E~0); 18947#L799-1 assume !(0 == ~T7_E~0); 18835#L804-1 assume !(0 == ~E_M~0); 18836#L809-1 assume !(0 == ~E_1~0); 18877#L814-1 assume !(0 == ~E_2~0); 18248#L819-1 assume !(0 == ~E_3~0); 18249#L824-1 assume !(0 == ~E_4~0); 18603#L829-1 assume !(0 == ~E_5~0); 19087#L834-1 assume !(0 == ~E_6~0); 18385#L839-1 assume !(0 == ~E_7~0); 18386#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18778#L376 assume !(1 == ~m_pc~0); 18765#L376-2 is_master_triggered_~__retres1~0#1 := 0; 18764#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19068#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18332#L955 assume !(0 != activate_threads_~tmp~1#1); 18333#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18689#L395 assume 1 == ~t1_pc~0; 18362#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18363#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18254#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18255#L963 assume !(0 != activate_threads_~tmp___0~0#1); 18783#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18784#L414 assume !(1 == ~t2_pc~0); 18388#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18389#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18589#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18590#L971 assume !(0 != activate_threads_~tmp___1~0#1); 19031#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18692#L433 assume 1 == ~t3_pc~0; 18636#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18506#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18666#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18667#L979 assume !(0 != activate_threads_~tmp___2~0#1); 18351#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18352#L452 assume !(1 == ~t4_pc~0); 18511#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18512#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18816#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18883#L987 assume !(0 != activate_threads_~tmp___3~0#1); 18544#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18545#L471 assume 1 == ~t5_pc~0; 18934#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18527#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18528#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18878#L995 assume !(0 != activate_threads_~tmp___4~0#1); 19078#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19079#L490 assume 1 == ~t6_pc~0; 19057#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18781#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18822#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18825#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 18704#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18669#L509 assume !(1 == ~t7_pc~0); 18670#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18490#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18491#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18549#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18550#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19041#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 19042#L857-2 assume !(1 == ~T1_E~0); 18611#L862-1 assume !(1 == ~T2_E~0); 18612#L867-1 assume !(1 == ~T3_E~0); 18693#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18694#L877-1 assume !(1 == ~T5_E~0); 19054#L882-1 assume !(1 == ~T6_E~0); 19055#L887-1 assume !(1 == ~T7_E~0); 18962#L892-1 assume !(1 == ~E_M~0); 18963#L897-1 assume !(1 == ~E_1~0); 18630#L902-1 assume !(1 == ~E_2~0); 18631#L907-1 assume !(1 == ~E_3~0); 19222#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19193#L917-1 assume !(1 == ~E_5~0); 19191#L922-1 assume !(1 == ~E_6~0); 19178#L927-1 assume !(1 == ~E_7~0); 19170#L932-1 assume { :end_inline_reset_delta_events } true; 19164#L1178-2 [2021-12-15 17:20:32,987 INFO L793 eck$LassoCheckResult]: Loop: 19164#L1178-2 assume !false; 19159#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19158#L744 assume !false; 19157#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19156#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19148#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19147#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19145#L641 assume !(0 != eval_~tmp~0#1); 19144#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19143#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19141#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19142#L769-5 assume !(0 == ~T1_E~0); 19972#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19970#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19949#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19939#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19931#L794-3 assume !(0 == ~T6_E~0); 19924#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19921#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19918#L809-3 assume !(0 == ~E_1~0); 19908#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19905#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19902#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19897#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19892#L834-3 assume !(0 == ~E_6~0); 19888#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19884#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19880#L376-27 assume !(1 == ~m_pc~0); 19875#L376-29 is_master_triggered_~__retres1~0#1 := 0; 19871#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19866#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19861#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19857#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19853#L395-27 assume 1 == ~t1_pc~0; 19848#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19844#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18997#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18854#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18855#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19828#L414-27 assume 1 == ~t2_pc~0; 19824#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19819#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19741#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19738#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19736#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19734#L433-27 assume 1 == ~t3_pc~0; 19731#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19729#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19727#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19725#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 19723#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19720#L452-27 assume 1 == ~t4_pc~0; 19717#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19715#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19713#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19711#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19709#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19706#L471-27 assume 1 == ~t5_pc~0; 19694#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19692#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19689#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19687#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19685#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19683#L490-27 assume 1 == ~t6_pc~0; 19677#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19675#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19673#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19671#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19669#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19667#L509-27 assume !(1 == ~t7_pc~0); 19658#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19612#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19609#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19607#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19605#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19603#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18810#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19600#L862-3 assume !(1 == ~T2_E~0); 19597#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19533#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19531#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19529#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19526#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19524#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19516#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19501#L902-3 assume !(1 == ~E_2~0); 19492#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19485#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19471#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19469#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19466#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19404#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19380#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19370#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19350#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 19313#L1197 assume !(0 == start_simulation_~tmp~3#1); 19123#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19276#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19266#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19229#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 19228#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19195#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19179#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19171#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 19164#L1178-2 [2021-12-15 17:20:32,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,987 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2021-12-15 17:20:32,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74374455] [2021-12-15 17:20:32,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,988 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,009 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,009 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74374455] [2021-12-15 17:20:33,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [74374455] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,010 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:33,010 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2092208626] [2021-12-15 17:20:33,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,011 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,011 INFO L85 PathProgramCache]: Analyzing trace with hash -933139996, now seen corresponding path program 1 times [2021-12-15 17:20:33,011 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261203385] [2021-12-15 17:20:33,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,043 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261203385] [2021-12-15 17:20:33,043 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261203385] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,043 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,043 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262131262] [2021-12-15 17:20:33,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,044 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,044 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,045 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:33,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:33,045 INFO L87 Difference]: Start difference. First operand 2701 states and 3989 transitions. cyclomatic complexity: 1292 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,105 INFO L93 Difference]: Finished difference Result 4999 states and 7328 transitions. [2021-12-15 17:20:33,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:33,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4999 states and 7328 transitions. [2021-12-15 17:20:33,124 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4865 [2021-12-15 17:20:33,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4999 states to 4999 states and 7328 transitions. [2021-12-15 17:20:33,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4999 [2021-12-15 17:20:33,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4999 [2021-12-15 17:20:33,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4999 states and 7328 transitions. [2021-12-15 17:20:33,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,151 INFO L681 BuchiCegarLoop]: Abstraction has 4999 states and 7328 transitions. [2021-12-15 17:20:33,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4999 states and 7328 transitions. [2021-12-15 17:20:33,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4999 to 4991. [2021-12-15 17:20:33,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4991 states, 4991 states have (on average 1.466639951913444) internal successors, (7320), 4990 states have internal predecessors, (7320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4991 states to 4991 states and 7320 transitions. [2021-12-15 17:20:33,262 INFO L704 BuchiCegarLoop]: Abstraction has 4991 states and 7320 transitions. [2021-12-15 17:20:33,262 INFO L587 BuchiCegarLoop]: Abstraction has 4991 states and 7320 transitions. [2021-12-15 17:20:33,262 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:33,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4991 states and 7320 transitions. [2021-12-15 17:20:33,273 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4857 [2021-12-15 17:20:33,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,275 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,275 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,275 INFO L791 eck$LassoCheckResult]: Stem: 26602#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 26473#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26417#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26418#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 26743#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26400#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26237#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26238#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26218#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26219#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26742#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26536#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26537#L769 assume !(0 == ~M_E~0); 26562#L769-2 assume !(0 == ~T1_E~0); 26563#L774-1 assume !(0 == ~T2_E~0); 26594#L779-1 assume !(0 == ~T3_E~0); 26725#L784-1 assume !(0 == ~T4_E~0); 26532#L789-1 assume !(0 == ~T5_E~0); 26533#L794-1 assume !(0 == ~T6_E~0); 26656#L799-1 assume !(0 == ~T7_E~0); 26540#L804-1 assume !(0 == ~E_M~0); 26541#L809-1 assume !(0 == ~E_1~0); 26585#L814-1 assume !(0 == ~E_2~0); 25955#L819-1 assume !(0 == ~E_3~0); 25956#L824-1 assume !(0 == ~E_4~0); 26307#L829-1 assume !(0 == ~E_5~0); 26820#L834-1 assume !(0 == ~E_6~0); 26088#L839-1 assume !(0 == ~E_7~0); 26089#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26480#L376 assume !(1 == ~m_pc~0); 26464#L376-2 is_master_triggered_~__retres1~0#1 := 0; 26463#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26788#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26038#L955 assume !(0 != activate_threads_~tmp~1#1); 26039#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26393#L395 assume !(1 == ~t1_pc~0); 26564#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26710#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25961#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25962#L963 assume !(0 != activate_threads_~tmp___0~0#1); 26486#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26487#L414 assume !(1 == ~t2_pc~0); 26091#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26092#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26293#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26294#L971 assume !(0 != activate_threads_~tmp___1~0#1); 26748#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26396#L433 assume 1 == ~t3_pc~0; 26339#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26209#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26371#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26372#L979 assume !(0 != activate_threads_~tmp___2~0#1); 26058#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26059#L452 assume !(1 == ~t4_pc~0); 26214#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26215#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26519#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26593#L987 assume !(0 != activate_threads_~tmp___3~0#1); 26249#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26250#L471 assume 1 == ~t5_pc~0; 26641#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26231#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26232#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26586#L995 assume !(0 != activate_threads_~tmp___4~0#1); 26809#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26810#L490 assume 1 == ~t6_pc~0; 26777#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26484#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26526#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26529#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 26407#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26374#L509 assume !(1 == ~t7_pc~0); 26375#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26190#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26191#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26254#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26255#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26758#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 26043#L857-2 assume !(1 == ~T1_E~0); 26044#L862-1 assume !(1 == ~T2_E~0); 26316#L867-1 assume !(1 == ~T3_E~0); 26321#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26397#L877-1 assume !(1 == ~T5_E~0); 26615#L882-1 assume !(1 == ~T6_E~0); 26775#L887-1 assume !(1 == ~T7_E~0); 26673#L892-1 assume !(1 == ~E_M~0); 26674#L897-1 assume !(1 == ~E_1~0); 28112#L902-1 assume !(1 == ~E_2~0); 28103#L907-1 assume !(1 == ~E_3~0); 28101#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28099#L917-1 assume !(1 == ~E_5~0); 28097#L922-1 assume !(1 == ~E_6~0); 28094#L927-1 assume !(1 == ~E_7~0); 28091#L932-1 assume { :end_inline_reset_delta_events } true; 28090#L1178-2 [2021-12-15 17:20:33,275 INFO L793 eck$LassoCheckResult]: Loop: 28090#L1178-2 assume !false; 28081#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28079#L744 assume !false; 28077#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28075#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28066#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28065#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28064#L641 assume !(0 != eval_~tmp~0#1); 26518#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26126#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26127#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26807#L769-5 assume !(0 == ~T1_E~0); 27351#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27350#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27349#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27348#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27347#L794-3 assume !(0 == ~T6_E~0); 27346#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27345#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27344#L809-3 assume !(0 == ~E_1~0); 27343#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27342#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27341#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27340#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27339#L834-3 assume !(0 == ~E_6~0); 27337#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27338#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30809#L376-27 assume !(1 == ~m_pc~0); 27330#L376-29 is_master_triggered_~__retres1~0#1 := 0; 27331#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30801#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30799#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27319#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27320#L395-27 assume !(1 == ~t1_pc~0); 30794#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 27311#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27308#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27309#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30773#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30772#L414-27 assume !(1 == ~t2_pc~0); 30770#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 30769#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30768#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30767#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30766#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30765#L433-27 assume 1 == ~t3_pc~0; 30763#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30762#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30760#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27278#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 27276#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27272#L452-27 assume 1 == ~t4_pc~0; 27273#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27265#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27263#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27259#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27260#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30734#L471-27 assume 1 == ~t5_pc~0; 30730#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30720#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29136#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29134#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29132#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29129#L490-27 assume 1 == ~t6_pc~0; 29126#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29124#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29122#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29120#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29119#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29118#L509-27 assume !(1 == ~t7_pc~0); 29114#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 29045#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29042#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29040#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29038#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29036#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27092#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28999#L862-3 assume !(1 == ~T2_E~0); 28996#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28994#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28992#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28990#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28965#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28962#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28960#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28945#L902-3 assume !(1 == ~E_2~0); 28927#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28925#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28923#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28922#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28920#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28919#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28900#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28894#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28872#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 28864#L1197 assume !(0 == start_simulation_~tmp~3#1); 26871#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28108#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28102#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28100#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 28098#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28095#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28093#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 28092#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 28090#L1178-2 [2021-12-15 17:20:33,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,276 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2021-12-15 17:20:33,276 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748627101] [2021-12-15 17:20:33,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,308 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748627101] [2021-12-15 17:20:33,308 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748627101] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,308 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283020359] [2021-12-15 17:20:33,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,308 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,309 INFO L85 PathProgramCache]: Analyzing trace with hash 1784148902, now seen corresponding path program 1 times [2021-12-15 17:20:33,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888383350] [2021-12-15 17:20:33,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,309 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,331 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888383350] [2021-12-15 17:20:33,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888383350] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,331 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,331 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,331 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540072139] [2021-12-15 17:20:33,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,332 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,332 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:33,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:33,333 INFO L87 Difference]: Start difference. First operand 4991 states and 7320 transitions. cyclomatic complexity: 2337 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,537 INFO L93 Difference]: Finished difference Result 11637 states and 16909 transitions. [2021-12-15 17:20:33,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:33,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11637 states and 16909 transitions. [2021-12-15 17:20:33,581 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11472 [2021-12-15 17:20:33,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11637 states to 11637 states and 16909 transitions. [2021-12-15 17:20:33,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11637 [2021-12-15 17:20:33,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11637 [2021-12-15 17:20:33,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11637 states and 16909 transitions. [2021-12-15 17:20:33,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,691 INFO L681 BuchiCegarLoop]: Abstraction has 11637 states and 16909 transitions. [2021-12-15 17:20:33,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11637 states and 16909 transitions. [2021-12-15 17:20:33,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11637 to 9309. [2021-12-15 17:20:33,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9309 states, 9309 states have (on average 1.4588033086260608) internal successors, (13580), 9308 states have internal predecessors, (13580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9309 states to 9309 states and 13580 transitions. [2021-12-15 17:20:33,844 INFO L704 BuchiCegarLoop]: Abstraction has 9309 states and 13580 transitions. [2021-12-15 17:20:33,844 INFO L587 BuchiCegarLoop]: Abstraction has 9309 states and 13580 transitions. [2021-12-15 17:20:33,844 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:33,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9309 states and 13580 transitions. [2021-12-15 17:20:33,863 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9172 [2021-12-15 17:20:33,863 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,864 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,864 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,864 INFO L791 eck$LassoCheckResult]: Stem: 43243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 43244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 43112#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43061#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43062#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 43376#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43039#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42873#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42874#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42855#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42856#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43375#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43178#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43179#L769 assume !(0 == ~M_E~0); 43201#L769-2 assume !(0 == ~T1_E~0); 43202#L774-1 assume !(0 == ~T2_E~0); 43234#L779-1 assume !(0 == ~T3_E~0); 43359#L784-1 assume !(0 == ~T4_E~0); 43172#L789-1 assume !(0 == ~T5_E~0); 43173#L794-1 assume !(0 == ~T6_E~0); 43293#L799-1 assume !(0 == ~T7_E~0); 43180#L804-1 assume !(0 == ~E_M~0); 43181#L809-1 assume !(0 == ~E_1~0); 43223#L814-1 assume !(0 == ~E_2~0); 42595#L819-1 assume !(0 == ~E_3~0); 42596#L824-1 assume !(0 == ~E_4~0); 42944#L829-1 assume !(0 == ~E_5~0); 43440#L834-1 assume !(0 == ~E_6~0); 42723#L839-1 assume !(0 == ~E_7~0); 42724#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43118#L376 assume !(1 == ~m_pc~0); 43108#L376-2 is_master_triggered_~__retres1~0#1 := 0; 43107#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43417#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42676#L955 assume !(0 != activate_threads_~tmp~1#1); 42677#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43031#L395 assume !(1 == ~t1_pc~0); 43203#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43348#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42599#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42600#L963 assume !(0 != activate_threads_~tmp___0~0#1); 43125#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43126#L414 assume !(1 == ~t2_pc~0); 42726#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42727#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42930#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42931#L971 assume !(0 != activate_threads_~tmp___1~0#1); 43381#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43034#L433 assume !(1 == ~t3_pc~0); 42845#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42846#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43009#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43010#L979 assume !(0 != activate_threads_~tmp___2~0#1); 42694#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42695#L452 assume !(1 == ~t4_pc~0); 42851#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 42852#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43159#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43233#L987 assume !(0 != activate_threads_~tmp___3~0#1); 42884#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42885#L471 assume 1 == ~t5_pc~0; 43281#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42867#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42868#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43224#L995 assume !(0 != activate_threads_~tmp___4~0#1); 43432#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43433#L490 assume 1 == ~t6_pc~0; 43408#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43122#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43167#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43170#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 43048#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43012#L509 assume !(1 == ~t7_pc~0); 43013#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 42829#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42830#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42889#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42890#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43391#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 43392#L857-2 assume !(1 == ~T1_E~0); 42954#L862-1 assume !(1 == ~T2_E~0); 42955#L867-1 assume !(1 == ~T3_E~0); 43035#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43036#L877-1 assume !(1 == ~T5_E~0); 43405#L882-1 assume !(1 == ~T6_E~0); 43406#L887-1 assume !(1 == ~T7_E~0); 43309#L892-1 assume !(1 == ~E_M~0); 43310#L897-1 assume !(1 == ~E_1~0); 42974#L902-1 assume !(1 == ~E_2~0); 42975#L907-1 assume !(1 == ~E_3~0); 43275#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43276#L917-1 assume !(1 == ~E_5~0); 43444#L922-1 assume !(1 == ~E_6~0); 43445#L927-1 assume !(1 == ~E_7~0); 43506#L932-1 assume { :end_inline_reset_delta_events } true; 51728#L1178-2 [2021-12-15 17:20:33,865 INFO L793 eck$LassoCheckResult]: Loop: 51728#L1178-2 assume !false; 51259#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51253#L744 assume !false; 48328#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 47071#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 47062#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 47060#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 47055#L641 assume !(0 != eval_~tmp~0#1); 43157#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42760#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42761#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 43032#L769-5 assume !(0 == ~T1_E~0); 43033#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42777#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42606#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42607#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42591#L794-3 assume !(0 == ~T6_E~0); 42592#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42646#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42899#L809-3 assume !(0 == ~E_1~0); 42642#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42643#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43336#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43331#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42958#L834-3 assume !(0 == ~E_6~0); 42959#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43292#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43386#L376-27 assume 1 == ~m_pc~0; 43269#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43211#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43212#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43315#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43450#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43512#L395-27 assume !(1 == ~t1_pc~0); 43053#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 42956#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42957#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43199#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43040#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43041#L414-27 assume 1 == ~t2_pc~0; 43430#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43262#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43263#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43104#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42656#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42657#L433-27 assume !(1 == ~t3_pc~0); 42749#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 43046#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43047#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42825#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 42826#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43485#L452-27 assume !(1 == ~t4_pc~0); 43220#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 43221#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43364#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43423#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43424#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42647#L471-27 assume !(1 == ~t5_pc~0); 42648#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 42969#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43385#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43284#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43204#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43117#L490-27 assume !(1 == ~t6_pc~0); 43008#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 42839#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42840#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43271#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43272#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42615#L509-27 assume !(1 == ~t7_pc~0); 42616#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 43011#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43147#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43138#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43139#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43153#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43154#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43197#L862-3 assume !(1 == ~T2_E~0); 43478#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43049#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43050#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43148#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 43191#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42799#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 42800#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43354#L902-3 assume !(1 == ~E_2~0); 42970#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42971#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43096#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43378#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42853#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42854#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 42701#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 42605#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43295#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 43022#L1197 assume !(0 == start_simulation_~tmp~3#1); 43023#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43339#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 51748#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 51746#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 51743#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51741#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51739#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 51729#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 51728#L1178-2 [2021-12-15 17:20:33,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2021-12-15 17:20:33,925 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703863887] [2021-12-15 17:20:33,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,925 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703863887] [2021-12-15 17:20:33,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703863887] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,952 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,952 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,952 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838964689] [2021-12-15 17:20:33,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,952 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,953 INFO L85 PathProgramCache]: Analyzing trace with hash -434906328, now seen corresponding path program 1 times [2021-12-15 17:20:33,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227216812] [2021-12-15 17:20:33,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,975 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227216812] [2021-12-15 17:20:33,975 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227216812] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,975 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,976 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,976 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779870267] [2021-12-15 17:20:33,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,977 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,977 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:33,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:33,978 INFO L87 Difference]: Start difference. First operand 9309 states and 13580 transitions. cyclomatic complexity: 4279 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,160 INFO L93 Difference]: Finished difference Result 22087 states and 31924 transitions. [2021-12-15 17:20:34,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:34,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22087 states and 31924 transitions. [2021-12-15 17:20:34,256 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21887 [2021-12-15 17:20:34,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22087 states to 22087 states and 31924 transitions. [2021-12-15 17:20:34,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22087 [2021-12-15 17:20:34,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22087 [2021-12-15 17:20:34,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22087 states and 31924 transitions. [2021-12-15 17:20:34,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,462 INFO L681 BuchiCegarLoop]: Abstraction has 22087 states and 31924 transitions. [2021-12-15 17:20:34,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22087 states and 31924 transitions. [2021-12-15 17:20:34,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22087 to 17868. [2021-12-15 17:20:34,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17868 states, 17868 states have (on average 1.4500223863890755) internal successors, (25909), 17867 states have internal predecessors, (25909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17868 states to 17868 states and 25909 transitions. [2021-12-15 17:20:34,789 INFO L704 BuchiCegarLoop]: Abstraction has 17868 states and 25909 transitions. [2021-12-15 17:20:34,789 INFO L587 BuchiCegarLoop]: Abstraction has 17868 states and 25909 transitions. [2021-12-15 17:20:34,789 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:34,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17868 states and 25909 transitions. [2021-12-15 17:20:34,859 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17724 [2021-12-15 17:20:34,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,861 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,861 INFO L791 eck$LassoCheckResult]: Stem: 74669#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 74670#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 74530#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74466#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74467#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 74820#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74448#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74277#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74278#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74259#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74260#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74818#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74601#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74602#L769 assume !(0 == ~M_E~0); 74626#L769-2 assume !(0 == ~T1_E~0); 74627#L774-1 assume !(0 == ~T2_E~0); 74661#L779-1 assume !(0 == ~T3_E~0); 74802#L784-1 assume !(0 == ~T4_E~0); 74596#L789-1 assume !(0 == ~T5_E~0); 74597#L794-1 assume !(0 == ~T6_E~0); 74725#L799-1 assume !(0 == ~T7_E~0); 74604#L804-1 assume !(0 == ~E_M~0); 74605#L809-1 assume !(0 == ~E_1~0); 74650#L814-1 assume !(0 == ~E_2~0); 74001#L819-1 assume !(0 == ~E_3~0); 74002#L824-1 assume !(0 == ~E_4~0); 74346#L829-1 assume !(0 == ~E_5~0); 74889#L834-1 assume !(0 == ~E_6~0); 74126#L839-1 assume !(0 == ~E_7~0); 74127#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74537#L376 assume !(1 == ~m_pc~0); 74523#L376-2 is_master_triggered_~__retres1~0#1 := 0; 74522#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74865#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 74079#L955 assume !(0 != activate_threads_~tmp~1#1); 74080#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74439#L395 assume !(1 == ~t1_pc~0); 74628#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74791#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74005#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 74006#L963 assume !(0 != activate_threads_~tmp___0~0#1); 74545#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74546#L414 assume !(1 == ~t2_pc~0); 74129#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74130#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74332#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74333#L971 assume !(0 != activate_threads_~tmp___1~0#1); 74824#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74443#L433 assume !(1 == ~t3_pc~0); 74249#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74250#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74412#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 74413#L979 assume !(0 != activate_threads_~tmp___2~0#1); 74097#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74098#L452 assume !(1 == ~t4_pc~0); 74255#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74256#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74581#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74660#L987 assume !(0 != activate_threads_~tmp___3~0#1); 74289#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74290#L471 assume !(1 == ~t5_pc~0); 74712#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 74271#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74272#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 74651#L995 assume !(0 != activate_threads_~tmp___4~0#1); 74879#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74880#L490 assume 1 == ~t6_pc~0; 74853#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74541#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74589#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74593#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 74456#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74418#L509 assume !(1 == ~t7_pc~0); 74419#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 74230#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74231#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74294#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 74295#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74833#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 74834#L857-2 assume !(1 == ~T1_E~0); 74356#L862-1 assume !(1 == ~T2_E~0); 74357#L867-1 assume !(1 == ~T3_E~0); 74444#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74445#L877-1 assume !(1 == ~T5_E~0); 74850#L882-1 assume !(1 == ~T6_E~0); 74851#L887-1 assume !(1 == ~T7_E~0); 86950#L892-1 assume !(1 == ~E_M~0); 86930#L897-1 assume !(1 == ~E_1~0); 86928#L902-1 assume !(1 == ~E_2~0); 86926#L907-1 assume !(1 == ~E_3~0); 86924#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 74692#L917-1 assume !(1 == ~E_5~0); 74693#L922-1 assume !(1 == ~E_6~0); 86882#L927-1 assume !(1 == ~E_7~0); 86880#L932-1 assume { :end_inline_reset_delta_events } true; 86870#L1178-2 [2021-12-15 17:20:34,861 INFO L793 eck$LassoCheckResult]: Loop: 86870#L1178-2 assume !false; 86861#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86857#L744 assume !false; 86852#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 86848#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 86837#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 86832#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86826#L641 assume !(0 != eval_~tmp~0#1); 86827#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 91745#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 91744#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 91743#L769-5 assume !(0 == ~T1_E~0); 91742#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 91741#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 91740#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91739#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 91738#L794-3 assume !(0 == ~T6_E~0); 91737#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 91736#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 91735#L809-3 assume !(0 == ~E_1~0); 91734#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 91733#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 91732#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 91731#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91730#L834-3 assume !(0 == ~E_6~0); 91729#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 91728#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91727#L376-27 assume !(1 == ~m_pc~0); 91725#L376-29 is_master_triggered_~__retres1~0#1 := 0; 91724#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91723#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91722#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91721#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91720#L395-27 assume !(1 == ~t1_pc~0); 91703#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 91702#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74786#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 74624#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74449#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74450#L414-27 assume !(1 == ~t2_pc~0); 74877#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 74690#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74691#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91339#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 91338#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88126#L433-27 assume !(1 == ~t3_pc~0); 88092#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 88089#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88087#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88085#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 88083#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88081#L452-27 assume !(1 == ~t4_pc~0); 88079#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 88077#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88075#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88073#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88071#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88069#L471-27 assume !(1 == ~t5_pc~0); 80378#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 88065#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88063#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88061#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88059#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88057#L490-27 assume 1 == ~t6_pc~0; 88051#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 88048#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88046#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88044#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88042#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88040#L509-27 assume !(1 == ~t7_pc~0); 88037#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 88034#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88032#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87163#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 87157#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87151#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 87143#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87137#L862-3 assume !(1 == ~T2_E~0); 87131#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87124#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87118#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87112#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87102#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87096#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87088#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87082#L902-3 assume !(1 == ~E_2~0); 87077#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87071#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87065#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87059#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 87052#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87049#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 86993#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 86983#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 86977#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 86971#L1197 assume !(0 == start_simulation_~tmp~3#1); 86967#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 86940#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 86934#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 86932#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 86922#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86918#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86907#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 86881#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 86870#L1178-2 [2021-12-15 17:20:34,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,862 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2021-12-15 17:20:34,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1270810250] [2021-12-15 17:20:34,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,862 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,920 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1270810250] [2021-12-15 17:20:34,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1270810250] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,920 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687494741] [2021-12-15 17:20:34,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,921 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:34,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,922 INFO L85 PathProgramCache]: Analyzing trace with hash -1414402583, now seen corresponding path program 1 times [2021-12-15 17:20:34,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81488177] [2021-12-15 17:20:34,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,922 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,959 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81488177] [2021-12-15 17:20:34,959 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81488177] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,960 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,960 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,960 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10930700] [2021-12-15 17:20:34,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,961 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,961 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:34,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:34,961 INFO L87 Difference]: Start difference. First operand 17868 states and 25909 transitions. cyclomatic complexity: 8049 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,265 INFO L93 Difference]: Finished difference Result 41325 states and 59492 transitions. [2021-12-15 17:20:35,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:35,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41325 states and 59492 transitions. [2021-12-15 17:20:35,580 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 41054 [2021-12-15 17:20:35,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41325 states to 41325 states and 59492 transitions. [2021-12-15 17:20:35,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41325 [2021-12-15 17:20:35,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41325 [2021-12-15 17:20:35,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41325 states and 59492 transitions. [2021-12-15 17:20:35,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,822 INFO L681 BuchiCegarLoop]: Abstraction has 41325 states and 59492 transitions. [2021-12-15 17:20:35,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41325 states and 59492 transitions. [2021-12-15 17:20:36,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41325 to 33495. [2021-12-15 17:20:36,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33495 states, 33495 states have (on average 1.444454396178534) internal successors, (48382), 33494 states have internal predecessors, (48382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33495 states to 33495 states and 48382 transitions. [2021-12-15 17:20:36,364 INFO L704 BuchiCegarLoop]: Abstraction has 33495 states and 48382 transitions. [2021-12-15 17:20:36,364 INFO L587 BuchiCegarLoop]: Abstraction has 33495 states and 48382 transitions. [2021-12-15 17:20:36,364 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:36,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33495 states and 48382 transitions. [2021-12-15 17:20:36,454 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 33336 [2021-12-15 17:20:36,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,457 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,457 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,457 INFO L791 eck$LassoCheckResult]: Stem: 133875#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 133876#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 133737#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133673#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 133674#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 134033#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133655#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133483#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133484#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 133465#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 133466#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 134032#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 133803#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 133804#L769 assume !(0 == ~M_E~0); 133827#L769-2 assume !(0 == ~T1_E~0); 133828#L774-1 assume !(0 == ~T2_E~0); 133866#L779-1 assume !(0 == ~T3_E~0); 134015#L784-1 assume !(0 == ~T4_E~0); 133797#L789-1 assume !(0 == ~T5_E~0); 133798#L794-1 assume !(0 == ~T6_E~0); 133937#L799-1 assume !(0 == ~T7_E~0); 133805#L804-1 assume !(0 == ~E_M~0); 133806#L809-1 assume !(0 == ~E_1~0); 133856#L814-1 assume !(0 == ~E_2~0); 133200#L819-1 assume !(0 == ~E_3~0); 133201#L824-1 assume !(0 == ~E_4~0); 133554#L829-1 assume !(0 == ~E_5~0); 134122#L834-1 assume !(0 == ~E_6~0); 133328#L839-1 assume !(0 == ~E_7~0); 133329#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133746#L376 assume !(1 == ~m_pc~0); 133730#L376-2 is_master_triggered_~__retres1~0#1 := 0; 133729#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134084#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 133280#L955 assume !(0 != activate_threads_~tmp~1#1); 133281#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133647#L395 assume !(1 == ~t1_pc~0); 133830#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133999#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133206#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 133207#L963 assume !(0 != activate_threads_~tmp___0~0#1); 133751#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133752#L414 assume !(1 == ~t2_pc~0); 133331#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 133332#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133538#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 133539#L971 assume !(0 != activate_threads_~tmp___1~0#1); 134036#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133650#L433 assume !(1 == ~t3_pc~0); 133455#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 133456#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133617#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 133618#L979 assume !(0 != activate_threads_~tmp___2~0#1); 133300#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133301#L452 assume !(1 == ~t4_pc~0); 133461#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 133462#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133784#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 133865#L987 assume !(0 != activate_threads_~tmp___3~0#1); 133494#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133495#L471 assume !(1 == ~t5_pc~0); 133918#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 133477#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133478#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 133857#L995 assume !(0 != activate_threads_~tmp___4~0#1); 134105#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134106#L490 assume !(1 == ~t6_pc~0); 133749#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 133750#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 133791#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 133794#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 133662#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133624#L509 assume !(1 == ~t7_pc~0); 133625#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 133435#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 133436#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 133499#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 133500#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134049#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 134050#L857-2 assume !(1 == ~T1_E~0); 133562#L862-1 assume !(1 == ~T2_E~0); 133563#L867-1 assume !(1 == ~T3_E~0); 133651#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133652#L877-1 assume !(1 == ~T5_E~0); 134067#L882-1 assume !(1 == ~T6_E~0); 134068#L887-1 assume !(1 == ~T7_E~0); 134185#L892-1 assume !(1 == ~E_M~0); 134159#L897-1 assume !(1 == ~E_1~0); 134160#L902-1 assume !(1 == ~E_2~0); 133978#L907-1 assume !(1 == ~E_3~0); 133979#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 133898#L917-1 assume !(1 == ~E_5~0); 133899#L922-1 assume !(1 == ~E_6~0); 134129#L927-1 assume !(1 == ~E_7~0); 146796#L932-1 assume { :end_inline_reset_delta_events } true; 146794#L1178-2 [2021-12-15 17:20:36,457 INFO L793 eck$LassoCheckResult]: Loop: 146794#L1178-2 assume !false; 146787#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 146785#L744 assume !false; 146783#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 146781#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 146772#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 146770#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 146768#L641 assume !(0 != eval_~tmp~0#1); 146769#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 165093#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 165091#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 165089#L769-5 assume !(0 == ~T1_E~0); 165087#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 165085#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 165083#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 165081#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 165079#L794-3 assume !(0 == ~T6_E~0); 165077#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 165075#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 165072#L809-3 assume !(0 == ~E_1~0); 165069#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 165067#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 165065#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 165063#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 165061#L834-3 assume !(0 == ~E_6~0); 165058#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 165055#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 165052#L376-27 assume 1 == ~m_pc~0; 165050#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 165047#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165045#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 165042#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 165039#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 165038#L395-27 assume !(1 == ~t1_pc~0); 164540#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 164539#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164538#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 164537#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 164536#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164535#L414-27 assume 1 == ~t2_pc~0; 164534#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 164531#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164528#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 164526#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 164524#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133356#L433-27 assume !(1 == ~t3_pc~0); 133357#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 164493#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 164458#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 164454#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 164452#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164375#L452-27 assume !(1 == ~t4_pc~0); 164374#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 164370#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164368#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 164367#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 164249#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147710#L471-27 assume !(1 == ~t5_pc~0); 147708#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 147706#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147704#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 147702#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 147700#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147698#L490-27 assume !(1 == ~t6_pc~0); 137630#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 147696#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147694#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 147692#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 147690#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 147688#L509-27 assume !(1 == ~t7_pc~0); 147684#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 147682#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 147680#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147678#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 147676#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 147674#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 146025#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 147669#L862-3 assume !(1 == ~T2_E~0); 147667#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147665#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 147663#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 147662#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 147651#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 147649#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 147647#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 147645#L902-3 assume !(1 == ~E_2~0); 147643#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 147641#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 147637#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 147628#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 147617#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 147600#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 147055#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 147049#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 147047#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 147030#L1197 assume !(0 == start_simulation_~tmp~3#1); 147029#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 146937#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 146932#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 146931#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 146926#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 146924#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 146921#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 146797#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 146794#L1178-2 [2021-12-15 17:20:36,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2021-12-15 17:20:36,458 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514066205] [2021-12-15 17:20:36,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,458 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,494 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514066205] [2021-12-15 17:20:36,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514066205] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,494 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,494 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:36,495 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812161532] [2021-12-15 17:20:36,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,496 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,497 INFO L85 PathProgramCache]: Analyzing trace with hash -434906328, now seen corresponding path program 2 times [2021-12-15 17:20:36,497 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596901238] [2021-12-15 17:20:36,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,497 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,520 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,521 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596901238] [2021-12-15 17:20:36,521 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596901238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,521 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,521 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,521 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415645711] [2021-12-15 17:20:36,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,522 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,522 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:36,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:36,522 INFO L87 Difference]: Start difference. First operand 33495 states and 48382 transitions. cyclomatic complexity: 14895 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,981 INFO L93 Difference]: Finished difference Result 75182 states and 109367 transitions. [2021-12-15 17:20:36,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:36,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75182 states and 109367 transitions. [2021-12-15 17:20:37,577 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 74864 [2021-12-15 17:20:37,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75182 states to 75182 states and 109367 transitions. [2021-12-15 17:20:37,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75182 [2021-12-15 17:20:37,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75182 [2021-12-15 17:20:37,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75182 states and 109367 transitions. [2021-12-15 17:20:37,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:37,961 INFO L681 BuchiCegarLoop]: Abstraction has 75182 states and 109367 transitions. [2021-12-15 17:20:38,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75182 states and 109367 transitions. [2021-12-15 17:20:38,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75182 to 34842. [2021-12-15 17:20:38,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34842 states, 34842 states have (on average 1.4272716836002526) internal successors, (49729), 34841 states have internal predecessors, (49729), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34842 states to 34842 states and 49729 transitions. [2021-12-15 17:20:38,714 INFO L704 BuchiCegarLoop]: Abstraction has 34842 states and 49729 transitions. [2021-12-15 17:20:38,715 INFO L587 BuchiCegarLoop]: Abstraction has 34842 states and 49729 transitions. [2021-12-15 17:20:38,715 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:38,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34842 states and 49729 transitions. [2021-12-15 17:20:38,785 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 34680 [2021-12-15 17:20:38,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,787 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,788 INFO L791 eck$LassoCheckResult]: Stem: 242562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 242563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 242427#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 242358#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 242359#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 242717#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 242341#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 242172#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 242173#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 242154#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 242155#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 242716#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 242493#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 242494#L769 assume !(0 == ~M_E~0); 242517#L769-2 assume !(0 == ~T1_E~0); 242518#L774-1 assume !(0 == ~T2_E~0); 242552#L779-1 assume !(0 == ~T3_E~0); 242694#L784-1 assume !(0 == ~T4_E~0); 242488#L789-1 assume !(0 == ~T5_E~0); 242489#L794-1 assume !(0 == ~T6_E~0); 242617#L799-1 assume !(0 == ~T7_E~0); 242497#L804-1 assume !(0 == ~E_M~0); 242498#L809-1 assume !(0 == ~E_1~0); 242544#L814-1 assume !(0 == ~E_2~0); 241890#L819-1 assume !(0 == ~E_3~0); 241891#L824-1 assume !(0 == ~E_4~0); 242242#L829-1 assume !(0 == ~E_5~0); 242802#L834-1 assume !(0 == ~E_6~0); 242022#L839-1 assume !(0 == ~E_7~0); 242023#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 242434#L376 assume !(1 == ~m_pc~0); 242414#L376-2 is_master_triggered_~__retres1~0#1 := 0; 242413#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 242766#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 241971#L955 assume !(0 != activate_threads_~tmp~1#1); 241972#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 242333#L395 assume !(1 == ~t1_pc~0); 242521#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 242680#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241896#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 241897#L963 assume !(0 != activate_threads_~tmp___0~0#1); 242438#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 242439#L414 assume !(1 == ~t2_pc~0); 242025#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 242026#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242228#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 242229#L971 assume !(0 != activate_threads_~tmp___1~0#1); 242722#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 242336#L433 assume !(1 == ~t3_pc~0); 242141#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 242142#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242303#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 242304#L979 assume !(0 != activate_threads_~tmp___2~0#1); 241992#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241993#L452 assume !(1 == ~t4_pc~0); 242150#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 242151#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 242475#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 242551#L987 assume !(0 != activate_threads_~tmp___3~0#1); 242183#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 242184#L471 assume !(1 == ~t5_pc~0); 242600#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 242166#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 242167#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 242545#L995 assume !(0 != activate_threads_~tmp___4~0#1); 242787#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 242788#L490 assume !(1 == ~t6_pc~0); 242436#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 242437#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 242482#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 242485#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 242346#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 242313#L509 assume !(1 == ~t7_pc~0); 242314#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 242123#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 242124#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 242188#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 242189#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 242733#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 241978#L857-2 assume !(1 == ~T1_E~0); 241979#L862-1 assume !(1 == ~T2_E~0); 242250#L867-1 assume !(1 == ~T3_E~0); 242337#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 242338#L877-1 assume !(1 == ~T5_E~0); 242575#L882-1 assume !(1 == ~T6_E~0); 242752#L887-1 assume !(1 == ~T7_E~0); 256555#L892-1 assume !(1 == ~E_M~0); 256549#L897-1 assume !(1 == ~E_1~0); 256545#L902-1 assume !(1 == ~E_2~0); 242653#L907-1 assume !(1 == ~E_3~0); 242593#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 242584#L917-1 assume !(1 == ~E_5~0); 242585#L922-1 assume !(1 == ~E_6~0); 242808#L927-1 assume !(1 == ~E_7~0); 242570#L932-1 assume { :end_inline_reset_delta_events } true; 242571#L1178-2 [2021-12-15 17:20:38,788 INFO L793 eck$LassoCheckResult]: Loop: 242571#L1178-2 assume !false; 258106#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 258095#L744 assume !false; 258089#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 258062#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 258047#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 258009#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 257986#L641 assume !(0 != eval_~tmp~0#1); 257987#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 259666#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 259664#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 259662#L769-5 assume !(0 == ~T1_E~0); 259660#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 259658#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 259656#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 259654#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 259652#L794-3 assume !(0 == ~T6_E~0); 259650#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 259648#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 259646#L809-3 assume !(0 == ~E_1~0); 259644#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 259642#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 259640#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 259638#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 259636#L834-3 assume !(0 == ~E_6~0); 259634#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 259632#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 259630#L376-27 assume !(1 == ~m_pc~0); 259627#L376-29 is_master_triggered_~__retres1~0#1 := 0; 259624#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 259622#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 259620#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 259618#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 259616#L395-27 assume !(1 == ~t1_pc~0); 259614#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 259612#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 259610#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 259608#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 259606#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 259604#L414-27 assume 1 == ~t2_pc~0; 259602#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 259598#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 259596#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 259594#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 259592#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 259590#L433-27 assume !(1 == ~t3_pc~0); 259305#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 259588#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 259583#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 259384#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 259385#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 259200#L452-27 assume !(1 == ~t4_pc~0); 259202#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 258877#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258878#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 258552#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 258553#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 258549#L471-27 assume !(1 == ~t5_pc~0); 258548#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 258547#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 258546#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 258545#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 258544#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 258543#L490-27 assume !(1 == ~t6_pc~0); 249063#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 258542#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 258541#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 258540#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 258539#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 258538#L509-27 assume !(1 == ~t7_pc~0); 258537#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 258535#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 258533#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 258531#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 258529#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 258528#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 256338#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 258507#L862-3 assume !(1 == ~T2_E~0); 258505#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 258503#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 258502#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 258500#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 256585#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 258497#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 258450#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 258447#L902-3 assume !(1 == ~E_2~0); 258425#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 258421#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 258415#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 258411#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 256315#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 258349#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 258295#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 258287#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 258284#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 258281#L1197 assume !(0 == start_simulation_~tmp~3#1); 258280#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 258275#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 258269#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 258268#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 258266#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 258265#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 258264#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 258233#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 242571#L1178-2 [2021-12-15 17:20:38,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,789 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2021-12-15 17:20:38,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164241270] [2021-12-15 17:20:38,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,813 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,813 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164241270] [2021-12-15 17:20:38,813 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164241270] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,813 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,813 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:38,813 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684578665] [2021-12-15 17:20:38,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,814 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,814 INFO L85 PathProgramCache]: Analyzing trace with hash -1575620245, now seen corresponding path program 1 times [2021-12-15 17:20:38,814 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785819085] [2021-12-15 17:20:38,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,814 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785819085] [2021-12-15 17:20:38,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785819085] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,838 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941641402] [2021-12-15 17:20:38,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,838 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,838 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:38,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:38,839 INFO L87 Difference]: Start difference. First operand 34842 states and 49729 transitions. cyclomatic complexity: 14895 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:39,088 INFO L93 Difference]: Finished difference Result 43700 states and 62388 transitions. [2021-12-15 17:20:39,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:39,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43700 states and 62388 transitions. [2021-12-15 17:20:39,243 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 43544 [2021-12-15 17:20:39,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43700 states to 43700 states and 62388 transitions. [2021-12-15 17:20:39,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43700 [2021-12-15 17:20:39,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43700 [2021-12-15 17:20:39,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43700 states and 62388 transitions. [2021-12-15 17:20:39,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:39,408 INFO L681 BuchiCegarLoop]: Abstraction has 43700 states and 62388 transitions. [2021-12-15 17:20:39,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43700 states and 62388 transitions. [2021-12-15 17:20:39,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43700 to 18790. [2021-12-15 17:20:39,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18790 states, 18790 states have (on average 1.4332623736029804) internal successors, (26931), 18789 states have internal predecessors, (26931), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18790 states to 18790 states and 26931 transitions. [2021-12-15 17:20:39,691 INFO L704 BuchiCegarLoop]: Abstraction has 18790 states and 26931 transitions. [2021-12-15 17:20:39,691 INFO L587 BuchiCegarLoop]: Abstraction has 18790 states and 26931 transitions. [2021-12-15 17:20:39,691 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:39,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18790 states and 26931 transitions. [2021-12-15 17:20:39,742 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18672 [2021-12-15 17:20:39,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:39,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:39,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,747 INFO L791 eck$LassoCheckResult]: Stem: 321098#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 321099#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 320962#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 320901#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 320902#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 321254#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 320884#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 320719#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 320720#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 320700#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 320701#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 321253#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 321030#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 321031#L769 assume !(0 == ~M_E~0); 321053#L769-2 assume !(0 == ~T1_E~0); 321054#L774-1 assume !(0 == ~T2_E~0); 321089#L779-1 assume !(0 == ~T3_E~0); 321234#L784-1 assume !(0 == ~T4_E~0); 321026#L789-1 assume !(0 == ~T5_E~0); 321027#L794-1 assume !(0 == ~T6_E~0); 321155#L799-1 assume !(0 == ~T7_E~0); 321033#L804-1 assume !(0 == ~E_M~0); 321034#L809-1 assume !(0 == ~E_1~0); 321080#L814-1 assume !(0 == ~E_2~0); 320439#L819-1 assume !(0 == ~E_3~0); 320440#L824-1 assume !(0 == ~E_4~0); 320789#L829-1 assume !(0 == ~E_5~0); 321327#L834-1 assume !(0 == ~E_6~0); 320568#L839-1 assume !(0 == ~E_7~0); 320569#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 320970#L376 assume !(1 == ~m_pc~0); 320951#L376-2 is_master_triggered_~__retres1~0#1 := 0; 320950#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 321299#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 320518#L955 assume !(0 != activate_threads_~tmp~1#1); 320519#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 320876#L395 assume !(1 == ~t1_pc~0); 321056#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 321219#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 320445#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 320446#L963 assume !(0 != activate_threads_~tmp___0~0#1); 320975#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 320976#L414 assume !(1 == ~t2_pc~0); 320571#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 320572#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 320774#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 320775#L971 assume !(0 != activate_threads_~tmp___1~0#1); 321260#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320880#L433 assume !(1 == ~t3_pc~0); 320688#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 320689#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 320847#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 320848#L979 assume !(0 != activate_threads_~tmp___2~0#1); 320539#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 320540#L452 assume !(1 == ~t4_pc~0); 320696#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 320697#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 321011#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 321088#L987 assume !(0 != activate_threads_~tmp___3~0#1); 320730#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 320731#L471 assume !(1 == ~t5_pc~0); 321137#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 320712#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 320713#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 321081#L995 assume !(0 != activate_threads_~tmp___4~0#1); 321316#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 321317#L490 assume !(1 == ~t6_pc~0); 320973#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 320974#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 321019#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 321022#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 320889#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 320855#L509 assume !(1 == ~t7_pc~0); 320856#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 321263#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 321428#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 320735#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 320736#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 321271#L857 assume !(1 == ~M_E~0); 320525#L857-2 assume !(1 == ~T1_E~0); 320526#L862-1 assume !(1 == ~T2_E~0); 320798#L867-1 assume !(1 == ~T3_E~0); 320803#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 320881#L877-1 assume !(1 == ~T5_E~0); 321110#L882-1 assume !(1 == ~T6_E~0); 321285#L887-1 assume !(1 == ~T7_E~0); 321176#L892-1 assume !(1 == ~E_M~0); 321177#L897-1 assume !(1 == ~E_1~0); 320813#L902-1 assume !(1 == ~E_2~0); 320814#L907-1 assume !(1 == ~E_3~0); 321130#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 321119#L917-1 assume !(1 == ~E_5~0); 321120#L922-1 assume !(1 == ~E_6~0); 321331#L927-1 assume !(1 == ~E_7~0); 321105#L932-1 assume { :end_inline_reset_delta_events } true; 321106#L1178-2 [2021-12-15 17:20:39,747 INFO L793 eck$LassoCheckResult]: Loop: 321106#L1178-2 assume !false; 336750#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 336748#L744 assume !false; 336746#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 336743#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 336727#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 336718#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 336710#L641 assume !(0 != eval_~tmp~0#1); 336711#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 339193#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 339192#L769-3 assume !(0 == ~M_E~0); 339191#L769-5 assume !(0 == ~T1_E~0); 339189#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 339186#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 339185#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 339184#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 338962#L794-3 assume !(0 == ~T6_E~0); 338961#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 338960#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 338959#L809-3 assume !(0 == ~E_1~0); 338958#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 338957#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 338956#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 338955#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 338954#L834-3 assume !(0 == ~E_6~0); 338953#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 338951#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 338948#L376-27 assume !(1 == ~m_pc~0); 338945#L376-29 is_master_triggered_~__retres1~0#1 := 0; 338943#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 338941#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 338939#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 338937#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 338934#L395-27 assume !(1 == ~t1_pc~0); 338932#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 338930#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 338928#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 338926#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 338924#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 338921#L414-27 assume !(1 == ~t2_pc~0); 338919#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 338918#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 338917#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 338916#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 338915#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336471#L433-27 assume !(1 == ~t3_pc~0); 336464#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 336458#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 336453#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 336448#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 336443#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 336437#L452-27 assume 1 == ~t4_pc~0; 336429#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 336422#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 336416#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 336410#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 336405#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336398#L471-27 assume !(1 == ~t5_pc~0); 332146#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 336386#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 336379#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336318#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 336317#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 332244#L490-27 assume !(1 == ~t6_pc~0); 332243#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 332242#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 332238#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 332236#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 332234#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 332233#L509-27 assume !(1 == ~t7_pc~0); 332231#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 332229#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 332227#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 332226#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 332224#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 332222#L857-3 assume !(1 == ~M_E~0); 326944#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 332221#L862-3 assume !(1 == ~T2_E~0); 332220#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 332219#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 332218#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 332217#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 332215#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 332213#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 332211#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 332209#L902-3 assume !(1 == ~E_2~0); 332207#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 332205#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 332203#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 332200#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 332198#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 332196#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 332183#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 332177#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 332175#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 327737#L1197 assume !(0 == start_simulation_~tmp~3#1); 327738#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 336803#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 336797#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 336796#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 336794#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 336792#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336790#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 336788#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 321106#L1178-2 [2021-12-15 17:20:39,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,748 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2021-12-15 17:20:39,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149944369] [2021-12-15 17:20:39,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,749 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,876 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149944369] [2021-12-15 17:20:39,877 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149944369] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,877 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,877 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,877 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985156493] [2021-12-15 17:20:39,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,877 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:39,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,878 INFO L85 PathProgramCache]: Analyzing trace with hash -1156970453, now seen corresponding path program 1 times [2021-12-15 17:20:39,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,878 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051902802] [2021-12-15 17:20:39,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,878 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051902802] [2021-12-15 17:20:39,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1051902802] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,898 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819571495] [2021-12-15 17:20:39,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,899 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:39,899 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:39,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:39,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:39,899 INFO L87 Difference]: Start difference. First operand 18790 states and 26931 transitions. cyclomatic complexity: 8143 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:40,004 INFO L93 Difference]: Finished difference Result 29858 states and 42654 transitions. [2021-12-15 17:20:40,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:40,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29858 states and 42654 transitions. [2021-12-15 17:20:40,141 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 29648 [2021-12-15 17:20:40,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29858 states to 29858 states and 42654 transitions. [2021-12-15 17:20:40,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29858 [2021-12-15 17:20:40,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29858 [2021-12-15 17:20:40,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29858 states and 42654 transitions. [2021-12-15 17:20:40,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:40,270 INFO L681 BuchiCegarLoop]: Abstraction has 29858 states and 42654 transitions. [2021-12-15 17:20:40,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29858 states and 42654 transitions. [2021-12-15 17:20:40,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29858 to 21230. [2021-12-15 17:20:40,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21230 states, 21230 states have (on average 1.4322656617993406) internal successors, (30407), 21229 states have internal predecessors, (30407), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21230 states to 21230 states and 30407 transitions. [2021-12-15 17:20:40,528 INFO L704 BuchiCegarLoop]: Abstraction has 21230 states and 30407 transitions. [2021-12-15 17:20:40,528 INFO L587 BuchiCegarLoop]: Abstraction has 21230 states and 30407 transitions. [2021-12-15 17:20:40,528 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:40,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21230 states and 30407 transitions. [2021-12-15 17:20:40,681 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21040 [2021-12-15 17:20:40,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:40,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:40,693 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,694 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,694 INFO L791 eck$LassoCheckResult]: Stem: 369761#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 369762#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 369629#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 369564#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 369565#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 369915#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 369547#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 369374#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 369375#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 369356#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 369357#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 369914#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 369695#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 369696#L769 assume !(0 == ~M_E~0); 369718#L769-2 assume !(0 == ~T1_E~0); 369719#L774-1 assume !(0 == ~T2_E~0); 369753#L779-1 assume !(0 == ~T3_E~0); 369894#L784-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 369691#L789-1 assume !(0 == ~T5_E~0); 369692#L794-1 assume !(0 == ~T6_E~0); 369816#L799-1 assume !(0 == ~T7_E~0); 369698#L804-1 assume !(0 == ~E_M~0); 369699#L809-1 assume !(0 == ~E_1~0); 369925#L814-1 assume !(0 == ~E_2~0); 369926#L819-1 assume !(0 == ~E_3~0); 369443#L824-1 assume !(0 == ~E_4~0); 369444#L829-1 assume !(0 == ~E_5~0); 369999#L834-1 assume !(0 == ~E_6~0); 370000#L839-1 assume !(0 == ~E_7~0); 370120#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 369636#L376 assume !(1 == ~m_pc~0); 369637#L376-2 is_master_triggered_~__retres1~0#1 := 0; 370066#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 370067#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 369178#L955 assume !(0 != activate_threads_~tmp~1#1); 369179#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 369538#L395 assume !(1 == ~t1_pc~0); 369880#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 369881#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 369103#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 369104#L963 assume !(0 != activate_threads_~tmp___0~0#1); 369643#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 369644#L414 assume !(1 == ~t2_pc~0); 369229#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 369230#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 369428#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 369429#L971 assume !(0 != activate_threads_~tmp___1~0#1); 370009#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 369542#L433 assume !(1 == ~t3_pc~0); 369543#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 370021#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370022#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 370117#L979 assume !(0 != activate_threads_~tmp___2~0#1); 370116#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 370072#L452 assume !(1 == ~t4_pc~0); 370073#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 369675#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 369676#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 370015#L987 assume !(0 != activate_threads_~tmp___3~0#1); 370016#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 370115#L471 assume !(1 == ~t5_pc~0); 370037#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 370038#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 369745#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 369746#L995 assume !(0 != activate_threads_~tmp___4~0#1); 369985#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 369986#L490 assume !(1 == ~t6_pc~0); 369641#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 369642#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 370114#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 369688#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 369552#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 369518#L509 assume !(1 == ~t7_pc~0); 369519#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 369325#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 369326#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 369390#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 369391#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369938#L857 assume !(1 == ~M_E~0); 369939#L857-2 assume !(1 == ~T1_E~0); 369452#L862-1 assume !(1 == ~T2_E~0); 369453#L867-1 assume !(1 == ~T3_E~0); 370110#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 369544#L877-1 assume !(1 == ~T5_E~0); 369773#L882-1 assume !(1 == ~T6_E~0); 369953#L887-1 assume !(1 == ~T7_E~0); 369838#L892-1 assume !(1 == ~E_M~0); 369839#L897-1 assume !(1 == ~E_1~0); 369471#L902-1 assume !(1 == ~E_2~0); 369472#L907-1 assume !(1 == ~E_3~0); 369790#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 369781#L917-1 assume !(1 == ~E_5~0); 369782#L922-1 assume !(1 == ~E_6~0); 370003#L927-1 assume !(1 == ~E_7~0); 369768#L932-1 assume { :end_inline_reset_delta_events } true; 369769#L1178-2 [2021-12-15 17:20:40,694 INFO L793 eck$LassoCheckResult]: Loop: 369769#L1178-2 assume !false; 387051#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 387047#L744 assume !false; 387043#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 384452#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 384443#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 384441#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 384438#L641 assume !(0 != eval_~tmp~0#1); 384439#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 387325#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 387323#L769-3 assume !(0 == ~M_E~0); 387321#L769-5 assume !(0 == ~T1_E~0); 387319#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 387317#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 387314#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 387313#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 387312#L794-3 assume !(0 == ~T6_E~0); 387311#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 387310#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 387309#L809-3 assume !(0 == ~E_1~0); 387308#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 387307#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 387306#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 387305#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 387304#L834-3 assume !(0 == ~E_6~0); 387303#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 387302#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 387301#L376-27 assume 1 == ~m_pc~0; 387300#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 387298#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 387297#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 387296#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 387295#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 387294#L395-27 assume !(1 == ~t1_pc~0); 387293#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 387292#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 387291#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 387290#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 387289#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 387288#L414-27 assume 1 == ~t2_pc~0; 387287#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 387285#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 387284#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 387283#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 387282#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 387281#L433-27 assume !(1 == ~t3_pc~0); 378065#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 387280#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 387279#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 387278#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 387277#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 387276#L452-27 assume !(1 == ~t4_pc~0); 387275#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 387273#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 387272#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 387271#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 387270#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 387269#L471-27 assume !(1 == ~t5_pc~0); 379456#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 387268#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 387267#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 387266#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 387265#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 387264#L490-27 assume !(1 == ~t6_pc~0); 377733#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 387263#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387262#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 387261#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 387260#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 387259#L509-27 assume 1 == ~t7_pc~0; 387257#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 387255#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 387253#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 387251#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 387250#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 387249#L857-3 assume !(1 == ~M_E~0); 377123#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 387248#L862-3 assume !(1 == ~T2_E~0); 387247#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 387245#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 387243#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 387241#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 387239#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 387238#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 387237#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 387236#L902-3 assume !(1 == ~E_2~0); 387234#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 387231#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 387225#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 387220#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 387215#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 387211#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 387191#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 387181#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 387175#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 387156#L1197 assume !(0 == start_simulation_~tmp~3#1); 387151#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 387104#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 387094#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 387086#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 387080#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 387075#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 387068#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 387063#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 369769#L1178-2 [2021-12-15 17:20:40,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2021-12-15 17:20:40,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366053574] [2021-12-15 17:20:40,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366053574] [2021-12-15 17:20:40,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366053574] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,715 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,715 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:40,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665788604] [2021-12-15 17:20:40,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,716 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:40,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1719126937, now seen corresponding path program 1 times [2021-12-15 17:20:40,716 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899254911] [2021-12-15 17:20:40,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,716 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,734 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,734 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899254911] [2021-12-15 17:20:40,735 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899254911] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,735 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,735 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:40,735 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726727023] [2021-12-15 17:20:40,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,735 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:40,735 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:40,736 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:40,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:40,736 INFO L87 Difference]: Start difference. First operand 21230 states and 30407 transitions. cyclomatic complexity: 9179 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:40,833 INFO L93 Difference]: Finished difference Result 27406 states and 39041 transitions. [2021-12-15 17:20:40,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:40,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27406 states and 39041 transitions. [2021-12-15 17:20:40,956 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27280 [2021-12-15 17:20:41,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27406 states to 27406 states and 39041 transitions. [2021-12-15 17:20:41,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27406 [2021-12-15 17:20:41,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27406 [2021-12-15 17:20:41,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27406 states and 39041 transitions. [2021-12-15 17:20:41,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:41,073 INFO L681 BuchiCegarLoop]: Abstraction has 27406 states and 39041 transitions. [2021-12-15 17:20:41,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27406 states and 39041 transitions. [2021-12-15 17:20:41,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27406 to 18790. [2021-12-15 17:20:41,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18790 states, 18790 states have (on average 1.428046833422033) internal successors, (26833), 18789 states have internal predecessors, (26833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18790 states to 18790 states and 26833 transitions. [2021-12-15 17:20:41,267 INFO L704 BuchiCegarLoop]: Abstraction has 18790 states and 26833 transitions. [2021-12-15 17:20:41,267 INFO L587 BuchiCegarLoop]: Abstraction has 18790 states and 26833 transitions. [2021-12-15 17:20:41,267 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:20:41,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18790 states and 26833 transitions. [2021-12-15 17:20:41,313 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18672 [2021-12-15 17:20:41,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:41,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:41,315 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,315 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,315 INFO L791 eck$LassoCheckResult]: Stem: 418405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 418406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 418271#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 418213#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 418214#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 418554#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 418193#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 418024#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 418025#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 418006#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 418007#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 418553#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 418343#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 418344#L769 assume !(0 == ~M_E~0); 418368#L769-2 assume !(0 == ~T1_E~0); 418369#L774-1 assume !(0 == ~T2_E~0); 418397#L779-1 assume !(0 == ~T3_E~0); 418533#L784-1 assume !(0 == ~T4_E~0); 418336#L789-1 assume !(0 == ~T5_E~0); 418337#L794-1 assume !(0 == ~T6_E~0); 418460#L799-1 assume !(0 == ~T7_E~0); 418345#L804-1 assume !(0 == ~E_M~0); 418346#L809-1 assume !(0 == ~E_1~0); 418390#L814-1 assume !(0 == ~E_2~0); 417747#L819-1 assume !(0 == ~E_3~0); 417748#L824-1 assume !(0 == ~E_4~0); 418094#L829-1 assume !(0 == ~E_5~0); 418630#L834-1 assume !(0 == ~E_6~0); 417872#L839-1 assume !(0 == ~E_7~0); 417873#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 418279#L376 assume !(1 == ~m_pc~0); 418266#L376-2 is_master_triggered_~__retres1~0#1 := 0; 418265#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 418601#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 417825#L955 assume !(0 != activate_threads_~tmp~1#1); 417826#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 418185#L395 assume !(1 == ~t1_pc~0); 418370#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 418520#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 417751#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 417752#L963 assume !(0 != activate_threads_~tmp___0~0#1); 418287#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 418288#L414 assume !(1 == ~t2_pc~0); 417875#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 417876#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 418079#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 418080#L971 assume !(0 != activate_threads_~tmp___1~0#1); 418561#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 418189#L433 assume !(1 == ~t3_pc~0); 417996#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 417997#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 418159#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 418160#L979 assume !(0 != activate_threads_~tmp___2~0#1); 417844#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 417845#L452 assume !(1 == ~t4_pc~0); 418002#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 418003#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418324#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 418396#L987 assume !(0 != activate_threads_~tmp___3~0#1); 418035#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 418036#L471 assume !(1 == ~t5_pc~0); 418442#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 418018#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418019#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 418391#L995 assume !(0 != activate_threads_~tmp___4~0#1); 418620#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 418621#L490 assume !(1 == ~t6_pc~0); 418283#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 418284#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 418332#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 418335#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 418201#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 418165#L509 assume !(1 == ~t7_pc~0); 418166#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 417980#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 417981#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 418040#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 418041#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 418572#L857 assume !(1 == ~M_E~0); 417830#L857-2 assume !(1 == ~T1_E~0); 417831#L862-1 assume !(1 == ~T2_E~0); 418103#L867-1 assume !(1 == ~T3_E~0); 418108#L872-1 assume !(1 == ~T4_E~0); 418190#L877-1 assume !(1 == ~T5_E~0); 418416#L882-1 assume !(1 == ~T6_E~0); 418589#L887-1 assume !(1 == ~T7_E~0); 418479#L892-1 assume !(1 == ~E_M~0); 418480#L897-1 assume !(1 == ~E_1~0); 418122#L902-1 assume !(1 == ~E_2~0); 418123#L907-1 assume !(1 == ~E_3~0); 418436#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 418425#L917-1 assume !(1 == ~E_5~0); 418426#L922-1 assume !(1 == ~E_6~0); 418634#L927-1 assume !(1 == ~E_7~0); 418411#L932-1 assume { :end_inline_reset_delta_events } true; 418412#L1178-2 [2021-12-15 17:20:41,316 INFO L793 eck$LassoCheckResult]: Loop: 418412#L1178-2 assume !false; 433974#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 433971#L744 assume !false; 433969#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 433967#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 433958#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 433956#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 433946#L641 assume !(0 != eval_~tmp~0#1); 433947#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 436484#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 436482#L769-3 assume !(0 == ~M_E~0); 436480#L769-5 assume !(0 == ~T1_E~0); 436478#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 436476#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 436474#L784-3 assume !(0 == ~T4_E~0); 436472#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 436471#L794-3 assume !(0 == ~T6_E~0); 436470#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 436469#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 418281#L809-3 assume !(0 == ~E_1~0); 417791#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 417792#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 436409#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 436408#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 436407#L834-3 assume !(0 == ~E_6~0); 436406#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 436405#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 436404#L376-27 assume !(1 == ~m_pc~0); 436402#L376-29 is_master_triggered_~__retres1~0#1 := 0; 436401#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 436400#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 436399#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 436398#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 436397#L395-27 assume !(1 == ~t1_pc~0); 436394#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 436392#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 436390#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 436388#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 436385#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 436383#L414-27 assume !(1 == ~t2_pc~0); 436380#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 436378#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 436376#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 436375#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 436363#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434976#L433-27 assume !(1 == ~t3_pc~0); 434972#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 434969#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 434965#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 434961#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 434957#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 434953#L452-27 assume !(1 == ~t4_pc~0); 434948#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 434944#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434940#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 434936#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 434933#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 434931#L471-27 assume !(1 == ~t5_pc~0); 433533#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 434924#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 434920#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 434916#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 434912#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 425963#L490-27 assume !(1 == ~t6_pc~0); 425961#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 425959#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 425958#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 425956#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 425954#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 425952#L509-27 assume 1 == ~t7_pc~0; 425950#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 425951#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 425975#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 425941#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 425939#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425937#L857-3 assume !(1 == ~M_E~0); 425695#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 425934#L862-3 assume !(1 == ~T2_E~0); 425932#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 425930#L872-3 assume !(1 == ~T4_E~0); 425928#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 425926#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 425925#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 425924#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 425923#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 425922#L902-3 assume !(1 == ~E_2~0); 425921#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 425912#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 425910#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 425908#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 425906#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 425904#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 425879#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 425873#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 425870#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 425867#L1197 assume !(0 == start_simulation_~tmp~3#1); 425868#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 433999#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 433991#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 433989#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 433987#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 433985#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 433983#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 433981#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 418412#L1178-2 [2021-12-15 17:20:41,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,316 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2021-12-15 17:20:41,316 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961638503] [2021-12-15 17:20:41,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,317 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,455 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961638503] [2021-12-15 17:20:41,455 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961638503] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,455 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,456 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,456 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926340989] [2021-12-15 17:20:41,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,456 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:41,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,456 INFO L85 PathProgramCache]: Analyzing trace with hash -1166186071, now seen corresponding path program 1 times [2021-12-15 17:20:41,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986011628] [2021-12-15 17:20:41,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986011628] [2021-12-15 17:20:41,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986011628] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,477 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,477 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451008625] [2021-12-15 17:20:41,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,478 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:41,478 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:41,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:41,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:41,479 INFO L87 Difference]: Start difference. First operand 18790 states and 26833 transitions. cyclomatic complexity: 8045 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:41,607 INFO L93 Difference]: Finished difference Result 29886 states and 42191 transitions. [2021-12-15 17:20:41,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:41,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29886 states and 42191 transitions. [2021-12-15 17:20:41,722 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 29636 [2021-12-15 17:20:41,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29886 states to 29886 states and 42191 transitions. [2021-12-15 17:20:41,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29886 [2021-12-15 17:20:41,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29886 [2021-12-15 17:20:41,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29886 states and 42191 transitions. [2021-12-15 17:20:41,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:41,828 INFO L681 BuchiCegarLoop]: Abstraction has 29886 states and 42191 transitions. [2021-12-15 17:20:41,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29886 states and 42191 transitions. [2021-12-15 17:20:41,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29886 to 21230. [2021-12-15 17:20:41,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21230 states, 21230 states have (on average 1.4170513424399436) internal successors, (30084), 21229 states have internal predecessors, (30084), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21230 states to 21230 states and 30084 transitions. [2021-12-15 17:20:42,021 INFO L704 BuchiCegarLoop]: Abstraction has 21230 states and 30084 transitions. [2021-12-15 17:20:42,021 INFO L587 BuchiCegarLoop]: Abstraction has 21230 states and 30084 transitions. [2021-12-15 17:20:42,021 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:20:42,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21230 states and 30084 transitions. [2021-12-15 17:20:42,137 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21040 [2021-12-15 17:20:42,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:42,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:42,141 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,141 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,141 INFO L791 eck$LassoCheckResult]: Stem: 467099#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 467100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 466957#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 466898#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 466899#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 467260#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 466877#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 466704#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 466705#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 466686#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 466687#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 467258#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 467032#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 467033#L769 assume !(0 == ~M_E~0); 467057#L769-2 assume !(0 == ~T1_E~0); 467058#L774-1 assume !(0 == ~T2_E~0); 467090#L779-1 assume !(0 == ~T3_E~0); 467235#L784-1 assume !(0 == ~T4_E~0); 467027#L789-1 assume !(0 == ~T5_E~0); 467028#L794-1 assume !(0 == ~T6_E~0); 467152#L799-1 assume !(0 == ~T7_E~0); 467034#L804-1 assume !(0 == ~E_M~0); 467035#L809-1 assume !(0 == ~E_1~0); 467080#L814-1 assume !(0 == ~E_2~0); 466433#L819-1 assume !(0 == ~E_3~0); 466434#L824-1 assume 0 == ~E_4~0;~E_4~0 := 1; 466777#L829-1 assume !(0 == ~E_5~0); 467436#L834-1 assume !(0 == ~E_6~0); 466558#L839-1 assume !(0 == ~E_7~0); 466559#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 466965#L376 assume !(1 == ~m_pc~0); 466966#L376-2 is_master_triggered_~__retres1~0#1 := 0; 467407#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467408#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 466511#L955 assume !(0 != activate_threads_~tmp~1#1); 466512#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467059#L395 assume !(1 == ~t1_pc~0); 467060#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 467236#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 467237#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 467282#L963 assume !(0 != activate_threads_~tmp___0~0#1); 467283#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 467444#L414 assume !(1 == ~t2_pc~0); 467445#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 467439#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 467440#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 467266#L971 assume !(0 != activate_threads_~tmp___1~0#1); 467267#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 466872#L433 assume !(1 == ~t3_pc~0); 466873#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 467362#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 467363#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 467203#L979 assume !(0 != activate_threads_~tmp___2~0#1); 467204#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 467416#L452 assume !(1 == ~t4_pc~0); 467417#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 467467#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 467489#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 467488#L987 assume !(0 != activate_threads_~tmp___3~0#1); 467487#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 467486#L471 assume !(1 == ~t5_pc~0); 467485#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 467484#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 467483#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 467482#L995 assume !(0 != activate_threads_~tmp___4~0#1); 467481#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 467480#L490 assume !(1 == ~t6_pc~0); 467479#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 467478#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 467477#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 467476#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 467475#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 467474#L509 assume !(1 == ~t7_pc~0); 467268#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 466658#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 466659#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 467466#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 467465#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 467464#L857 assume !(1 == ~M_E~0); 467463#L857-2 assume !(1 == ~T1_E~0); 467462#L862-1 assume !(1 == ~T2_E~0); 467461#L867-1 assume !(1 == ~T3_E~0); 467460#L872-1 assume !(1 == ~T4_E~0); 467459#L877-1 assume !(1 == ~T5_E~0); 467458#L882-1 assume !(1 == ~T6_E~0); 467457#L887-1 assume !(1 == ~T7_E~0); 467456#L892-1 assume !(1 == ~E_M~0); 467455#L897-1 assume !(1 == ~E_1~0); 467454#L902-1 assume !(1 == ~E_2~0); 467453#L907-1 assume !(1 == ~E_3~0); 467452#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 467123#L917-1 assume !(1 == ~E_5~0); 467124#L922-1 assume !(1 == ~E_6~0); 467347#L927-1 assume !(1 == ~E_7~0); 467108#L932-1 assume { :end_inline_reset_delta_events } true; 467109#L1178-2 [2021-12-15 17:20:42,141 INFO L793 eck$LassoCheckResult]: Loop: 467109#L1178-2 assume !false; 483250#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 483246#L744 assume !false; 483244#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 483242#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 483233#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 483221#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 483217#L641 assume !(0 != eval_~tmp~0#1); 467011#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 466595#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 466596#L769-3 assume !(0 == ~M_E~0); 466870#L769-5 assume !(0 == ~T1_E~0); 466871#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 466612#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 466444#L784-3 assume !(0 == ~T4_E~0); 466445#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 466429#L794-3 assume !(0 == ~T6_E~0); 466430#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 466482#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 466729#L809-3 assume !(0 == ~E_1~0); 466478#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 466479#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 467206#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 467207#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 486711#L834-3 assume !(0 == ~E_6~0); 486710#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 486709#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486708#L376-27 assume 1 == ~m_pc~0; 486707#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 486705#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 486704#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 486703#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 486702#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 486701#L395-27 assume !(1 == ~t1_pc~0); 486700#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 486699#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 486698#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 486697#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 486696#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486695#L414-27 assume 1 == ~t2_pc~0; 486694#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 486692#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486691#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 486690#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 486689#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486688#L433-27 assume !(1 == ~t3_pc~0); 484328#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 486687#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 486686#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 486685#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 486684#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 486683#L452-27 assume !(1 == ~t4_pc~0); 486682#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 486680#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486679#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486678#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 486677#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 486676#L471-27 assume !(1 == ~t5_pc~0); 485012#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 486675#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486674#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 486673#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 486672#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 486671#L490-27 assume !(1 == ~t6_pc~0); 485564#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 486670#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486669#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 486668#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 486667#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 486666#L509-27 assume !(1 == ~t7_pc~0); 486665#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 486663#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 486661#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 486659#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 486657#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 486656#L857-3 assume !(1 == ~M_E~0); 476666#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 486655#L862-3 assume !(1 == ~T2_E~0); 486654#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 486653#L872-3 assume !(1 == ~T4_E~0); 486652#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 486651#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 486650#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 486649#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 486648#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 486647#L902-3 assume !(1 == ~E_2~0); 486646#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 486645#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 466939#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 466892#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 466684#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 466685#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 466537#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 466443#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 467154#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 466859#L1197 assume !(0 == start_simulation_~tmp~3#1); 466860#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 483344#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 483339#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 483338#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 483337#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 483336#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 483335#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 483334#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 467109#L1178-2 [2021-12-15 17:20:42,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,142 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2021-12-15 17:20:42,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861136700] [2021-12-15 17:20:42,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,143 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:42,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:42,162 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:42,162 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861136700] [2021-12-15 17:20:42,163 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861136700] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:42,163 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:42,163 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:42,163 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266511509] [2021-12-15 17:20:42,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:42,163 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:42,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,164 INFO L85 PathProgramCache]: Analyzing trace with hash 2051533866, now seen corresponding path program 1 times [2021-12-15 17:20:42,164 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142909041] [2021-12-15 17:20:42,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,164 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:42,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:42,183 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:42,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142909041] [2021-12-15 17:20:42,183 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142909041] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:42,183 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:42,183 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:42,183 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617136927] [2021-12-15 17:20:42,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:42,185 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:42,185 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:42,185 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:42,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:42,185 INFO L87 Difference]: Start difference. First operand 21230 states and 30084 transitions. cyclomatic complexity: 8856 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:42,301 INFO L93 Difference]: Finished difference Result 26938 states and 37946 transitions. [2021-12-15 17:20:42,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:42,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26938 states and 37946 transitions. [2021-12-15 17:20:42,405 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26804 [2021-12-15 17:20:42,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26938 states to 26938 states and 37946 transitions. [2021-12-15 17:20:42,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26938 [2021-12-15 17:20:42,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26938 [2021-12-15 17:20:42,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26938 states and 37946 transitions. [2021-12-15 17:20:42,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:42,501 INFO L681 BuchiCegarLoop]: Abstraction has 26938 states and 37946 transitions. [2021-12-15 17:20:42,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26938 states and 37946 transitions. [2021-12-15 17:20:42,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26938 to 18790. [2021-12-15 17:20:42,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18790 states, 18790 states have (on average 1.4108568387440128) internal successors, (26510), 18789 states have internal predecessors, (26510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18790 states to 18790 states and 26510 transitions. [2021-12-15 17:20:42,702 INFO L704 BuchiCegarLoop]: Abstraction has 18790 states and 26510 transitions. [2021-12-15 17:20:42,702 INFO L587 BuchiCegarLoop]: Abstraction has 18790 states and 26510 transitions. [2021-12-15 17:20:42,702 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:20:42,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18790 states and 26510 transitions. [2021-12-15 17:20:42,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18672 [2021-12-15 17:20:42,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:42,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:42,754 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,754 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,754 INFO L791 eck$LassoCheckResult]: Stem: 515264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 515265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 515128#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 515069#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 515070#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 515425#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 515051#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 514883#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 514884#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 514866#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 514867#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 515424#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 515196#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 515197#L769 assume !(0 == ~M_E~0); 515219#L769-2 assume !(0 == ~T1_E~0); 515220#L774-1 assume !(0 == ~T2_E~0); 515255#L779-1 assume !(0 == ~T3_E~0); 515406#L784-1 assume !(0 == ~T4_E~0); 515192#L789-1 assume !(0 == ~T5_E~0); 515193#L794-1 assume !(0 == ~T6_E~0); 515324#L799-1 assume !(0 == ~T7_E~0); 515199#L804-1 assume !(0 == ~E_M~0); 515200#L809-1 assume !(0 == ~E_1~0); 515245#L814-1 assume !(0 == ~E_2~0); 514607#L819-1 assume !(0 == ~E_3~0); 514608#L824-1 assume !(0 == ~E_4~0); 514951#L829-1 assume !(0 == ~E_5~0); 515495#L834-1 assume !(0 == ~E_6~0); 514737#L839-1 assume !(0 == ~E_7~0); 514738#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 515136#L376 assume !(1 == ~m_pc~0); 515117#L376-2 is_master_triggered_~__retres1~0#1 := 0; 515116#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 515465#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 514687#L955 assume !(0 != activate_threads_~tmp~1#1); 514688#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 515044#L395 assume !(1 == ~t1_pc~0); 515222#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 515389#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514613#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 514614#L963 assume !(0 != activate_threads_~tmp___0~0#1); 515141#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 515142#L414 assume !(1 == ~t2_pc~0); 514740#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 514741#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 514937#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 514938#L971 assume !(0 != activate_threads_~tmp___1~0#1); 515431#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 515047#L433 assume !(1 == ~t3_pc~0); 514854#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 514855#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 515013#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 515014#L979 assume !(0 != activate_threads_~tmp___2~0#1); 514708#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 514709#L452 assume !(1 == ~t4_pc~0); 514862#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 514863#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 515177#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 515254#L987 assume !(0 != activate_threads_~tmp___3~0#1); 514894#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 514895#L471 assume !(1 == ~t5_pc~0); 515303#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 514877#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 514878#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 515246#L995 assume !(0 != activate_threads_~tmp___4~0#1); 515484#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 515485#L490 assume !(1 == ~t6_pc~0); 515139#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 515140#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 515184#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 515188#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 515057#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 515024#L509 assume !(1 == ~t7_pc~0); 515025#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 514836#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 514837#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 514899#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 514900#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515442#L857 assume !(1 == ~M_E~0); 514694#L857-2 assume !(1 == ~T1_E~0); 514695#L862-1 assume !(1 == ~T2_E~0); 514961#L867-1 assume !(1 == ~T3_E~0); 514966#L872-1 assume !(1 == ~T4_E~0); 515048#L877-1 assume !(1 == ~T5_E~0); 515278#L882-1 assume !(1 == ~T6_E~0); 515457#L887-1 assume !(1 == ~T7_E~0); 515348#L892-1 assume !(1 == ~E_M~0); 515349#L897-1 assume !(1 == ~E_1~0); 514977#L902-1 assume !(1 == ~E_2~0); 514978#L907-1 assume !(1 == ~E_3~0); 515297#L912-1 assume !(1 == ~E_4~0); 515286#L917-1 assume !(1 == ~E_5~0); 515287#L922-1 assume !(1 == ~E_6~0); 515501#L927-1 assume !(1 == ~E_7~0); 515273#L932-1 assume { :end_inline_reset_delta_events } true; 515274#L1178-2 [2021-12-15 17:20:42,755 INFO L793 eck$LassoCheckResult]: Loop: 515274#L1178-2 assume !false; 530982#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 530980#L744 assume !false; 530978#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 530976#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 530963#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 530956#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 530951#L641 assume !(0 != eval_~tmp~0#1); 530952#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 532905#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 532902#L769-3 assume !(0 == ~M_E~0); 532900#L769-5 assume !(0 == ~T1_E~0); 532896#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 532894#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 532892#L784-3 assume !(0 == ~T4_E~0); 532890#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 532888#L794-3 assume !(0 == ~T6_E~0); 532886#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 532885#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 532882#L809-3 assume !(0 == ~E_1~0); 532879#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 532876#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 532873#L824-3 assume !(0 == ~E_4~0); 532870#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 532867#L834-3 assume !(0 == ~E_6~0); 532864#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 532862#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 532859#L376-27 assume !(1 == ~m_pc~0); 532854#L376-29 is_master_triggered_~__retres1~0#1 := 0; 532851#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 532849#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 532847#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 532844#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 532841#L395-27 assume !(1 == ~t1_pc~0); 532837#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 532833#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 532830#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 532827#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 532825#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 532822#L414-27 assume !(1 == ~t2_pc~0); 532817#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 532814#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 532811#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 532808#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 532806#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 532804#L433-27 assume !(1 == ~t3_pc~0); 527640#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 532798#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 532795#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 532792#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 532789#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 532787#L452-27 assume !(1 == ~t4_pc~0); 532784#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 532781#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 532779#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 532778#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 532777#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 532776#L471-27 assume !(1 == ~t5_pc~0); 525600#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 533219#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 533217#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 533215#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 533213#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 533211#L490-27 assume !(1 == ~t6_pc~0); 525049#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 533207#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 533205#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 533203#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 533202#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 533201#L509-27 assume !(1 == ~t7_pc~0); 533199#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 533197#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 533195#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 533194#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 533192#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533191#L857-3 assume !(1 == ~M_E~0); 521213#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 533190#L862-3 assume !(1 == ~T2_E~0); 533189#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 533188#L872-3 assume !(1 == ~T4_E~0); 533187#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 533186#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 533185#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 533184#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 533182#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 533180#L902-3 assume !(1 == ~E_2~0); 533178#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 533177#L912-3 assume !(1 == ~E_4~0); 533176#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 532378#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 532359#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 532358#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 532354#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 515326#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 515327#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 515035#L1197 assume !(0 == start_simulation_~tmp~3#1); 515036#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 531060#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 531051#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 531044#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 531038#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 531033#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 531027#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 531021#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 515274#L1178-2 [2021-12-15 17:20:42,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2021-12-15 17:20:42,755 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,756 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327947067] [2021-12-15 17:20:42,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:42,763 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:42,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:42,798 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:42,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,799 INFO L85 PathProgramCache]: Analyzing trace with hash 565272940, now seen corresponding path program 1 times [2021-12-15 17:20:42,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518504894] [2021-12-15 17:20:42,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,799 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:42,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:42,819 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:42,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518504894] [2021-12-15 17:20:42,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518504894] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:42,820 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:42,820 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:42,820 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156087974] [2021-12-15 17:20:42,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:42,820 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:42,820 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:42,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:42,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:42,821 INFO L87 Difference]: Start difference. First operand 18790 states and 26510 transitions. cyclomatic complexity: 7722 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:42,877 INFO L93 Difference]: Finished difference Result 21230 states and 29919 transitions. [2021-12-15 17:20:42,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:42,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21230 states and 29919 transitions. [2021-12-15 17:20:42,951 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21040 [2021-12-15 17:20:42,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21230 states to 21230 states and 29919 transitions. [2021-12-15 17:20:42,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21230 [2021-12-15 17:20:43,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21230 [2021-12-15 17:20:43,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21230 states and 29919 transitions. [2021-12-15 17:20:43,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,025 INFO L681 BuchiCegarLoop]: Abstraction has 21230 states and 29919 transitions. [2021-12-15 17:20:43,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21230 states and 29919 transitions. [2021-12-15 17:20:43,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21230 to 21230. [2021-12-15 17:20:43,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21230 states, 21230 states have (on average 1.409279321714555) internal successors, (29919), 21229 states have internal predecessors, (29919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21230 states to 21230 states and 29919 transitions. [2021-12-15 17:20:43,296 INFO L704 BuchiCegarLoop]: Abstraction has 21230 states and 29919 transitions. [2021-12-15 17:20:43,296 INFO L587 BuchiCegarLoop]: Abstraction has 21230 states and 29919 transitions. [2021-12-15 17:20:43,296 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:20:43,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21230 states and 29919 transitions. [2021-12-15 17:20:43,347 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21040 [2021-12-15 17:20:43,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,349 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,349 INFO L791 eck$LassoCheckResult]: Stem: 555309#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 555310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 555162#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 555098#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 555099#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 555466#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 555081#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 554910#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 554911#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 554893#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 554894#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 555465#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 555232#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 555233#L769 assume !(0 == ~M_E~0); 555255#L769-2 assume !(0 == ~T1_E~0); 555256#L774-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 555300#L779-1 assume !(0 == ~T3_E~0); 555444#L784-1 assume !(0 == ~T4_E~0); 555445#L789-1 assume !(0 == ~T5_E~0); 555684#L794-1 assume !(0 == ~T6_E~0); 555683#L799-1 assume !(0 == ~T7_E~0); 555235#L804-1 assume !(0 == ~E_M~0); 555236#L809-1 assume !(0 == ~E_1~0); 555475#L814-1 assume !(0 == ~E_2~0); 555476#L819-1 assume !(0 == ~E_3~0); 554983#L824-1 assume !(0 == ~E_4~0); 554984#L829-1 assume !(0 == ~E_5~0); 555548#L834-1 assume !(0 == ~E_6~0); 555549#L839-1 assume !(0 == ~E_7~0); 555682#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 555169#L376 assume !(1 == ~m_pc~0); 555170#L376-2 is_master_triggered_~__retres1~0#1 := 0; 555617#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 555618#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 554712#L955 assume !(0 != activate_threads_~tmp~1#1); 554713#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 555073#L395 assume !(1 == ~t1_pc~0); 555428#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 555429#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 554639#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 554640#L963 assume !(0 != activate_threads_~tmp___0~0#1); 555175#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 555176#L414 assume !(1 == ~t2_pc~0); 555654#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 555679#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 554968#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 554969#L971 assume !(0 != activate_threads_~tmp___1~0#1); 555559#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 555076#L433 assume !(1 == ~t3_pc~0); 555077#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 555572#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 555045#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 555046#L979 assume !(0 != activate_threads_~tmp___2~0#1); 554733#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 554734#L452 assume !(1 == ~t4_pc~0); 554889#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 554890#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 555298#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555299#L987 assume !(0 != activate_threads_~tmp___3~0#1); 554921#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 554922#L471 assume !(1 == ~t5_pc~0); 555347#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 554904#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 554905#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 555288#L995 assume !(0 != activate_threads_~tmp___4~0#1); 555647#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 555595#L490 assume !(1 == ~t6_pc~0); 555596#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 555221#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 555222#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 555351#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 555669#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 555668#L509 assume !(1 == ~t7_pc~0); 555479#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 555667#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 555665#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 554926#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 554927#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 555487#L857 assume !(1 == ~M_E~0); 554719#L857-2 assume !(1 == ~T1_E~0); 554720#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 554993#L867-1 assume !(1 == ~T3_E~0); 554998#L872-1 assume !(1 == ~T4_E~0); 555078#L877-1 assume !(1 == ~T5_E~0); 555321#L882-1 assume !(1 == ~T6_E~0); 555504#L887-1 assume !(1 == ~T7_E~0); 555391#L892-1 assume !(1 == ~E_M~0); 555392#L897-1 assume !(1 == ~E_1~0); 555009#L902-1 assume !(1 == ~E_2~0); 555010#L907-1 assume !(1 == ~E_3~0); 555340#L912-1 assume !(1 == ~E_4~0); 555330#L917-1 assume !(1 == ~E_5~0); 555331#L922-1 assume !(1 == ~E_6~0); 555554#L927-1 assume !(1 == ~E_7~0); 555316#L932-1 assume { :end_inline_reset_delta_events } true; 555317#L1178-2 [2021-12-15 17:20:43,350 INFO L793 eck$LassoCheckResult]: Loop: 555317#L1178-2 assume !false; 564238#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 564235#L744 assume !false; 564233#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 564231#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 564223#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 564222#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 564220#L641 assume !(0 != eval_~tmp~0#1); 564221#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 568089#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 568087#L769-3 assume !(0 == ~M_E~0); 568084#L769-5 assume !(0 == ~T1_E~0); 568081#L774-3 assume !(0 == ~T2_E~0); 568079#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 568077#L784-3 assume !(0 == ~T4_E~0); 568075#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 568073#L794-3 assume !(0 == ~T6_E~0); 568071#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 568069#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 568067#L809-3 assume !(0 == ~E_1~0); 568065#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 568064#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 568063#L824-3 assume !(0 == ~E_4~0); 568062#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 568061#L834-3 assume !(0 == ~E_6~0); 568060#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 568058#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 568056#L376-27 assume !(1 == ~m_pc~0); 568053#L376-29 is_master_triggered_~__retres1~0#1 := 0; 568051#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 568049#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 568047#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 568045#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 568043#L395-27 assume !(1 == ~t1_pc~0); 568041#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 568039#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 568037#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567994#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 567986#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567978#L414-27 assume !(1 == ~t2_pc~0); 567961#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 567948#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567939#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567929#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 567920#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567797#L433-27 assume !(1 == ~t3_pc~0); 567792#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 567788#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567555#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567551#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 567549#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567547#L452-27 assume !(1 == ~t4_pc~0); 567543#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 567541#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567491#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567485#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 567480#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 565227#L471-27 assume !(1 == ~t5_pc~0); 565225#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 565223#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 565209#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 565203#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 565199#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 564514#L490-27 assume !(1 == ~t6_pc~0); 564512#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 564510#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 564507#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 564505#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 564503#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 564501#L509-27 assume !(1 == ~t7_pc~0); 564497#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 564495#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 564493#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 564491#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 564488#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 564486#L857-3 assume !(1 == ~M_E~0); 564483#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 564442#L862-3 assume !(1 == ~T2_E~0); 564440#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 564438#L872-3 assume !(1 == ~T4_E~0); 564437#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 564435#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 564433#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 564431#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 564429#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 564425#L902-3 assume !(1 == ~E_2~0); 564423#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 564421#L912-3 assume !(1 == ~E_4~0); 564419#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 564416#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 564414#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 564411#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 564401#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 564395#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 564393#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 564377#L1197 assume !(0 == start_simulation_~tmp~3#1); 564375#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 564363#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 564357#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 564355#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 564352#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 564350#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 564349#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 564348#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 555317#L1178-2 [2021-12-15 17:20:43,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,350 INFO L85 PathProgramCache]: Analyzing trace with hash -243852155, now seen corresponding path program 1 times [2021-12-15 17:20:43,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184859697] [2021-12-15 17:20:43,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,370 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,370 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184859697] [2021-12-15 17:20:43,370 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184859697] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,371 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,371 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,371 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029033811] [2021-12-15 17:20:43,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,371 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:43,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,372 INFO L85 PathProgramCache]: Analyzing trace with hash 536772650, now seen corresponding path program 1 times [2021-12-15 17:20:43,372 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948393107] [2021-12-15 17:20:43,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,372 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,389 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948393107] [2021-12-15 17:20:43,389 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948393107] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,389 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,389 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,389 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502079493] [2021-12-15 17:20:43,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,390 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:43,390 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:43,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:43,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:43,390 INFO L87 Difference]: Start difference. First operand 21230 states and 29919 transitions. cyclomatic complexity: 8691 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:43,483 INFO L93 Difference]: Finished difference Result 27420 states and 38558 transitions. [2021-12-15 17:20:43,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:43,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27420 states and 38558 transitions. [2021-12-15 17:20:43,594 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27280 [2021-12-15 17:20:43,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27420 states to 27420 states and 38558 transitions. [2021-12-15 17:20:43,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27420 [2021-12-15 17:20:43,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27420 [2021-12-15 17:20:43,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27420 states and 38558 transitions. [2021-12-15 17:20:43,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,701 INFO L681 BuchiCegarLoop]: Abstraction has 27420 states and 38558 transitions. [2021-12-15 17:20:43,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27420 states and 38558 transitions. [2021-12-15 17:20:43,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27420 to 18790. [2021-12-15 17:20:43,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18790 states, 18790 states have (on average 1.4091005854177754) internal successors, (26477), 18789 states have internal predecessors, (26477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18790 states to 18790 states and 26477 transitions. [2021-12-15 17:20:43,892 INFO L704 BuchiCegarLoop]: Abstraction has 18790 states and 26477 transitions. [2021-12-15 17:20:43,892 INFO L587 BuchiCegarLoop]: Abstraction has 18790 states and 26477 transitions. [2021-12-15 17:20:43,893 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:20:43,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18790 states and 26477 transitions. [2021-12-15 17:20:43,940 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18672 [2021-12-15 17:20:43,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,942 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,942 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,943 INFO L791 eck$LassoCheckResult]: Stem: 603944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 603945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 603815#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 603756#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 603757#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 604101#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 603734#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 603570#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 603571#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 603552#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 603553#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 604098#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 603878#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 603879#L769 assume !(0 == ~M_E~0); 603903#L769-2 assume !(0 == ~T1_E~0); 603904#L774-1 assume !(0 == ~T2_E~0); 603936#L779-1 assume !(0 == ~T3_E~0); 604081#L784-1 assume !(0 == ~T4_E~0); 603873#L789-1 assume !(0 == ~T5_E~0); 603874#L794-1 assume !(0 == ~T6_E~0); 604001#L799-1 assume !(0 == ~T7_E~0); 603880#L804-1 assume !(0 == ~E_M~0); 603881#L809-1 assume !(0 == ~E_1~0); 603929#L814-1 assume !(0 == ~E_2~0); 603297#L819-1 assume !(0 == ~E_3~0); 603298#L824-1 assume !(0 == ~E_4~0); 603639#L829-1 assume !(0 == ~E_5~0); 604171#L834-1 assume !(0 == ~E_6~0); 603423#L839-1 assume !(0 == ~E_7~0); 603424#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 603823#L376 assume !(1 == ~m_pc~0); 603811#L376-2 is_master_triggered_~__retres1~0#1 := 0; 603810#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 604139#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 603375#L955 assume !(0 != activate_threads_~tmp~1#1); 603376#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 603727#L395 assume !(1 == ~t1_pc~0); 603905#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 604065#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 603301#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 603302#L963 assume !(0 != activate_threads_~tmp___0~0#1); 603829#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 603830#L414 assume !(1 == ~t2_pc~0); 603426#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 603427#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 603625#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 603626#L971 assume !(0 != activate_threads_~tmp___1~0#1); 604109#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 603730#L433 assume !(1 == ~t3_pc~0); 603542#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 603543#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 603699#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 603700#L979 assume !(0 != activate_threads_~tmp___2~0#1); 603395#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 603396#L452 assume !(1 == ~t4_pc~0); 603548#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 603549#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 603862#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 603935#L987 assume !(0 != activate_threads_~tmp___3~0#1); 603581#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 603582#L471 assume !(1 == ~t5_pc~0); 603984#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 603564#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 603565#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 603930#L995 assume !(0 != activate_threads_~tmp___4~0#1); 604158#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 604159#L490 assume !(1 == ~t6_pc~0); 603826#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 603827#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 603870#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 603872#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 603744#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 603705#L509 assume !(1 == ~t7_pc~0); 603706#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 603526#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 603527#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 603586#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 603587#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 604119#L857 assume !(1 == ~M_E~0); 603380#L857-2 assume !(1 == ~T1_E~0); 603381#L862-1 assume !(1 == ~T2_E~0); 603647#L867-1 assume !(1 == ~T3_E~0); 603652#L872-1 assume !(1 == ~T4_E~0); 603731#L877-1 assume !(1 == ~T5_E~0); 603956#L882-1 assume !(1 == ~T6_E~0); 604130#L887-1 assume !(1 == ~T7_E~0); 604020#L892-1 assume !(1 == ~E_M~0); 604021#L897-1 assume !(1 == ~E_1~0); 603664#L902-1 assume !(1 == ~E_2~0); 603665#L907-1 assume !(1 == ~E_3~0); 603978#L912-1 assume !(1 == ~E_4~0); 603965#L917-1 assume !(1 == ~E_5~0); 603966#L922-1 assume !(1 == ~E_6~0); 604174#L927-1 assume !(1 == ~E_7~0); 603951#L932-1 assume { :end_inline_reset_delta_events } true; 603952#L1178-2 [2021-12-15 17:20:43,943 INFO L793 eck$LassoCheckResult]: Loop: 603952#L1178-2 assume !false; 618625#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 618623#L744 assume !false; 618621#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 618619#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 618610#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 618608#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 618605#L641 assume !(0 != eval_~tmp~0#1); 618606#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 621778#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 621776#L769-3 assume !(0 == ~M_E~0); 621774#L769-5 assume !(0 == ~T1_E~0); 621771#L774-3 assume !(0 == ~T2_E~0); 621769#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 621767#L784-3 assume !(0 == ~T4_E~0); 621762#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 621758#L794-3 assume !(0 == ~T6_E~0); 621751#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 621742#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 621739#L809-3 assume !(0 == ~E_1~0); 621736#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 621734#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 621730#L824-3 assume !(0 == ~E_4~0); 621723#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 621718#L834-3 assume !(0 == ~E_6~0); 621713#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 621707#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 621702#L376-27 assume 1 == ~m_pc~0; 621697#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 621690#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 621685#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 621680#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 621672#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 604246#L395-27 assume !(1 == ~t1_pc~0); 604247#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 621888#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 621886#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 621885#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 603735#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 603736#L414-27 assume 1 == ~t2_pc~0; 604153#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 603963#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 603964#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 603805#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 603357#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 603358#L433-27 assume !(1 == ~t3_pc~0); 603449#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 603742#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 603743#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 603523#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 603524#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 604215#L452-27 assume !(1 == ~t4_pc~0); 603924#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 603925#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 604087#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 604145#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 604146#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 604157#L471-27 assume !(1 == ~t5_pc~0); 619049#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 619047#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 619045#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 619043#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 618996#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 616159#L490-27 assume !(1 == ~t6_pc~0); 616158#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 616157#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 616155#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 616154#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 616153#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 616152#L509-27 assume 1 == ~t7_pc~0; 616151#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 616149#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 616147#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 616144#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 616143#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 616142#L857-3 assume !(1 == ~M_E~0); 610699#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 616139#L862-3 assume !(1 == ~T2_E~0); 616137#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 616135#L872-3 assume !(1 == ~T4_E~0); 616133#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 616131#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 616128#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 616126#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 616124#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 616122#L902-3 assume !(1 == ~E_2~0); 616120#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 616118#L912-3 assume !(1 == ~E_4~0); 616115#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 616114#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 615174#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 615171#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 615020#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 614063#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 614059#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 610804#L1197 assume !(0 == start_simulation_~tmp~3#1); 610805#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 618650#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 618644#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 618641#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 618639#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 618638#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 618637#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 618633#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 603952#L1178-2 [2021-12-15 17:20:43,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,944 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2021-12-15 17:20:43,944 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093073232] [2021-12-15 17:20:43,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:43,951 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:43,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:43,971 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:43,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,972 INFO L85 PathProgramCache]: Analyzing trace with hash 248394661, now seen corresponding path program 1 times [2021-12-15 17:20:43,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547742057] [2021-12-15 17:20:43,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,988 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547742057] [2021-12-15 17:20:43,988 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547742057] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,988 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,988 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054888811] [2021-12-15 17:20:43,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,989 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:43,989 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:43,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:43,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:43,990 INFO L87 Difference]: Start difference. First operand 18790 states and 26477 transitions. cyclomatic complexity: 7689 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,205 INFO L93 Difference]: Finished difference Result 35054 states and 48830 transitions. [2021-12-15 17:20:44,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:44,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35054 states and 48830 transitions. [2021-12-15 17:20:44,338 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 34848 [2021-12-15 17:20:44,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35054 states to 35054 states and 48830 transitions. [2021-12-15 17:20:44,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35054 [2021-12-15 17:20:44,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35054 [2021-12-15 17:20:44,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35054 states and 48830 transitions. [2021-12-15 17:20:44,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,458 INFO L681 BuchiCegarLoop]: Abstraction has 35054 states and 48830 transitions. [2021-12-15 17:20:44,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35054 states and 48830 transitions. [2021-12-15 17:20:44,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35054 to 35038. [2021-12-15 17:20:44,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35038 states, 35038 states have (on average 1.3931731263199953) internal successors, (48814), 35037 states have internal predecessors, (48814), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35038 states to 35038 states and 48814 transitions. [2021-12-15 17:20:44,748 INFO L704 BuchiCegarLoop]: Abstraction has 35038 states and 48814 transitions. [2021-12-15 17:20:44,748 INFO L587 BuchiCegarLoop]: Abstraction has 35038 states and 48814 transitions. [2021-12-15 17:20:44,748 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-15 17:20:44,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35038 states and 48814 transitions. [2021-12-15 17:20:44,842 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 34832 [2021-12-15 17:20:44,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,846 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,846 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,846 INFO L791 eck$LassoCheckResult]: Stem: 657822#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 657823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 657676#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 657612#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 657613#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 657978#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 657592#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 657419#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 657420#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 657401#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 657402#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 657977#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 657750#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 657751#L769 assume !(0 == ~M_E~0); 657774#L769-2 assume !(0 == ~T1_E~0); 657775#L774-1 assume !(0 == ~T2_E~0); 657812#L779-1 assume !(0 == ~T3_E~0); 657957#L784-1 assume !(0 == ~T4_E~0); 657745#L789-1 assume !(0 == ~T5_E~0); 657746#L794-1 assume !(0 == ~T6_E~0); 657874#L799-1 assume !(0 == ~T7_E~0); 657753#L804-1 assume !(0 == ~E_M~0); 657754#L809-1 assume !(0 == ~E_1~0); 657799#L814-1 assume 0 == ~E_2~0;~E_2~0 := 1; 657988#L819-1 assume !(0 == ~E_3~0); 657488#L824-1 assume !(0 == ~E_4~0); 657489#L829-1 assume !(0 == ~E_5~0); 658171#L834-1 assume !(0 == ~E_6~0); 657272#L839-1 assume !(0 == ~E_7~0); 657273#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 657880#L376 assume !(1 == ~m_pc~0); 657667#L376-2 is_master_triggered_~__retres1~0#1 := 0; 657666#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 658032#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 658033#L955 assume !(0 != activate_threads_~tmp~1#1); 658190#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 657778#L395 assume !(1 == ~t1_pc~0); 657779#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 657958#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 657959#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 658003#L963 assume !(0 != activate_threads_~tmp___0~0#1); 658004#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 658187#L414 assume !(1 == ~t2_pc~0); 657987#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 657275#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 658175#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 657985#L971 assume !(0 != activate_threads_~tmp___1~0#1); 657986#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 658206#L433 assume !(1 == ~t3_pc~0); 657389#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 657390#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 658205#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 658204#L979 assume !(0 != activate_threads_~tmp___2~0#1); 658203#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 658160#L452 assume !(1 == ~t4_pc~0); 658146#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 657727#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 657728#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 657811#L987 assume !(0 != activate_threads_~tmp___3~0#1); 657430#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 657431#L471 assume !(1 == ~t5_pc~0); 657858#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 657413#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 657414#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 658199#L995 assume !(0 != activate_threads_~tmp___4~0#1); 658050#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 658051#L490 assume !(1 == ~t6_pc~0); 657688#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 657689#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 658197#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 657742#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 657599#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 657564#L509 assume !(1 == ~t7_pc~0); 657565#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 657372#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 657373#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 658183#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 658089#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 658090#L857 assume !(1 == ~M_E~0); 657231#L857-2 assume !(1 == ~T1_E~0); 657232#L862-1 assume !(1 == ~T2_E~0); 657505#L867-1 assume !(1 == ~T3_E~0); 657506#L872-1 assume !(1 == ~T4_E~0); 657589#L877-1 assume !(1 == ~T5_E~0); 657834#L882-1 assume !(1 == ~T6_E~0); 658134#L887-1 assume !(1 == ~T7_E~0); 657897#L892-1 assume !(1 == ~E_M~0); 657898#L897-1 assume !(1 == ~E_1~0); 657516#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 657517#L907-1 assume !(1 == ~E_3~0); 657850#L912-1 assume !(1 == ~E_4~0); 657842#L917-1 assume !(1 == ~E_5~0); 657843#L922-1 assume !(1 == ~E_6~0); 658071#L927-1 assume !(1 == ~E_7~0); 657829#L932-1 assume { :end_inline_reset_delta_events } true; 657830#L1178-2 [2021-12-15 17:20:44,846 INFO L793 eck$LassoCheckResult]: Loop: 657830#L1178-2 assume !false; 682717#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 682707#L744 assume !false; 682699#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 682691#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 682682#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 682680#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 682678#L641 assume !(0 != eval_~tmp~0#1); 682679#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 683867#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 683865#L769-3 assume !(0 == ~M_E~0); 683863#L769-5 assume !(0 == ~T1_E~0); 683861#L774-3 assume !(0 == ~T2_E~0); 683859#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 683858#L784-3 assume !(0 == ~T4_E~0); 683856#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 683854#L794-3 assume !(0 == ~T6_E~0); 683852#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 683850#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 683848#L809-3 assume !(0 == ~E_1~0); 683845#L814-3 assume !(0 == ~E_2~0); 683842#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 683840#L824-3 assume !(0 == ~E_4~0); 683838#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 683836#L834-3 assume !(0 == ~E_6~0); 683834#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 683832#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 683830#L376-27 assume !(1 == ~m_pc~0); 683827#L376-29 is_master_triggered_~__retres1~0#1 := 0; 683825#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 683823#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 683821#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 683819#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 683816#L395-27 assume !(1 == ~t1_pc~0); 683815#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 683813#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 683811#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 683809#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 683807#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 683806#L414-27 assume !(1 == ~t2_pc~0); 683800#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 683798#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 683796#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 683794#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 683791#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 683789#L433-27 assume !(1 == ~t3_pc~0); 681343#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 683771#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 683762#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 683753#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 683748#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 683546#L452-27 assume !(1 == ~t4_pc~0); 683543#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 683541#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 683539#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 683537#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 683535#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 683507#L471-27 assume !(1 == ~t5_pc~0); 674531#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 683493#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 683483#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 683476#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 683470#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 683462#L490-27 assume !(1 == ~t6_pc~0); 669866#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 683449#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 683441#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 683433#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 683423#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 683305#L509-27 assume !(1 == ~t7_pc~0); 683298#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 683290#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 683281#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 683272#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 683263#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 683256#L857-3 assume !(1 == ~M_E~0); 678911#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 683243#L862-3 assume !(1 == ~T2_E~0); 683235#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 683225#L872-3 assume !(1 == ~T4_E~0); 683217#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 683209#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 683202#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 683195#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 683188#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 683181#L902-3 assume !(1 == ~E_2~0); 683174#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 683167#L912-3 assume !(1 == ~E_4~0); 683160#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 683153#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 682912#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 682909#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 682842#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 682831#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 682823#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 682816#L1197 assume !(0 == start_simulation_~tmp~3#1); 682812#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 682782#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 682771#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 682752#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 682751#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 682750#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 682746#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 682744#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 657830#L1178-2 [2021-12-15 17:20:44,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,847 INFO L85 PathProgramCache]: Analyzing trace with hash -223159163, now seen corresponding path program 1 times [2021-12-15 17:20:44,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418096257] [2021-12-15 17:20:44,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,847 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418096257] [2021-12-15 17:20:44,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418096257] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,863 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536078346] [2021-12-15 17:20:44,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,864 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1342358296, now seen corresponding path program 1 times [2021-12-15 17:20:44,864 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810328180] [2021-12-15 17:20:44,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,886 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810328180] [2021-12-15 17:20:44,886 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810328180] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,886 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,886 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:44,886 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466866468] [2021-12-15 17:20:44,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,887 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,887 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:44,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:44,887 INFO L87 Difference]: Start difference. First operand 35038 states and 48814 transitions. cyclomatic complexity: 13778 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:45,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:45,347 INFO L93 Difference]: Finished difference Result 50766 states and 70561 transitions. [2021-12-15 17:20:45,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:45,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50766 states and 70561 transitions. [2021-12-15 17:20:45,557 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 49160 [2021-12-15 17:20:45,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50766 states to 50766 states and 70561 transitions. [2021-12-15 17:20:45,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50766 [2021-12-15 17:20:45,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50766 [2021-12-15 17:20:45,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50766 states and 70561 transitions. [2021-12-15 17:20:45,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:45,754 INFO L681 BuchiCegarLoop]: Abstraction has 50766 states and 70561 transitions. [2021-12-15 17:20:45,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50766 states and 70561 transitions. [2021-12-15 17:20:46,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50766 to 35016. [2021-12-15 17:20:46,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35016 states, 35016 states have (on average 1.3922492574822938) internal successors, (48751), 35015 states have internal predecessors, (48751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:46,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35016 states to 35016 states and 48751 transitions. [2021-12-15 17:20:46,089 INFO L704 BuchiCegarLoop]: Abstraction has 35016 states and 48751 transitions. [2021-12-15 17:20:46,089 INFO L587 BuchiCegarLoop]: Abstraction has 35016 states and 48751 transitions. [2021-12-15 17:20:46,089 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-15 17:20:46,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35016 states and 48751 transitions. [2021-12-15 17:20:46,298 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 34832 [2021-12-15 17:20:46,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:46,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:46,301 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:46,302 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:46,302 INFO L791 eck$LassoCheckResult]: Stem: 743643#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 743644#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 743500#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 743435#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 743436#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 743823#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 743415#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 743235#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 743236#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 743217#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 743218#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 743822#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 743574#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 743575#L769 assume !(0 == ~M_E~0); 743596#L769-2 assume !(0 == ~T1_E~0); 743597#L774-1 assume !(0 == ~T2_E~0); 743635#L779-1 assume !(0 == ~T3_E~0); 743796#L784-1 assume !(0 == ~T4_E~0); 743570#L789-1 assume !(0 == ~T5_E~0); 743571#L794-1 assume !(0 == ~T6_E~0); 743706#L799-1 assume !(0 == ~T7_E~0); 743577#L804-1 assume !(0 == ~E_M~0); 743578#L809-1 assume !(0 == ~E_1~0); 743620#L814-1 assume !(0 == ~E_2~0); 742959#L819-1 assume !(0 == ~E_3~0); 742960#L824-1 assume !(0 == ~E_4~0); 743309#L829-1 assume !(0 == ~E_5~0); 743925#L834-1 assume !(0 == ~E_6~0); 743086#L839-1 assume !(0 == ~E_7~0); 743087#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 743507#L376 assume !(1 == ~m_pc~0); 743490#L376-2 is_master_triggered_~__retres1~0#1 := 0; 743489#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 743886#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 743039#L955 assume !(0 != activate_threads_~tmp~1#1); 743040#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 743404#L395 assume !(1 == ~t1_pc~0); 743599#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 743777#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 742965#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 742966#L963 assume !(0 != activate_threads_~tmp___0~0#1); 743513#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 743514#L414 assume !(1 == ~t2_pc~0); 743089#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 743834#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 744040#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 743831#L971 assume !(0 != activate_threads_~tmp___1~0#1); 743832#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743409#L433 assume !(1 == ~t3_pc~0); 743410#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 743950#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 743951#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 744062#L979 assume !(0 != activate_threads_~tmp___2~0#1); 743059#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 743060#L452 assume !(1 == ~t4_pc~0); 743213#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 743214#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 743633#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 743634#L987 assume !(0 != activate_threads_~tmp___3~0#1); 743246#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743247#L471 assume !(1 == ~t5_pc~0); 743973#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 743974#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 743621#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 743622#L995 assume !(0 != activate_threads_~tmp___4~0#1); 743912#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 743913#L490 assume !(1 == ~t6_pc~0); 743510#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 743511#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 743690#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 743691#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 743421#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 743422#L509 assume !(1 == ~t7_pc~0); 743835#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 743836#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 744057#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 744058#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 743948#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 743949#L857 assume !(1 == ~M_E~0); 743046#L857-2 assume !(1 == ~T1_E~0); 743047#L862-1 assume !(1 == ~T2_E~0); 743326#L867-1 assume !(1 == ~T3_E~0); 743327#L872-1 assume !(1 == ~T4_E~0); 743656#L877-1 assume !(1 == ~T5_E~0); 743657#L882-1 assume !(1 == ~T6_E~0); 743988#L887-1 assume !(1 == ~T7_E~0); 743989#L892-1 assume !(1 == ~E_M~0); 743960#L897-1 assume !(1 == ~E_1~0); 743961#L902-1 assume !(1 == ~E_2~0); 743338#L907-1 assume !(1 == ~E_3~0); 743677#L912-1 assume !(1 == ~E_4~0); 743666#L917-1 assume !(1 == ~E_5~0); 743667#L922-1 assume !(1 == ~E_6~0); 743929#L927-1 assume !(1 == ~E_7~0); 743651#L932-1 assume { :end_inline_reset_delta_events } true; 743652#L1178-2 [2021-12-15 17:20:46,302 INFO L793 eck$LassoCheckResult]: Loop: 743652#L1178-2 assume !false; 773708#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 773701#L744 assume !false; 772975#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 772811#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 772798#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 772766#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 772758#L641 assume !(0 != eval_~tmp~0#1); 772759#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 777853#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 777851#L769-3 assume !(0 == ~M_E~0); 777848#L769-5 assume !(0 == ~T1_E~0); 777846#L774-3 assume !(0 == ~T2_E~0); 777844#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 777841#L784-3 assume !(0 == ~T4_E~0); 777839#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 777837#L794-3 assume !(0 == ~T6_E~0); 777835#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 777833#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 777831#L809-3 assume !(0 == ~E_1~0); 777828#L814-3 assume !(0 == ~E_2~0); 777826#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 777824#L824-3 assume !(0 == ~E_4~0); 777822#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 777820#L834-3 assume !(0 == ~E_6~0); 777783#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 777782#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 777775#L376-27 assume 1 == ~m_pc~0; 777713#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 777710#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 777708#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 777702#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 777696#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 777690#L395-27 assume !(1 == ~t1_pc~0); 777680#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 777679#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 777678#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 777676#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 777674#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 777670#L414-27 assume !(1 == ~t2_pc~0); 777666#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 777663#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 777660#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 777658#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 777657#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743112#L433-27 assume !(1 == ~t3_pc~0); 743113#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 743424#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 743425#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 743188#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 743189#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 744000#L452-27 assume !(1 == ~t4_pc~0); 777668#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 743801#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 743802#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 743898#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 743899#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 774929#L471-27 assume !(1 == ~t5_pc~0); 774927#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 774924#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 774922#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 774920#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 774918#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 774916#L490-27 assume !(1 == ~t6_pc~0); 771596#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 774913#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 774911#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 774909#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 774907#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 774905#L509-27 assume 1 == ~t7_pc~0; 774903#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 774904#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 774934#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 774895#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 774893#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 774891#L857-3 assume !(1 == ~M_E~0); 753321#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 774888#L862-3 assume !(1 == ~T2_E~0); 774885#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 774884#L872-3 assume !(1 == ~T4_E~0); 774881#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 774879#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 774877#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 774875#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 774873#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 774797#L902-3 assume !(1 == ~E_2~0); 774795#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 774793#L912-3 assume !(1 == ~E_4~0); 774791#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 774788#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 774786#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 774784#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 774773#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 774767#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 774765#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 767196#L1197 assume !(0 == start_simulation_~tmp~3#1); 743770#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 743119#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 743084#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 743405#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 773762#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 773758#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 773757#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 773756#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 743652#L1178-2 [2021-12-15 17:20:46,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:46,303 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2021-12-15 17:20:46,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:46,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731671183] [2021-12-15 17:20:46,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:46,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:46,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:46,309 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:46,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:46,337 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:46,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:46,340 INFO L85 PathProgramCache]: Analyzing trace with hash -1253093468, now seen corresponding path program 1 times [2021-12-15 17:20:46,340 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:46,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580668610] [2021-12-15 17:20:46,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:46,340 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:46,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:46,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:46,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:46,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580668610] [2021-12-15 17:20:46,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580668610] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:46,364 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:46,364 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:46,364 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487405770] [2021-12-15 17:20:46,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:46,365 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:46,365 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:46,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:46,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:46,366 INFO L87 Difference]: Start difference. First operand 35016 states and 48751 transitions. cyclomatic complexity: 13737 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:46,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:46,567 INFO L93 Difference]: Finished difference Result 63928 states and 88271 transitions. [2021-12-15 17:20:46,567 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:46,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63928 states and 88271 transitions. [2021-12-15 17:20:46,849 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 63712 [2021-12-15 17:20:47,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63928 states to 63928 states and 88271 transitions. [2021-12-15 17:20:47,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63928 [2021-12-15 17:20:47,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63928 [2021-12-15 17:20:47,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63928 states and 88271 transitions. [2021-12-15 17:20:47,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:47,121 INFO L681 BuchiCegarLoop]: Abstraction has 63928 states and 88271 transitions. [2021-12-15 17:20:47,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63928 states and 88271 transitions. [2021-12-15 17:20:47,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63928 to 35208. [2021-12-15 17:20:47,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35208 states, 35208 states have (on average 1.3901102022267666) internal successors, (48943), 35207 states have internal predecessors, (48943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:47,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35208 states to 35208 states and 48943 transitions. [2021-12-15 17:20:47,940 INFO L704 BuchiCegarLoop]: Abstraction has 35208 states and 48943 transitions. [2021-12-15 17:20:47,940 INFO L587 BuchiCegarLoop]: Abstraction has 35208 states and 48943 transitions. [2021-12-15 17:20:47,940 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-15 17:20:47,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35208 states and 48943 transitions. [2021-12-15 17:20:48,030 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 35024 [2021-12-15 17:20:48,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:48,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:48,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:48,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:48,034 INFO L791 eck$LassoCheckResult]: Stem: 842599#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 842600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 842455#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 842396#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 842397#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 842755#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 842371#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 842196#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 842197#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 842178#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 842179#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 842754#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 842528#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 842529#L769 assume !(0 == ~M_E~0); 842554#L769-2 assume !(0 == ~T1_E~0); 842555#L774-1 assume !(0 == ~T2_E~0); 842591#L779-1 assume !(0 == ~T3_E~0); 842735#L784-1 assume !(0 == ~T4_E~0); 842522#L789-1 assume !(0 == ~T5_E~0); 842523#L794-1 assume !(0 == ~T6_E~0); 842652#L799-1 assume !(0 == ~T7_E~0); 842530#L804-1 assume !(0 == ~E_M~0); 842531#L809-1 assume !(0 == ~E_1~0); 842578#L814-1 assume !(0 == ~E_2~0); 841923#L819-1 assume !(0 == ~E_3~0); 841924#L824-1 assume !(0 == ~E_4~0); 842264#L829-1 assume !(0 == ~E_5~0); 842837#L834-1 assume !(0 == ~E_6~0); 842045#L839-1 assume !(0 == ~E_7~0); 842046#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 842463#L376 assume !(1 == ~m_pc~0); 842450#L376-2 is_master_triggered_~__retres1~0#1 := 0; 842449#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842802#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 842000#L955 assume !(0 != activate_threads_~tmp~1#1); 842001#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 842362#L395 assume !(1 == ~t1_pc~0); 842556#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 842721#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 841927#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 841928#L963 assume !(0 != activate_threads_~tmp___0~0#1); 842469#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 842470#L414 assume !(1 == ~t2_pc~0); 842048#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 842765#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 842250#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 842251#L971 assume !(0 != activate_threads_~tmp___1~0#1); 842844#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 842366#L433 assume !(1 == ~t3_pc~0); 842367#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 842856#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 842335#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 842336#L979 assume !(0 != activate_threads_~tmp___2~0#1); 842018#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 842019#L452 assume !(1 == ~t4_pc~0); 842174#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 842175#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 842589#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 842590#L987 assume !(0 != activate_threads_~tmp___3~0#1); 842207#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 842208#L471 assume !(1 == ~t5_pc~0); 842635#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 842189#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 842190#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 842943#L995 assume !(0 != activate_threads_~tmp___4~0#1); 842820#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 842821#L490 assume !(1 == ~t6_pc~0); 842465#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 842466#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 842942#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 842520#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 842380#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 842341#L509 assume !(1 == ~t7_pc~0); 842342#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 842152#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 842153#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842212#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 842213#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 842778#L857 assume !(1 == ~M_E~0); 842779#L857-2 assume !(1 == ~T1_E~0); 842274#L862-1 assume !(1 == ~T2_E~0); 842275#L867-1 assume !(1 == ~T3_E~0); 842938#L872-1 assume !(1 == ~T4_E~0); 842937#L877-1 assume !(1 == ~T5_E~0); 842791#L882-1 assume !(1 == ~T6_E~0); 842792#L887-1 assume !(1 == ~T7_E~0); 842936#L892-1 assume !(1 == ~E_M~0); 842864#L897-1 assume !(1 == ~E_1~0); 842865#L902-1 assume !(1 == ~E_2~0); 842296#L907-1 assume !(1 == ~E_3~0); 842630#L912-1 assume !(1 == ~E_4~0); 842621#L917-1 assume !(1 == ~E_5~0); 842622#L922-1 assume !(1 == ~E_6~0); 842840#L927-1 assume !(1 == ~E_7~0); 842607#L932-1 assume { :end_inline_reset_delta_events } true; 842608#L1178-2 [2021-12-15 17:20:48,034 INFO L793 eck$LassoCheckResult]: Loop: 842608#L1178-2 assume !false; 863488#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 863486#L744 assume !false; 863484#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 863482#L584 assume !(0 == ~m_st~0); 863478#L588 assume !(0 == ~t1_st~0); 863479#L592 assume !(0 == ~t2_st~0); 863481#L596 assume !(0 == ~t3_st~0); 863476#L600 assume !(0 == ~t4_st~0); 863477#L604 assume !(0 == ~t5_st~0); 863480#L608 assume !(0 == ~t6_st~0); 863474#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 863472#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 856261#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 856262#L641 assume !(0 != eval_~tmp~0#1); 874782#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 874780#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 874779#L769-3 assume !(0 == ~M_E~0); 874776#L769-5 assume !(0 == ~T1_E~0); 874774#L774-3 assume !(0 == ~T2_E~0); 874772#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 874771#L784-3 assume !(0 == ~T4_E~0); 874472#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 874465#L794-3 assume !(0 == ~T6_E~0); 874464#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 874451#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 874422#L809-3 assume !(0 == ~E_1~0); 874418#L814-3 assume !(0 == ~E_2~0); 874419#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 875498#L824-3 assume !(0 == ~E_4~0); 875496#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 875494#L834-3 assume !(0 == ~E_6~0); 874406#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 874404#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 874402#L376-27 assume !(1 == ~m_pc~0); 874399#L376-29 is_master_triggered_~__retres1~0#1 := 0; 874397#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 874395#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 874392#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 874391#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 874388#L395-27 assume !(1 == ~t1_pc~0); 874386#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 874384#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 874382#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 874380#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 874378#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 874375#L414-27 assume !(1 == ~t2_pc~0); 874377#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 874367#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 874368#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 874363#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 874364#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 873854#L433-27 assume !(1 == ~t3_pc~0); 873855#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 873851#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 873852#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 873845#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 873846#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 873567#L452-27 assume !(1 == ~t4_pc~0); 873566#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 873561#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 873562#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 871270#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 871271#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 863955#L471-27 assume !(1 == ~t5_pc~0); 863956#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 863949#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 863950#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 863942#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 863943#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 863913#L490-27 assume !(1 == ~t6_pc~0); 863909#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 863905#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 863901#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 863897#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 863893#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 863889#L509-27 assume !(1 == ~t7_pc~0); 863883#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 863875#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 863867#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 863859#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 863853#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 863848#L857-3 assume !(1 == ~M_E~0); 863844#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 863842#L862-3 assume !(1 == ~T2_E~0); 863840#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 863838#L872-3 assume !(1 == ~T4_E~0); 863836#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 863834#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 863832#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 863830#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 863828#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 863826#L902-3 assume !(1 == ~E_2~0); 863825#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 863824#L912-3 assume !(1 == ~E_4~0); 863823#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 863822#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 863821#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 863820#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 863816#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 863810#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 863809#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 863807#L1197 assume !(0 == start_simulation_~tmp~3#1); 863667#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 863663#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 863657#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 863654#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 863652#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 863651#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 863650#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 863646#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 842608#L1178-2 [2021-12-15 17:20:48,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:48,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2021-12-15 17:20:48,034 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:48,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750922896] [2021-12-15 17:20:48,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:48,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:48,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:48,040 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:48,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:48,056 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:48,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:48,057 INFO L85 PathProgramCache]: Analyzing trace with hash 1565522552, now seen corresponding path program 1 times [2021-12-15 17:20:48,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:48,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940069336] [2021-12-15 17:20:48,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:48,057 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:48,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:48,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:48,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:48,098 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1940069336] [2021-12-15 17:20:48,098 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1940069336] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:48,098 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:48,098 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:48,098 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135020358] [2021-12-15 17:20:48,098 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:48,098 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:48,099 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:48,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:48,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:48,099 INFO L87 Difference]: Start difference. First operand 35208 states and 48943 transitions. cyclomatic complexity: 13737 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:48,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:48,465 INFO L93 Difference]: Finished difference Result 101523 states and 140014 transitions. [2021-12-15 17:20:48,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:48,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101523 states and 140014 transitions. [2021-12-15 17:20:48,948 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 101040 [2021-12-15 17:20:49,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101523 states to 101523 states and 140014 transitions. [2021-12-15 17:20:49,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101523 [2021-12-15 17:20:49,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101523 [2021-12-15 17:20:49,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101523 states and 140014 transitions. [2021-12-15 17:20:49,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:49,719 INFO L681 BuchiCegarLoop]: Abstraction has 101523 states and 140014 transitions. [2021-12-15 17:20:49,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101523 states and 140014 transitions. [2021-12-15 17:20:50,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101523 to 36555. [2021-12-15 17:20:50,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36555 states, 36555 states have (on average 1.3757351935439748) internal successors, (50290), 36554 states have internal predecessors, (50290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:50,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36555 states to 36555 states and 50290 transitions. [2021-12-15 17:20:50,263 INFO L704 BuchiCegarLoop]: Abstraction has 36555 states and 50290 transitions. [2021-12-15 17:20:50,263 INFO L587 BuchiCegarLoop]: Abstraction has 36555 states and 50290 transitions. [2021-12-15 17:20:50,263 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-15 17:20:50,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36555 states and 50290 transitions. [2021-12-15 17:20:50,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 36368 [2021-12-15 17:20:50,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:50,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:50,365 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:50,365 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:50,365 INFO L791 eck$LassoCheckResult]: Stem: 979333#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 979334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 979194#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 979132#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 979133#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 979504#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 979111#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 978943#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 978944#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 978926#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 978927#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 979503#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 979268#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 979269#L769 assume !(0 == ~M_E~0); 979292#L769-2 assume !(0 == ~T1_E~0); 979293#L774-1 assume !(0 == ~T2_E~0); 979323#L779-1 assume !(0 == ~T3_E~0); 979482#L784-1 assume !(0 == ~T4_E~0); 979263#L789-1 assume !(0 == ~T5_E~0); 979264#L794-1 assume !(0 == ~T6_E~0); 979399#L799-1 assume !(0 == ~T7_E~0); 979271#L804-1 assume !(0 == ~E_M~0); 979272#L809-1 assume !(0 == ~E_1~0); 979313#L814-1 assume !(0 == ~E_2~0); 978663#L819-1 assume !(0 == ~E_3~0); 978664#L824-1 assume !(0 == ~E_4~0); 979010#L829-1 assume !(0 == ~E_5~0); 979594#L834-1 assume !(0 == ~E_6~0); 978792#L839-1 assume !(0 == ~E_7~0); 978793#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 979203#L376 assume !(1 == ~m_pc~0); 979185#L376-2 is_master_triggered_~__retres1~0#1 := 0; 979200#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 979665#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 978743#L955 assume !(0 != activate_threads_~tmp~1#1); 978744#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 979103#L395 assume !(1 == ~t1_pc~0); 979295#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 979464#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 978669#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 978670#L963 assume !(0 != activate_threads_~tmp___0~0#1); 979209#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 979210#L414 assume !(1 == ~t2_pc~0); 978795#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 979514#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 979692#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 979511#L971 assume !(0 != activate_threads_~tmp___1~0#1); 979512#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 979721#L433 assume !(1 == ~t3_pc~0); 978913#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 978914#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 979720#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 979719#L979 assume !(0 != activate_threads_~tmp___2~0#1); 979718#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 979673#L452 assume !(1 == ~t4_pc~0); 979661#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 979245#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 979246#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 979611#L987 assume !(0 != activate_threads_~tmp___3~0#1); 979612#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 979716#L471 assume !(1 == ~t5_pc~0); 979636#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 979637#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 979314#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 979315#L995 assume !(0 != activate_threads_~tmp___4~0#1); 979691#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 979644#L490 assume !(1 == ~t6_pc~0); 979645#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 979254#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 979255#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 979383#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 979713#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 979712#L509 assume !(1 == ~t7_pc~0); 979515#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 978894#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 978895#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 978959#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 978960#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 979523#L857 assume !(1 == ~M_E~0); 979524#L857-2 assume !(1 == ~T1_E~0); 979018#L862-1 assume !(1 == ~T2_E~0); 979019#L867-1 assume !(1 == ~T3_E~0); 979709#L872-1 assume !(1 == ~T4_E~0); 979708#L877-1 assume !(1 == ~T5_E~0); 979541#L882-1 assume !(1 == ~T6_E~0); 979542#L887-1 assume !(1 == ~T7_E~0); 979707#L892-1 assume !(1 == ~E_M~0); 979627#L897-1 assume !(1 == ~E_1~0); 979628#L902-1 assume !(1 == ~E_2~0); 979039#L907-1 assume !(1 == ~E_3~0); 979362#L912-1 assume !(1 == ~E_4~0); 979353#L917-1 assume !(1 == ~E_5~0); 979354#L922-1 assume !(1 == ~E_6~0); 979599#L927-1 assume !(1 == ~E_7~0); 979340#L932-1 assume { :end_inline_reset_delta_events } true; 979341#L1178-2 [2021-12-15 17:20:50,366 INFO L793 eck$LassoCheckResult]: Loop: 979341#L1178-2 assume !false; 994079#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 994078#L744 assume !false; 994077#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 994076#L584 assume !(0 == ~m_st~0); 994072#L588 assume !(0 == ~t1_st~0); 994073#L592 assume !(0 == ~t2_st~0); 994075#L596 assume !(0 == ~t3_st~0); 994070#L600 assume !(0 == ~t4_st~0); 994071#L604 assume !(0 == ~t5_st~0); 994074#L608 assume !(0 == ~t6_st~0); 994068#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 994069#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 993699#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 993700#L641 assume !(0 != eval_~tmp~0#1); 1000340#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1000328#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1000324#L769-3 assume !(0 == ~M_E~0); 1000320#L769-5 assume !(0 == ~T1_E~0); 1000316#L774-3 assume !(0 == ~T2_E~0); 1000312#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1000308#L784-3 assume !(0 == ~T4_E~0); 1000303#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1000298#L794-3 assume !(0 == ~T6_E~0); 1000293#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1000287#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1000284#L809-3 assume !(0 == ~E_1~0); 1000278#L814-3 assume !(0 == ~E_2~0); 1000274#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1000261#L824-3 assume !(0 == ~E_4~0); 1000255#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1000252#L834-3 assume !(0 == ~E_6~0); 1000248#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1000238#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1000237#L376-27 assume !(1 == ~m_pc~0); 1000236#L376-29 is_master_triggered_~__retres1~0#1 := 0; 1000234#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1000232#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1000230#L955-27 assume !(0 != activate_threads_~tmp~1#1); 1000227#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1000225#L395-27 assume !(1 == ~t1_pc~0); 1000222#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1000220#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1000218#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1000216#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1000211#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1000204#L414-27 assume !(1 == ~t2_pc~0); 1000206#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1001978#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1001977#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1001976#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1001975#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1001965#L433-27 assume !(1 == ~t3_pc~0); 998832#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1001962#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1001960#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1001938#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1001933#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1001928#L452-27 assume !(1 == ~t4_pc~0); 1001922#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1001916#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1001912#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1001907#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1001791#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 994364#L471-27 assume !(1 == ~t5_pc~0); 994360#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 994356#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 994352#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 994348#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 994344#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 994340#L490-27 assume !(1 == ~t6_pc~0); 985976#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 994335#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 994330#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 994325#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 994320#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 994315#L509-27 assume !(1 == ~t7_pc~0); 994308#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 994299#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 994291#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 994282#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 994275#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 994269#L857-3 assume !(1 == ~M_E~0); 994264#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 994261#L862-3 assume !(1 == ~T2_E~0); 994257#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 994253#L872-3 assume !(1 == ~T4_E~0); 994249#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 994245#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 994241#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 994236#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 994232#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 994228#L902-3 assume !(1 == ~E_2~0); 994225#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 994222#L912-3 assume !(1 == ~E_4~0); 994218#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 994215#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 994212#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 994209#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 994184#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 994178#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 994176#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 994159#L1197 assume !(0 == start_simulation_~tmp~3#1); 994157#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 994121#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 994113#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 994107#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 994101#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 994095#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 994090#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 994086#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 979341#L1178-2 [2021-12-15 17:20:50,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:50,366 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2021-12-15 17:20:50,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:50,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31498215] [2021-12-15 17:20:50,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:50,367 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:50,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:50,373 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:50,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:50,390 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:50,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:50,390 INFO L85 PathProgramCache]: Analyzing trace with hash -345520006, now seen corresponding path program 1 times [2021-12-15 17:20:50,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:50,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017206300] [2021-12-15 17:20:50,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:50,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:50,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:50,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:50,410 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:50,410 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017206300] [2021-12-15 17:20:50,410 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017206300] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:50,410 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:50,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:50,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936314168] [2021-12-15 17:20:50,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:50,410 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:50,411 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:50,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:50,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:50,411 INFO L87 Difference]: Start difference. First operand 36555 states and 50290 transitions. cyclomatic complexity: 13737 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:50,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:50,588 INFO L93 Difference]: Finished difference Result 69051 states and 94130 transitions. [2021-12-15 17:20:50,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:50,954 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69051 states and 94130 transitions. [2021-12-15 17:20:51,217 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 68832 [2021-12-15 17:20:51,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69051 states to 69051 states and 94130 transitions. [2021-12-15 17:20:51,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69051 [2021-12-15 17:20:51,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69051 [2021-12-15 17:20:51,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69051 states and 94130 transitions. [2021-12-15 17:20:51,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:51,420 INFO L681 BuchiCegarLoop]: Abstraction has 69051 states and 94130 transitions. [2021-12-15 17:20:51,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69051 states and 94130 transitions. [2021-12-15 17:20:51,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69051 to 65723. [2021-12-15 17:20:51,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65723 states, 65723 states have (on average 1.3664927042283523) internal successors, (89810), 65722 states have internal predecessors, (89810), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:52,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65723 states to 65723 states and 89810 transitions. [2021-12-15 17:20:52,294 INFO L704 BuchiCegarLoop]: Abstraction has 65723 states and 89810 transitions. [2021-12-15 17:20:52,294 INFO L587 BuchiCegarLoop]: Abstraction has 65723 states and 89810 transitions. [2021-12-15 17:20:52,295 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-15 17:20:52,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65723 states and 89810 transitions. [2021-12-15 17:20:52,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 65504 [2021-12-15 17:20:52,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:52,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:52,484 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:52,484 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:52,484 INFO L791 eck$LassoCheckResult]: Stem: 1084964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1084965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1084817#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1084757#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1084758#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1085144#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1084734#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1084558#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1084559#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1084540#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1084541#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1085142#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1084894#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1084895#L769 assume !(0 == ~M_E~0); 1084919#L769-2 assume !(0 == ~T1_E~0); 1084920#L774-1 assume !(0 == ~T2_E~0); 1084953#L779-1 assume !(0 == ~T3_E~0); 1085123#L784-1 assume !(0 == ~T4_E~0); 1084887#L789-1 assume !(0 == ~T5_E~0); 1084888#L794-1 assume !(0 == ~T6_E~0); 1085027#L799-1 assume !(0 == ~T7_E~0); 1084896#L804-1 assume !(0 == ~E_M~0); 1084897#L809-1 assume !(0 == ~E_1~0); 1084941#L814-1 assume !(0 == ~E_2~0); 1084279#L819-1 assume !(0 == ~E_3~0); 1084280#L824-1 assume !(0 == ~E_4~0); 1084628#L829-1 assume !(0 == ~E_5~0); 1085238#L834-1 assume !(0 == ~E_6~0); 1084402#L839-1 assume !(0 == ~E_7~0); 1084403#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1084826#L376 assume !(1 == ~m_pc~0); 1084809#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1084823#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1085201#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1084356#L955 assume !(0 != activate_threads_~tmp~1#1); 1084357#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1084725#L395 assume !(1 == ~t1_pc~0); 1084921#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1085103#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1084283#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1084284#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1084832#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1084833#L414 assume !(1 == ~t2_pc~0); 1084405#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1085152#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1084614#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1084615#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1085251#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1084729#L433 assume !(1 == ~t3_pc~0); 1084730#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1085263#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1084696#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1084697#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1084375#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1084376#L452 assume !(1 == ~t4_pc~0); 1084536#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1084537#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1084951#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1084952#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1084569#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1084570#L471 assume !(1 == ~t5_pc~0); 1085006#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1084551#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1084552#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1085392#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1085223#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1085224#L490 assume !(1 == ~t6_pc~0); 1084829#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1084830#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1085391#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1084886#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1084743#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1084703#L509 assume !(1 == ~t7_pc~0); 1084704#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1084512#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1084513#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1084574#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1084575#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1085164#L857 assume !(1 == ~M_E~0); 1085165#L857-2 assume !(1 == ~T1_E~0); 1084637#L862-1 assume !(1 == ~T2_E~0); 1084638#L867-1 assume !(1 == ~T3_E~0); 1085387#L872-1 assume !(1 == ~T4_E~0); 1085386#L877-1 assume !(1 == ~T5_E~0); 1085183#L882-1 assume !(1 == ~T6_E~0); 1085184#L887-1 assume !(1 == ~T7_E~0); 1085385#L892-1 assume !(1 == ~E_M~0); 1085275#L897-1 assume !(1 == ~E_1~0); 1085276#L902-1 assume !(1 == ~E_2~0); 1084660#L907-1 assume !(1 == ~E_3~0); 1084999#L912-1 assume !(1 == ~E_4~0); 1084988#L917-1 assume !(1 == ~E_5~0); 1084989#L922-1 assume !(1 == ~E_6~0); 1085244#L927-1 assume !(1 == ~E_7~0); 1084972#L932-1 assume { :end_inline_reset_delta_events } true; 1084973#L1178-2 [2021-12-15 17:20:52,484 INFO L793 eck$LassoCheckResult]: Loop: 1084973#L1178-2 assume !false; 1123913#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1123911#L744 assume !false; 1123909#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1123906#L584 assume !(0 == ~m_st~0); 1123907#L588 assume !(0 == ~t1_st~0); 1141466#L592 assume !(0 == ~t2_st~0); 1141461#L596 assume !(0 == ~t3_st~0); 1141457#L600 assume !(0 == ~t4_st~0); 1141454#L604 assume !(0 == ~t5_st~0); 1141449#L608 assume !(0 == ~t6_st~0); 1141444#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1141440#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1141436#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1141433#L641 assume !(0 != eval_~tmp~0#1); 1141429#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1141425#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1141423#L769-3 assume !(0 == ~M_E~0); 1141419#L769-5 assume !(0 == ~T1_E~0); 1141416#L774-3 assume !(0 == ~T2_E~0); 1141413#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1141409#L784-3 assume !(0 == ~T4_E~0); 1141406#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1141401#L794-3 assume !(0 == ~T6_E~0); 1141398#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1141394#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1141388#L809-3 assume !(0 == ~E_1~0); 1141224#L814-3 assume !(0 == ~E_2~0); 1141220#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1141215#L824-3 assume !(0 == ~E_4~0); 1141212#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1141209#L834-3 assume !(0 == ~E_6~0); 1141207#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1141205#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1141201#L376-27 assume 1 == ~m_pc~0; 1141195#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1141190#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1141185#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1141180#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1141177#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1141175#L395-27 assume !(1 == ~t1_pc~0); 1141174#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1141172#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1141170#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1141168#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1141165#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1141000#L414-27 assume 1 == ~t2_pc~0; 1141001#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1134741#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134739#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1134737#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1134735#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1134734#L433-27 assume !(1 == ~t3_pc~0); 1120519#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1134731#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1134729#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1134727#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1134724#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1134722#L452-27 assume !(1 == ~t4_pc~0); 1134719#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1134717#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1134715#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1134713#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1134711#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1134708#L471-27 assume !(1 == ~t5_pc~0); 1116793#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1134705#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1134703#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1134701#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1134699#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1124071#L490-27 assume !(1 == ~t6_pc~0); 1124070#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1124069#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1124067#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1124065#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1124063#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1124060#L509-27 assume !(1 == ~t7_pc~0); 1124056#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1124054#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1124052#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1124050#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1124047#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1124044#L857-3 assume !(1 == ~M_E~0); 1120755#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1124042#L862-3 assume !(1 == ~T2_E~0); 1124040#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1124038#L872-3 assume !(1 == ~T4_E~0); 1124036#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1124035#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1124033#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1124031#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1124029#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1124027#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1124023#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1124021#L912-3 assume !(1 == ~E_4~0); 1124019#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1124017#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1124015#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1124013#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1124009#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1124008#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1124005#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1123939#L1197 assume !(0 == start_simulation_~tmp~3#1); 1123937#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1123934#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1123932#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1123929#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1123927#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1123926#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1123925#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1123921#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1084973#L1178-2 [2021-12-15 17:20:52,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:52,485 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 6 times [2021-12-15 17:20:52,485 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:52,486 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383861446] [2021-12-15 17:20:52,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:52,486 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:52,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:52,491 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:52,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:52,508 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:52,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:52,509 INFO L85 PathProgramCache]: Analyzing trace with hash 424169972, now seen corresponding path program 1 times [2021-12-15 17:20:52,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:52,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764766208] [2021-12-15 17:20:52,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:52,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:52,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:52,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:52,545 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:52,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764766208] [2021-12-15 17:20:52,545 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [764766208] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:52,545 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:52,545 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:52,545 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805248219] [2021-12-15 17:20:52,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:52,546 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:52,546 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:52,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:52,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:52,547 INFO L87 Difference]: Start difference. First operand 65723 states and 89810 transitions. cyclomatic complexity: 24089 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:52,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:52,984 INFO L93 Difference]: Finished difference Result 126027 states and 171489 transitions. [2021-12-15 17:20:52,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:52,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126027 states and 171489 transitions. [2021-12-15 17:20:53,574 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 125808 [2021-12-15 17:20:54,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126027 states to 126027 states and 171489 transitions. [2021-12-15 17:20:54,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126027 [2021-12-15 17:20:54,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126027 [2021-12-15 17:20:54,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126027 states and 171489 transitions. [2021-12-15 17:20:54,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:54,468 INFO L681 BuchiCegarLoop]: Abstraction has 126027 states and 171489 transitions. [2021-12-15 17:20:54,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126027 states and 171489 transitions. [2021-12-15 17:20:55,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126027 to 67019. [2021-12-15 17:20:55,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67019 states, 67019 states have (on average 1.353422163863979) internal successors, (90705), 67018 states have internal predecessors, (90705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:55,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67019 states to 67019 states and 90705 transitions. [2021-12-15 17:20:55,248 INFO L704 BuchiCegarLoop]: Abstraction has 67019 states and 90705 transitions. [2021-12-15 17:20:55,248 INFO L587 BuchiCegarLoop]: Abstraction has 67019 states and 90705 transitions. [2021-12-15 17:20:55,248 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-15 17:20:55,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67019 states and 90705 transitions. [2021-12-15 17:20:55,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 66800 [2021-12-15 17:20:55,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:55,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:55,807 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:55,809 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:55,810 INFO L791 eck$LassoCheckResult]: Stem: 1276722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1276723#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1276577#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1276518#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1276519#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1276897#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1276497#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1276324#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1276325#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1276306#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1276307#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1276896#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1276651#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1276652#L769 assume !(0 == ~M_E~0); 1276675#L769-2 assume !(0 == ~T1_E~0); 1276676#L774-1 assume !(0 == ~T2_E~0); 1276712#L779-1 assume !(0 == ~T3_E~0); 1276871#L784-1 assume !(0 == ~T4_E~0); 1276647#L789-1 assume !(0 == ~T5_E~0); 1276648#L794-1 assume !(0 == ~T6_E~0); 1276786#L799-1 assume !(0 == ~T7_E~0); 1276654#L804-1 assume !(0 == ~E_M~0); 1276655#L809-1 assume !(0 == ~E_1~0); 1276699#L814-1 assume !(0 == ~E_2~0); 1276039#L819-1 assume !(0 == ~E_3~0); 1276040#L824-1 assume !(0 == ~E_4~0); 1276393#L829-1 assume !(0 == ~E_5~0); 1276985#L834-1 assume !(0 == ~E_6~0); 1276168#L839-1 assume !(0 == ~E_7~0); 1276169#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1276586#L376 assume !(1 == ~m_pc~0); 1276567#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1276583#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1276956#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1276120#L955 assume !(0 != activate_threads_~tmp~1#1); 1276121#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1276489#L395 assume !(1 == ~t1_pc~0); 1276678#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1276854#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1276045#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1276046#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1276591#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1276592#L414 assume !(1 == ~t2_pc~0); 1276171#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1276906#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1276379#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1276380#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1276997#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1276492#L433 assume !(1 == ~t3_pc~0); 1276493#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1277011#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1276460#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1276461#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1276141#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1276142#L452 assume !(1 == ~t4_pc~0); 1276302#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1276303#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1276710#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1276711#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1276335#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1276336#L471 assume !(1 == ~t5_pc~0); 1276764#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1276317#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1276318#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1277120#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1276971#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1276972#L490 assume !(1 == ~t6_pc~0); 1276589#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1276590#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1277119#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1276644#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1276503#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1276468#L509 assume !(1 == ~t7_pc~0); 1276469#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1276273#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1276274#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1276340#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1276341#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1276917#L857 assume !(1 == ~M_E~0); 1276918#L857-2 assume !(1 == ~T1_E~0); 1276402#L862-1 assume !(1 == ~T2_E~0); 1276403#L867-1 assume !(1 == ~T3_E~0); 1277115#L872-1 assume !(1 == ~T4_E~0); 1277114#L877-1 assume !(1 == ~T5_E~0); 1276936#L882-1 assume !(1 == ~T6_E~0); 1276937#L887-1 assume !(1 == ~T7_E~0); 1277113#L892-1 assume !(1 == ~E_M~0); 1277021#L897-1 assume !(1 == ~E_1~0); 1277022#L902-1 assume !(1 == ~E_2~0); 1276421#L907-1 assume !(1 == ~E_3~0); 1276753#L912-1 assume !(1 == ~E_4~0); 1276743#L917-1 assume !(1 == ~E_5~0); 1276744#L922-1 assume !(1 == ~E_6~0); 1276991#L927-1 assume !(1 == ~E_7~0); 1276729#L932-1 assume { :end_inline_reset_delta_events } true; 1276730#L1178-2 [2021-12-15 17:20:55,810 INFO L793 eck$LassoCheckResult]: Loop: 1276730#L1178-2 assume !false; 1291048#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1291047#L744 assume !false; 1291046#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1291041#L584 assume !(0 == ~m_st~0); 1291042#L588 assume !(0 == ~t1_st~0); 1296654#L592 assume !(0 == ~t2_st~0); 1296656#L596 assume !(0 == ~t3_st~0); 1296652#L600 assume !(0 == ~t4_st~0); 1296653#L604 assume !(0 == ~t5_st~0); 1296655#L608 assume !(0 == ~t6_st~0); 1296650#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1296651#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1305045#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1305032#L641 assume !(0 != eval_~tmp~0#1); 1305029#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1305027#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1305025#L769-3 assume !(0 == ~M_E~0); 1305023#L769-5 assume !(0 == ~T1_E~0); 1305015#L774-3 assume !(0 == ~T2_E~0); 1303558#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1298661#L784-3 assume !(0 == ~T4_E~0); 1298657#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1298655#L794-3 assume !(0 == ~T6_E~0); 1298653#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1298651#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1298649#L809-3 assume !(0 == ~E_1~0); 1298647#L814-3 assume !(0 == ~E_2~0); 1298644#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1298645#L824-3 assume !(0 == ~E_4~0); 1307023#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1307021#L834-3 assume !(0 == ~E_6~0); 1307019#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1307017#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1293655#L376-27 assume 1 == ~m_pc~0; 1293652#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1293649#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1293650#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1307007#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1293641#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1293639#L395-27 assume !(1 == ~t1_pc~0); 1293637#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1293635#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1293632#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1293630#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 1293627#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1293625#L414-27 assume 1 == ~t2_pc~0; 1293622#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1293623#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1308004#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1308002#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1308000#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1307291#L433-27 assume !(1 == ~t3_pc~0); 1295360#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1307290#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1307289#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1307288#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1307287#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1307285#L452-27 assume !(1 == ~t4_pc~0); 1307282#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1307280#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1307276#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1307274#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1307272#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1305299#L471-27 assume !(1 == ~t5_pc~0); 1305298#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1301452#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1301451#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1301450#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1301448#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1291619#L490-27 assume !(1 == ~t6_pc~0); 1291617#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1291615#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1291613#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1291612#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1291610#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1291608#L509-27 assume 1 == ~t7_pc~0; 1291606#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1291607#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1291678#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1291598#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1291596#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1291594#L857-3 assume !(1 == ~M_E~0); 1291590#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1291588#L862-3 assume !(1 == ~T2_E~0); 1291584#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1291582#L872-3 assume !(1 == ~T4_E~0); 1291580#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1291578#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1291575#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1291573#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1291570#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1291568#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1291565#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1291563#L912-3 assume !(1 == ~E_4~0); 1291561#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1291559#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1291557#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1291555#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1291552#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1291550#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1291547#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1291536#L1197 assume !(0 == start_simulation_~tmp~3#1); 1291534#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1291531#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1291529#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1291527#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1291525#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1291522#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1291520#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1291518#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1276730#L1178-2 [2021-12-15 17:20:55,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:55,811 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 7 times [2021-12-15 17:20:55,811 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:55,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76255240] [2021-12-15 17:20:55,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:55,812 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:55,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:55,839 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:55,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:55,859 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:55,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:55,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1749934579, now seen corresponding path program 1 times [2021-12-15 17:20:55,860 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:55,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152179518] [2021-12-15 17:20:55,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:55,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:55,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:55,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:55,902 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:55,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152179518] [2021-12-15 17:20:55,902 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152179518] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:55,902 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:55,902 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:55,903 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [943090176] [2021-12-15 17:20:55,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:55,903 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:55,903 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:55,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:55,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:55,904 INFO L87 Difference]: Start difference. First operand 67019 states and 90705 transitions. cyclomatic complexity: 23688 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:56,204 INFO L93 Difference]: Finished difference Result 95259 states and 128415 transitions. [2021-12-15 17:20:56,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:56,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95259 states and 128415 transitions. [2021-12-15 17:20:56,596 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 94976 [2021-12-15 17:20:56,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95259 states to 95259 states and 128415 transitions. [2021-12-15 17:20:56,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95259 [2021-12-15 17:20:56,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95259 [2021-12-15 17:20:56,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95259 states and 128415 transitions. [2021-12-15 17:20:56,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:56,971 INFO L681 BuchiCegarLoop]: Abstraction has 95259 states and 128415 transitions. [2021-12-15 17:20:57,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95259 states and 128415 transitions. [2021-12-15 17:20:57,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95259 to 67211. [2021-12-15 17:20:57,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67211 states, 67211 states have (on average 1.3404799809554984) internal successors, (90095), 67210 states have internal predecessors, (90095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67211 states to 67211 states and 90095 transitions. [2021-12-15 17:20:58,071 INFO L704 BuchiCegarLoop]: Abstraction has 67211 states and 90095 transitions. [2021-12-15 17:20:58,071 INFO L587 BuchiCegarLoop]: Abstraction has 67211 states and 90095 transitions. [2021-12-15 17:20:58,071 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-15 17:20:58,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67211 states and 90095 transitions. [2021-12-15 17:20:58,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 66992 [2021-12-15 17:20:58,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:58,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:58,270 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,272 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,272 INFO L791 eck$LassoCheckResult]: Stem: 1439028#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1439029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1438880#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1438817#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1438818#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1439210#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1438797#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1438616#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1438617#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1438598#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1438599#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1439209#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1438956#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1438957#L769 assume !(0 == ~M_E~0); 1438983#L769-2 assume !(0 == ~T1_E~0); 1438984#L774-1 assume !(0 == ~T2_E~0); 1439017#L779-1 assume !(0 == ~T3_E~0); 1439188#L784-1 assume !(0 == ~T4_E~0); 1438951#L789-1 assume !(0 == ~T5_E~0); 1438952#L794-1 assume !(0 == ~T6_E~0); 1439095#L799-1 assume !(0 == ~T7_E~0); 1438960#L804-1 assume !(0 == ~E_M~0); 1438961#L809-1 assume !(0 == ~E_1~0); 1439006#L814-1 assume !(0 == ~E_2~0); 1438331#L819-1 assume !(0 == ~E_3~0); 1438332#L824-1 assume !(0 == ~E_4~0); 1438687#L829-1 assume !(0 == ~E_5~0); 1439310#L834-1 assume !(0 == ~E_6~0); 1438460#L839-1 assume !(0 == ~E_7~0); 1438461#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1438890#L376 assume !(1 == ~m_pc~0); 1438869#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1438887#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1439274#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1438410#L955 assume !(0 != activate_threads_~tmp~1#1); 1438411#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1438785#L395 assume !(1 == ~t1_pc~0); 1438986#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1439169#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1438337#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1438338#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1438895#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1438896#L414 assume !(1 == ~t2_pc~0); 1438463#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1439222#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1439430#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1439219#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1439220#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1439464#L433 assume !(1 == ~t3_pc~0); 1438585#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1438586#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1439463#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1439462#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1439461#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1439408#L452 assume !(1 == ~t4_pc~0); 1439389#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1438933#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1438934#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1439330#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1439331#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1439459#L471 assume !(1 == ~t5_pc~0); 1439361#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1439362#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1439007#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1439008#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1439429#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1439369#L490 assume !(1 == ~t6_pc~0); 1439370#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1438942#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1438943#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1439080#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1439456#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1439455#L509 assume !(1 == ~t7_pc~0); 1439223#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1438563#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1438564#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1438632#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1438633#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1439233#L857 assume !(1 == ~M_E~0); 1439234#L857-2 assume !(1 == ~T1_E~0); 1438696#L862-1 assume !(1 == ~T2_E~0); 1438697#L867-1 assume !(1 == ~T3_E~0); 1439452#L872-1 assume !(1 == ~T4_E~0); 1439451#L877-1 assume !(1 == ~T5_E~0); 1439258#L882-1 assume !(1 == ~T6_E~0); 1439259#L887-1 assume !(1 == ~T7_E~0); 1439450#L892-1 assume !(1 == ~E_M~0); 1439345#L897-1 assume !(1 == ~E_1~0); 1439346#L902-1 assume !(1 == ~E_2~0); 1438716#L907-1 assume !(1 == ~E_3~0); 1439063#L912-1 assume !(1 == ~E_4~0); 1439053#L917-1 assume !(1 == ~E_5~0); 1439054#L922-1 assume !(1 == ~E_6~0); 1439319#L927-1 assume !(1 == ~E_7~0); 1439037#L932-1 assume { :end_inline_reset_delta_events } true; 1439038#L1178-2 [2021-12-15 17:20:58,272 INFO L793 eck$LassoCheckResult]: Loop: 1439038#L1178-2 assume !false; 1441764#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1441758#L744 assume !false; 1441751#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1441745#L584 assume !(0 == ~m_st~0); 1441746#L588 assume !(0 == ~t1_st~0); 1446251#L592 assume !(0 == ~t2_st~0); 1446253#L596 assume !(0 == ~t3_st~0); 1446249#L600 assume !(0 == ~t4_st~0); 1446250#L604 assume !(0 == ~t5_st~0); 1446252#L608 assume !(0 == ~t6_st~0); 1446247#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1446248#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1445761#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1445762#L641 assume !(0 != eval_~tmp~0#1); 1475666#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1475662#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1475663#L769-3 assume !(0 == ~M_E~0); 1475646#L769-5 assume !(0 == ~T1_E~0); 1475647#L774-3 assume !(0 == ~T2_E~0); 1475627#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1475628#L784-3 assume !(0 == ~T4_E~0); 1475231#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1475232#L794-3 assume !(0 == ~T6_E~0); 1475217#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1475218#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1475203#L809-3 assume !(0 == ~E_1~0); 1475204#L814-3 assume !(0 == ~E_2~0); 1475187#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1475188#L824-3 assume !(0 == ~E_4~0); 1475172#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1475173#L834-3 assume !(0 == ~E_6~0); 1475157#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1475158#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1439368#L376-27 assume 1 == ~m_pc~0; 1439058#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1439059#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1501673#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1499944#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1439435#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1439424#L395-27 assume !(1 == ~t1_pc~0); 1439425#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1498948#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1439164#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1439165#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 1438798#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1438799#L414-27 assume 1 == ~t2_pc~0; 1498946#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1439051#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1439052#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1500175#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1500173#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1500172#L433-27 assume !(1 == ~t3_pc~0); 1462864#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1500171#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1500170#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1500168#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1499676#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1499675#L452-27 assume !(1 == ~t4_pc~0); 1499673#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1499671#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1499668#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1499666#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 1498472#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1443684#L471-27 assume !(1 == ~t5_pc~0); 1443685#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1443678#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1443679#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1443673#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1443674#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1441959#L490-27 assume !(1 == ~t6_pc~0); 1441957#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1441955#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1441953#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1441951#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1441949#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1441947#L509-27 assume 1 == ~t7_pc~0; 1441944#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1441941#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1441939#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1441926#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1441924#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1441881#L857-3 assume !(1 == ~M_E~0); 1441875#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1441873#L862-3 assume !(1 == ~T2_E~0); 1441871#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1441869#L872-3 assume !(1 == ~T4_E~0); 1441867#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1441865#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1441863#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1441847#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1441846#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1441844#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1441841#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1441839#L912-3 assume !(1 == ~E_4~0); 1441837#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1441835#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1441833#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1441831#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1441827#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1441825#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1441823#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1441819#L1197 assume !(0 == start_simulation_~tmp~3#1); 1441817#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1441813#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1441811#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1441809#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1441807#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1441805#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1441793#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1441784#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1439038#L1178-2 [2021-12-15 17:20:58,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 8 times [2021-12-15 17:20:58,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391795408] [2021-12-15 17:20:58,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:58,297 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:58,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:58,315 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:58,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,316 INFO L85 PathProgramCache]: Analyzing trace with hash 1734415861, now seen corresponding path program 1 times [2021-12-15 17:20:58,316 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793297110] [2021-12-15 17:20:58,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,316 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:58,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:58,349 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:58,349 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793297110] [2021-12-15 17:20:58,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793297110] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:58,349 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:58,349 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:58,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957913730] [2021-12-15 17:20:58,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:58,349 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:58,350 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:58,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:58,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:58,350 INFO L87 Difference]: Start difference. First operand 67211 states and 90095 transitions. cyclomatic complexity: 22886 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:59,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:59,132 INFO L93 Difference]: Finished difference Result 117395 states and 157373 transitions. [2021-12-15 17:20:59,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:59,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117395 states and 157373 transitions. [2021-12-15 17:20:59,594 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 117112 [2021-12-15 17:20:59,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117395 states to 117395 states and 157373 transitions. [2021-12-15 17:20:59,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117395 [2021-12-15 17:20:59,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117395 [2021-12-15 17:20:59,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117395 states and 157373 transitions. [2021-12-15 17:20:59,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:59,962 INFO L681 BuchiCegarLoop]: Abstraction has 117395 states and 157373 transitions. [2021-12-15 17:21:00,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117395 states and 157373 transitions. [2021-12-15 17:21:01,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117395 to 68603. [2021-12-15 17:21:01,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68603 states, 68603 states have (on average 1.3277116161100826) internal successors, (91085), 68602 states have internal predecessors, (91085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68603 states to 68603 states and 91085 transitions. [2021-12-15 17:21:01,167 INFO L704 BuchiCegarLoop]: Abstraction has 68603 states and 91085 transitions. [2021-12-15 17:21:01,167 INFO L587 BuchiCegarLoop]: Abstraction has 68603 states and 91085 transitions. [2021-12-15 17:21:01,167 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-15 17:21:01,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68603 states and 91085 transitions. [2021-12-15 17:21:01,368 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 68384 [2021-12-15 17:21:01,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:01,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:01,372 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,372 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,373 INFO L791 eck$LassoCheckResult]: Stem: 1623632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1623633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1623487#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1623431#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1623432#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1623801#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1623408#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1623231#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1623232#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1623213#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1623214#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1623800#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1623564#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1623565#L769 assume !(0 == ~M_E~0); 1623587#L769-2 assume !(0 == ~T1_E~0); 1623588#L774-1 assume !(0 == ~T2_E~0); 1623623#L779-1 assume !(0 == ~T3_E~0); 1623779#L784-1 assume !(0 == ~T4_E~0); 1623557#L789-1 assume !(0 == ~T5_E~0); 1623558#L794-1 assume !(0 == ~T6_E~0); 1623693#L799-1 assume !(0 == ~T7_E~0); 1623566#L804-1 assume !(0 == ~E_M~0); 1623567#L809-1 assume !(0 == ~E_1~0); 1623612#L814-1 assume !(0 == ~E_2~0); 1622955#L819-1 assume !(0 == ~E_3~0); 1622956#L824-1 assume !(0 == ~E_4~0); 1623300#L829-1 assume !(0 == ~E_5~0); 1623879#L834-1 assume !(0 == ~E_6~0); 1623080#L839-1 assume !(0 == ~E_7~0); 1623081#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1623497#L376 assume !(1 == ~m_pc~0); 1623482#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1623494#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1623852#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1623033#L955 assume !(0 != activate_threads_~tmp~1#1); 1623034#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1623398#L395 assume !(1 == ~t1_pc~0); 1623589#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1623765#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1622959#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1622960#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1623504#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1623505#L414 assume !(1 == ~t2_pc~0); 1623083#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1623808#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1623999#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1623806#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1623807#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1624029#L433 assume !(1 == ~t3_pc~0); 1623201#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1623202#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1624028#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1624027#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1624026#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1623980#L452 assume !(1 == ~t4_pc~0); 1623956#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1623542#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1623543#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1623899#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1623900#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1624024#L471 assume !(1 == ~t5_pc~0); 1623929#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1623930#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1623613#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1623614#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1623998#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1623938#L490 assume !(1 == ~t6_pc~0); 1623939#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1623552#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1623553#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1623677#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1624021#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1624020#L509 assume !(1 == ~t7_pc~0); 1623809#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1623185#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1623186#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1623247#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1623248#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1623821#L857 assume !(1 == ~M_E~0); 1623822#L857-2 assume !(1 == ~T1_E~0); 1623310#L862-1 assume !(1 == ~T2_E~0); 1623311#L867-1 assume !(1 == ~T3_E~0); 1624017#L872-1 assume !(1 == ~T4_E~0); 1624016#L877-1 assume !(1 == ~T5_E~0); 1623839#L882-1 assume !(1 == ~T6_E~0); 1623840#L887-1 assume !(1 == ~T7_E~0); 1624015#L892-1 assume !(1 == ~E_M~0); 1623914#L897-1 assume !(1 == ~E_1~0); 1623915#L902-1 assume !(1 == ~E_2~0); 1623332#L907-1 assume !(1 == ~E_3~0); 1623663#L912-1 assume !(1 == ~E_4~0); 1623654#L917-1 assume !(1 == ~E_5~0); 1623655#L922-1 assume !(1 == ~E_6~0); 1623884#L927-1 assume !(1 == ~E_7~0); 1623639#L932-1 assume { :end_inline_reset_delta_events } true; 1623640#L1178-2 [2021-12-15 17:21:01,373 INFO L793 eck$LassoCheckResult]: Loop: 1623640#L1178-2 assume !false; 1648661#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1648653#L744 assume !false; 1648646#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1648638#L584 assume !(0 == ~m_st~0); 1648639#L588 assume !(0 == ~t1_st~0); 1650360#L592 assume !(0 == ~t2_st~0); 1650362#L596 assume !(0 == ~t3_st~0); 1650358#L600 assume !(0 == ~t4_st~0); 1650359#L604 assume !(0 == ~t5_st~0); 1650361#L608 assume !(0 == ~t6_st~0); 1650356#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1650357#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1650349#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1650350#L641 assume !(0 != eval_~tmp~0#1); 1665473#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1665472#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1665471#L769-3 assume !(0 == ~M_E~0); 1665470#L769-5 assume !(0 == ~T1_E~0); 1665469#L774-3 assume !(0 == ~T2_E~0); 1665468#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1665467#L784-3 assume !(0 == ~T4_E~0); 1665466#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1665465#L794-3 assume !(0 == ~T6_E~0); 1665464#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1665463#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1665462#L809-3 assume !(0 == ~E_1~0); 1665461#L814-3 assume !(0 == ~E_2~0); 1665460#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1665459#L824-3 assume !(0 == ~E_4~0); 1665458#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1665457#L834-3 assume !(0 == ~E_6~0); 1665456#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1665455#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1665454#L376-27 assume 1 == ~m_pc~0; 1665452#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1665451#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1665450#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1665448#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1665447#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1665446#L395-27 assume !(1 == ~t1_pc~0); 1665445#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1665444#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1665443#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1665442#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 1665441#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1665438#L414-27 assume 1 == ~t2_pc~0; 1665439#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1665328#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1665326#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1665324#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1665322#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1665320#L433-27 assume !(1 == ~t3_pc~0); 1665319#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1665318#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1665317#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1665316#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1665315#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1665314#L452-27 assume !(1 == ~t4_pc~0); 1665312#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1665311#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1665310#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1665309#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 1665308#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1657458#L471-27 assume !(1 == ~t5_pc~0); 1657456#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1657454#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1657452#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1657450#L995-27 assume !(0 != activate_threads_~tmp___4~0#1); 1657448#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1657446#L490-27 assume !(1 == ~t6_pc~0); 1644401#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1657444#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1657442#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1657440#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1657438#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1657434#L509-27 assume 1 == ~t7_pc~0; 1657432#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1657433#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1657508#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1657422#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1657420#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1657418#L857-3 assume !(1 == ~M_E~0); 1629679#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1657416#L862-3 assume !(1 == ~T2_E~0); 1657414#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1657412#L872-3 assume !(1 == ~T4_E~0); 1657410#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1657408#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1657406#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1657404#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1657402#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1657401#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1657399#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1657398#L912-3 assume !(1 == ~E_4~0); 1657396#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1657394#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1657392#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1657390#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1657387#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1657385#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1657383#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1657364#L1197 assume !(0 == start_simulation_~tmp~3#1); 1657360#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1657357#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1657355#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1657353#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1657350#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1648725#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1648691#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1648680#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1623640#L1178-2 [2021-12-15 17:21:01,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 9 times [2021-12-15 17:21:01,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783457758] [2021-12-15 17:21:01,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:01,379 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:01,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:01,394 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:01,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,395 INFO L85 PathProgramCache]: Analyzing trace with hash 837022583, now seen corresponding path program 1 times [2021-12-15 17:21:01,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272238360] [2021-12-15 17:21:01,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,395 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,432 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272238360] [2021-12-15 17:21:01,432 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272238360] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,432 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,432 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:01,432 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885965942] [2021-12-15 17:21:01,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,432 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:01,433 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:01,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:01,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:01,433 INFO L87 Difference]: Start difference. First operand 68603 states and 91085 transitions. cyclomatic complexity: 22484 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:01,857 INFO L93 Difference]: Finished difference Result 116499 states and 154899 transitions. [2021-12-15 17:21:01,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:01,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 116499 states and 154899 transitions. [2021-12-15 17:21:02,358 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 116216 [2021-12-15 17:21:03,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 116499 states to 116499 states and 154899 transitions. [2021-12-15 17:21:03,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116499 [2021-12-15 17:21:03,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116499 [2021-12-15 17:21:03,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116499 states and 154899 transitions. [2021-12-15 17:21:03,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:03,378 INFO L681 BuchiCegarLoop]: Abstraction has 116499 states and 154899 transitions. [2021-12-15 17:21:03,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116499 states and 154899 transitions. [2021-12-15 17:21:04,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116499 to 69995. [2021-12-15 17:21:04,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69995 states, 69995 states have (on average 1.3154511036502607) internal successors, (92075), 69994 states have internal predecessors, (92075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:04,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69995 states to 69995 states and 92075 transitions. [2021-12-15 17:21:04,205 INFO L704 BuchiCegarLoop]: Abstraction has 69995 states and 92075 transitions. [2021-12-15 17:21:04,205 INFO L587 BuchiCegarLoop]: Abstraction has 69995 states and 92075 transitions. [2021-12-15 17:21:04,205 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-15 17:21:04,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69995 states and 92075 transitions. [2021-12-15 17:21:04,413 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 69776 [2021-12-15 17:21:04,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:04,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:04,418 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,418 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,418 INFO L791 eck$LassoCheckResult]: Stem: 1808747#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1808748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1808598#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1808537#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1808538#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 1808911#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1808518#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1808341#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1808342#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1808324#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1808325#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1808910#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1808671#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1808672#L769 assume !(0 == ~M_E~0); 1808696#L769-2 assume !(0 == ~T1_E~0); 1808697#L774-1 assume !(0 == ~T2_E~0); 1808735#L779-1 assume !(0 == ~T3_E~0); 1808892#L784-1 assume !(0 == ~T4_E~0); 1808666#L789-1 assume !(0 == ~T5_E~0); 1808667#L794-1 assume !(0 == ~T6_E~0); 1808808#L799-1 assume !(0 == ~T7_E~0); 1808674#L804-1 assume !(0 == ~E_M~0); 1808675#L809-1 assume !(0 == ~E_1~0); 1808720#L814-1 assume !(0 == ~E_2~0); 1808067#L819-1 assume !(0 == ~E_3~0); 1808068#L824-1 assume !(0 == ~E_4~0); 1808410#L829-1 assume !(0 == ~E_5~0); 1809005#L834-1 assume !(0 == ~E_6~0); 1808195#L839-1 assume !(0 == ~E_7~0); 1808196#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1808607#L376 assume !(1 == ~m_pc~0); 1808588#L376-2 is_master_triggered_~__retres1~0#1 := 0; 1808604#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1808970#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1808147#L955 assume !(0 != activate_threads_~tmp~1#1); 1808148#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1808509#L395 assume !(1 == ~t1_pc~0); 1808699#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1808876#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1808073#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1808074#L963 assume !(0 != activate_threads_~tmp___0~0#1); 1808612#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1808613#L414 assume !(1 == ~t2_pc~0); 1808198#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1808922#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1808395#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1808396#L971 assume !(0 != activate_threads_~tmp___1~0#1); 1809014#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1808513#L433 assume !(1 == ~t3_pc~0); 1808514#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1809026#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1808479#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1808480#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1808167#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1808168#L452 assume !(1 == ~t4_pc~0); 1808320#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1808321#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1808733#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1808734#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1808352#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1808353#L471 assume !(1 == ~t5_pc~0); 1808791#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1808335#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1808336#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1809147#L995 assume !(0 != activate_threads_~tmp___4~0#1); 1808989#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1808990#L490 assume !(1 == ~t6_pc~0); 1808609#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1808610#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1809146#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1808663#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 1808524#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1808488#L509 assume !(1 == ~t7_pc~0); 1808489#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1808294#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1808295#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1808357#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 1808358#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1808935#L857 assume !(1 == ~M_E~0); 1808936#L857-2 assume !(1 == ~T1_E~0); 1808420#L862-1 assume !(1 == ~T2_E~0); 1808421#L867-1 assume !(1 == ~T3_E~0); 1809142#L872-1 assume !(1 == ~T4_E~0); 1809141#L877-1 assume !(1 == ~T5_E~0); 1808956#L882-1 assume !(1 == ~T6_E~0); 1808957#L887-1 assume !(1 == ~T7_E~0); 1809140#L892-1 assume !(1 == ~E_M~0); 1809036#L897-1 assume !(1 == ~E_1~0); 1809037#L902-1 assume !(1 == ~E_2~0); 1808440#L907-1 assume !(1 == ~E_3~0); 1808781#L912-1 assume !(1 == ~E_4~0); 1808769#L917-1 assume !(1 == ~E_5~0); 1808770#L922-1 assume !(1 == ~E_6~0); 1809010#L927-1 assume !(1 == ~E_7~0); 1808755#L932-1 assume { :end_inline_reset_delta_events } true; 1808756#L1178-2 [2021-12-15 17:21:04,419 INFO L793 eck$LassoCheckResult]: Loop: 1808756#L1178-2 assume !false; 1816207#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1816206#L744 assume !false; 1816205#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1816203#L584 assume !(0 == ~m_st~0); 1816204#L588 assume !(0 == ~t1_st~0); 1819846#L592 assume !(0 == ~t2_st~0); 1819848#L596 assume !(0 == ~t3_st~0); 1819844#L600 assume !(0 == ~t4_st~0); 1819845#L604 assume !(0 == ~t5_st~0); 1819847#L608 assume !(0 == ~t6_st~0); 1819842#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1819843#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1819834#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1819835#L641 assume !(0 != eval_~tmp~0#1); 1847580#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1847579#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1847578#L769-3 assume !(0 == ~M_E~0); 1847577#L769-5 assume !(0 == ~T1_E~0); 1847576#L774-3 assume !(0 == ~T2_E~0); 1847575#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1847574#L784-3 assume !(0 == ~T4_E~0); 1847573#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1847572#L794-3 assume !(0 == ~T6_E~0); 1847571#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1847570#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1847569#L809-3 assume !(0 == ~E_1~0); 1847568#L814-3 assume !(0 == ~E_2~0); 1847567#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1847566#L824-3 assume !(0 == ~E_4~0); 1847565#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1847564#L834-3 assume !(0 == ~E_6~0); 1847563#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1847562#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1847561#L376-27 assume 1 == ~m_pc~0; 1847559#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1847558#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1847557#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1847555#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1847554#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1847553#L395-27 assume !(1 == ~t1_pc~0); 1847552#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1847551#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1847550#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1847549#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 1847548#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1847547#L414-27 assume !(1 == ~t2_pc~0); 1847544#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1847543#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1847542#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1847541#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1847540#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1847539#L433-27 assume !(1 == ~t3_pc~0); 1834394#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1847538#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1847537#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1847536#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1847535#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1847534#L452-27 assume !(1 == ~t4_pc~0); 1847532#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1847531#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1847530#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1847529#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 1847528#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1847527#L471-27 assume !(1 == ~t5_pc~0); 1832366#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1847526#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1847525#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1847524#L995-27 assume !(0 != activate_threads_~tmp___4~0#1); 1847523#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1816377#L490-27 assume !(1 == ~t6_pc~0); 1816375#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1816373#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1816371#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1816369#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 1816367#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1816365#L509-27 assume !(1 == ~t7_pc~0); 1816362#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1816358#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1816354#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1816350#L1011-27 assume !(0 != activate_threads_~tmp___6~0#1); 1816347#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1816345#L857-3 assume !(1 == ~M_E~0); 1815279#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1816343#L862-3 assume !(1 == ~T2_E~0); 1816341#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1816339#L872-3 assume !(1 == ~T4_E~0); 1816337#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1816334#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1816331#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1816328#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1816325#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1816321#L902-3 assume !(1 == ~E_2~0); 1816318#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1816314#L912-3 assume !(1 == ~E_4~0); 1816310#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1816305#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1816300#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1816295#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1816288#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1816282#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1816275#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1816268#L1197 assume !(0 == start_simulation_~tmp~3#1); 1816263#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1816254#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1816249#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1816242#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1816235#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1816229#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1816221#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1816216#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1808756#L1178-2 [2021-12-15 17:21:04,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:04,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 10 times [2021-12-15 17:21:04,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:04,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063960899] [2021-12-15 17:21:04,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:04,420 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:04,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:04,425 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:04,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:04,896 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:04,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:04,896 INFO L85 PathProgramCache]: Analyzing trace with hash 1938302143, now seen corresponding path program 1 times [2021-12-15 17:21:04,896 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:04,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981482369] [2021-12-15 17:21:04,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:04,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:04,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:04,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:04,937 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:04,937 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981482369] [2021-12-15 17:21:04,937 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981482369] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:04,937 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:04,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:04,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [990366810] [2021-12-15 17:21:04,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:04,937 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:04,938 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:04,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:04,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:04,938 INFO L87 Difference]: Start difference. First operand 69995 states and 92075 transitions. cyclomatic complexity: 22082 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:05,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:05,404 INFO L93 Difference]: Finished difference Result 146742 states and 193530 transitions. [2021-12-15 17:21:05,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:05,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146742 states and 193530 transitions. [2021-12-15 17:21:06,064 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 146336 [2021-12-15 17:21:06,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146742 states to 146742 states and 193530 transitions. [2021-12-15 17:21:06,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146742 [2021-12-15 17:21:06,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146742 [2021-12-15 17:21:06,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146742 states and 193530 transitions. [2021-12-15 17:21:07,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:07,157 INFO L681 BuchiCegarLoop]: Abstraction has 146742 states and 193530 transitions. [2021-12-15 17:21:07,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146742 states and 193530 transitions. [2021-12-15 17:21:07,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146742 to 71243. [2021-12-15 17:21:08,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71243 states, 71243 states have (on average 1.3040719790014457) internal successors, (92906), 71242 states have internal predecessors, (92906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:08,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71243 states to 71243 states and 92906 transitions. [2021-12-15 17:21:08,161 INFO L704 BuchiCegarLoop]: Abstraction has 71243 states and 92906 transitions. [2021-12-15 17:21:08,161 INFO L587 BuchiCegarLoop]: Abstraction has 71243 states and 92906 transitions. [2021-12-15 17:21:08,161 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-15 17:21:08,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71243 states and 92906 transitions. [2021-12-15 17:21:08,371 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 71024 [2021-12-15 17:21:08,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:08,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:08,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:08,379 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:08,380 INFO L791 eck$LassoCheckResult]: Stem: 2025488#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2025489#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2025350#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2025288#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2025289#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2025654#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2025268#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2025096#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2025097#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2025078#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2025079#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2025653#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2025421#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2025422#L769 assume !(0 == ~M_E~0); 2025445#L769-2 assume !(0 == ~T1_E~0); 2025446#L774-1 assume !(0 == ~T2_E~0); 2025478#L779-1 assume !(0 == ~T3_E~0); 2025635#L784-1 assume !(0 == ~T4_E~0); 2025416#L789-1 assume !(0 == ~T5_E~0); 2025417#L794-1 assume !(0 == ~T6_E~0); 2025550#L799-1 assume !(0 == ~T7_E~0); 2025424#L804-1 assume !(0 == ~E_M~0); 2025425#L809-1 assume !(0 == ~E_1~0); 2025470#L814-1 assume !(0 == ~E_2~0); 2024818#L819-1 assume !(0 == ~E_3~0); 2024819#L824-1 assume !(0 == ~E_4~0); 2025163#L829-1 assume !(0 == ~E_5~0); 2025736#L834-1 assume !(0 == ~E_6~0); 2024947#L839-1 assume !(0 == ~E_7~0); 2024948#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2025358#L376 assume !(1 == ~m_pc~0); 2025338#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2025355#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2025703#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2024898#L955 assume !(0 != activate_threads_~tmp~1#1); 2024899#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2025260#L395 assume !(1 == ~t1_pc~0); 2025448#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2025617#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2024824#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2024825#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2025364#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2025365#L414 assume !(1 == ~t2_pc~0); 2024950#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2025662#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2025816#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2025659#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2025660#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2025868#L433 assume !(1 == ~t3_pc~0); 2025867#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2025866#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2025865#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2025864#L979 assume !(0 != activate_threads_~tmp___2~0#1); 2025863#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2025861#L452 assume !(1 == ~t4_pc~0); 2025860#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2025859#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2025858#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2025857#L987 assume !(0 != activate_threads_~tmp___3~0#1); 2025856#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2025855#L471 assume !(1 == ~t5_pc~0); 2025854#L471-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2025853#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2025852#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2025851#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2025850#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2025849#L490 assume !(1 == ~t6_pc~0); 2025848#L490-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2025847#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2025846#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2025845#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2025844#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2025843#L509 assume !(1 == ~t7_pc~0); 2025842#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2025840#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2025838#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2025836#L1011 assume !(0 != activate_threads_~tmp___6~0#1); 2025834#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2025833#L857 assume !(1 == ~M_E~0); 2025832#L857-2 assume !(1 == ~T1_E~0); 2025831#L862-1 assume !(1 == ~T2_E~0); 2025830#L867-1 assume !(1 == ~T3_E~0); 2025829#L872-1 assume !(1 == ~T4_E~0); 2025828#L877-1 assume !(1 == ~T5_E~0); 2025827#L882-1 assume !(1 == ~T6_E~0); 2025826#L887-1 assume !(1 == ~T7_E~0); 2025825#L892-1 assume !(1 == ~E_M~0); 2025824#L897-1 assume !(1 == ~E_1~0); 2025823#L902-1 assume !(1 == ~E_2~0); 2025193#L907-1 assume !(1 == ~E_3~0); 2025522#L912-1 assume !(1 == ~E_4~0); 2025511#L917-1 assume !(1 == ~E_5~0); 2025512#L922-1 assume !(1 == ~E_6~0); 2025742#L927-1 assume !(1 == ~E_7~0); 2025496#L932-1 assume { :end_inline_reset_delta_events } true; 2025497#L1178-2 [2021-12-15 17:21:08,380 INFO L793 eck$LassoCheckResult]: Loop: 2025497#L1178-2 assume !false; 2045767#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2045766#L744 assume !false; 2045765#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2045758#L584 assume !(0 == ~m_st~0); 2039294#L588 assume !(0 == ~t1_st~0); 2039292#L592 assume !(0 == ~t2_st~0); 2039290#L596 assume !(0 == ~t3_st~0); 2039288#L600 assume !(0 == ~t4_st~0); 2039286#L604 assume !(0 == ~t5_st~0); 2039284#L608 assume !(0 == ~t6_st~0); 2039281#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2039278#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2039276#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2039273#L641 assume !(0 != eval_~tmp~0#1); 2039270#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2039268#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2039266#L769-3 assume !(0 == ~M_E~0); 2039264#L769-5 assume !(0 == ~T1_E~0); 2039262#L774-3 assume !(0 == ~T2_E~0); 2039260#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2039258#L784-3 assume !(0 == ~T4_E~0); 2039256#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2039254#L794-3 assume !(0 == ~T6_E~0); 2039252#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2039250#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2039248#L809-3 assume !(0 == ~E_1~0); 2039246#L814-3 assume !(0 == ~E_2~0); 2039244#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2039242#L824-3 assume !(0 == ~E_4~0); 2039240#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2039238#L834-3 assume !(0 == ~E_6~0); 2039236#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2039234#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2039230#L376-27 assume 1 == ~m_pc~0; 2039225#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2039218#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2039214#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2039209#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2039201#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2039196#L395-27 assume !(1 == ~t1_pc~0); 2039191#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2039186#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2039181#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2039175#L963-27 assume !(0 != activate_threads_~tmp___0~0#1); 2039169#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2035900#L414-27 assume !(1 == ~t2_pc~0); 2035899#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2035891#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2035892#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2035885#L971-27 assume !(0 != activate_threads_~tmp___1~0#1); 2035886#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2035880#L433-27 assume !(1 == ~t3_pc~0); 2035879#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2035878#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2035877#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2035876#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 2035875#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2035874#L452-27 assume !(1 == ~t4_pc~0); 2035872#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2035871#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2035870#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2035869#L987-27 assume !(0 != activate_threads_~tmp___3~0#1); 2035868#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2035867#L471-27 assume !(1 == ~t5_pc~0); 2034126#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2035866#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2035865#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2035864#L995-27 assume !(0 != activate_threads_~tmp___4~0#1); 2035863#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2035862#L490-27 assume !(1 == ~t6_pc~0); 2032925#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2035861#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2035860#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2035859#L1003-27 assume !(0 != activate_threads_~tmp___5~0#1); 2035858#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2035857#L509-27 assume 1 == ~t7_pc~0; 2035855#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2035853#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2035851#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2035849#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2035848#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2035847#L857-3 assume !(1 == ~M_E~0); 2035367#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2035846#L862-3 assume !(1 == ~T2_E~0); 2035845#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2035844#L872-3 assume !(1 == ~T4_E~0); 2035843#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2035842#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2035841#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2035840#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2035839#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2035837#L902-3 assume !(1 == ~E_2~0); 2035831#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2035721#L912-3 assume !(1 == ~E_4~0); 2035617#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2035424#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2035354#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2035346#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2035340#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2035338#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2035335#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2035331#L1197 assume !(0 == start_simulation_~tmp~3#1); 2035332#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2046048#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2046047#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2046046#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 2046045#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2046044#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2046043#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2046042#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 2025497#L1178-2 [2021-12-15 17:21:08,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:08,382 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 11 times [2021-12-15 17:21:08,383 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:08,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44897302] [2021-12-15 17:21:08,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:08,384 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:08,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:08,394 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:08,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:08,411 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:08,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:08,411 INFO L85 PathProgramCache]: Analyzing trace with hash 2146827838, now seen corresponding path program 1 times [2021-12-15 17:21:08,412 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:08,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568449897] [2021-12-15 17:21:08,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:08,412 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:08,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:08,418 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:08,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:08,433 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:08,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:08,434 INFO L85 PathProgramCache]: Analyzing trace with hash -193867526, now seen corresponding path program 1 times [2021-12-15 17:21:08,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:08,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029746912] [2021-12-15 17:21:08,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:08,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:08,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:08,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:08,456 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:08,456 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029746912] [2021-12-15 17:21:08,457 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029746912] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:08,457 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:08,457 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:08,457 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029536400] [2021-12-15 17:21:08,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:10,478 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:21:10,488 INFO L158 Benchmark]: Toolchain (without parser) took 41082.13ms. Allocated memory was 100.7MB in the beginning and 14.2GB in the end (delta: 14.1GB). Free memory was 73.3MB in the beginning and 10.8GB in the end (delta: -10.8GB). Peak memory consumption was 3.8GB. Max. memory is 16.1GB. [2021-12-15 17:21:10,488 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 100.7MB. Free memory was 60.2MB in the beginning and 60.2MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:21:10,489 INFO L158 Benchmark]: CACSL2BoogieTranslator took 367.83ms. Allocated memory is still 100.7MB. Free memory was 73.0MB in the beginning and 71.7MB in the end (delta: 1.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-15 17:21:10,489 INFO L158 Benchmark]: Boogie Procedure Inliner took 80.15ms. Allocated memory is still 100.7MB. Free memory was 71.7MB in the beginning and 64.8MB in the end (delta: 6.8MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-15 17:21:10,489 INFO L158 Benchmark]: Boogie Preprocessor took 97.12ms. Allocated memory is still 100.7MB. Free memory was 64.8MB in the beginning and 58.9MB in the end (delta: 5.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-15 17:21:10,492 INFO L158 Benchmark]: RCFGBuilder took 1118.52ms. Allocated memory was 100.7MB in the beginning and 140.5MB in the end (delta: 39.8MB). Free memory was 58.5MB in the beginning and 96.0MB in the end (delta: -37.5MB). Peak memory consumption was 32.7MB. Max. memory is 16.1GB. [2021-12-15 17:21:10,492 INFO L158 Benchmark]: BuchiAutomizer took 39413.40ms. Allocated memory was 140.5MB in the beginning and 14.2GB in the end (delta: 14.0GB). Free memory was 96.0MB in the beginning and 10.8GB in the end (delta: -10.7GB). Peak memory consumption was 3.8GB. Max. memory is 16.1GB. [2021-12-15 17:21:10,493 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 100.7MB. Free memory was 60.2MB in the beginning and 60.2MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 367.83ms. Allocated memory is still 100.7MB. Free memory was 73.0MB in the beginning and 71.7MB in the end (delta: 1.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 80.15ms. Allocated memory is still 100.7MB. Free memory was 71.7MB in the beginning and 64.8MB in the end (delta: 6.8MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 97.12ms. Allocated memory is still 100.7MB. Free memory was 64.8MB in the beginning and 58.9MB in the end (delta: 5.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1118.52ms. Allocated memory was 100.7MB in the beginning and 140.5MB in the end (delta: 39.8MB). Free memory was 58.5MB in the beginning and 96.0MB in the end (delta: -37.5MB). Peak memory consumption was 32.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 39413.40ms. Allocated memory was 140.5MB in the beginning and 14.2GB in the end (delta: 14.0GB). Free memory was 96.0MB in the beginning and 10.8GB in the end (delta: -10.7GB). Peak memory consumption was 3.8GB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:21:10,520 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable