./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:29,261 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:29,268 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:29,326 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:29,327 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:29,330 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:29,331 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:29,333 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:29,334 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:29,338 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:29,339 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:29,339 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:29,340 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:29,342 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:29,343 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:29,344 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:29,347 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:29,348 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:29,349 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:29,355 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:29,356 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:29,357 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:29,358 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:29,358 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:29,359 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:29,361 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:29,361 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:29,361 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:29,362 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:29,363 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:29,363 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:29,363 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:29,364 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:29,365 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:29,366 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:29,366 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:29,367 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:29,367 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:29,367 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:29,368 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:29,368 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:29,369 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:29,384 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:29,384 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:29,384 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:29,384 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:29,385 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:29,386 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:29,386 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:29,386 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:29,386 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:29,386 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:29,387 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:29,387 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:29,387 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:29,387 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:29,387 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:29,387 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:29,388 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:29,388 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:29,388 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:29,388 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:29,388 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:29,388 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:29,388 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:29,389 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:29,389 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:29,389 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:29,389 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:29,389 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:29,389 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:29,390 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:29,390 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:29,390 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:29,391 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:29,391 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2021-12-15 17:20:29,612 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:29,627 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:29,630 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:29,630 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:29,631 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:29,632 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2021-12-15 17:20:29,679 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/10ba61323/d17600a885104a6d8aad815dbe2fb29c/FLAG338fa32ad [2021-12-15 17:20:30,058 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:30,060 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2021-12-15 17:20:30,070 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/10ba61323/d17600a885104a6d8aad815dbe2fb29c/FLAG338fa32ad [2021-12-15 17:20:30,457 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/10ba61323/d17600a885104a6d8aad815dbe2fb29c [2021-12-15 17:20:30,459 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:30,460 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:30,475 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:30,476 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:30,479 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:30,479 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,480 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38cd3e09 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30, skipping insertion in model container [2021-12-15 17:20:30,480 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,486 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:30,521 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:30,640 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2021-12-15 17:20:30,713 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:30,732 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:30,740 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2021-12-15 17:20:30,772 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:30,787 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:30,790 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30 WrapperNode [2021-12-15 17:20:30,791 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:30,792 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:30,792 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:30,792 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:30,797 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,811 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,865 INFO L137 Inliner]: procedures = 42, calls = 53, calls flagged for inlining = 48, calls inlined = 135, statements flattened = 2001 [2021-12-15 17:20:30,865 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:30,865 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:30,866 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:30,866 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:30,871 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,871 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,877 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,877 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,902 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,937 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,940 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,946 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:30,947 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:30,947 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:30,947 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:30,959 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (1/1) ... [2021-12-15 17:20:30,974 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:30,983 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:31,007 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:31,012 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:31,033 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:31,033 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:31,034 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:31,034 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:31,131 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:31,138 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:32,085 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:32,093 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:32,093 INFO L301 CfgBuilder]: Removed 10 assume(true) statements. [2021-12-15 17:20:32,095 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:32 BoogieIcfgContainer [2021-12-15 17:20:32,095 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:32,096 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:32,096 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:32,098 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:32,098 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:32,099 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:30" (1/3) ... [2021-12-15 17:20:32,099 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@22149951 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:32, skipping insertion in model container [2021-12-15 17:20:32,099 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:32,100 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:30" (2/3) ... [2021-12-15 17:20:32,100 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@22149951 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:32, skipping insertion in model container [2021-12-15 17:20:32,100 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:32,100 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:32" (3/3) ... [2021-12-15 17:20:32,101 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2021-12-15 17:20:32,138 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:32,138 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:32,138 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:32,138 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:32,139 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:32,139 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:32,139 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:32,139 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:32,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2021-12-15 17:20:32,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,215 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,215 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,215 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:32,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,229 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2021-12-15 17:20:32,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,234 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,234 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,241 INFO L791 eck$LassoCheckResult]: Stem: 411#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 770#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 44#L1153true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 683#L541true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 790#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 212#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 389#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 288#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 747#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 157#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 42#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 777#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 132#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 492#L781true assume !(0 == ~M_E~0); 808#L781-2true assume !(0 == ~T1_E~0); 836#L786-1true assume !(0 == ~T2_E~0); 23#L791-1true assume !(0 == ~T3_E~0); 375#L796-1true assume !(0 == ~T4_E~0); 346#L801-1true assume !(0 == ~T5_E~0); 377#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 753#L811-1true assume !(0 == ~T7_E~0); 136#L816-1true assume !(0 == ~E_M~0); 614#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 345#L831-1true assume !(0 == ~E_3~0); 210#L836-1true assume !(0 == ~E_4~0); 494#L841-1true assume !(0 == ~E_5~0); 110#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 783#L851-1true assume !(0 == ~E_7~0); 122#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 634#L388true assume !(1 == ~m_pc~0); 119#L388-2true is_master_triggered_~__retres1~0#1 := 0; 464#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 674#L400true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46#L967true assume !(0 != activate_threads_~tmp~1#1); 754#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12#L407true assume 1 == ~t1_pc~0; 401#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3#L419true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 604#L975true assume !(0 != activate_threads_~tmp___0~0#1); 628#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L426true assume !(1 == ~t2_pc~0); 644#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 738#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 819#L438true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 730#L983true assume !(0 != activate_threads_~tmp___1~0#1); 837#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238#L445true assume 1 == ~t3_pc~0; 828#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 502#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120#L457true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 425#L991true assume !(0 != activate_threads_~tmp___2~0#1); 498#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 402#L464true assume !(1 == ~t4_pc~0); 124#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 55#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244#L476true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 835#L999true assume !(0 != activate_threads_~tmp___3~0#1); 222#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 398#L483true assume 1 == ~t5_pc~0; 722#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 578#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 327#L495true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 682#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 177#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 442#L502true assume 1 == ~t6_pc~0; 373#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 472#L514true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 313#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 545#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 692#L521true assume !(1 == ~t7_pc~0); 647#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 43#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98#L533true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 594#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 555#L1023-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 450#L869true assume !(1 == ~M_E~0); 218#L869-2true assume !(1 == ~T1_E~0); 723#L874-1true assume !(1 == ~T2_E~0); 667#L879-1true assume !(1 == ~T3_E~0); 268#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 7#L889-1true assume !(1 == ~T5_E~0); 140#L894-1true assume !(1 == ~T6_E~0); 825#L899-1true assume !(1 == ~T7_E~0); 416#L904-1true assume !(1 == ~E_M~0); 232#L909-1true assume !(1 == ~E_1~0); 361#L914-1true assume !(1 == ~E_2~0); 382#L919-1true assume !(1 == ~E_3~0); 186#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L929-1true assume !(1 == ~E_5~0); 687#L934-1true assume !(1 == ~E_6~0); 220#L939-1true assume !(1 == ~E_7~0); 543#L944-1true assume { :end_inline_reset_delta_events } true; 539#L1190-2true [2021-12-15 17:20:32,243 INFO L793 eck$LassoCheckResult]: Loop: 539#L1190-2true assume !false; 137#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 276#L756true assume !true; 823#L771true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271#L541-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 386#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 61#L781-5true assume !(0 == ~T1_E~0); 251#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 299#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 35#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 618#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 178#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 294#L811-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 484#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 645#L821-3true assume !(0 == ~E_1~0); 765#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 422#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 660#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 115#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 593#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 312#L851-3true assume 0 == ~E_7~0;~E_7~0 := 1; 58#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 746#L388-27true assume !(1 == ~m_pc~0); 793#L388-29true is_master_triggered_~__retres1~0#1 := 0; 761#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 554#L400-9true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 690#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 440#L407-27true assume !(1 == ~t1_pc~0); 677#L407-29true is_transmit1_triggered_~__retres1~1#1 := 0; 526#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 303#L419-9true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 468#L975-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 329#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112#L426-27true assume 1 == ~t2_pc~0; 671#L427-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 571#L438-9true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 689#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 589#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 291#L445-27true assume 1 == ~t3_pc~0; 274#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275#L457-9true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 845#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 366#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173#L464-27true assume !(1 == ~t4_pc~0); 32#L464-29true is_transmit4_triggered_~__retres1~4#1 := 0; 64#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 439#L476-9true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 780#L483-27true assume !(1 == ~t5_pc~0); 572#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 59#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 625#L495-9true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 536#L1007-27true assume !(0 != activate_threads_~tmp___4~0#1); 811#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 699#L502-27true assume !(1 == ~t6_pc~0); 309#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 688#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 613#L514-9true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 445#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 735#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8#L521-27true assume 1 == ~t7_pc~0; 193#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 771#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 284#L533-9true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 321#L1023-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 659#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 443#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 250#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 287#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 311#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 282#L889-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 84#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 412#L899-3true assume !(1 == ~T7_E~0); 100#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 265#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 71#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 95#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 605#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 431#L929-3true assume 1 == ~E_5~0;~E_5~0 := 2; 363#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 550#L939-3true assume !(1 == ~E_7~0); 104#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 588#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 653#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 255#L639-1true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 776#L1209true assume !(0 == start_simulation_~tmp~3#1); 307#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 293#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 530#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 334#L639-2true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 596#L1164true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 156#L1172true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 130#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 539#L1190-2true [2021-12-15 17:20:32,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2021-12-15 17:20:32,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694712621] [2021-12-15 17:20:32,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,415 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,416 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694712621] [2021-12-15 17:20:32,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694712621] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,417 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,418 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,419 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1399067609] [2021-12-15 17:20:32,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,423 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,425 INFO L85 PathProgramCache]: Analyzing trace with hash -432739696, now seen corresponding path program 1 times [2021-12-15 17:20:32,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [525601604] [2021-12-15 17:20:32,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,425 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,458 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [525601604] [2021-12-15 17:20:32,459 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [525601604] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,459 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,459 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:32,459 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584116067] [2021-12-15 17:20:32,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,461 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,462 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,488 INFO L87 Difference]: Start difference. First operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,538 INFO L93 Difference]: Finished difference Result 841 states and 1255 transitions. [2021-12-15 17:20:32,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841 states and 1255 transitions. [2021-12-15 17:20:32,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:32,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841 states to 835 states and 1249 transitions. [2021-12-15 17:20:32,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2021-12-15 17:20:32,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2021-12-15 17:20:32,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1249 transitions. [2021-12-15 17:20:32,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,582 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2021-12-15 17:20:32,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1249 transitions. [2021-12-15 17:20:32,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2021-12-15 17:20:32,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1249 transitions. [2021-12-15 17:20:32,625 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2021-12-15 17:20:32,625 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2021-12-15 17:20:32,625 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:32,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1249 transitions. [2021-12-15 17:20:32,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:32,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,631 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,631 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,631 INFO L791 eck$LassoCheckResult]: Stem: 2328#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2329#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1782#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1783#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2503#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2078#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2079#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2198#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2199#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1991#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1778#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1779#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1948#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1949#L781 assume !(0 == ~M_E~0); 2403#L781-2 assume !(0 == ~T1_E~0); 2526#L786-1 assume !(0 == ~T2_E~0); 1739#L791-1 assume !(0 == ~T3_E~0); 1740#L796-1 assume !(0 == ~T4_E~0); 2265#L801-1 assume !(0 == ~T5_E~0); 2266#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2292#L811-1 assume !(0 == ~T7_E~0); 1957#L816-1 assume !(0 == ~E_M~0); 1958#L821-1 assume !(0 == ~E_1~0); 1767#L826-1 assume !(0 == ~E_2~0); 1768#L831-1 assume !(0 == ~E_3~0); 2075#L836-1 assume !(0 == ~E_4~0); 2076#L841-1 assume !(0 == ~E_5~0); 1910#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1911#L851-1 assume !(0 == ~E_7~0); 1933#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1934#L388 assume !(1 == ~m_pc~0); 1927#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1928#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2376#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1786#L967 assume !(0 != activate_threads_~tmp~1#1); 1787#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1714#L407 assume 1 == ~t1_pc~0; 1715#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1719#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1693#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1694#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2474#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2037#L426 assume !(1 == ~t2_pc~0); 2038#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2489#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2518#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2516#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2517#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2117#L445 assume 1 == ~t3_pc~0; 2118#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2407#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1929#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1930#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2344#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2315#L464 assume !(1 == ~t4_pc~0); 1936#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1807#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1808#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2128#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2093#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2094#L483 assume 1 == ~t5_pc~0; 2312#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2454#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2247#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2248#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2021#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2022#L502 assume 1 == ~t6_pc~0; 2289#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1838#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1839#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2231#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2232#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2431#L521 assume !(1 == ~t7_pc~0); 2470#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1780#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1781#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1888#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2438#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2365#L869 assume !(1 == ~M_E~0); 2086#L869-2 assume !(1 == ~T1_E~0); 2087#L874-1 assume !(1 == ~T2_E~0); 2499#L879-1 assume !(1 == ~T3_E~0); 2167#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1702#L889-1 assume !(1 == ~T5_E~0); 1703#L894-1 assume !(1 == ~T6_E~0); 1964#L899-1 assume !(1 == ~T7_E~0); 2332#L904-1 assume !(1 == ~E_M~0); 2109#L909-1 assume !(1 == ~E_1~0); 2110#L914-1 assume !(1 == ~E_2~0); 2279#L919-1 assume !(1 == ~E_3~0); 2036#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1876#L929-1 assume !(1 == ~E_5~0); 1877#L934-1 assume !(1 == ~E_6~0); 2089#L939-1 assume !(1 == ~E_7~0); 2090#L944-1 assume { :end_inline_reset_delta_events } true; 1946#L1190-2 [2021-12-15 17:20:32,632 INFO L793 eck$LassoCheckResult]: Loop: 1946#L1190-2 assume !false; 1959#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1960#L756 assume !false; 2182#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2522#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1800#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2308#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2131#L653 assume !(0 != eval_~tmp~0#1); 2133#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2173#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2174#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1819#L781-5 assume !(0 == ~T1_E~0); 1820#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2140#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1763#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1764#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2023#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2024#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2206#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2393#L821-3 assume !(0 == ~E_1~0); 2490#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2339#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2340#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1920#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1921#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2230#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1814#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1815#L388-27 assume 1 == ~m_pc~0; 2465#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2467#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2436#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2437#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1994#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1995#L407-27 assume 1 == ~t1_pc~0; 2345#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2346#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2218#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2219#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2250#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1914#L426-27 assume !(1 == ~t2_pc~0); 1915#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1925#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1926#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2450#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2463#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2201#L445-27 assume 1 == ~t3_pc~0; 2179#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1760#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1761#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2181#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2284#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2015#L464-27 assume 1 == ~t4_pc~0; 2016#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1759#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1826#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2207#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1906#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1907#L483-27 assume 1 == ~t5_pc~0; 2412#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1816#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1817#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2426#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2427#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2506#L502-27 assume !(1 == ~t6_pc~0); 2226#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2227#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2476#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2362#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2363#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1704#L521-27 assume !(1 == ~t7_pc~0); 1705#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2047#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2194#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1754#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1755#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2242#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2359#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2138#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2139#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2197#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2193#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1864#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1865#L899-3 assume !(1 == ~T7_E~0); 1892#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1893#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1840#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1841#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1884#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2351#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2280#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2281#L939-3 assume !(1 == ~E_7~0); 1899#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1900#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1721#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2147#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2148#L1209 assume !(0 == start_simulation_~tmp~3#1); 2222#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2205#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1857#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2253#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2254#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1748#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1749#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1945#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1946#L1190-2 [2021-12-15 17:20:32,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,632 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2021-12-15 17:20:32,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017056634] [2021-12-15 17:20:32,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,633 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,694 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017056634] [2021-12-15 17:20:32,694 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017056634] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,694 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,695 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,695 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084485204] [2021-12-15 17:20:32,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,695 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,696 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 1 times [2021-12-15 17:20:32,696 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007147661] [2021-12-15 17:20:32,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,697 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007147661] [2021-12-15 17:20:32,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007147661] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,771 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,771 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,771 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211811193] [2021-12-15 17:20:32,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,771 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,771 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,772 INFO L87 Difference]: Start difference. First operand 835 states and 1249 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,802 INFO L93 Difference]: Finished difference Result 835 states and 1248 transitions. [2021-12-15 17:20:32,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1248 transitions. [2021-12-15 17:20:32,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:32,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1248 transitions. [2021-12-15 17:20:32,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2021-12-15 17:20:32,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2021-12-15 17:20:32,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1248 transitions. [2021-12-15 17:20:32,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,814 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2021-12-15 17:20:32,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1248 transitions. [2021-12-15 17:20:32,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2021-12-15 17:20:32,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1248 transitions. [2021-12-15 17:20:32,830 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2021-12-15 17:20:32,830 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2021-12-15 17:20:32,831 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:32,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1248 transitions. [2021-12-15 17:20:32,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:32,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:32,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:32,839 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:32,841 INFO L791 eck$LassoCheckResult]: Stem: 4005#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 4006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3459#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3460#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4180#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3755#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3756#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3875#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3876#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3668#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3455#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3456#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3625#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3626#L781 assume !(0 == ~M_E~0); 4080#L781-2 assume !(0 == ~T1_E~0); 4203#L786-1 assume !(0 == ~T2_E~0); 3416#L791-1 assume !(0 == ~T3_E~0); 3417#L796-1 assume !(0 == ~T4_E~0); 3942#L801-1 assume !(0 == ~T5_E~0); 3943#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3969#L811-1 assume !(0 == ~T7_E~0); 3634#L816-1 assume !(0 == ~E_M~0); 3635#L821-1 assume !(0 == ~E_1~0); 3444#L826-1 assume !(0 == ~E_2~0); 3445#L831-1 assume !(0 == ~E_3~0); 3752#L836-1 assume !(0 == ~E_4~0); 3753#L841-1 assume !(0 == ~E_5~0); 3587#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3588#L851-1 assume !(0 == ~E_7~0); 3610#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3611#L388 assume !(1 == ~m_pc~0); 3604#L388-2 is_master_triggered_~__retres1~0#1 := 0; 3605#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4053#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3463#L967 assume !(0 != activate_threads_~tmp~1#1); 3464#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3391#L407 assume 1 == ~t1_pc~0; 3392#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3396#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3370#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3371#L975 assume !(0 != activate_threads_~tmp___0~0#1); 4151#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3714#L426 assume !(1 == ~t2_pc~0); 3715#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4166#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4195#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4193#L983 assume !(0 != activate_threads_~tmp___1~0#1); 4194#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3794#L445 assume 1 == ~t3_pc~0; 3795#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4084#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3606#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3607#L991 assume !(0 != activate_threads_~tmp___2~0#1); 4021#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3992#L464 assume !(1 == ~t4_pc~0); 3613#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3484#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3485#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3805#L999 assume !(0 != activate_threads_~tmp___3~0#1); 3770#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3771#L483 assume 1 == ~t5_pc~0; 3989#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4131#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3924#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3925#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 3698#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3699#L502 assume 1 == ~t6_pc~0; 3966#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3515#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3516#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3908#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 3909#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4108#L521 assume !(1 == ~t7_pc~0); 4147#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3457#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3458#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3565#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4115#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4042#L869 assume !(1 == ~M_E~0); 3763#L869-2 assume !(1 == ~T1_E~0); 3764#L874-1 assume !(1 == ~T2_E~0); 4176#L879-1 assume !(1 == ~T3_E~0); 3844#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3379#L889-1 assume !(1 == ~T5_E~0); 3380#L894-1 assume !(1 == ~T6_E~0); 3641#L899-1 assume !(1 == ~T7_E~0); 4009#L904-1 assume !(1 == ~E_M~0); 3786#L909-1 assume !(1 == ~E_1~0); 3787#L914-1 assume !(1 == ~E_2~0); 3956#L919-1 assume !(1 == ~E_3~0); 3713#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3553#L929-1 assume !(1 == ~E_5~0); 3554#L934-1 assume !(1 == ~E_6~0); 3766#L939-1 assume !(1 == ~E_7~0); 3767#L944-1 assume { :end_inline_reset_delta_events } true; 3623#L1190-2 [2021-12-15 17:20:32,842 INFO L793 eck$LassoCheckResult]: Loop: 3623#L1190-2 assume !false; 3636#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3637#L756 assume !false; 3859#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4199#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3477#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3985#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3808#L653 assume !(0 != eval_~tmp~0#1); 3810#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3850#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3851#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3496#L781-5 assume !(0 == ~T1_E~0); 3497#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3817#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3440#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3441#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3700#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3701#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3883#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4070#L821-3 assume !(0 == ~E_1~0); 4167#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4016#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4017#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3597#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3598#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3907#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3491#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3492#L388-27 assume 1 == ~m_pc~0; 4142#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4144#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4113#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4114#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3671#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3672#L407-27 assume 1 == ~t1_pc~0; 4022#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4023#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3895#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3896#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3927#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3591#L426-27 assume !(1 == ~t2_pc~0); 3592#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 3602#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3603#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4127#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4140#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3878#L445-27 assume 1 == ~t3_pc~0; 3856#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3437#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3438#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3858#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3961#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3692#L464-27 assume !(1 == ~t4_pc~0); 3435#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 3436#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3503#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3884#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3583#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3584#L483-27 assume 1 == ~t5_pc~0; 4089#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3493#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3494#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4103#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 4104#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4183#L502-27 assume 1 == ~t6_pc~0; 4184#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3904#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4153#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4039#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4040#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3381#L521-27 assume !(1 == ~t7_pc~0); 3382#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 3724#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3871#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3431#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3432#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3919#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4036#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3815#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3816#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3874#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3870#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3541#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3542#L899-3 assume !(1 == ~T7_E~0); 3569#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3570#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3517#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3518#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3561#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4028#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3957#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3958#L939-3 assume !(1 == ~E_7~0); 3576#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3577#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3398#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3824#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3825#L1209 assume !(0 == start_simulation_~tmp~3#1); 3899#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3882#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3534#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3930#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3931#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3425#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3426#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3622#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3623#L1190-2 [2021-12-15 17:20:32,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,843 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2021-12-15 17:20:32,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574656117] [2021-12-15 17:20:32,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,844 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,897 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,897 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574656117] [2021-12-15 17:20:32,897 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574656117] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,897 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,898 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838624771] [2021-12-15 17:20:32,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,898 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:32,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:32,899 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 1 times [2021-12-15 17:20:32,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:32,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672404020] [2021-12-15 17:20:32,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:32,901 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:32,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:32,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:32,959 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:32,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672404020] [2021-12-15 17:20:32,960 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672404020] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:32,960 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:32,960 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:32,960 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [212013077] [2021-12-15 17:20:32,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:32,969 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:32,971 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:32,972 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:32,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:32,972 INFO L87 Difference]: Start difference. First operand 835 states and 1248 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:32,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:32,988 INFO L93 Difference]: Finished difference Result 835 states and 1247 transitions. [2021-12-15 17:20:32,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:32,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1247 transitions. [2021-12-15 17:20:32,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:32,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1247 transitions. [2021-12-15 17:20:32,996 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2021-12-15 17:20:32,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2021-12-15 17:20:32,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1247 transitions. [2021-12-15 17:20:32,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:32,998 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2021-12-15 17:20:32,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1247 transitions. [2021-12-15 17:20:33,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2021-12-15 17:20:33,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1247 transitions. [2021-12-15 17:20:33,008 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2021-12-15 17:20:33,008 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2021-12-15 17:20:33,008 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:33,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1247 transitions. [2021-12-15 17:20:33,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,015 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,015 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,016 INFO L791 eck$LassoCheckResult]: Stem: 5682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5136#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5137#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5857#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5432#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5433#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5552#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5553#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5345#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5132#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5133#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5302#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5303#L781 assume !(0 == ~M_E~0); 5757#L781-2 assume !(0 == ~T1_E~0); 5880#L786-1 assume !(0 == ~T2_E~0); 5093#L791-1 assume !(0 == ~T3_E~0); 5094#L796-1 assume !(0 == ~T4_E~0); 5619#L801-1 assume !(0 == ~T5_E~0); 5620#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5646#L811-1 assume !(0 == ~T7_E~0); 5311#L816-1 assume !(0 == ~E_M~0); 5312#L821-1 assume !(0 == ~E_1~0); 5121#L826-1 assume !(0 == ~E_2~0); 5122#L831-1 assume !(0 == ~E_3~0); 5429#L836-1 assume !(0 == ~E_4~0); 5430#L841-1 assume !(0 == ~E_5~0); 5264#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5265#L851-1 assume !(0 == ~E_7~0); 5287#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5288#L388 assume !(1 == ~m_pc~0); 5281#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5282#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5730#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5140#L967 assume !(0 != activate_threads_~tmp~1#1); 5141#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5068#L407 assume 1 == ~t1_pc~0; 5069#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5073#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5047#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5048#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5828#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5391#L426 assume !(1 == ~t2_pc~0); 5392#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5843#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5872#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5870#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5871#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5471#L445 assume 1 == ~t3_pc~0; 5472#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5761#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5283#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5284#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5698#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5669#L464 assume !(1 == ~t4_pc~0); 5290#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5161#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5162#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5482#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5447#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5448#L483 assume 1 == ~t5_pc~0; 5666#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5808#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5601#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5602#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5375#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5376#L502 assume 1 == ~t6_pc~0; 5643#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5192#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5193#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5585#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5586#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5785#L521 assume !(1 == ~t7_pc~0); 5824#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5134#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5135#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5242#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5792#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5719#L869 assume !(1 == ~M_E~0); 5440#L869-2 assume !(1 == ~T1_E~0); 5441#L874-1 assume !(1 == ~T2_E~0); 5853#L879-1 assume !(1 == ~T3_E~0); 5521#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5056#L889-1 assume !(1 == ~T5_E~0); 5057#L894-1 assume !(1 == ~T6_E~0); 5318#L899-1 assume !(1 == ~T7_E~0); 5686#L904-1 assume !(1 == ~E_M~0); 5463#L909-1 assume !(1 == ~E_1~0); 5464#L914-1 assume !(1 == ~E_2~0); 5633#L919-1 assume !(1 == ~E_3~0); 5390#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5230#L929-1 assume !(1 == ~E_5~0); 5231#L934-1 assume !(1 == ~E_6~0); 5443#L939-1 assume !(1 == ~E_7~0); 5444#L944-1 assume { :end_inline_reset_delta_events } true; 5300#L1190-2 [2021-12-15 17:20:33,016 INFO L793 eck$LassoCheckResult]: Loop: 5300#L1190-2 assume !false; 5313#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5314#L756 assume !false; 5536#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5876#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5154#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5662#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5485#L653 assume !(0 != eval_~tmp~0#1); 5487#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5527#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5528#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5173#L781-5 assume !(0 == ~T1_E~0); 5174#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5494#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5117#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5118#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5377#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5378#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5560#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5747#L821-3 assume !(0 == ~E_1~0); 5844#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5693#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5694#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5274#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5275#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5584#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5168#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5169#L388-27 assume 1 == ~m_pc~0; 5819#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5821#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5790#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5791#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5348#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5349#L407-27 assume 1 == ~t1_pc~0; 5699#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5700#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5572#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5573#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5604#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5268#L426-27 assume !(1 == ~t2_pc~0); 5269#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 5279#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5280#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5804#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5817#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5555#L445-27 assume 1 == ~t3_pc~0; 5533#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5114#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5115#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5535#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5638#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5369#L464-27 assume !(1 == ~t4_pc~0); 5112#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5113#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5180#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5561#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5260#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5261#L483-27 assume 1 == ~t5_pc~0; 5766#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5170#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5171#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5780#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 5781#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5860#L502-27 assume 1 == ~t6_pc~0; 5861#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5581#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5830#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5716#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5717#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5058#L521-27 assume !(1 == ~t7_pc~0); 5059#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5401#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5548#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5108#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5109#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5596#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5713#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5492#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5493#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5551#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5547#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5218#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5219#L899-3 assume !(1 == ~T7_E~0); 5246#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5247#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5194#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5195#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5238#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5705#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5634#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5635#L939-3 assume !(1 == ~E_7~0); 5253#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5254#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5075#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5501#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5502#L1209 assume !(0 == start_simulation_~tmp~3#1); 5576#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5559#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5211#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5607#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5608#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5102#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5103#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5299#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5300#L1190-2 [2021-12-15 17:20:33,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,017 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2021-12-15 17:20:33,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791317263] [2021-12-15 17:20:33,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,018 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791317263] [2021-12-15 17:20:33,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791317263] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902439575] [2021-12-15 17:20:33,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,057 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,058 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 2 times [2021-12-15 17:20:33,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327139442] [2021-12-15 17:20:33,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,115 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327139442] [2021-12-15 17:20:33,116 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1327139442] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,116 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,116 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,116 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289476943] [2021-12-15 17:20:33,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,117 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,117 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:33,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:33,118 INFO L87 Difference]: Start difference. First operand 835 states and 1247 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,131 INFO L93 Difference]: Finished difference Result 835 states and 1246 transitions. [2021-12-15 17:20:33,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:33,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1246 transitions. [2021-12-15 17:20:33,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1246 transitions. [2021-12-15 17:20:33,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2021-12-15 17:20:33,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2021-12-15 17:20:33,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1246 transitions. [2021-12-15 17:20:33,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,139 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2021-12-15 17:20:33,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1246 transitions. [2021-12-15 17:20:33,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2021-12-15 17:20:33,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1246 transitions. [2021-12-15 17:20:33,149 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2021-12-15 17:20:33,150 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2021-12-15 17:20:33,150 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:33,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1246 transitions. [2021-12-15 17:20:33,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,156 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,157 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,157 INFO L791 eck$LassoCheckResult]: Stem: 7359#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6813#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6814#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7534#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7109#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7110#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7229#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7230#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7022#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6809#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6810#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6982#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6983#L781 assume !(0 == ~M_E~0); 7435#L781-2 assume !(0 == ~T1_E~0); 7557#L786-1 assume !(0 == ~T2_E~0); 6770#L791-1 assume !(0 == ~T3_E~0); 6771#L796-1 assume !(0 == ~T4_E~0); 7296#L801-1 assume !(0 == ~T5_E~0); 7297#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7323#L811-1 assume !(0 == ~T7_E~0); 6988#L816-1 assume !(0 == ~E_M~0); 6989#L821-1 assume !(0 == ~E_1~0); 6798#L826-1 assume !(0 == ~E_2~0); 6799#L831-1 assume !(0 == ~E_3~0); 7106#L836-1 assume !(0 == ~E_4~0); 7107#L841-1 assume !(0 == ~E_5~0); 6943#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6944#L851-1 assume !(0 == ~E_7~0); 6964#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6965#L388 assume !(1 == ~m_pc~0); 6958#L388-2 is_master_triggered_~__retres1~0#1 := 0; 6959#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7407#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6817#L967 assume !(0 != activate_threads_~tmp~1#1); 6818#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6745#L407 assume 1 == ~t1_pc~0; 6746#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6753#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6724#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6725#L975 assume !(0 != activate_threads_~tmp___0~0#1); 7505#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7068#L426 assume !(1 == ~t2_pc~0); 7069#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7520#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7549#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7547#L983 assume !(0 != activate_threads_~tmp___1~0#1); 7548#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7148#L445 assume 1 == ~t3_pc~0; 7149#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7438#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6960#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6961#L991 assume !(0 != activate_threads_~tmp___2~0#1); 7375#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7346#L464 assume !(1 == ~t4_pc~0); 6967#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6838#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6839#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7161#L999 assume !(0 != activate_threads_~tmp___3~0#1); 7124#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7125#L483 assume 1 == ~t5_pc~0; 7343#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7485#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7278#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7279#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 7052#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7053#L502 assume 1 == ~t6_pc~0; 7321#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6869#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6870#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7262#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 7263#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7462#L521 assume !(1 == ~t7_pc~0); 7501#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6811#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6812#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6919#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7469#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7398#L869 assume !(1 == ~M_E~0); 7117#L869-2 assume !(1 == ~T1_E~0); 7118#L874-1 assume !(1 == ~T2_E~0); 7530#L879-1 assume !(1 == ~T3_E~0); 7198#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6733#L889-1 assume !(1 == ~T5_E~0); 6734#L894-1 assume !(1 == ~T6_E~0); 6998#L899-1 assume !(1 == ~T7_E~0); 7365#L904-1 assume !(1 == ~E_M~0); 7140#L909-1 assume !(1 == ~E_1~0); 7141#L914-1 assume !(1 == ~E_2~0); 7310#L919-1 assume !(1 == ~E_3~0); 7067#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6907#L929-1 assume !(1 == ~E_5~0); 6908#L934-1 assume !(1 == ~E_6~0); 7122#L939-1 assume !(1 == ~E_7~0); 7123#L944-1 assume { :end_inline_reset_delta_events } true; 6976#L1190-2 [2021-12-15 17:20:33,158 INFO L793 eck$LassoCheckResult]: Loop: 6976#L1190-2 assume !false; 6990#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6991#L756 assume !false; 7213#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7553#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6833#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7339#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7164#L653 assume !(0 != eval_~tmp~0#1); 7166#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7204#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7205#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6850#L781-5 assume !(0 == ~T1_E~0); 6851#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7171#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6794#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6795#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7054#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7055#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7238#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7424#L821-3 assume !(0 == ~E_1~0); 7521#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7370#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7371#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6951#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6952#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7261#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6845#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6846#L388-27 assume 1 == ~m_pc~0; 7496#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7498#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7467#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7468#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7025#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7026#L407-27 assume 1 == ~t1_pc~0; 7376#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7377#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7247#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7248#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7281#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6945#L426-27 assume !(1 == ~t2_pc~0); 6946#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 6956#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6957#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7481#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7494#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7232#L445-27 assume 1 == ~t3_pc~0; 7208#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6791#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6792#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7212#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7314#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7046#L464-27 assume !(1 == ~t4_pc~0); 6789#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 6790#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6857#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7237#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6937#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6938#L483-27 assume 1 == ~t5_pc~0; 7443#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6847#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6848#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7457#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 7458#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7537#L502-27 assume 1 == ~t6_pc~0; 7538#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7258#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7507#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7393#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7394#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6735#L521-27 assume !(1 == ~t7_pc~0); 6736#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 7078#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7225#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6785#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6786#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7273#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7390#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7169#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7170#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7228#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7224#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6895#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6896#L899-3 assume !(1 == ~T7_E~0); 6923#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6924#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6871#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6872#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6915#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7382#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7311#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7312#L939-3 assume !(1 == ~E_7~0); 6929#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6930#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6751#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7178#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7179#L1209 assume !(0 == start_simulation_~tmp~3#1); 7253#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7236#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6888#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7284#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7285#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6779#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6780#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6975#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 6976#L1190-2 [2021-12-15 17:20:33,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,158 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2021-12-15 17:20:33,158 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179780963] [2021-12-15 17:20:33,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,159 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,197 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179780963] [2021-12-15 17:20:33,198 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179780963] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,198 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,198 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513199119] [2021-12-15 17:20:33,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,199 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,199 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 3 times [2021-12-15 17:20:33,199 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578094537] [2021-12-15 17:20:33,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,200 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578094537] [2021-12-15 17:20:33,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578094537] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,267 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830891920] [2021-12-15 17:20:33,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,268 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,268 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:33,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:33,268 INFO L87 Difference]: Start difference. First operand 835 states and 1246 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,279 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2021-12-15 17:20:33,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:33,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2021-12-15 17:20:33,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1245 transitions. [2021-12-15 17:20:33,287 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2021-12-15 17:20:33,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2021-12-15 17:20:33,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1245 transitions. [2021-12-15 17:20:33,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,289 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2021-12-15 17:20:33,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1245 transitions. [2021-12-15 17:20:33,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2021-12-15 17:20:33,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1245 transitions. [2021-12-15 17:20:33,299 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2021-12-15 17:20:33,299 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2021-12-15 17:20:33,299 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:33,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1245 transitions. [2021-12-15 17:20:33,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,303 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,303 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,304 INFO L791 eck$LassoCheckResult]: Stem: 9036#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 9037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8490#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8491#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9211#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8786#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8787#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8906#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8907#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8699#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8486#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8487#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8659#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8660#L781 assume !(0 == ~M_E~0); 9111#L781-2 assume !(0 == ~T1_E~0); 9234#L786-1 assume !(0 == ~T2_E~0); 8447#L791-1 assume !(0 == ~T3_E~0); 8448#L796-1 assume !(0 == ~T4_E~0); 8973#L801-1 assume !(0 == ~T5_E~0); 8974#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9000#L811-1 assume !(0 == ~T7_E~0); 8665#L816-1 assume !(0 == ~E_M~0); 8666#L821-1 assume !(0 == ~E_1~0); 8475#L826-1 assume !(0 == ~E_2~0); 8476#L831-1 assume !(0 == ~E_3~0); 8783#L836-1 assume !(0 == ~E_4~0); 8784#L841-1 assume !(0 == ~E_5~0); 8618#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8619#L851-1 assume !(0 == ~E_7~0); 8641#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8642#L388 assume !(1 == ~m_pc~0); 8635#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8636#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9084#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8494#L967 assume !(0 != activate_threads_~tmp~1#1); 8495#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8422#L407 assume 1 == ~t1_pc~0; 8423#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8430#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8401#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8402#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9182#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8745#L426 assume !(1 == ~t2_pc~0); 8746#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9197#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9226#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9224#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9225#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8825#L445 assume 1 == ~t3_pc~0; 8826#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9115#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8637#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8638#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9052#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9023#L464 assume !(1 == ~t4_pc~0); 8644#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8515#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8516#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8836#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8801#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8802#L483 assume 1 == ~t5_pc~0; 9020#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9162#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8955#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8956#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8729#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8730#L502 assume 1 == ~t6_pc~0; 8998#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8546#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8547#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8939#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 8940#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9139#L521 assume !(1 == ~t7_pc~0); 9178#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8488#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8489#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8596#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9146#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9073#L869 assume !(1 == ~M_E~0); 8794#L869-2 assume !(1 == ~T1_E~0); 8795#L874-1 assume !(1 == ~T2_E~0); 9207#L879-1 assume !(1 == ~T3_E~0); 8875#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8410#L889-1 assume !(1 == ~T5_E~0); 8411#L894-1 assume !(1 == ~T6_E~0); 8672#L899-1 assume !(1 == ~T7_E~0); 9042#L904-1 assume !(1 == ~E_M~0); 8817#L909-1 assume !(1 == ~E_1~0); 8818#L914-1 assume !(1 == ~E_2~0); 8987#L919-1 assume !(1 == ~E_3~0); 8744#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8584#L929-1 assume !(1 == ~E_5~0); 8585#L934-1 assume !(1 == ~E_6~0); 8797#L939-1 assume !(1 == ~E_7~0); 8798#L944-1 assume { :end_inline_reset_delta_events } true; 8653#L1190-2 [2021-12-15 17:20:33,304 INFO L793 eck$LassoCheckResult]: Loop: 8653#L1190-2 assume !false; 8667#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8668#L756 assume !false; 8890#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9230#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8510#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9016#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8839#L653 assume !(0 != eval_~tmp~0#1); 8841#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8881#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8882#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8527#L781-5 assume !(0 == ~T1_E~0); 8528#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8848#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8471#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8472#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8731#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8732#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8914#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9101#L821-3 assume !(0 == ~E_1~0); 9198#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9047#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9048#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8628#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8629#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8938#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8522#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8523#L388-27 assume 1 == ~m_pc~0; 9173#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9175#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9144#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9145#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8702#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8703#L407-27 assume 1 == ~t1_pc~0; 9053#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9054#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8926#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8927#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8958#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8622#L426-27 assume 1 == ~t2_pc~0; 8624#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8633#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8634#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9158#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9171#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8909#L445-27 assume 1 == ~t3_pc~0; 8887#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8468#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8469#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8889#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8992#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8723#L464-27 assume !(1 == ~t4_pc~0); 8466#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8467#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8534#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8915#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8614#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8615#L483-27 assume 1 == ~t5_pc~0; 9120#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8524#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8525#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9134#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 9135#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9214#L502-27 assume !(1 == ~t6_pc~0); 8934#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 8935#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9184#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9070#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9071#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8412#L521-27 assume !(1 == ~t7_pc~0); 8413#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8755#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8902#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8462#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8463#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8948#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9067#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8846#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8847#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8905#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8901#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8572#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8573#L899-3 assume !(1 == ~T7_E~0); 8600#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8601#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8548#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8549#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8590#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9059#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8988#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8989#L939-3 assume !(1 == ~E_7~0); 8606#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8607#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8428#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8854#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8855#L1209 assume !(0 == start_simulation_~tmp~3#1); 8930#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8913#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8565#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8960#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8961#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8456#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8457#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8652#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8653#L1190-2 [2021-12-15 17:20:33,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,305 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2021-12-15 17:20:33,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350655385] [2021-12-15 17:20:33,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350655385] [2021-12-15 17:20:33,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350655385] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1824312808] [2021-12-15 17:20:33,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,326 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,327 INFO L85 PathProgramCache]: Analyzing trace with hash -1001713119, now seen corresponding path program 1 times [2021-12-15 17:20:33,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023909964] [2021-12-15 17:20:33,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,331 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,367 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,367 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023909964] [2021-12-15 17:20:33,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1023909964] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,368 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,368 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,368 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198506401] [2021-12-15 17:20:33,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,368 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,369 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:33,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:33,369 INFO L87 Difference]: Start difference. First operand 835 states and 1245 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,381 INFO L93 Difference]: Finished difference Result 835 states and 1244 transitions. [2021-12-15 17:20:33,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:33,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1244 transitions. [2021-12-15 17:20:33,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1244 transitions. [2021-12-15 17:20:33,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2021-12-15 17:20:33,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2021-12-15 17:20:33,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1244 transitions. [2021-12-15 17:20:33,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,389 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2021-12-15 17:20:33,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1244 transitions. [2021-12-15 17:20:33,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2021-12-15 17:20:33,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1244 transitions. [2021-12-15 17:20:33,399 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2021-12-15 17:20:33,399 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2021-12-15 17:20:33,399 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:33,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1244 transitions. [2021-12-15 17:20:33,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,403 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,403 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,403 INFO L791 eck$LassoCheckResult]: Stem: 10713#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10167#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10168#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10888#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10463#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10464#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10583#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10584#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10376#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10163#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10164#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10333#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10334#L781 assume !(0 == ~M_E~0); 10788#L781-2 assume !(0 == ~T1_E~0); 10911#L786-1 assume !(0 == ~T2_E~0); 10124#L791-1 assume !(0 == ~T3_E~0); 10125#L796-1 assume !(0 == ~T4_E~0); 10650#L801-1 assume !(0 == ~T5_E~0); 10651#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10677#L811-1 assume !(0 == ~T7_E~0); 10342#L816-1 assume !(0 == ~E_M~0); 10343#L821-1 assume !(0 == ~E_1~0); 10152#L826-1 assume !(0 == ~E_2~0); 10153#L831-1 assume !(0 == ~E_3~0); 10460#L836-1 assume !(0 == ~E_4~0); 10461#L841-1 assume !(0 == ~E_5~0); 10295#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10296#L851-1 assume !(0 == ~E_7~0); 10318#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10319#L388 assume !(1 == ~m_pc~0); 10312#L388-2 is_master_triggered_~__retres1~0#1 := 0; 10313#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10761#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10171#L967 assume !(0 != activate_threads_~tmp~1#1); 10172#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10099#L407 assume 1 == ~t1_pc~0; 10100#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10104#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10078#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10079#L975 assume !(0 != activate_threads_~tmp___0~0#1); 10859#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10422#L426 assume !(1 == ~t2_pc~0); 10423#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10874#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10903#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10901#L983 assume !(0 != activate_threads_~tmp___1~0#1); 10902#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10502#L445 assume 1 == ~t3_pc~0; 10503#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10792#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10314#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10315#L991 assume !(0 != activate_threads_~tmp___2~0#1); 10729#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10700#L464 assume !(1 == ~t4_pc~0); 10321#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10192#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10193#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10513#L999 assume !(0 != activate_threads_~tmp___3~0#1); 10478#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10479#L483 assume 1 == ~t5_pc~0; 10697#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10839#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10632#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10633#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 10406#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10407#L502 assume 1 == ~t6_pc~0; 10674#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10223#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10224#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10616#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 10617#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10816#L521 assume !(1 == ~t7_pc~0); 10855#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10165#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10166#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10273#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10823#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10750#L869 assume !(1 == ~M_E~0); 10471#L869-2 assume !(1 == ~T1_E~0); 10472#L874-1 assume !(1 == ~T2_E~0); 10884#L879-1 assume !(1 == ~T3_E~0); 10552#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10087#L889-1 assume !(1 == ~T5_E~0); 10088#L894-1 assume !(1 == ~T6_E~0); 10349#L899-1 assume !(1 == ~T7_E~0); 10717#L904-1 assume !(1 == ~E_M~0); 10494#L909-1 assume !(1 == ~E_1~0); 10495#L914-1 assume !(1 == ~E_2~0); 10664#L919-1 assume !(1 == ~E_3~0); 10421#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10261#L929-1 assume !(1 == ~E_5~0); 10262#L934-1 assume !(1 == ~E_6~0); 10474#L939-1 assume !(1 == ~E_7~0); 10475#L944-1 assume { :end_inline_reset_delta_events } true; 10331#L1190-2 [2021-12-15 17:20:33,403 INFO L793 eck$LassoCheckResult]: Loop: 10331#L1190-2 assume !false; 10344#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10345#L756 assume !false; 10567#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10907#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10185#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10693#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10516#L653 assume !(0 != eval_~tmp~0#1); 10518#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10558#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10559#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10204#L781-5 assume !(0 == ~T1_E~0); 10205#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10525#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10148#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10149#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10408#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10409#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10591#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10778#L821-3 assume !(0 == ~E_1~0); 10875#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10724#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10725#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10305#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10306#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10615#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10199#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10200#L388-27 assume 1 == ~m_pc~0; 10850#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10852#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10821#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10822#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10379#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10380#L407-27 assume 1 == ~t1_pc~0; 10730#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10731#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10603#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10604#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10635#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10299#L426-27 assume !(1 == ~t2_pc~0); 10300#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10310#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10311#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10835#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10848#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10586#L445-27 assume 1 == ~t3_pc~0; 10564#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10145#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10146#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10566#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10669#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10400#L464-27 assume 1 == ~t4_pc~0; 10401#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10144#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10211#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10592#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10291#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10292#L483-27 assume 1 == ~t5_pc~0; 10797#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10201#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10202#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10811#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 10812#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10891#L502-27 assume !(1 == ~t6_pc~0); 10611#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 10612#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10861#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10747#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10748#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10089#L521-27 assume !(1 == ~t7_pc~0); 10090#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 10432#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10579#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10139#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10140#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10627#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10744#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10523#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10524#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10582#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10578#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10249#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10250#L899-3 assume !(1 == ~T7_E~0); 10277#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10278#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10225#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10226#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10269#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10736#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10665#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10666#L939-3 assume !(1 == ~E_7~0); 10284#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10285#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10106#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10532#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 10533#L1209 assume !(0 == start_simulation_~tmp~3#1); 10607#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10590#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10242#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10638#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10639#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10133#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10134#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10330#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10331#L1190-2 [2021-12-15 17:20:33,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2021-12-15 17:20:33,404 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,404 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665118461] [2021-12-15 17:20:33,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,404 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,419 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665118461] [2021-12-15 17:20:33,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665118461] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,420 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,420 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641835055] [2021-12-15 17:20:33,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,420 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,421 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 2 times [2021-12-15 17:20:33,421 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,421 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387975345] [2021-12-15 17:20:33,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,421 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,448 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387975345] [2021-12-15 17:20:33,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387975345] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,449 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005703160] [2021-12-15 17:20:33,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,449 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,449 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:33,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:33,450 INFO L87 Difference]: Start difference. First operand 835 states and 1244 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,480 INFO L93 Difference]: Finished difference Result 835 states and 1243 transitions. [2021-12-15 17:20:33,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:33,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1243 transitions. [2021-12-15 17:20:33,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1243 transitions. [2021-12-15 17:20:33,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2021-12-15 17:20:33,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2021-12-15 17:20:33,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1243 transitions. [2021-12-15 17:20:33,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,490 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2021-12-15 17:20:33,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1243 transitions. [2021-12-15 17:20:33,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2021-12-15 17:20:33,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1243 transitions. [2021-12-15 17:20:33,502 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2021-12-15 17:20:33,502 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2021-12-15 17:20:33,502 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:33,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1243 transitions. [2021-12-15 17:20:33,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2021-12-15 17:20:33,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,506 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,506 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,506 INFO L791 eck$LassoCheckResult]: Stem: 12390#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11844#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11845#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12565#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12140#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12141#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12260#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12261#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12053#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11840#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11841#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12010#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12011#L781 assume !(0 == ~M_E~0); 12465#L781-2 assume !(0 == ~T1_E~0); 12588#L786-1 assume !(0 == ~T2_E~0); 11801#L791-1 assume !(0 == ~T3_E~0); 11802#L796-1 assume !(0 == ~T4_E~0); 12327#L801-1 assume !(0 == ~T5_E~0); 12328#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12354#L811-1 assume !(0 == ~T7_E~0); 12019#L816-1 assume !(0 == ~E_M~0); 12020#L821-1 assume !(0 == ~E_1~0); 11829#L826-1 assume !(0 == ~E_2~0); 11830#L831-1 assume !(0 == ~E_3~0); 12137#L836-1 assume !(0 == ~E_4~0); 12138#L841-1 assume !(0 == ~E_5~0); 11972#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11973#L851-1 assume !(0 == ~E_7~0); 11995#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11996#L388 assume !(1 == ~m_pc~0); 11989#L388-2 is_master_triggered_~__retres1~0#1 := 0; 11990#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12438#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11848#L967 assume !(0 != activate_threads_~tmp~1#1); 11849#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11776#L407 assume 1 == ~t1_pc~0; 11777#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11781#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11755#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11756#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12536#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12099#L426 assume !(1 == ~t2_pc~0); 12100#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12551#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12580#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12578#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12579#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12179#L445 assume 1 == ~t3_pc~0; 12180#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12469#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11991#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11992#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12406#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12377#L464 assume !(1 == ~t4_pc~0); 11998#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11869#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11870#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12190#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12155#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12156#L483 assume 1 == ~t5_pc~0; 12374#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12516#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12309#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12310#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12083#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12084#L502 assume 1 == ~t6_pc~0; 12351#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11900#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11901#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12293#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12294#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12493#L521 assume !(1 == ~t7_pc~0); 12532#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11842#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11843#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11950#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12500#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12427#L869 assume !(1 == ~M_E~0); 12148#L869-2 assume !(1 == ~T1_E~0); 12149#L874-1 assume !(1 == ~T2_E~0); 12561#L879-1 assume !(1 == ~T3_E~0); 12229#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11764#L889-1 assume !(1 == ~T5_E~0); 11765#L894-1 assume !(1 == ~T6_E~0); 12026#L899-1 assume !(1 == ~T7_E~0); 12394#L904-1 assume !(1 == ~E_M~0); 12171#L909-1 assume !(1 == ~E_1~0); 12172#L914-1 assume !(1 == ~E_2~0); 12341#L919-1 assume !(1 == ~E_3~0); 12098#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11938#L929-1 assume !(1 == ~E_5~0); 11939#L934-1 assume !(1 == ~E_6~0); 12151#L939-1 assume !(1 == ~E_7~0); 12152#L944-1 assume { :end_inline_reset_delta_events } true; 12008#L1190-2 [2021-12-15 17:20:33,506 INFO L793 eck$LassoCheckResult]: Loop: 12008#L1190-2 assume !false; 12021#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12022#L756 assume !false; 12244#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12584#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11862#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12370#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12193#L653 assume !(0 != eval_~tmp~0#1); 12195#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12235#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12236#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11881#L781-5 assume !(0 == ~T1_E~0); 11882#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12202#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11825#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11826#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12085#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12086#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12268#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12455#L821-3 assume !(0 == ~E_1~0); 12552#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12401#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12402#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11982#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11983#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12292#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11876#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11877#L388-27 assume !(1 == ~m_pc~0); 12528#L388-29 is_master_triggered_~__retres1~0#1 := 0; 12529#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12498#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12499#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12056#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12057#L407-27 assume 1 == ~t1_pc~0; 12407#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12408#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12280#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12281#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12312#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11976#L426-27 assume !(1 == ~t2_pc~0); 11977#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 11987#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11988#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12512#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12525#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12263#L445-27 assume 1 == ~t3_pc~0; 12241#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11822#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11823#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12243#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12346#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12077#L464-27 assume !(1 == ~t4_pc~0); 11820#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 11821#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11888#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12269#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11968#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11969#L483-27 assume 1 == ~t5_pc~0; 12474#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11878#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11879#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12488#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 12489#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12568#L502-27 assume !(1 == ~t6_pc~0); 12288#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 12289#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12538#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12424#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12425#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11766#L521-27 assume !(1 == ~t7_pc~0); 11767#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12109#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12256#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11816#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11817#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12304#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12421#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12200#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12201#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12259#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12255#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11926#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11927#L899-3 assume !(1 == ~T7_E~0); 11954#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11955#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11902#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11903#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11946#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12413#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12342#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12343#L939-3 assume !(1 == ~E_7~0); 11961#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11962#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11783#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12209#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12210#L1209 assume !(0 == start_simulation_~tmp~3#1); 12284#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12267#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11919#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12315#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 12316#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11810#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11811#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12007#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12008#L1190-2 [2021-12-15 17:20:33,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,507 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2021-12-15 17:20:33,507 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,507 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323626504] [2021-12-15 17:20:33,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,507 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,533 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,533 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323626504] [2021-12-15 17:20:33,533 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323626504] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,534 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,534 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,534 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447318147] [2021-12-15 17:20:33,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,534 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,535 INFO L85 PathProgramCache]: Analyzing trace with hash 1828583203, now seen corresponding path program 1 times [2021-12-15 17:20:33,535 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311830817] [2021-12-15 17:20:33,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,539 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,563 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311830817] [2021-12-15 17:20:33,565 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1311830817] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,565 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,566 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,566 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552578190] [2021-12-15 17:20:33,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,566 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,567 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:33,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:33,567 INFO L87 Difference]: Start difference. First operand 835 states and 1243 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,624 INFO L93 Difference]: Finished difference Result 1509 states and 2238 transitions. [2021-12-15 17:20:33,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:33,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1509 states and 2238 transitions. [2021-12-15 17:20:33,634 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2021-12-15 17:20:33,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1509 states to 1509 states and 2238 transitions. [2021-12-15 17:20:33,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1509 [2021-12-15 17:20:33,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1509 [2021-12-15 17:20:33,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1509 states and 2238 transitions. [2021-12-15 17:20:33,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,642 INFO L681 BuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2021-12-15 17:20:33,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1509 states and 2238 transitions. [2021-12-15 17:20:33,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1509 to 1509. [2021-12-15 17:20:33,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1509 states to 1509 states and 2238 transitions. [2021-12-15 17:20:33,664 INFO L704 BuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2021-12-15 17:20:33,664 INFO L587 BuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2021-12-15 17:20:33,664 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:33,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1509 states and 2238 transitions. [2021-12-15 17:20:33,668 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2021-12-15 17:20:33,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,669 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,669 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,669 INFO L791 eck$LassoCheckResult]: Stem: 14759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14198#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14199#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14956#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 14498#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14499#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14620#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14621#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14410#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14194#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14195#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14365#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14366#L781 assume !(0 == ~M_E~0); 14841#L781-2 assume !(0 == ~T1_E~0); 14987#L786-1 assume !(0 == ~T2_E~0); 14155#L791-1 assume !(0 == ~T3_E~0); 14156#L796-1 assume !(0 == ~T4_E~0); 14691#L801-1 assume !(0 == ~T5_E~0); 14692#L806-1 assume !(0 == ~T6_E~0); 14720#L811-1 assume !(0 == ~T7_E~0); 14374#L816-1 assume !(0 == ~E_M~0); 14375#L821-1 assume !(0 == ~E_1~0); 14183#L826-1 assume !(0 == ~E_2~0); 14184#L831-1 assume !(0 == ~E_3~0); 14495#L836-1 assume !(0 == ~E_4~0); 14496#L841-1 assume !(0 == ~E_5~0); 14327#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14328#L851-1 assume !(0 == ~E_7~0); 14350#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14351#L388 assume !(1 == ~m_pc~0); 14344#L388-2 is_master_triggered_~__retres1~0#1 := 0; 14345#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14811#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14202#L967 assume !(0 != activate_threads_~tmp~1#1); 14203#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14130#L407 assume 1 == ~t1_pc~0; 14131#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14135#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14109#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14110#L975 assume !(0 != activate_threads_~tmp___0~0#1); 14920#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14456#L426 assume !(1 == ~t2_pc~0); 14457#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14937#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14975#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14973#L983 assume !(0 != activate_threads_~tmp___1~0#1); 14974#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14537#L445 assume 1 == ~t3_pc~0; 14538#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14846#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14346#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14347#L991 assume !(0 != activate_threads_~tmp___2~0#1); 14776#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14746#L464 assume !(1 == ~t4_pc~0); 14353#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14223#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14224#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14548#L999 assume !(0 != activate_threads_~tmp___3~0#1); 14513#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L483 assume 1 == ~t5_pc~0; 14743#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14898#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14671#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14672#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 14440#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14441#L502 assume 1 == ~t6_pc~0; 14717#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14254#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14255#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14653#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 14654#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14871#L521 assume !(1 == ~t7_pc~0); 14915#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 14196#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14197#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14305#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14879#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14797#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 14798#L869-2 assume !(1 == ~T1_E~0); 15541#L874-1 assume !(1 == ~T2_E~0); 15539#L879-1 assume !(1 == ~T3_E~0); 15536#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15534#L889-1 assume !(1 == ~T5_E~0); 15532#L894-1 assume !(1 == ~T6_E~0); 14381#L899-1 assume !(1 == ~T7_E~0); 15529#L904-1 assume !(1 == ~E_M~0); 15527#L909-1 assume !(1 == ~E_1~0); 15524#L914-1 assume !(1 == ~E_2~0); 15522#L919-1 assume !(1 == ~E_3~0); 15520#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15518#L929-1 assume !(1 == ~E_5~0); 15516#L934-1 assume !(1 == ~E_6~0); 15514#L939-1 assume !(1 == ~E_7~0); 15432#L944-1 assume { :end_inline_reset_delta_events } true; 15431#L1190-2 [2021-12-15 17:20:33,670 INFO L793 eck$LassoCheckResult]: Loop: 15431#L1190-2 assume !false; 15006#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15005#L756 assume !false; 15004#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15003#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14738#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14739#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14980#L653 assume !(0 != eval_~tmp~0#1); 14994#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14594#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14595#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14993#L781-5 assume !(0 == ~T1_E~0); 15556#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15555#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15554#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15553#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15552#L806-3 assume !(0 == ~T6_E~0); 15551#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15550#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15549#L821-3 assume !(0 == ~E_1~0); 15548#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15547#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15546#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15545#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15544#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15543#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15542#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15540#L388-27 assume !(1 == ~m_pc~0); 15537#L388-29 is_master_triggered_~__retres1~0#1 := 0; 15535#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15533#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15531#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15530#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15528#L407-27 assume 1 == ~t1_pc~0; 15525#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15523#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15521#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15519#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15517#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15515#L426-27 assume !(1 == ~t2_pc~0); 15512#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15511#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15510#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15509#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15508#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15507#L445-27 assume 1 == ~t3_pc~0; 15505#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15504#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15503#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15502#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15501#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15500#L464-27 assume !(1 == ~t4_pc~0); 15498#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15497#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15496#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15495#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15494#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15493#L483-27 assume 1 == ~t5_pc~0; 15491#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15490#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15489#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15488#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 15487#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15486#L502-27 assume 1 == ~t6_pc~0; 15484#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15483#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15482#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15481#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15480#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15479#L521-27 assume !(1 == ~t7_pc~0); 15477#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 15476#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15475#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15474#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15473#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15472#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14947#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15471#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15470#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15469#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15468#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15467#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14281#L899-3 assume !(1 == ~T7_E~0); 15466#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15465#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15464#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15463#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15462#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15461#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15460#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15459#L939-3 assume !(1 == ~E_7~0); 15458#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15455#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15449#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15448#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15447#L1209 assume !(0 == start_simulation_~tmp~3#1); 14655#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15444#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15438#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15437#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15436#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15435#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15434#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15433#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 15431#L1190-2 [2021-12-15 17:20:33,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,670 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2021-12-15 17:20:33,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507895465] [2021-12-15 17:20:33,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,703 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507895465] [2021-12-15 17:20:33,703 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507895465] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,703 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,703 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,703 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058314319] [2021-12-15 17:20:33,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,704 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,704 INFO L85 PathProgramCache]: Analyzing trace with hash 1319064224, now seen corresponding path program 1 times [2021-12-15 17:20:33,704 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,704 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029531713] [2021-12-15 17:20:33,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,704 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,741 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,741 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029531713] [2021-12-15 17:20:33,742 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029531713] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,742 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,744 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,744 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928578120] [2021-12-15 17:20:33,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,745 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:33,745 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:33,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:33,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:33,745 INFO L87 Difference]: Start difference. First operand 1509 states and 2238 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:33,856 INFO L93 Difference]: Finished difference Result 2723 states and 4027 transitions. [2021-12-15 17:20:33,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:33,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2723 states and 4027 transitions. [2021-12-15 17:20:33,869 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2021-12-15 17:20:33,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2723 states to 2723 states and 4027 transitions. [2021-12-15 17:20:33,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2723 [2021-12-15 17:20:33,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2723 [2021-12-15 17:20:33,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2723 states and 4027 transitions. [2021-12-15 17:20:33,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:33,883 INFO L681 BuchiCegarLoop]: Abstraction has 2723 states and 4027 transitions. [2021-12-15 17:20:33,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2723 states and 4027 transitions. [2021-12-15 17:20:33,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2723 to 2721. [2021-12-15 17:20:33,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2721 states to 2721 states and 4025 transitions. [2021-12-15 17:20:33,927 INFO L704 BuchiCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2021-12-15 17:20:33,927 INFO L587 BuchiCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2021-12-15 17:20:33,927 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:33,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2721 states and 4025 transitions. [2021-12-15 17:20:33,937 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2021-12-15 17:20:33,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,939 INFO L791 eck$LassoCheckResult]: Stem: 19001#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 19002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 18440#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18441#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19191#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18740#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18741#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18864#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18865#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18652#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18436#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18437#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18611#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18612#L781 assume !(0 == ~M_E~0); 19085#L781-2 assume !(0 == ~T1_E~0); 19219#L786-1 assume !(0 == ~T2_E~0); 18397#L791-1 assume !(0 == ~T3_E~0); 18398#L796-1 assume !(0 == ~T4_E~0); 18935#L801-1 assume !(0 == ~T5_E~0); 18936#L806-1 assume !(0 == ~T6_E~0); 18963#L811-1 assume !(0 == ~T7_E~0); 18618#L816-1 assume !(0 == ~E_M~0); 18619#L821-1 assume !(0 == ~E_1~0); 18425#L826-1 assume !(0 == ~E_2~0); 18426#L831-1 assume !(0 == ~E_3~0); 18737#L836-1 assume !(0 == ~E_4~0); 18738#L841-1 assume !(0 == ~E_5~0); 18571#L846-1 assume !(0 == ~E_6~0); 18572#L851-1 assume !(0 == ~E_7~0); 18592#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18593#L388 assume !(1 == ~m_pc~0); 18586#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18587#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19054#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18444#L967 assume !(0 != activate_threads_~tmp~1#1); 18445#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18372#L407 assume 1 == ~t1_pc~0; 18373#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18380#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18351#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18352#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19159#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18699#L426 assume !(1 == ~t2_pc~0); 18700#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19176#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19211#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19209#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19210#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18780#L445 assume 1 == ~t3_pc~0; 18781#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19089#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18588#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18589#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19019#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18988#L464 assume !(1 == ~t4_pc~0); 18595#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18465#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18466#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18793#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18755#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18756#L483 assume 1 == ~t5_pc~0; 18984#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19138#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18917#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18918#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18683#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18684#L502 assume 1 == ~t6_pc~0; 18961#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18496#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18497#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18899#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 18900#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19114#L521 assume !(1 == ~t7_pc~0); 19155#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18438#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18439#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18547#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19121#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19044#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 18748#L869-2 assume !(1 == ~T1_E~0); 18749#L874-1 assume !(1 == ~T2_E~0); 19187#L879-1 assume !(1 == ~T3_E~0); 18832#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18360#L889-1 assume !(1 == ~T5_E~0); 18361#L894-1 assume !(1 == ~T6_E~0); 18628#L899-1 assume !(1 == ~T7_E~0); 19009#L904-1 assume !(1 == ~E_M~0); 18772#L909-1 assume !(1 == ~E_1~0); 18773#L914-1 assume !(1 == ~E_2~0); 18949#L919-1 assume !(1 == ~E_3~0); 18970#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19275#L929-1 assume !(1 == ~E_5~0); 19273#L934-1 assume !(1 == ~E_6~0); 19261#L939-1 assume !(1 == ~E_7~0); 19253#L944-1 assume { :end_inline_reset_delta_events } true; 19247#L1190-2 [2021-12-15 17:20:33,939 INFO L793 eck$LassoCheckResult]: Loop: 19247#L1190-2 assume !false; 19242#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19241#L756 assume !false; 19240#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19239#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19231#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19230#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19228#L653 assume !(0 != eval_~tmp~0#1); 19227#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19226#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19224#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19225#L781-5 assume !(0 == ~T1_E~0); 20461#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20460#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20459#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20458#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20457#L806-3 assume !(0 == ~T6_E~0); 20456#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20455#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20454#L821-3 assume !(0 == ~E_1~0); 20191#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20076#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20010#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20008#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20005#L846-3 assume !(0 == ~E_6~0); 20003#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19961#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19959#L388-27 assume !(1 == ~m_pc~0); 19956#L388-29 is_master_triggered_~__retres1~0#1 := 0; 19954#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19952#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19950#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19948#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19927#L407-27 assume 1 == ~t1_pc~0; 19924#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19894#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19876#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19857#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19855#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19853#L426-27 assume !(1 == ~t2_pc~0); 19838#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 19818#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19793#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19765#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19763#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19761#L445-27 assume 1 == ~t3_pc~0; 19741#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19738#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19736#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19733#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19705#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19703#L464-27 assume !(1 == ~t4_pc~0); 19700#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19670#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19645#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19643#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19623#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19621#L483-27 assume 1 == ~t5_pc~0; 19604#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19602#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19600#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19580#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 19555#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19553#L502-27 assume 1 == ~t6_pc~0; 19550#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19549#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19548#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19546#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19545#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19544#L521-27 assume !(1 == ~t7_pc~0); 19515#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 19513#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19512#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19511#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19509#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19507#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19034#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18801#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18802#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18863#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18897#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19430#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18523#L899-3 assume !(1 == ~T7_E~0); 19429#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19390#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19388#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19386#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19384#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19382#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19381#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19378#L939-3 assume !(1 == ~E_7~0); 19377#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19356#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19349#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19348#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 19347#L1209 assume !(0 == start_simulation_~tmp~3#1); 18901#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19322#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 19315#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19294#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 19292#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19274#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19262#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 19254#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 19247#L1190-2 [2021-12-15 17:20:33,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,940 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2021-12-15 17:20:33,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573220540] [2021-12-15 17:20:33,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,940 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573220540] [2021-12-15 17:20:33,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573220540] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,972 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,972 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:33,973 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612778453] [2021-12-15 17:20:33,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:33,974 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:33,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,974 INFO L85 PathProgramCache]: Analyzing trace with hash 176561758, now seen corresponding path program 1 times [2021-12-15 17:20:33,974 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457134800] [2021-12-15 17:20:33,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,975 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457134800] [2021-12-15 17:20:33,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457134800] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,999 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,000 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768263148] [2021-12-15 17:20:34,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,000 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,000 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:34,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:34,002 INFO L87 Difference]: Start difference. First operand 2721 states and 4025 transitions. cyclomatic complexity: 1308 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,061 INFO L93 Difference]: Finished difference Result 5039 states and 7400 transitions. [2021-12-15 17:20:34,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:34,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5039 states and 7400 transitions. [2021-12-15 17:20:34,118 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4905 [2021-12-15 17:20:34,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5039 states to 5039 states and 7400 transitions. [2021-12-15 17:20:34,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5039 [2021-12-15 17:20:34,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5039 [2021-12-15 17:20:34,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5039 states and 7400 transitions. [2021-12-15 17:20:34,149 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,149 INFO L681 BuchiCegarLoop]: Abstraction has 5039 states and 7400 transitions. [2021-12-15 17:20:34,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5039 states and 7400 transitions. [2021-12-15 17:20:34,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5039 to 5031. [2021-12-15 17:20:34,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5031 states, 5031 states have (on average 1.4692903995229576) internal successors, (7392), 5030 states have internal predecessors, (7392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5031 states to 5031 states and 7392 transitions. [2021-12-15 17:20:34,239 INFO L704 BuchiCegarLoop]: Abstraction has 5031 states and 7392 transitions. [2021-12-15 17:20:34,239 INFO L587 BuchiCegarLoop]: Abstraction has 5031 states and 7392 transitions. [2021-12-15 17:20:34,239 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:34,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5031 states and 7392 transitions. [2021-12-15 17:20:34,256 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4897 [2021-12-15 17:20:34,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,259 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,259 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,259 INFO L791 eck$LassoCheckResult]: Stem: 26804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 26206#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26207#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27054#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 26518#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26519#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26651#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26652#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26426#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26202#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26203#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26382#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26383#L781 assume !(0 == ~M_E~0); 26902#L781-2 assume !(0 == ~T1_E~0); 27118#L786-1 assume !(0 == ~T2_E~0); 26163#L791-1 assume !(0 == ~T3_E~0); 26164#L796-1 assume !(0 == ~T4_E~0); 26726#L801-1 assume !(0 == ~T5_E~0); 26727#L806-1 assume !(0 == ~T6_E~0); 26759#L811-1 assume !(0 == ~T7_E~0); 26389#L816-1 assume !(0 == ~E_M~0); 26390#L821-1 assume !(0 == ~E_1~0); 26191#L826-1 assume !(0 == ~E_2~0); 26192#L831-1 assume !(0 == ~E_3~0); 26515#L836-1 assume !(0 == ~E_4~0); 26516#L841-1 assume !(0 == ~E_5~0); 26343#L846-1 assume !(0 == ~E_6~0); 26344#L851-1 assume !(0 == ~E_7~0); 26364#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26365#L388 assume !(1 == ~m_pc~0); 26358#L388-2 is_master_triggered_~__retres1~0#1 := 0; 26359#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26867#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26210#L967 assume !(0 != activate_threads_~tmp~1#1); 26211#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26139#L407 assume !(1 == ~t1_pc~0); 26140#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26146#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26118#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26119#L975 assume !(0 != activate_threads_~tmp___0~0#1); 27004#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26477#L426 assume !(1 == ~t2_pc~0); 26478#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27028#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27087#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27085#L983 assume !(0 != activate_threads_~tmp___1~0#1); 27086#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26561#L445 assume 1 == ~t3_pc~0; 26562#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26910#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26360#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26361#L991 assume !(0 != activate_threads_~tmp___2~0#1); 26825#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26789#L464 assume !(1 == ~t4_pc~0); 26367#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26231#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26232#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26574#L999 assume !(0 != activate_threads_~tmp___3~0#1); 26533#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26534#L483 assume 1 == ~t5_pc~0; 26786#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26978#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26706#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26707#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 26461#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26462#L502 assume 1 == ~t6_pc~0; 26757#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26262#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26263#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26686#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 26687#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26945#L521 assume !(1 == ~t7_pc~0); 27000#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26204#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26205#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26315#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26955#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26853#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 26854#L869-2 assume !(1 == ~T1_E~0); 27812#L874-1 assume !(1 == ~T2_E~0); 27811#L879-1 assume !(1 == ~T3_E~0); 27810#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26127#L889-1 assume !(1 == ~T5_E~0); 26128#L894-1 assume !(1 == ~T6_E~0); 27800#L899-1 assume !(1 == ~T7_E~0); 27798#L904-1 assume !(1 == ~E_M~0); 27796#L909-1 assume !(1 == ~E_1~0); 27787#L914-1 assume !(1 == ~E_2~0); 27785#L919-1 assume !(1 == ~E_3~0); 27783#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27781#L929-1 assume !(1 == ~E_5~0); 27779#L934-1 assume !(1 == ~E_6~0); 27768#L939-1 assume !(1 == ~E_7~0); 27761#L944-1 assume { :end_inline_reset_delta_events } true; 27756#L1190-2 [2021-12-15 17:20:34,260 INFO L793 eck$LassoCheckResult]: Loop: 27756#L1190-2 assume !false; 27751#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27750#L756 assume !false; 27749#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27748#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27740#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27739#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27737#L653 assume !(0 != eval_~tmp~0#1); 27736#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27735#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27732#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27733#L781-5 assume !(0 == ~T1_E~0); 28394#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28392#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28371#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28369#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28367#L806-3 assume !(0 == ~T6_E~0); 28350#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28348#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28346#L821-3 assume !(0 == ~E_1~0); 28343#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27677#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27668#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27667#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27666#L846-3 assume !(0 == ~E_6~0); 26685#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26238#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26239#L388-27 assume 1 == ~m_pc~0; 26994#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26996#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26953#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26954#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26429#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26430#L407-27 assume !(1 == ~t1_pc~0); 26842#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 26926#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26670#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26671#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26708#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26345#L426-27 assume !(1 == ~t2_pc~0); 26346#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 26353#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26354#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26973#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26990#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26654#L445-27 assume 1 == ~t3_pc~0; 26624#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26184#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26185#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26629#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26749#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26454#L464-27 assume !(1 == ~t4_pc~0); 26182#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 26183#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26250#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26658#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26337#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26338#L483-27 assume 1 == ~t5_pc~0; 27104#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27989#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27986#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27984#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 27954#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27952#L502-27 assume 1 == ~t6_pc~0; 27949#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27947#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27946#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27945#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27942#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27940#L521-27 assume !(1 == ~t7_pc~0); 27904#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 27903#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27902#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27901#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27900#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27898#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27041#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27896#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27895#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27670#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27671#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27862#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27616#L899-3 assume !(1 == ~T7_E~0); 27841#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27839#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27837#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27836#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27827#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27823#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27821#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27818#L939-3 assume !(1 == ~E_7~0); 27813#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27807#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27801#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27799#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 27797#L1209 assume !(0 == start_simulation_~tmp~3#1); 27617#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27793#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27786#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27784#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 27782#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27780#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27769#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 27762#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 27756#L1190-2 [2021-12-15 17:20:34,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,260 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2021-12-15 17:20:34,260 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550952042] [2021-12-15 17:20:34,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,261 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,303 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550952042] [2021-12-15 17:20:34,304 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550952042] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,304 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95172829] [2021-12-15 17:20:34,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,305 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:34,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,305 INFO L85 PathProgramCache]: Analyzing trace with hash 63554334, now seen corresponding path program 1 times [2021-12-15 17:20:34,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817946546] [2021-12-15 17:20:34,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817946546] [2021-12-15 17:20:34,347 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817946546] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,347 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,347 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,348 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744247794] [2021-12-15 17:20:34,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,348 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,348 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:34,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:34,349 INFO L87 Difference]: Start difference. First operand 5031 states and 7392 transitions. cyclomatic complexity: 2369 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,562 INFO L93 Difference]: Finished difference Result 11737 states and 17089 transitions. [2021-12-15 17:20:34,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:34,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11737 states and 17089 transitions. [2021-12-15 17:20:34,613 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11572 [2021-12-15 17:20:34,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11737 states to 11737 states and 17089 transitions. [2021-12-15 17:20:34,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11737 [2021-12-15 17:20:34,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11737 [2021-12-15 17:20:34,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11737 states and 17089 transitions. [2021-12-15 17:20:34,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,678 INFO L681 BuchiCegarLoop]: Abstraction has 11737 states and 17089 transitions. [2021-12-15 17:20:34,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11737 states and 17089 transitions. [2021-12-15 17:20:34,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11737 to 9389. [2021-12-15 17:20:34,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9389 states, 9389 states have (on average 1.4617105123016296) internal successors, (13724), 9388 states have internal predecessors, (13724), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9389 states to 9389 states and 13724 transitions. [2021-12-15 17:20:34,884 INFO L704 BuchiCegarLoop]: Abstraction has 9389 states and 13724 transitions. [2021-12-15 17:20:34,884 INFO L587 BuchiCegarLoop]: Abstraction has 9389 states and 13724 transitions. [2021-12-15 17:20:34,884 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:34,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9389 states and 13724 transitions. [2021-12-15 17:20:34,956 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9252 [2021-12-15 17:20:34,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,958 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,958 INFO L791 eck$LassoCheckResult]: Stem: 43555#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 43556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 42982#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42983#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43786#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 43286#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43287#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43409#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43410#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43198#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42978#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42979#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43156#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43157#L781 assume !(0 == ~M_E~0); 43650#L781-2 assume !(0 == ~T1_E~0); 43850#L786-1 assume !(0 == ~T2_E~0); 42943#L791-1 assume !(0 == ~T3_E~0); 42944#L796-1 assume !(0 == ~T4_E~0); 43484#L801-1 assume !(0 == ~T5_E~0); 43485#L806-1 assume !(0 == ~T6_E~0); 43514#L811-1 assume !(0 == ~T7_E~0); 43162#L816-1 assume !(0 == ~E_M~0); 43163#L821-1 assume !(0 == ~E_1~0); 42968#L826-1 assume !(0 == ~E_2~0); 42969#L831-1 assume !(0 == ~E_3~0); 43283#L836-1 assume !(0 == ~E_4~0); 43284#L841-1 assume !(0 == ~E_5~0); 43116#L846-1 assume !(0 == ~E_6~0); 43117#L851-1 assume !(0 == ~E_7~0); 43137#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43138#L388 assume !(1 == ~m_pc~0); 43131#L388-2 is_master_triggered_~__retres1~0#1 := 0; 43132#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43618#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42986#L967 assume !(0 != activate_threads_~tmp~1#1); 42987#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42917#L407 assume !(1 == ~t1_pc~0); 42918#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42924#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42896#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42897#L975 assume !(0 != activate_threads_~tmp___0~0#1); 43744#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43246#L426 assume !(1 == ~t2_pc~0); 43247#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43767#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43821#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43816#L983 assume !(0 != activate_threads_~tmp___1~0#1); 43817#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43326#L445 assume !(1 == ~t3_pc~0); 43327#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43653#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43133#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43134#L991 assume !(0 != activate_threads_~tmp___2~0#1); 43577#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43542#L464 assume !(1 == ~t4_pc~0); 43140#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43007#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43008#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43338#L999 assume !(0 != activate_threads_~tmp___3~0#1); 43300#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43301#L483 assume 1 == ~t5_pc~0; 43539#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43720#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43464#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43465#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 43232#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43233#L502 assume 1 == ~t6_pc~0; 43512#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43038#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43039#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43444#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 43445#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43686#L521 assume !(1 == ~t7_pc~0); 43740#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 42980#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42981#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43090#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43699#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43605#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 43293#L869-2 assume !(1 == ~T1_E~0); 43294#L874-1 assume !(1 == ~T2_E~0); 43779#L879-1 assume !(1 == ~T3_E~0); 43780#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42905#L889-1 assume !(1 == ~T5_E~0); 42906#L894-1 assume !(1 == ~T6_E~0); 47123#L899-1 assume !(1 == ~T7_E~0); 47122#L904-1 assume !(1 == ~E_M~0); 47120#L909-1 assume !(1 == ~E_1~0); 47074#L914-1 assume !(1 == ~E_2~0); 43523#L919-1 assume !(1 == ~E_3~0); 43524#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 47070#L929-1 assume !(1 == ~E_5~0); 47068#L934-1 assume !(1 == ~E_6~0); 47066#L939-1 assume !(1 == ~E_7~0); 47064#L944-1 assume { :end_inline_reset_delta_events } true; 47053#L1190-2 [2021-12-15 17:20:34,959 INFO L793 eck$LassoCheckResult]: Loop: 47053#L1190-2 assume !false; 47045#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47039#L756 assume !false; 47036#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 47001#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 46990#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 46986#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 46980#L653 assume !(0 != eval_~tmp~0#1); 46981#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48169#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48168#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48166#L781-5 assume !(0 == ~T1_E~0); 48164#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48162#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48160#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48158#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48155#L806-3 assume !(0 == ~T6_E~0); 47987#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47984#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47982#L821-3 assume !(0 == ~E_1~0); 47980#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47978#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47976#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47974#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47971#L846-3 assume !(0 == ~E_6~0); 47969#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47967#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47965#L388-27 assume !(1 == ~m_pc~0); 47962#L388-29 is_master_triggered_~__retres1~0#1 := 0; 47960#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47957#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47955#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47953#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47898#L407-27 assume !(1 == ~t1_pc~0); 47351#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 47348#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47346#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47344#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47342#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47340#L426-27 assume !(1 == ~t2_pc~0); 47337#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 47334#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47332#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47330#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47328#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47326#L445-27 assume !(1 == ~t3_pc~0); 46354#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 47324#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47321#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47319#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47317#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47315#L464-27 assume !(1 == ~t4_pc~0); 47312#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 47310#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47307#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47305#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47303#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47301#L483-27 assume 1 == ~t5_pc~0; 47298#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47296#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47294#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47292#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 47290#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47288#L502-27 assume 1 == ~t6_pc~0; 47285#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47284#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47283#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47282#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47280#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47279#L521-27 assume !(1 == ~t7_pc~0); 47277#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 47274#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47272#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47270#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47268#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47266#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47262#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47260#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47258#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47256#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47254#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47252#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47249#L899-3 assume !(1 == ~T7_E~0); 47246#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47244#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47242#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47240#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47238#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47236#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47235#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47231#L939-3 assume !(1 == ~E_7~0); 47229#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 47221#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 47214#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 47212#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 47209#L1209 assume !(0 == start_simulation_~tmp~3#1); 43447#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 47196#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 47189#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 47187#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 47185#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47183#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47180#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 47065#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 47053#L1190-2 [2021-12-15 17:20:34,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2021-12-15 17:20:34,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153768691] [2021-12-15 17:20:34,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,960 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,987 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153768691] [2021-12-15 17:20:34,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1153768691] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,988 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,988 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975431640] [2021-12-15 17:20:34,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,990 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:34,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1484877024, now seen corresponding path program 1 times [2021-12-15 17:20:34,990 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689913303] [2021-12-15 17:20:34,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,991 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,017 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689913303] [2021-12-15 17:20:35,017 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689913303] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,017 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,018 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660611414] [2021-12-15 17:20:35,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,018 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,018 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:35,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:35,019 INFO L87 Difference]: Start difference. First operand 9389 states and 13724 transitions. cyclomatic complexity: 4343 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,233 INFO L93 Difference]: Finished difference Result 22287 states and 32284 transitions. [2021-12-15 17:20:35,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:35,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22287 states and 32284 transitions. [2021-12-15 17:20:35,420 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22087 [2021-12-15 17:20:35,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22287 states to 22287 states and 32284 transitions. [2021-12-15 17:20:35,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22287 [2021-12-15 17:20:35,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22287 [2021-12-15 17:20:35,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22287 states and 32284 transitions. [2021-12-15 17:20:35,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,542 INFO L681 BuchiCegarLoop]: Abstraction has 22287 states and 32284 transitions. [2021-12-15 17:20:35,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22287 states and 32284 transitions. [2021-12-15 17:20:35,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22287 to 18028. [2021-12-15 17:20:35,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18028 states, 18028 states have (on average 1.4531284668293765) internal successors, (26197), 18027 states have internal predecessors, (26197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18028 states to 18028 states and 26197 transitions. [2021-12-15 17:20:35,884 INFO L704 BuchiCegarLoop]: Abstraction has 18028 states and 26197 transitions. [2021-12-15 17:20:35,884 INFO L587 BuchiCegarLoop]: Abstraction has 18028 states and 26197 transitions. [2021-12-15 17:20:35,884 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:35,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18028 states and 26197 transitions. [2021-12-15 17:20:35,929 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17884 [2021-12-15 17:20:35,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,931 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,931 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,931 INFO L791 eck$LassoCheckResult]: Stem: 75246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 75247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 74668#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74669#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75477#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 74970#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74971#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75097#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75098#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74882#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74664#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74665#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74839#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74840#L781 assume !(0 == ~M_E~0); 75331#L781-2 assume !(0 == ~T1_E~0); 75538#L786-1 assume !(0 == ~T2_E~0); 74626#L791-1 assume !(0 == ~T3_E~0); 74627#L796-1 assume !(0 == ~T4_E~0); 75174#L801-1 assume !(0 == ~T5_E~0); 75175#L806-1 assume !(0 == ~T6_E~0); 75203#L811-1 assume !(0 == ~T7_E~0); 74846#L816-1 assume !(0 == ~E_M~0); 74847#L821-1 assume !(0 == ~E_1~0); 74654#L826-1 assume !(0 == ~E_2~0); 74655#L831-1 assume !(0 == ~E_3~0); 74967#L836-1 assume !(0 == ~E_4~0); 74968#L841-1 assume !(0 == ~E_5~0); 74801#L846-1 assume !(0 == ~E_6~0); 74802#L851-1 assume !(0 == ~E_7~0); 74821#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74822#L388 assume !(1 == ~m_pc~0); 74815#L388-2 is_master_triggered_~__retres1~0#1 := 0; 74816#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75302#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 74672#L967 assume !(0 != activate_threads_~tmp~1#1); 74673#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74603#L407 assume !(1 == ~t1_pc~0); 74604#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74610#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74582#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74583#L975 assume !(0 != activate_threads_~tmp___0~0#1); 75432#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74927#L426 assume !(1 == ~t2_pc~0); 74928#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75457#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75513#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75509#L983 assume !(0 != activate_threads_~tmp___1~0#1); 75510#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75012#L445 assume !(1 == ~t3_pc~0); 75013#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75338#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74817#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74818#L991 assume !(0 != activate_threads_~tmp___2~0#1); 75263#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75233#L464 assume !(1 == ~t4_pc~0); 74824#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74693#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74694#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75025#L999 assume !(0 != activate_threads_~tmp___3~0#1); 74986#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74987#L483 assume !(1 == ~t5_pc~0); 75231#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75408#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75155#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75156#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 74914#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74915#L502 assume 1 == ~t6_pc~0; 75201#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74724#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74725#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75133#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 75134#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75376#L521 assume !(1 == ~t7_pc~0); 75428#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 74666#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74667#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74776#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75386#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75288#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 75289#L869-2 assume !(1 == ~T1_E~0); 84908#L874-1 assume !(1 == ~T2_E~0); 84906#L879-1 assume !(1 == ~T3_E~0); 84904#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84902#L889-1 assume !(1 == ~T5_E~0); 84900#L894-1 assume !(1 == ~T6_E~0); 84896#L899-1 assume !(1 == ~T7_E~0); 84897#L904-1 assume !(1 == ~E_M~0); 84890#L909-1 assume !(1 == ~E_1~0); 84891#L914-1 assume !(1 == ~E_2~0); 84884#L919-1 assume !(1 == ~E_3~0); 84885#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 84879#L929-1 assume !(1 == ~E_5~0); 84880#L934-1 assume !(1 == ~E_6~0); 75480#L939-1 assume !(1 == ~E_7~0); 88947#L944-1 assume { :end_inline_reset_delta_events } true; 88934#L1190-2 [2021-12-15 17:20:35,931 INFO L793 eck$LassoCheckResult]: Loop: 88934#L1190-2 assume !false; 88925#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88922#L756 assume !false; 88920#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 88858#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 88846#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 88841#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 88833#L653 assume !(0 != eval_~tmp~0#1); 88834#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 91878#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 91876#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 91874#L781-5 assume !(0 == ~T1_E~0); 91872#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 91869#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 91867#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91865#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74912#L806-3 assume !(0 == ~T6_E~0); 74913#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75107#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 75319#L821-3 assume !(0 == ~E_1~0); 75458#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75258#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75259#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74809#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74810#L846-3 assume !(0 == ~E_6~0); 75132#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74700#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74701#L388-27 assume !(1 == ~m_pc~0); 75424#L388-29 is_master_triggered_~__retres1~0#1 := 0; 75425#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75384#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75385#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 74885#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74886#L407-27 assume !(1 == ~t1_pc~0); 75279#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 75357#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75119#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75120#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75158#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74803#L426-27 assume 1 == ~t2_pc~0; 74805#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 74813#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74814#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75403#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75419#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75420#L445-27 assume !(1 == ~t3_pc~0); 89345#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 89344#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89343#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89342#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89341#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89340#L464-27 assume 1 == ~t4_pc~0; 89339#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89337#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89336#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89335#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89334#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89333#L483-27 assume !(1 == ~t5_pc~0); 89331#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 89329#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89326#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89324#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 89322#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89320#L502-27 assume 1 == ~t6_pc~0; 89317#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 89316#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89315#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89314#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 89312#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89310#L521-27 assume !(1 == ~t7_pc~0); 89307#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 89305#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89303#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89302#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 89300#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89298#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 84745#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89293#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 89291#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89289#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89288#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89287#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84734#L899-3 assume !(1 == ~T7_E~0); 89284#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 89282#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89280#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 89278#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 89276#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89274#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89271#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89267#L939-3 assume !(1 == ~E_7~0); 89265#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 89258#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 89251#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 89249#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 89047#L1209 assume !(0 == start_simulation_~tmp~3#1); 89045#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 89036#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 89028#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 89027#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 89026#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88960#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88950#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 88948#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 88934#L1190-2 [2021-12-15 17:20:35,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,932 INFO L85 PathProgramCache]: Analyzing trace with hash -2127260292, now seen corresponding path program 1 times [2021-12-15 17:20:35,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133917197] [2021-12-15 17:20:35,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133917197] [2021-12-15 17:20:35,953 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133917197] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,953 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,953 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,953 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122238482] [2021-12-15 17:20:35,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,954 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,954 INFO L85 PathProgramCache]: Analyzing trace with hash -512429473, now seen corresponding path program 1 times [2021-12-15 17:20:35,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917694108] [2021-12-15 17:20:35,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,955 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917694108] [2021-12-15 17:20:36,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917694108] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,065 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,065 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,066 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995046414] [2021-12-15 17:20:36,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,066 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,066 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:36,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:36,067 INFO L87 Difference]: Start difference. First operand 18028 states and 26197 transitions. cyclomatic complexity: 8177 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,412 INFO L93 Difference]: Finished difference Result 41725 states and 60212 transitions. [2021-12-15 17:20:36,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:36,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41725 states and 60212 transitions. [2021-12-15 17:20:36,602 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 41454 [2021-12-15 17:20:36,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41725 states to 41725 states and 60212 transitions. [2021-12-15 17:20:36,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41725 [2021-12-15 17:20:36,962 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41725 [2021-12-15 17:20:36,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41725 states and 60212 transitions. [2021-12-15 17:20:36,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,990 INFO L681 BuchiCegarLoop]: Abstraction has 41725 states and 60212 transitions. [2021-12-15 17:20:37,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41725 states and 60212 transitions. [2021-12-15 17:20:37,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41725 to 33815. [2021-12-15 17:20:37,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33815 states, 33815 states have (on average 1.4478190152299275) internal successors, (48958), 33814 states have internal predecessors, (48958), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33815 states to 33815 states and 48958 transitions. [2021-12-15 17:20:37,519 INFO L704 BuchiCegarLoop]: Abstraction has 33815 states and 48958 transitions. [2021-12-15 17:20:37,519 INFO L587 BuchiCegarLoop]: Abstraction has 33815 states and 48958 transitions. [2021-12-15 17:20:37,519 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:37,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33815 states and 48958 transitions. [2021-12-15 17:20:37,612 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 33656 [2021-12-15 17:20:37,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:37,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:37,615 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,615 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,615 INFO L791 eck$LassoCheckResult]: Stem: 135010#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 135011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 134431#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134432#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135254#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 134733#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 134734#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 134860#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 134861#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134643#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 134427#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 134428#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 134601#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 134602#L781 assume !(0 == ~M_E~0); 135105#L781-2 assume !(0 == ~T1_E~0); 135324#L786-1 assume !(0 == ~T2_E~0); 134389#L791-1 assume !(0 == ~T3_E~0); 134390#L796-1 assume !(0 == ~T4_E~0); 134936#L801-1 assume !(0 == ~T5_E~0); 134937#L806-1 assume !(0 == ~T6_E~0); 134964#L811-1 assume !(0 == ~T7_E~0); 134607#L816-1 assume !(0 == ~E_M~0); 134608#L821-1 assume !(0 == ~E_1~0); 134417#L826-1 assume !(0 == ~E_2~0); 134418#L831-1 assume !(0 == ~E_3~0); 134730#L836-1 assume !(0 == ~E_4~0); 134731#L841-1 assume !(0 == ~E_5~0); 134560#L846-1 assume !(0 == ~E_6~0); 134561#L851-1 assume !(0 == ~E_7~0); 134582#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134583#L388 assume !(1 == ~m_pc~0); 134576#L388-2 is_master_triggered_~__retres1~0#1 := 0; 134577#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135073#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134435#L967 assume !(0 != activate_threads_~tmp~1#1); 134436#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134366#L407 assume !(1 == ~t1_pc~0); 134367#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 134373#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134345#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134346#L975 assume !(0 != activate_threads_~tmp___0~0#1); 135206#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134689#L426 assume !(1 == ~t2_pc~0); 134690#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 135232#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135291#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 135287#L983 assume !(0 != activate_threads_~tmp___1~0#1); 135288#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134776#L445 assume !(1 == ~t3_pc~0); 134777#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 135112#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134578#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 134579#L991 assume !(0 != activate_threads_~tmp___2~0#1); 135033#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134992#L464 assume !(1 == ~t4_pc~0); 134585#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 134456#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134457#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134787#L999 assume !(0 != activate_threads_~tmp___3~0#1); 134748#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134749#L483 assume !(1 == ~t5_pc~0); 134989#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 135181#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134914#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134915#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 134673#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134674#L502 assume !(1 == ~t6_pc~0); 134534#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 134487#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134488#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134897#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 134898#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135151#L521 assume !(1 == ~t7_pc~0); 135201#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 134429#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134430#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 134537#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 135159#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135058#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 135059#L869-2 assume !(1 == ~T1_E~0); 135281#L874-1 assume !(1 == ~T2_E~0); 135282#L879-1 assume !(1 == ~T3_E~0); 134828#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 134829#L889-1 assume !(1 == ~T5_E~0); 134617#L894-1 assume !(1 == ~T6_E~0); 134618#L899-1 assume !(1 == ~T7_E~0); 135332#L904-1 assume !(1 == ~E_M~0); 134768#L909-1 assume !(1 == ~E_1~0); 134769#L914-1 assume !(1 == ~E_2~0); 134972#L919-1 assume !(1 == ~E_3~0); 134973#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 134525#L929-1 assume !(1 == ~E_5~0); 134526#L934-1 assume !(1 == ~E_6~0); 143253#L939-1 assume !(1 == ~E_7~0); 143251#L944-1 assume { :end_inline_reset_delta_events } true; 143248#L1190-2 [2021-12-15 17:20:37,616 INFO L793 eck$LassoCheckResult]: Loop: 143248#L1190-2 assume !false; 143209#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143207#L756 assume !false; 143205#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 143203#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 143191#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 143187#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 143182#L653 assume !(0 != eval_~tmp~0#1); 143183#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 150314#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 150315#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 150302#L781-5 assume !(0 == ~T1_E~0); 150303#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 150288#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 150289#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 150274#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 150275#L806-3 assume !(0 == ~T6_E~0); 150262#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 150263#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 150249#L821-3 assume !(0 == ~E_1~0); 150250#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 150236#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 150237#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 150224#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 150225#L846-3 assume !(0 == ~E_6~0); 150204#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 150205#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150186#L388-27 assume !(1 == ~m_pc~0); 150187#L388-29 is_master_triggered_~__retres1~0#1 := 0; 150170#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150171#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 150115#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 150116#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150101#L407-27 assume !(1 == ~t1_pc~0); 150102#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 150087#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150088#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 150071#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 150072#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150055#L426-27 assume !(1 == ~t2_pc~0); 150056#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 150037#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150038#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 150024#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 150025#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149977#L445-27 assume !(1 == ~t3_pc~0); 148277#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 149961#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149962#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 149945#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 149946#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 149926#L464-27 assume 1 == ~t4_pc~0; 149927#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 149904#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149905#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 149887#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 149888#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143480#L483-27 assume !(1 == ~t5_pc~0); 143472#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 143465#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143459#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 143453#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 143447#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143425#L502-27 assume !(1 == ~t6_pc~0); 137540#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 143417#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143413#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 143409#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 143405#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 143399#L521-27 assume 1 == ~t7_pc~0; 143394#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 143388#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 143383#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 143378#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 143368#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143366#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 143362#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143361#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 143359#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143357#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143355#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 143353#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 143349#L899-3 assume !(1 == ~T7_E~0); 143346#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 143344#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 143342#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 143340#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 143338#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 143336#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143334#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 143330#L939-3 assume !(1 == ~E_7~0); 143328#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 143307#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 143299#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 143296#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 143292#L1209 assume !(0 == start_simulation_~tmp~3#1); 143290#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 143285#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 143278#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 143276#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 143273#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143266#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143259#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 143252#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 143248#L1190-2 [2021-12-15 17:20:37,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1196032317, now seen corresponding path program 1 times [2021-12-15 17:20:37,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339678191] [2021-12-15 17:20:37,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,617 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339678191] [2021-12-15 17:20:37,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339678191] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,649 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:37,649 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072063560] [2021-12-15 17:20:37,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,650 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1671410464, now seen corresponding path program 1 times [2021-12-15 17:20:37,651 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111005488] [2021-12-15 17:20:37,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,652 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,675 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111005488] [2021-12-15 17:20:37,675 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111005488] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,676 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,676 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,676 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672407432] [2021-12-15 17:20:37,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,676 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:37,676 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:37,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:37,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:37,677 INFO L87 Difference]: Start difference. First operand 33815 states and 48958 transitions. cyclomatic complexity: 15151 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,147 INFO L93 Difference]: Finished difference Result 76142 states and 111095 transitions. [2021-12-15 17:20:38,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:38,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76142 states and 111095 transitions. [2021-12-15 17:20:38,633 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 75824 [2021-12-15 17:20:38,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76142 states to 76142 states and 111095 transitions. [2021-12-15 17:20:38,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76142 [2021-12-15 17:20:38,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76142 [2021-12-15 17:20:38,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76142 states and 111095 transitions. [2021-12-15 17:20:39,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:39,082 INFO L681 BuchiCegarLoop]: Abstraction has 76142 states and 111095 transitions. [2021-12-15 17:20:39,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76142 states and 111095 transitions. [2021-12-15 17:20:39,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76142 to 35162. [2021-12-15 17:20:39,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35162 states, 35162 states have (on average 1.4306637847676469) internal successors, (50305), 35161 states have internal predecessors, (50305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35162 states to 35162 states and 50305 transitions. [2021-12-15 17:20:39,680 INFO L704 BuchiCegarLoop]: Abstraction has 35162 states and 50305 transitions. [2021-12-15 17:20:39,680 INFO L587 BuchiCegarLoop]: Abstraction has 35162 states and 50305 transitions. [2021-12-15 17:20:39,680 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:39,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35162 states and 50305 transitions. [2021-12-15 17:20:39,772 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 35000 [2021-12-15 17:20:39,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:39,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:39,774 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,774 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,774 INFO L791 eck$LassoCheckResult]: Stem: 244992#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 244993#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 244401#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 244402#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 245261#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 244713#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 244714#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 244844#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 244845#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 244623#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 244397#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 244398#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 244574#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244575#L781 assume !(0 == ~M_E~0); 245089#L781-2 assume !(0 == ~T1_E~0); 245332#L786-1 assume !(0 == ~T2_E~0); 244359#L791-1 assume !(0 == ~T3_E~0); 244360#L796-1 assume !(0 == ~T4_E~0); 244920#L801-1 assume !(0 == ~T5_E~0); 244921#L806-1 assume !(0 == ~T6_E~0); 244951#L811-1 assume !(0 == ~T7_E~0); 244584#L816-1 assume !(0 == ~E_M~0); 244585#L821-1 assume !(0 == ~E_1~0); 244387#L826-1 assume !(0 == ~E_2~0); 244388#L831-1 assume !(0 == ~E_3~0); 244710#L836-1 assume !(0 == ~E_4~0); 244711#L841-1 assume !(0 == ~E_5~0); 244534#L846-1 assume !(0 == ~E_6~0); 244535#L851-1 assume !(0 == ~E_7~0); 244556#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244557#L388 assume !(1 == ~m_pc~0); 244550#L388-2 is_master_triggered_~__retres1~0#1 := 0; 244551#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 245057#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 244405#L967 assume !(0 != activate_threads_~tmp~1#1); 244406#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244336#L407 assume !(1 == ~t1_pc~0); 244337#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 244340#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244315#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 244316#L975 assume !(0 != activate_threads_~tmp___0~0#1); 245201#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244668#L426 assume !(1 == ~t2_pc~0); 244669#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 245229#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245292#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 245288#L983 assume !(0 != activate_threads_~tmp___1~0#1); 245289#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 244756#L445 assume !(1 == ~t3_pc~0); 244757#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 245099#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 244552#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 244553#L991 assume !(0 != activate_threads_~tmp___2~0#1); 245015#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 244976#L464 assume !(1 == ~t4_pc~0); 244560#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 244426#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244427#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 244766#L999 assume !(0 != activate_threads_~tmp___3~0#1); 244729#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 244730#L483 assume !(1 == ~t5_pc~0); 244974#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 245171#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244900#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 244901#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 244653#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 244654#L502 assume !(1 == ~t6_pc~0); 244505#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 244457#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244458#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 244883#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 244884#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 245140#L521 assume !(1 == ~t7_pc~0); 245197#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 244399#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 244400#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 245188#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 245149#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245040#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 245041#L869-2 assume !(1 == ~T1_E~0); 258571#L874-1 assume !(1 == ~T2_E~0); 258569#L879-1 assume !(1 == ~T3_E~0); 244808#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 244809#L889-1 assume !(1 == ~T5_E~0); 244591#L894-1 assume !(1 == ~T6_E~0); 244592#L899-1 assume !(1 == ~T7_E~0); 245001#L904-1 assume !(1 == ~E_M~0); 244748#L909-1 assume !(1 == ~E_1~0); 244749#L914-1 assume !(1 == ~E_2~0); 244936#L919-1 assume !(1 == ~E_3~0); 244667#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 244496#L929-1 assume !(1 == ~E_5~0); 244497#L934-1 assume !(1 == ~E_6~0); 244725#L939-1 assume !(1 == ~E_7~0); 244726#L944-1 assume { :end_inline_reset_delta_events } true; 245137#L1190-2 [2021-12-15 17:20:39,775 INFO L793 eck$LassoCheckResult]: Loop: 245137#L1190-2 assume !false; 259702#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 259585#L756 assume !false; 259580#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 259465#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 259435#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 259428#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 259418#L653 assume !(0 != eval_~tmp~0#1); 259419#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 261948#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 261947#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 261946#L781-5 assume !(0 == ~T1_E~0); 261945#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 261923#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 261922#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 261921#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 261920#L806-3 assume !(0 == ~T6_E~0); 261919#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 261904#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 261903#L821-3 assume !(0 == ~E_1~0); 261902#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 261893#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 261891#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 261889#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 261834#L846-3 assume !(0 == ~E_6~0); 261831#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 261827#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 261826#L388-27 assume 1 == ~m_pc~0; 261825#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 261823#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 261822#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261821#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 261820#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 261819#L407-27 assume !(1 == ~t1_pc~0); 261818#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 261817#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261816#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 261815#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 261814#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 261813#L426-27 assume !(1 == ~t2_pc~0); 261811#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 261810#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 261809#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 261808#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 261807#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 261806#L445-27 assume !(1 == ~t3_pc~0); 258828#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 261805#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 261804#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 261803#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 261802#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 261801#L464-27 assume !(1 == ~t4_pc~0); 261799#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 261798#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 261797#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 261796#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 261795#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 261794#L483-27 assume !(1 == ~t5_pc~0); 246965#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 261793#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 261792#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 261791#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 261790#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 261789#L502-27 assume !(1 == ~t6_pc~0); 259170#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 261788#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 261787#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 261786#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 261785#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 261784#L521-27 assume !(1 == ~t7_pc~0); 261783#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 261781#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 261779#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 261777#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 261775#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261774#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 257726#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 260240#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 260227#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 260225#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 260224#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 260222#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 257712#L899-3 assume !(1 == ~T7_E~0); 260217#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 260210#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 260205#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 260177#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 260174#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 260116#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 260113#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 258953#L939-3 assume !(1 == ~E_7~0); 260109#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 259931#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 259758#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 259749#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 245922#L1209 assume !(0 == start_simulation_~tmp~3#1); 245923#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 259755#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 259748#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 259744#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 259742#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 259740#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 259734#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 259730#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 245137#L1190-2 [2021-12-15 17:20:39,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,775 INFO L85 PathProgramCache]: Analyzing trace with hash -492911425, now seen corresponding path program 1 times [2021-12-15 17:20:39,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637679320] [2021-12-15 17:20:39,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,796 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637679320] [2021-12-15 17:20:39,796 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637679320] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,796 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,796 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:39,796 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164053513] [2021-12-15 17:20:39,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,797 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:39,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,797 INFO L85 PathProgramCache]: Analyzing trace with hash 1650173795, now seen corresponding path program 1 times [2021-12-15 17:20:39,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53324022] [2021-12-15 17:20:39,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,797 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53324022] [2021-12-15 17:20:39,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53324022] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,817 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552115301] [2021-12-15 17:20:39,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,818 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:39,818 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:39,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:39,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:39,819 INFO L87 Difference]: Start difference. First operand 35162 states and 50305 transitions. cyclomatic complexity: 15151 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:40,092 INFO L93 Difference]: Finished difference Result 44100 states and 63108 transitions. [2021-12-15 17:20:40,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:40,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44100 states and 63108 transitions. [2021-12-15 17:20:40,252 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 43944 [2021-12-15 17:20:40,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44100 states to 44100 states and 63108 transitions. [2021-12-15 17:20:40,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44100 [2021-12-15 17:20:40,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44100 [2021-12-15 17:20:40,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44100 states and 63108 transitions. [2021-12-15 17:20:40,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:40,402 INFO L681 BuchiCegarLoop]: Abstraction has 44100 states and 63108 transitions. [2021-12-15 17:20:40,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44100 states and 63108 transitions. [2021-12-15 17:20:40,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44100 to 18950. [2021-12-15 17:20:40,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18950 states, 18950 states have (on average 1.4363588390501318) internal successors, (27219), 18949 states have internal predecessors, (27219), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18950 states to 18950 states and 27219 transitions. [2021-12-15 17:20:40,712 INFO L704 BuchiCegarLoop]: Abstraction has 18950 states and 27219 transitions. [2021-12-15 17:20:40,712 INFO L587 BuchiCegarLoop]: Abstraction has 18950 states and 27219 transitions. [2021-12-15 17:20:40,712 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:40,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18950 states and 27219 transitions. [2021-12-15 17:20:40,886 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18832 [2021-12-15 17:20:40,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:40,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:40,888 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,888 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,888 INFO L791 eck$LassoCheckResult]: Stem: 324255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 324256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 323670#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 323671#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 324509#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 323975#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 323976#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 324107#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 324108#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 323885#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 323666#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 323667#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 323839#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 323840#L781 assume !(0 == ~M_E~0); 324348#L781-2 assume !(0 == ~T1_E~0); 324576#L786-1 assume !(0 == ~T2_E~0); 323628#L791-1 assume !(0 == ~T3_E~0); 323629#L796-1 assume !(0 == ~T4_E~0); 324186#L801-1 assume !(0 == ~T5_E~0); 324187#L806-1 assume !(0 == ~T6_E~0); 324212#L811-1 assume !(0 == ~T7_E~0); 323848#L816-1 assume !(0 == ~E_M~0); 323849#L821-1 assume !(0 == ~E_1~0); 323656#L826-1 assume !(0 == ~E_2~0); 323657#L831-1 assume !(0 == ~E_3~0); 323972#L836-1 assume !(0 == ~E_4~0); 323973#L841-1 assume !(0 == ~E_5~0); 323800#L846-1 assume !(0 == ~E_6~0); 323801#L851-1 assume !(0 == ~E_7~0); 323822#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 323823#L388 assume !(1 == ~m_pc~0); 323816#L388-2 is_master_triggered_~__retres1~0#1 := 0; 323817#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 324315#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 323674#L967 assume !(0 != activate_threads_~tmp~1#1); 323675#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323605#L407 assume !(1 == ~t1_pc~0); 323606#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 323609#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 323584#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 323585#L975 assume !(0 != activate_threads_~tmp___0~0#1); 324450#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323931#L426 assume !(1 == ~t2_pc~0); 323932#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 324481#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 324542#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 324539#L983 assume !(0 != activate_threads_~tmp___1~0#1); 324540#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 324017#L445 assume !(1 == ~t3_pc~0); 324018#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 324354#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 323818#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 323819#L991 assume !(0 != activate_threads_~tmp___2~0#1); 324273#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 324239#L464 assume !(1 == ~t4_pc~0); 323826#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 323695#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323696#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 324027#L999 assume !(0 != activate_threads_~tmp___3~0#1); 323992#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 323993#L483 assume !(1 == ~t5_pc~0); 324237#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 324423#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 324161#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 324162#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 323916#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 323917#L502 assume !(1 == ~t6_pc~0); 323774#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 323726#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 323727#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 324142#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 324143#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 324390#L521 assume !(1 == ~t7_pc~0); 324446#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 323668#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 323669#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 324439#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 324399#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 324302#L869 assume !(1 == ~M_E~0); 323985#L869-2 assume !(1 == ~T1_E~0); 323986#L874-1 assume !(1 == ~T2_E~0); 324499#L879-1 assume !(1 == ~T3_E~0); 324072#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 323593#L889-1 assume !(1 == ~T5_E~0); 323594#L894-1 assume !(1 == ~T6_E~0); 323855#L899-1 assume !(1 == ~T7_E~0); 324261#L904-1 assume !(1 == ~E_M~0); 324009#L909-1 assume !(1 == ~E_1~0); 324010#L914-1 assume !(1 == ~E_2~0); 324199#L919-1 assume !(1 == ~E_3~0); 323930#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 323765#L929-1 assume !(1 == ~E_5~0); 323766#L934-1 assume !(1 == ~E_6~0); 323988#L939-1 assume !(1 == ~E_7~0); 323989#L944-1 assume { :end_inline_reset_delta_events } true; 324387#L1190-2 [2021-12-15 17:20:40,889 INFO L793 eck$LassoCheckResult]: Loop: 324387#L1190-2 assume !false; 339809#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 339800#L756 assume !false; 339798#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 339796#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 339787#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 339784#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 339781#L653 assume !(0 != eval_~tmp~0#1); 339782#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 341753#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 341751#L781-3 assume !(0 == ~M_E~0); 341749#L781-5 assume !(0 == ~T1_E~0); 341747#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 341745#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 341743#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 341742#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 341740#L806-3 assume !(0 == ~T6_E~0); 341738#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 341736#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 341734#L821-3 assume !(0 == ~E_1~0); 341732#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 341731#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 341729#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 341727#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 341723#L846-3 assume !(0 == ~E_6~0); 341718#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 341713#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 341707#L388-27 assume 1 == ~m_pc~0; 341699#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 341692#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 341686#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 341681#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 341676#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 341672#L407-27 assume !(1 == ~t1_pc~0); 341666#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 341660#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 341655#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 341650#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 341645#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 341640#L426-27 assume 1 == ~t2_pc~0; 341633#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 341627#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 341623#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 341618#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 324434#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 324111#L445-27 assume !(1 == ~t3_pc~0); 324112#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 323649#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 323650#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 324087#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 324204#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 323910#L464-27 assume 1 == ~t4_pc~0; 323911#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 323648#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323714#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 324117#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 323796#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 323797#L483-27 assume !(1 == ~t5_pc~0); 324417#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 323704#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 323705#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 324380#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 324381#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 324578#L502-27 assume !(1 == ~t6_pc~0); 334732#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 334730#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 334728#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 334711#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 334706#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 334702#L521-27 assume 1 == ~t7_pc~0; 334697#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 334691#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 334683#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 334674#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 334667#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 334661#L869-3 assume !(1 == ~M_E~0); 329510#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 334652#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 334646#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 334640#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 334634#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 334628#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 334622#L899-3 assume !(1 == ~T7_E~0); 334617#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 334612#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 334607#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 334601#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 334595#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 334589#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 334584#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 334580#L939-3 assume !(1 == ~E_7~0); 334577#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 334569#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 334559#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 334547#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 330399#L1209 assume !(0 == start_simulation_~tmp~3#1); 330400#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 340045#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 340038#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 340036#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 340034#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 340032#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 340031#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 340029#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 324387#L1190-2 [2021-12-15 17:20:40,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,889 INFO L85 PathProgramCache]: Analyzing trace with hash -2081259327, now seen corresponding path program 1 times [2021-12-15 17:20:40,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132934588] [2021-12-15 17:20:40,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,927 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132934588] [2021-12-15 17:20:40,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132934588] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,927 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,928 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:40,928 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964746452] [2021-12-15 17:20:40,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,928 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:40,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,929 INFO L85 PathProgramCache]: Analyzing trace with hash -439511010, now seen corresponding path program 1 times [2021-12-15 17:20:40,929 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731301917] [2021-12-15 17:20:40,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,929 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,957 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731301917] [2021-12-15 17:20:40,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [731301917] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,958 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,958 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:40,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194898314] [2021-12-15 17:20:40,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,959 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:40,959 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:40,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:40,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:40,959 INFO L87 Difference]: Start difference. First operand 18950 states and 27219 transitions. cyclomatic complexity: 8271 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:41,086 INFO L93 Difference]: Finished difference Result 30098 states and 43086 transitions. [2021-12-15 17:20:41,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:41,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30098 states and 43086 transitions. [2021-12-15 17:20:41,206 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 29888 [2021-12-15 17:20:41,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30098 states to 30098 states and 43086 transitions. [2021-12-15 17:20:41,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30098 [2021-12-15 17:20:41,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30098 [2021-12-15 17:20:41,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30098 states and 43086 transitions. [2021-12-15 17:20:41,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:41,338 INFO L681 BuchiCegarLoop]: Abstraction has 30098 states and 43086 transitions. [2021-12-15 17:20:41,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30098 states and 43086 transitions. [2021-12-15 17:20:41,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30098 to 21390. [2021-12-15 17:20:41,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21390 states, 21390 states have (on average 1.4350163627863488) internal successors, (30695), 21389 states have internal predecessors, (30695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21390 states to 21390 states and 30695 transitions. [2021-12-15 17:20:41,672 INFO L704 BuchiCegarLoop]: Abstraction has 21390 states and 30695 transitions. [2021-12-15 17:20:41,672 INFO L587 BuchiCegarLoop]: Abstraction has 21390 states and 30695 transitions. [2021-12-15 17:20:41,672 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:41,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21390 states and 30695 transitions. [2021-12-15 17:20:41,727 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21200 [2021-12-15 17:20:41,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:41,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:41,730 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,731 INFO L791 eck$LassoCheckResult]: Stem: 373302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 373303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 372730#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 372731#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 373566#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 373032#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 373033#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 373157#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 373158#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 372944#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 372726#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 372727#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 372899#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 372900#L781 assume !(0 == ~M_E~0); 373393#L781-2 assume !(0 == ~T1_E~0); 373637#L786-1 assume !(0 == ~T2_E~0); 372687#L791-1 assume !(0 == ~T3_E~0); 372688#L796-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 373229#L801-1 assume !(0 == ~T5_E~0); 373230#L806-1 assume !(0 == ~T6_E~0); 373600#L811-1 assume !(0 == ~T7_E~0); 373601#L816-1 assume !(0 == ~E_M~0); 373508#L821-1 assume !(0 == ~E_1~0); 373509#L826-1 assume !(0 == ~E_2~0); 373228#L831-1 assume !(0 == ~E_3~0); 373029#L836-1 assume !(0 == ~E_4~0); 373030#L841-1 assume !(0 == ~E_5~0); 372862#L846-1 assume !(0 == ~E_6~0); 372863#L851-1 assume !(0 == ~E_7~0); 373681#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 373529#L388 assume !(1 == ~m_pc~0); 373530#L388-2 is_master_triggered_~__retres1~0#1 := 0; 373680#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 373558#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 373559#L967 assume !(0 != activate_threads_~tmp~1#1); 373602#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 373603#L407 assume !(1 == ~t1_pc~0); 373613#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 373614#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 372642#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 372643#L975 assume !(0 != activate_threads_~tmp___0~0#1); 373525#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 373526#L426 assume !(1 == ~t2_pc~0); 373538#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 373539#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 373679#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 373595#L983 assume !(0 != activate_threads_~tmp___1~0#1); 373596#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 373073#L445 assume !(1 == ~t3_pc~0); 373074#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 373676#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 373675#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 373674#L991 assume !(0 != activate_threads_~tmp___2~0#1); 373673#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 373286#L464 assume !(1 == ~t4_pc~0); 372887#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 372755#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 372756#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 373083#L999 assume !(0 != activate_threads_~tmp___3~0#1); 373048#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 373049#L483 assume !(1 == ~t5_pc~0); 373511#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 373512#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 373210#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 373211#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 373565#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 373665#L502 assume !(1 == ~t6_pc~0); 373664#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 372786#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 372787#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 373367#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 373443#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 373444#L521 assume !(1 == ~t7_pc~0); 373497#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 373662#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 373660#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 373489#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 373490#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 373657#L869 assume !(1 == ~M_E~0); 373656#L869-2 assume !(1 == ~T1_E~0); 373655#L874-1 assume !(1 == ~T2_E~0); 373555#L879-1 assume !(1 == ~T3_E~0); 373556#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 372651#L889-1 assume !(1 == ~T5_E~0); 372652#L894-1 assume !(1 == ~T6_E~0); 372915#L899-1 assume !(1 == ~T7_E~0); 373310#L904-1 assume !(1 == ~E_M~0); 373065#L909-1 assume !(1 == ~E_1~0); 373066#L914-1 assume !(1 == ~E_2~0); 373244#L919-1 assume !(1 == ~E_3~0); 372988#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 372824#L929-1 assume !(1 == ~E_5~0); 372825#L934-1 assume !(1 == ~E_6~0); 373044#L939-1 assume !(1 == ~E_7~0); 373045#L944-1 assume { :end_inline_reset_delta_events } true; 373441#L1190-2 [2021-12-15 17:20:41,731 INFO L793 eck$LassoCheckResult]: Loop: 373441#L1190-2 assume !false; 391817#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 391816#L756 assume !false; 391813#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 391811#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 391802#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 391800#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 391797#L653 assume !(0 != eval_~tmp~0#1); 391798#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 393430#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 393428#L781-3 assume !(0 == ~M_E~0); 393426#L781-5 assume !(0 == ~T1_E~0); 393424#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 393263#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 393036#L796-3 assume !(0 == ~T4_E~0); 373514#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 372976#L806-3 assume !(0 == ~T6_E~0); 372977#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 373166#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 373383#L821-3 assume !(0 == ~E_1~0); 373540#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 373318#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 373319#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 372872#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 372873#L846-3 assume !(0 == ~E_6~0); 373192#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 372762#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 372763#L388-27 assume !(1 == ~m_pc~0); 373492#L388-29 is_master_triggered_~__retres1~0#1 := 0; 373493#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 373449#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 373450#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 372947#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 372948#L407-27 assume !(1 == ~t1_pc~0); 373339#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 373423#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 373180#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 373181#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 373213#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372866#L426-27 assume 1 == ~t2_pc~0; 372868#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 372874#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 372875#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 373467#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 373485#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 373486#L445-27 assume !(1 == ~t3_pc~0); 393744#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 393742#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393740#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 393738#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 393736#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 393734#L464-27 assume 1 == ~t4_pc~0; 393732#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 393729#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 393727#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 393726#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 393725#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 390865#L483-27 assume !(1 == ~t5_pc~0); 390860#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 390856#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 390852#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 390848#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 390844#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 390838#L502-27 assume !(1 == ~t6_pc~0); 378483#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 390826#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 390818#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 390813#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 390810#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 390696#L521-27 assume 1 == ~t7_pc~0; 390694#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 390695#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 390803#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 390684#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 390682#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 390680#L869-3 assume !(1 == ~M_E~0); 380338#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 390664#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 390658#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 389731#L884-3 assume !(1 == ~T4_E~0); 389728#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 389726#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 389723#L899-3 assume !(1 == ~T7_E~0); 389722#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 389719#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 389717#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 389715#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 389713#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 389711#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 389707#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 389705#L939-3 assume !(1 == ~E_7~0); 389703#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 389670#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 389658#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 389646#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 389275#L1209 assume !(0 == start_simulation_~tmp~3#1); 389276#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 391931#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 391924#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 391922#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 391920#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 391916#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 391914#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 391912#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 373441#L1190-2 [2021-12-15 17:20:41,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1374674307, now seen corresponding path program 1 times [2021-12-15 17:20:41,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986439574] [2021-12-15 17:20:41,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,749 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986439574] [2021-12-15 17:20:41,750 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986439574] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,750 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,750 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,750 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067755856] [2021-12-15 17:20:41,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,750 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:41,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,751 INFO L85 PathProgramCache]: Analyzing trace with hash -264212961, now seen corresponding path program 1 times [2021-12-15 17:20:41,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320066271] [2021-12-15 17:20:41,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,768 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320066271] [2021-12-15 17:20:41,768 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320066271] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,768 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,768 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,769 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012424731] [2021-12-15 17:20:41,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,769 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:41,769 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:41,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:41,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:41,770 INFO L87 Difference]: Start difference. First operand 21390 states and 30695 transitions. cyclomatic complexity: 9307 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:41,868 INFO L93 Difference]: Finished difference Result 27646 states and 39473 transitions. [2021-12-15 17:20:41,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:41,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27646 states and 39473 transitions. [2021-12-15 17:20:41,971 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27520 [2021-12-15 17:20:42,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27646 states to 27646 states and 39473 transitions. [2021-12-15 17:20:42,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27646 [2021-12-15 17:20:42,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27646 [2021-12-15 17:20:42,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27646 states and 39473 transitions. [2021-12-15 17:20:42,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:42,082 INFO L681 BuchiCegarLoop]: Abstraction has 27646 states and 39473 transitions. [2021-12-15 17:20:42,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27646 states and 39473 transitions. [2021-12-15 17:20:42,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27646 to 18950. [2021-12-15 17:20:42,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18950 states, 18950 states have (on average 1.4311873350923483) internal successors, (27121), 18949 states have internal predecessors, (27121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18950 states to 18950 states and 27121 transitions. [2021-12-15 17:20:42,421 INFO L704 BuchiCegarLoop]: Abstraction has 18950 states and 27121 transitions. [2021-12-15 17:20:42,421 INFO L587 BuchiCegarLoop]: Abstraction has 18950 states and 27121 transitions. [2021-12-15 17:20:42,421 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:20:42,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18950 states and 27121 transitions. [2021-12-15 17:20:42,469 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18832 [2021-12-15 17:20:42,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:42,469 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:42,471 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,471 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,472 INFO L791 eck$LassoCheckResult]: Stem: 422344#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 422345#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 421774#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 421775#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 422584#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 422077#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 422078#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 422204#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 422205#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 421988#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 421770#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 421771#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 421943#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 421944#L781 assume !(0 == ~M_E~0); 422439#L781-2 assume !(0 == ~T1_E~0); 422651#L786-1 assume !(0 == ~T2_E~0); 421732#L791-1 assume !(0 == ~T3_E~0); 421733#L796-1 assume !(0 == ~T4_E~0); 422275#L801-1 assume !(0 == ~T5_E~0); 422276#L806-1 assume !(0 == ~T6_E~0); 422304#L811-1 assume !(0 == ~T7_E~0); 421952#L816-1 assume !(0 == ~E_M~0); 421953#L821-1 assume !(0 == ~E_1~0); 421760#L826-1 assume !(0 == ~E_2~0); 421761#L831-1 assume !(0 == ~E_3~0); 422074#L836-1 assume !(0 == ~E_4~0); 422075#L841-1 assume !(0 == ~E_5~0); 421905#L846-1 assume !(0 == ~E_6~0); 421906#L851-1 assume !(0 == ~E_7~0); 421927#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 421928#L388 assume !(1 == ~m_pc~0); 421921#L388-2 is_master_triggered_~__retres1~0#1 := 0; 421922#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 422406#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 421778#L967 assume !(0 != activate_threads_~tmp~1#1); 421779#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 421709#L407 assume !(1 == ~t1_pc~0); 421710#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 421713#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 421688#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 421689#L975 assume !(0 != activate_threads_~tmp___0~0#1); 422536#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 422034#L426 assume !(1 == ~t2_pc~0); 422035#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422558#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 422624#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 422621#L983 assume !(0 != activate_threads_~tmp___1~0#1); 422622#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422119#L445 assume !(1 == ~t3_pc~0); 422120#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 422445#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421923#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 421924#L991 assume !(0 != activate_threads_~tmp___2~0#1); 422364#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 422329#L464 assume !(1 == ~t4_pc~0); 421930#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 421799#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421800#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422129#L999 assume !(0 != activate_threads_~tmp___3~0#1); 422094#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422095#L483 assume !(1 == ~t5_pc~0); 422327#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422510#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422256#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 422257#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 422019#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 422020#L502 assume !(1 == ~t6_pc~0); 421878#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 421830#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 421831#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 422239#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 422240#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 422482#L521 assume !(1 == ~t7_pc~0); 422532#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 421772#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 421773#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 422525#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 422489#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422392#L869 assume !(1 == ~M_E~0); 422087#L869-2 assume !(1 == ~T1_E~0); 422088#L874-1 assume !(1 == ~T2_E~0); 422575#L879-1 assume !(1 == ~T3_E~0); 422171#L884-1 assume !(1 == ~T4_E~0); 421697#L889-1 assume !(1 == ~T5_E~0); 421698#L894-1 assume !(1 == ~T6_E~0); 421959#L899-1 assume !(1 == ~T7_E~0); 422352#L904-1 assume !(1 == ~E_M~0); 422111#L909-1 assume !(1 == ~E_1~0); 422112#L914-1 assume !(1 == ~E_2~0); 422291#L919-1 assume !(1 == ~E_3~0); 422033#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 421869#L929-1 assume !(1 == ~E_5~0); 421870#L934-1 assume !(1 == ~E_6~0); 422090#L939-1 assume !(1 == ~E_7~0); 422091#L944-1 assume { :end_inline_reset_delta_events } true; 422480#L1190-2 [2021-12-15 17:20:42,472 INFO L793 eck$LassoCheckResult]: Loop: 422480#L1190-2 assume !false; 438480#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 438478#L756 assume !false; 438476#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 438448#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 438434#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 438427#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 438420#L653 assume !(0 != eval_~tmp~0#1); 438421#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 440614#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 440613#L781-3 assume !(0 == ~M_E~0); 440612#L781-5 assume !(0 == ~T1_E~0); 440611#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 440610#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 440609#L796-3 assume !(0 == ~T4_E~0); 440608#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 440607#L806-3 assume !(0 == ~T6_E~0); 440606#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 440605#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 440604#L821-3 assume !(0 == ~E_1~0); 440603#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 440602#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 440601#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 440600#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 440599#L846-3 assume !(0 == ~E_6~0); 440598#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 440597#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 440596#L388-27 assume !(1 == ~m_pc~0); 440594#L388-29 is_master_triggered_~__retres1~0#1 := 0; 440593#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 440561#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 422587#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 421991#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 421992#L407-27 assume !(1 == ~t1_pc~0); 422382#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 422462#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422225#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 422226#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 422259#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 421909#L426-27 assume !(1 == ~t2_pc~0); 421910#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 422576#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 422505#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 422506#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 422520#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422208#L445-27 assume !(1 == ~t3_pc~0); 422209#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 421753#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 421754#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 422187#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 422296#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 422013#L464-27 assume !(1 == ~t4_pc~0); 421751#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 421752#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421818#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422214#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 421901#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 421902#L483-27 assume !(1 == ~t5_pc~0); 432742#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 432739#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 432736#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 432733#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 432730#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432615#L502-27 assume !(1 == ~t6_pc~0); 432613#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 432611#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 432607#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 432605#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 432603#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 432601#L521-27 assume 1 == ~t7_pc~0; 432599#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 432600#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 432626#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 432590#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 432588#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 432586#L869-3 assume !(1 == ~M_E~0); 432380#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 432583#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 432581#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 432579#L884-3 assume !(1 == ~T4_E~0); 432577#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 432575#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 432573#L899-3 assume !(1 == ~T7_E~0); 432571#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 432569#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 432567#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 432565#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 432563#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 432561#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 432560#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 432559#L939-3 assume !(1 == ~E_7~0); 432558#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 432555#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 432541#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 432210#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 431674#L1209 assume !(0 == start_simulation_~tmp~3#1); 431675#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 438570#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 438558#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 438551#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 438544#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 438538#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 438501#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 438494#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 422480#L1190-2 [2021-12-15 17:20:42,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,473 INFO L85 PathProgramCache]: Analyzing trace with hash 1626901955, now seen corresponding path program 1 times [2021-12-15 17:20:42,473 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538325367] [2021-12-15 17:20:42,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:42,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:42,493 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:42,493 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538325367] [2021-12-15 17:20:42,493 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538325367] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:42,493 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:42,493 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:42,493 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1659258006] [2021-12-15 17:20:42,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:42,493 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:42,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,494 INFO L85 PathProgramCache]: Analyzing trace with hash -160348639, now seen corresponding path program 1 times [2021-12-15 17:20:42,494 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109342128] [2021-12-15 17:20:42,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,494 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:42,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:42,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:42,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109342128] [2021-12-15 17:20:42,518 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109342128] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:42,518 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:42,519 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:42,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573971756] [2021-12-15 17:20:42,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:42,519 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:42,519 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:42,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:42,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:42,520 INFO L87 Difference]: Start difference. First operand 18950 states and 27121 transitions. cyclomatic complexity: 8173 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:42,652 INFO L93 Difference]: Finished difference Result 30126 states and 42623 transitions. [2021-12-15 17:20:42,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:42,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30126 states and 42623 transitions. [2021-12-15 17:20:42,775 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 29876 [2021-12-15 17:20:42,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30126 states to 30126 states and 42623 transitions. [2021-12-15 17:20:42,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30126 [2021-12-15 17:20:42,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30126 [2021-12-15 17:20:42,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30126 states and 42623 transitions. [2021-12-15 17:20:42,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:42,890 INFO L681 BuchiCegarLoop]: Abstraction has 30126 states and 42623 transitions. [2021-12-15 17:20:42,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30126 states and 42623 transitions. [2021-12-15 17:20:43,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30126 to 21390. [2021-12-15 17:20:43,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21390 states, 21390 states have (on average 1.4199158485273493) internal successors, (30372), 21389 states have internal predecessors, (30372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21390 states to 21390 states and 30372 transitions. [2021-12-15 17:20:43,293 INFO L704 BuchiCegarLoop]: Abstraction has 21390 states and 30372 transitions. [2021-12-15 17:20:43,293 INFO L587 BuchiCegarLoop]: Abstraction has 21390 states and 30372 transitions. [2021-12-15 17:20:43,293 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:20:43,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21390 states and 30372 transitions. [2021-12-15 17:20:43,348 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21200 [2021-12-15 17:20:43,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,350 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,351 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,351 INFO L791 eck$LassoCheckResult]: Stem: 471434#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 471435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 470861#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 470862#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 471697#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 471160#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 471161#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 471290#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 471291#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 471070#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 470857#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 470858#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 471028#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 471029#L781 assume !(0 == ~M_E~0); 471531#L781-2 assume !(0 == ~T1_E~0); 471772#L786-1 assume !(0 == ~T2_E~0); 470822#L791-1 assume !(0 == ~T3_E~0); 470823#L796-1 assume !(0 == ~T4_E~0); 471364#L801-1 assume !(0 == ~T5_E~0); 471365#L806-1 assume !(0 == ~T6_E~0); 471394#L811-1 assume !(0 == ~T7_E~0); 471034#L816-1 assume !(0 == ~E_M~0); 471035#L821-1 assume !(0 == ~E_1~0); 470847#L826-1 assume !(0 == ~E_2~0); 470848#L831-1 assume !(0 == ~E_3~0); 471156#L836-1 assume 0 == ~E_4~0;~E_4~0 := 1; 471157#L841-1 assume !(0 == ~E_5~0); 470990#L846-1 assume !(0 == ~E_6~0); 470991#L851-1 assume !(0 == ~E_7~0); 471839#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 471653#L388 assume !(1 == ~m_pc~0); 471654#L388-2 is_master_triggered_~__retres1~0#1 := 0; 471838#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471690#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 471691#L967 assume !(0 != activate_threads_~tmp~1#1); 471740#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 471741#L407 assume !(1 == ~t1_pc~0); 471837#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 471836#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 470774#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 470775#L975 assume !(0 != activate_threads_~tmp___0~0#1); 471649#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 471650#L426 assume !(1 == ~t2_pc~0); 471662#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 471663#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 471835#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 471729#L983 assume !(0 != activate_threads_~tmp___1~0#1); 471730#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 471202#L445 assume !(1 == ~t3_pc~0); 471203#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 471535#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 471006#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 471007#L991 assume !(0 != activate_threads_~tmp___2~0#1); 471454#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 471534#L464 assume !(1 == ~t4_pc~0); 471823#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 471822#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 471821#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 471820#L999 assume !(0 != activate_threads_~tmp___3~0#1); 471819#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 471818#L483 assume !(1 == ~t5_pc~0); 471817#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 471816#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 471815#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 471814#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 471813#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 471812#L502 assume !(1 == ~t6_pc~0); 471811#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 471810#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 471809#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 471808#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 471807#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 471806#L521 assume !(1 == ~t7_pc~0); 471805#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 471828#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 471826#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 471800#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 471799#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 471798#L869 assume !(1 == ~M_E~0); 471797#L869-2 assume !(1 == ~T1_E~0); 471796#L874-1 assume !(1 == ~T2_E~0); 471795#L879-1 assume !(1 == ~T3_E~0); 471794#L884-1 assume !(1 == ~T4_E~0); 471793#L889-1 assume !(1 == ~T5_E~0); 471792#L894-1 assume !(1 == ~T6_E~0); 471791#L899-1 assume !(1 == ~T7_E~0); 471790#L904-1 assume !(1 == ~E_M~0); 471789#L909-1 assume !(1 == ~E_1~0); 471788#L914-1 assume !(1 == ~E_2~0); 471787#L919-1 assume !(1 == ~E_3~0); 471786#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 470954#L929-1 assume !(1 == ~E_5~0); 470955#L934-1 assume !(1 == ~E_6~0); 471174#L939-1 assume !(1 == ~E_7~0); 471175#L944-1 assume { :end_inline_reset_delta_events } true; 471022#L1190-2 [2021-12-15 17:20:43,351 INFO L793 eck$LassoCheckResult]: Loop: 471022#L1190-2 assume !false; 471036#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 471037#L756 assume !false; 471272#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 471751#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 470879#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 471413#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 471217#L653 assume !(0 != eval_~tmp~0#1); 471219#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 491267#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 491263#L781-3 assume !(0 == ~M_E~0); 491260#L781-5 assume !(0 == ~T1_E~0); 491257#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 491254#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 491251#L796-3 assume !(0 == ~T4_E~0); 491247#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 491243#L806-3 assume !(0 == ~T6_E~0); 491240#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 491237#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 491234#L821-3 assume !(0 == ~E_1~0); 491152#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 491151#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 471676#L836-3 assume !(0 == ~E_4~0); 471678#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 490687#L846-3 assume !(0 == ~E_6~0); 490685#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 490683#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 490681#L388-27 assume 1 == ~m_pc~0; 490679#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 490676#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 490674#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 490672#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 490669#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 490666#L407-27 assume !(1 == ~t1_pc~0); 490665#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 490664#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 490663#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 490662#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 490661#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 490659#L426-27 assume !(1 == ~t2_pc~0); 490655#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 490653#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 490650#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 490644#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 490630#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 490436#L445-27 assume !(1 == ~t3_pc~0); 490435#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 490434#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 490433#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 490432#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 490430#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 490428#L464-27 assume !(1 == ~t4_pc~0); 490425#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 490422#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 490420#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 490418#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 490416#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 490414#L483-27 assume !(1 == ~t5_pc~0); 483652#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 490411#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 490409#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 490407#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 490405#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 490403#L502-27 assume !(1 == ~t6_pc~0); 483505#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 490399#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 490397#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 490395#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 490393#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 490391#L521-27 assume 1 == ~t7_pc~0; 490389#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 490390#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 490438#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 490380#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490378#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 490376#L869-3 assume !(1 == ~M_E~0); 482702#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 490373#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 490370#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 490369#L884-3 assume !(1 == ~T4_E~0); 490366#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 490364#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 490362#L899-3 assume !(1 == ~T7_E~0); 490360#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 490358#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 490356#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 490353#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 490351#L924-3 assume !(1 == ~E_4~0); 490348#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 490347#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 490346#L939-3 assume !(1 == ~E_7~0); 490345#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 490342#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 490335#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 490333#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 471752#L1209 assume !(0 == start_simulation_~tmp~3#1); 471315#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 471298#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 470935#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 471349#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 471350#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 470828#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 470829#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 471021#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 471022#L1190-2 [2021-12-15 17:20:43,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,352 INFO L85 PathProgramCache]: Analyzing trace with hash -281555835, now seen corresponding path program 1 times [2021-12-15 17:20:43,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10244178] [2021-12-15 17:20:43,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,352 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,370 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,370 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10244178] [2021-12-15 17:20:43,370 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10244178] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,370 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,370 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,370 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704429296] [2021-12-15 17:20:43,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,371 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:43,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,371 INFO L85 PathProgramCache]: Analyzing trace with hash 1660375200, now seen corresponding path program 1 times [2021-12-15 17:20:43,371 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926900148] [2021-12-15 17:20:43,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,372 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,389 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926900148] [2021-12-15 17:20:43,389 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926900148] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,389 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,390 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,390 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000717564] [2021-12-15 17:20:43,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,390 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:43,390 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:43,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:43,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:43,391 INFO L87 Difference]: Start difference. First operand 21390 states and 30372 transitions. cyclomatic complexity: 8984 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:43,509 INFO L93 Difference]: Finished difference Result 27178 states and 38378 transitions. [2021-12-15 17:20:43,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:43,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27178 states and 38378 transitions. [2021-12-15 17:20:43,622 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27044 [2021-12-15 17:20:43,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27178 states to 27178 states and 38378 transitions. [2021-12-15 17:20:43,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27178 [2021-12-15 17:20:43,712 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27178 [2021-12-15 17:20:43,712 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27178 states and 38378 transitions. [2021-12-15 17:20:43,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,729 INFO L681 BuchiCegarLoop]: Abstraction has 27178 states and 38378 transitions. [2021-12-15 17:20:43,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27178 states and 38378 transitions. [2021-12-15 17:20:43,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27178 to 18950. [2021-12-15 17:20:43,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18950 states, 18950 states have (on average 1.4141424802110818) internal successors, (26798), 18949 states have internal predecessors, (26798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18950 states to 18950 states and 26798 transitions. [2021-12-15 17:20:43,936 INFO L704 BuchiCegarLoop]: Abstraction has 18950 states and 26798 transitions. [2021-12-15 17:20:43,936 INFO L587 BuchiCegarLoop]: Abstraction has 18950 states and 26798 transitions. [2021-12-15 17:20:43,936 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:20:43,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18950 states and 26798 transitions. [2021-12-15 17:20:43,985 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18832 [2021-12-15 17:20:43,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,987 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,987 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,988 INFO L791 eck$LassoCheckResult]: Stem: 520022#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 520023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 519438#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 519439#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 520274#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 519737#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 519738#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 519866#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 519867#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 519651#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 519434#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 519435#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 519606#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 519607#L781 assume !(0 == ~M_E~0); 520115#L781-2 assume !(0 == ~T1_E~0); 520349#L786-1 assume !(0 == ~T2_E~0); 519396#L791-1 assume !(0 == ~T3_E~0); 519397#L796-1 assume !(0 == ~T4_E~0); 519947#L801-1 assume !(0 == ~T5_E~0); 519948#L806-1 assume !(0 == ~T6_E~0); 519979#L811-1 assume !(0 == ~T7_E~0); 519614#L816-1 assume !(0 == ~E_M~0); 519615#L821-1 assume !(0 == ~E_1~0); 519424#L826-1 assume !(0 == ~E_2~0); 519425#L831-1 assume !(0 == ~E_3~0); 519734#L836-1 assume !(0 == ~E_4~0); 519735#L841-1 assume !(0 == ~E_5~0); 519568#L846-1 assume !(0 == ~E_6~0); 519569#L851-1 assume !(0 == ~E_7~0); 519590#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 519591#L388 assume !(1 == ~m_pc~0); 519584#L388-2 is_master_triggered_~__retres1~0#1 := 0; 519585#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 520081#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 519442#L967 assume !(0 != activate_threads_~tmp~1#1); 519443#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 519373#L407 assume !(1 == ~t1_pc~0); 519374#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 519377#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 519352#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 519353#L975 assume !(0 != activate_threads_~tmp___0~0#1); 520223#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 519697#L426 assume !(1 == ~t2_pc~0); 519698#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 520250#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 520314#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 520311#L983 assume !(0 != activate_threads_~tmp___1~0#1); 520312#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 519779#L445 assume !(1 == ~t3_pc~0); 519780#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 520121#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 519586#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 519587#L991 assume !(0 != activate_threads_~tmp___2~0#1); 520042#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 520006#L464 assume !(1 == ~t4_pc~0); 519593#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 519463#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 519464#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 519789#L999 assume !(0 != activate_threads_~tmp___3~0#1); 519752#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 519753#L483 assume !(1 == ~t5_pc~0); 520003#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 520190#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 519925#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 519926#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 519682#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 519683#L502 assume !(1 == ~t6_pc~0); 519541#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 519493#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 519494#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 519904#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 519905#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 520160#L521 assume !(1 == ~t7_pc~0); 520218#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 519436#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 519437#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 520209#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 520167#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 520068#L869 assume !(1 == ~M_E~0); 519745#L869-2 assume !(1 == ~T1_E~0); 519746#L874-1 assume !(1 == ~T2_E~0); 520266#L879-1 assume !(1 == ~T3_E~0); 519833#L884-1 assume !(1 == ~T4_E~0); 519361#L889-1 assume !(1 == ~T5_E~0); 519362#L894-1 assume !(1 == ~T6_E~0); 519621#L899-1 assume !(1 == ~T7_E~0); 520029#L904-1 assume !(1 == ~E_M~0); 519771#L909-1 assume !(1 == ~E_1~0); 519772#L914-1 assume !(1 == ~E_2~0); 519966#L919-1 assume !(1 == ~E_3~0); 519696#L924-1 assume !(1 == ~E_4~0); 519532#L929-1 assume !(1 == ~E_5~0); 519533#L934-1 assume !(1 == ~E_6~0); 519748#L939-1 assume !(1 == ~E_7~0); 519749#L944-1 assume { :end_inline_reset_delta_events } true; 520158#L1190-2 [2021-12-15 17:20:43,988 INFO L793 eck$LassoCheckResult]: Loop: 520158#L1190-2 assume !false; 535760#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 535741#L756 assume !false; 535736#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 535704#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 535690#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 535683#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 535669#L653 assume !(0 != eval_~tmp~0#1); 535670#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 538135#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 538134#L781-3 assume !(0 == ~M_E~0); 538133#L781-5 assume !(0 == ~T1_E~0); 538132#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 538131#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 538130#L796-3 assume !(0 == ~T4_E~0); 538129#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 538128#L806-3 assume !(0 == ~T6_E~0); 538127#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 538126#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 538125#L821-3 assume !(0 == ~E_1~0); 538124#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 538123#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 538122#L836-3 assume !(0 == ~E_4~0); 538121#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 538120#L846-3 assume !(0 == ~E_6~0); 538119#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 538118#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 538117#L388-27 assume !(1 == ~m_pc~0); 538115#L388-29 is_master_triggered_~__retres1~0#1 := 0; 538114#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538113#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 538112#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 538111#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 538110#L407-27 assume !(1 == ~t1_pc~0); 538109#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 538108#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 538107#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 538106#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 538105#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 538104#L426-27 assume !(1 == ~t2_pc~0); 537966#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 537964#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 537962#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 537961#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 537960#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 519870#L445-27 assume !(1 == ~t3_pc~0); 519871#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 519417#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 519418#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 519848#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 519971#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 519676#L464-27 assume !(1 == ~t4_pc~0); 519415#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 519416#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 519482#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 519876#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 519564#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 519565#L483-27 assume !(1 == ~t5_pc~0); 520334#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 537546#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 520240#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 520151#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 520152#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 520350#L502-27 assume !(1 == ~t6_pc~0); 532857#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 532855#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 532853#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 532851#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 532849#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 532847#L521-27 assume 1 == ~t7_pc~0; 532843#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 532841#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 532839#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 532833#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 532830#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 532828#L869-3 assume !(1 == ~M_E~0); 529702#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 532825#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 532823#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 532821#L884-3 assume !(1 == ~T4_E~0); 532818#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 532817#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 532814#L899-3 assume !(1 == ~T7_E~0); 532812#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 532810#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 532808#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 532806#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 532804#L924-3 assume !(1 == ~E_4~0); 532803#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 532774#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 532764#L939-3 assume !(1 == ~E_7~0); 532756#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 532717#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 532707#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 532237#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 529614#L1209 assume !(0 == start_simulation_~tmp~3#1); 529615#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 535795#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 535788#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 535786#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 535784#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 535781#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 535779#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 535778#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 520158#L1190-2 [2021-12-15 17:20:43,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2021-12-15 17:20:43,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456958933] [2021-12-15 17:20:43,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,989 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:43,996 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:44,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:44,062 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:44,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,063 INFO L85 PathProgramCache]: Analyzing trace with hash -181938591, now seen corresponding path program 1 times [2021-12-15 17:20:44,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142953334] [2021-12-15 17:20:44,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,064 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142953334] [2021-12-15 17:20:44,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142953334] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,190 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,191 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007610978] [2021-12-15 17:20:44,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,191 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,191 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:44,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:44,192 INFO L87 Difference]: Start difference. First operand 18950 states and 26798 transitions. cyclomatic complexity: 7850 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,247 INFO L93 Difference]: Finished difference Result 21390 states and 30240 transitions. [2021-12-15 17:20:44,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:44,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21390 states and 30240 transitions. [2021-12-15 17:20:44,323 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21200 [2021-12-15 17:20:44,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21390 states to 21390 states and 30240 transitions. [2021-12-15 17:20:44,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21390 [2021-12-15 17:20:44,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21390 [2021-12-15 17:20:44,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21390 states and 30240 transitions. [2021-12-15 17:20:44,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,399 INFO L681 BuchiCegarLoop]: Abstraction has 21390 states and 30240 transitions. [2021-12-15 17:20:44,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21390 states and 30240 transitions. [2021-12-15 17:20:44,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21390 to 21390. [2021-12-15 17:20:44,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21390 states, 21390 states have (on average 1.4137447405329593) internal successors, (30240), 21389 states have internal predecessors, (30240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21390 states to 21390 states and 30240 transitions. [2021-12-15 17:20:44,560 INFO L704 BuchiCegarLoop]: Abstraction has 21390 states and 30240 transitions. [2021-12-15 17:20:44,560 INFO L587 BuchiCegarLoop]: Abstraction has 21390 states and 30240 transitions. [2021-12-15 17:20:44,560 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:20:44,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21390 states and 30240 transitions. [2021-12-15 17:20:44,610 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21200 [2021-12-15 17:20:44,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,612 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,612 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,613 INFO L791 eck$LassoCheckResult]: Stem: 560361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 560362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 559785#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 559786#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 560625#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 560087#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 560088#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 560218#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 560219#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 560000#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 559781#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 559782#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 559956#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 559957#L781 assume !(0 == ~M_E~0); 560457#L781-2 assume !(0 == ~T1_E~0); 560700#L786-1 assume !(0 == ~T2_E~0); 559743#L791-1 assume !(0 == ~T3_E~0); 559744#L796-1 assume !(0 == ~T4_E~0); 560295#L801-1 assume !(0 == ~T5_E~0); 560296#L806-1 assume !(0 == ~T6_E~0); 560323#L811-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 560672#L816-1 assume !(0 == ~E_M~0); 560570#L821-1 assume !(0 == ~E_1~0); 560571#L826-1 assume !(0 == ~E_2~0); 560293#L831-1 assume !(0 == ~E_3~0); 560294#L836-1 assume !(0 == ~E_4~0); 560746#L841-1 assume !(0 == ~E_5~0); 560745#L846-1 assume !(0 == ~E_6~0); 560688#L851-1 assume !(0 == ~E_7~0); 559941#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 559942#L388 assume !(1 == ~m_pc~0); 559935#L388-2 is_master_triggered_~__retres1~0#1 := 0; 559936#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 560423#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 559789#L967 assume !(0 != activate_threads_~tmp~1#1); 559790#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 559719#L407 assume !(1 == ~t1_pc~0); 559720#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 560742#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 559698#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 559699#L975 assume !(0 != activate_threads_~tmp___0~0#1); 560584#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560585#L426 assume !(1 == ~t2_pc~0); 560596#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 560597#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 560741#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 560660#L983 assume !(0 != activate_threads_~tmp___1~0#1); 560661#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 560131#L445 assume !(1 == ~t3_pc~0); 560132#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 560738#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560737#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 560736#L991 assume !(0 != activate_threads_~tmp___2~0#1); 560735#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560347#L464 assume !(1 == ~t4_pc~0); 559944#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 559810#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 559811#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 560145#L999 assume !(0 != activate_threads_~tmp___3~0#1); 560104#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 560105#L483 assume !(1 == ~t5_pc~0); 560574#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 560575#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560274#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 560275#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 560030#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 560031#L502 assume !(1 == ~t6_pc~0); 560403#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 559843#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 559844#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 560429#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 560503#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560504#L521 assume !(1 == ~t7_pc~0); 560559#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 560600#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560725#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 560551#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 560552#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 560723#L869 assume !(1 == ~M_E~0); 560722#L869-2 assume !(1 == ~T1_E~0); 560721#L874-1 assume !(1 == ~T2_E~0); 560612#L879-1 assume !(1 == ~T3_E~0); 560613#L884-1 assume !(1 == ~T4_E~0); 559707#L889-1 assume !(1 == ~T5_E~0); 559708#L894-1 assume !(1 == ~T6_E~0); 559974#L899-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 560369#L904-1 assume !(1 == ~E_M~0); 560123#L909-1 assume !(1 == ~E_1~0); 560124#L914-1 assume !(1 == ~E_2~0); 560311#L919-1 assume !(1 == ~E_3~0); 560044#L924-1 assume !(1 == ~E_4~0); 559882#L929-1 assume !(1 == ~E_5~0); 559883#L934-1 assume !(1 == ~E_6~0); 560102#L939-1 assume !(1 == ~E_7~0); 560103#L944-1 assume { :end_inline_reset_delta_events } true; 560501#L1190-2 [2021-12-15 17:20:44,613 INFO L793 eck$LassoCheckResult]: Loop: 560501#L1190-2 assume !false; 570288#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 570286#L756 assume !false; 570284#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 570282#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 570273#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 570271#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 570268#L653 assume !(0 != eval_~tmp~0#1); 570269#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 578020#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 578019#L781-3 assume !(0 == ~M_E~0); 578018#L781-5 assume !(0 == ~T1_E~0); 578017#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 578016#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 578015#L796-3 assume !(0 == ~T4_E~0); 578014#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 578013#L806-3 assume !(0 == ~T6_E~0); 578011#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 578010#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 578009#L821-3 assume !(0 == ~E_1~0); 578008#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 578007#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 578005#L836-3 assume !(0 == ~E_4~0); 578003#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 578001#L846-3 assume !(0 == ~E_6~0); 577998#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 577996#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 577994#L388-27 assume 1 == ~m_pc~0; 577992#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 577989#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 577987#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 577986#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 577985#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 577983#L407-27 assume !(1 == ~t1_pc~0); 577980#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 577978#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 577976#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 577974#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 577972#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577970#L426-27 assume !(1 == ~t2_pc~0); 577967#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 577965#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 577963#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 577961#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 577959#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 577956#L445-27 assume !(1 == ~t3_pc~0); 569231#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 577950#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 577947#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 577944#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 577941#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 577937#L464-27 assume !(1 == ~t4_pc~0); 577934#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 577931#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 577928#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 577925#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 577922#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 577918#L483-27 assume !(1 == ~t5_pc~0); 577008#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 577914#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 577911#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 577908#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 577903#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 570424#L502-27 assume !(1 == ~t6_pc~0); 570422#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 570420#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 570418#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 570416#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 570414#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 570410#L521-27 assume 1 == ~t7_pc~0; 570408#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 570409#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 570442#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 570398#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 570396#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 570392#L869-3 assume !(1 == ~M_E~0); 570173#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 570389#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 570387#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 570385#L884-3 assume !(1 == ~T4_E~0); 570383#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 570381#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 570380#L899-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 570378#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 570377#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 570376#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 570374#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 570372#L924-3 assume !(1 == ~E_4~0); 570370#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 570368#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 570366#L939-3 assume !(1 == ~E_7~0); 570364#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 570356#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 570349#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 570347#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 570344#L1209 assume !(0 == start_simulation_~tmp~3#1); 570343#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 570340#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 570334#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 570333#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 570332#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 570331#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 570330#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 570329#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 560501#L1190-2 [2021-12-15 17:20:44,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,614 INFO L85 PathProgramCache]: Analyzing trace with hash 287671557, now seen corresponding path program 1 times [2021-12-15 17:20:44,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606185226] [2021-12-15 17:20:44,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,630 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606185226] [2021-12-15 17:20:44,630 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606185226] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,630 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,630 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,630 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373304268] [2021-12-15 17:20:44,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,630 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,631 INFO L85 PathProgramCache]: Analyzing trace with hash 1441520482, now seen corresponding path program 1 times [2021-12-15 17:20:44,631 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481328627] [2021-12-15 17:20:44,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,631 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,647 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,647 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481328627] [2021-12-15 17:20:44,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1481328627] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,647 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,648 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,648 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124102627] [2021-12-15 17:20:44,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,648 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,648 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:44,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:44,649 INFO L87 Difference]: Start difference. First operand 21390 states and 30240 transitions. cyclomatic complexity: 8852 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,735 INFO L93 Difference]: Finished difference Result 27655 states and 38981 transitions. [2021-12-15 17:20:44,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:44,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27655 states and 38981 transitions. [2021-12-15 17:20:44,842 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27520 [2021-12-15 17:20:44,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27655 states to 27655 states and 38981 transitions. [2021-12-15 17:20:44,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27655 [2021-12-15 17:20:44,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27655 [2021-12-15 17:20:44,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27655 states and 38981 transitions. [2021-12-15 17:20:44,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,950 INFO L681 BuchiCegarLoop]: Abstraction has 27655 states and 38981 transitions. [2021-12-15 17:20:44,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27655 states and 38981 transitions. [2021-12-15 17:20:45,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27655 to 18950. [2021-12-15 17:20:45,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18950 states, 18950 states have (on average 1.412401055408971) internal successors, (26765), 18949 states have internal predecessors, (26765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:45,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18950 states to 18950 states and 26765 transitions. [2021-12-15 17:20:45,263 INFO L704 BuchiCegarLoop]: Abstraction has 18950 states and 26765 transitions. [2021-12-15 17:20:45,263 INFO L587 BuchiCegarLoop]: Abstraction has 18950 states and 26765 transitions. [2021-12-15 17:20:45,263 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:20:45,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18950 states and 26765 transitions. [2021-12-15 17:20:45,306 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18832 [2021-12-15 17:20:45,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:45,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:45,307 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,308 INFO L791 eck$LassoCheckResult]: Stem: 609423#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 609424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 608839#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 608840#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609675#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 609142#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 609143#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 609272#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 609273#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 609052#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 608835#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 608836#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 609008#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 609009#L781 assume !(0 == ~M_E~0); 609517#L781-2 assume !(0 == ~T1_E~0); 609742#L786-1 assume !(0 == ~T2_E~0); 608800#L791-1 assume !(0 == ~T3_E~0); 608801#L796-1 assume !(0 == ~T4_E~0); 609351#L801-1 assume !(0 == ~T5_E~0); 609352#L806-1 assume !(0 == ~T6_E~0); 609382#L811-1 assume !(0 == ~T7_E~0); 609015#L816-1 assume !(0 == ~E_M~0); 609016#L821-1 assume !(0 == ~E_1~0); 608825#L826-1 assume !(0 == ~E_2~0); 608826#L831-1 assume !(0 == ~E_3~0); 609139#L836-1 assume !(0 == ~E_4~0); 609140#L841-1 assume !(0 == ~E_5~0); 608971#L846-1 assume !(0 == ~E_6~0); 608972#L851-1 assume !(0 == ~E_7~0); 608991#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 608992#L388 assume !(1 == ~m_pc~0); 608985#L388-2 is_master_triggered_~__retres1~0#1 := 0; 608986#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 609484#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 608843#L967 assume !(0 != activate_threads_~tmp~1#1); 608844#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608774#L407 assume !(1 == ~t1_pc~0); 608775#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 608781#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 608753#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 608754#L975 assume !(0 != activate_threads_~tmp___0~0#1); 609616#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 609100#L426 assume !(1 == ~t2_pc~0); 609101#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 609647#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 609709#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 609705#L983 assume !(0 != activate_threads_~tmp___1~0#1); 609706#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 609186#L445 assume !(1 == ~t3_pc~0); 609187#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 609521#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 608987#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 608988#L991 assume !(0 != activate_threads_~tmp___2~0#1); 609443#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 609408#L464 assume !(1 == ~t4_pc~0); 608994#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 608864#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 608865#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 609199#L999 assume !(0 != activate_threads_~tmp___3~0#1); 609160#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 609161#L483 assume !(1 == ~t5_pc~0); 609406#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 609589#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 609329#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 609330#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 609088#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 609089#L502 assume !(1 == ~t6_pc~0); 608943#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 608894#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 608895#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 609308#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 609309#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 609561#L521 assume !(1 == ~t7_pc~0); 609612#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 609649#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 609753#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 609606#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 609568#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 609472#L869 assume !(1 == ~M_E~0); 609153#L869-2 assume !(1 == ~T1_E~0); 609154#L874-1 assume !(1 == ~T2_E~0); 609665#L879-1 assume !(1 == ~T3_E~0); 609240#L884-1 assume !(1 == ~T4_E~0); 608762#L889-1 assume !(1 == ~T5_E~0); 608763#L894-1 assume !(1 == ~T6_E~0); 609025#L899-1 assume !(1 == ~T7_E~0); 609434#L904-1 assume !(1 == ~E_M~0); 609178#L909-1 assume !(1 == ~E_1~0); 609179#L914-1 assume !(1 == ~E_2~0); 609369#L919-1 assume !(1 == ~E_3~0); 609099#L924-1 assume !(1 == ~E_4~0); 608934#L929-1 assume !(1 == ~E_5~0); 608935#L934-1 assume !(1 == ~E_6~0); 609158#L939-1 assume !(1 == ~E_7~0); 609159#L944-1 assume { :end_inline_reset_delta_events } true; 609560#L1190-2 [2021-12-15 17:20:45,308 INFO L793 eck$LassoCheckResult]: Loop: 609560#L1190-2 assume !false; 624873#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 624871#L756 assume !false; 624869#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 624867#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 624858#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 624857#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 624854#L653 assume !(0 != eval_~tmp~0#1); 624855#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 627553#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 627552#L781-3 assume !(0 == ~M_E~0); 627550#L781-5 assume !(0 == ~T1_E~0); 627547#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 627517#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 627515#L796-3 assume !(0 == ~T4_E~0); 627290#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 627263#L806-3 assume !(0 == ~T6_E~0); 627221#L811-3 assume !(0 == ~T7_E~0); 627220#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 627218#L821-3 assume !(0 == ~E_1~0); 627215#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 627207#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 627190#L836-3 assume !(0 == ~E_4~0); 627184#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 627183#L846-3 assume !(0 == ~E_6~0); 627174#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 627173#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 627172#L388-27 assume 1 == ~m_pc~0; 627169#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 627166#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 627165#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 609679#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 609055#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 609056#L407-27 assume !(1 == ~t1_pc~0); 609461#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 627493#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 627492#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 627491#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 627490#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 627489#L426-27 assume !(1 == ~t2_pc~0); 627487#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 627486#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 627485#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 627484#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 627483#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 627482#L445-27 assume !(1 == ~t3_pc~0); 624262#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 627481#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 627480#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 627479#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 627478#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 627477#L464-27 assume !(1 == ~t4_pc~0); 627475#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 627474#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 609460#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 609281#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 608965#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 608966#L483-27 assume !(1 == ~t5_pc~0); 624093#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 624090#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 624086#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 624081#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 624076#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 624071#L502-27 assume !(1 == ~t6_pc~0); 621268#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 624064#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 624060#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 624057#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 623538#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 623430#L521-27 assume !(1 == ~t7_pc~0); 623426#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 623424#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 623422#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 623420#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 623409#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 623401#L869-3 assume !(1 == ~M_E~0); 618378#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 623389#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 623387#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 623384#L884-3 assume !(1 == ~T4_E~0); 623381#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 623378#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 623375#L899-3 assume !(1 == ~T7_E~0); 623372#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 623369#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 623366#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 623362#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 623359#L924-3 assume !(1 == ~E_4~0); 623356#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 623353#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 623350#L939-3 assume !(1 == ~E_7~0); 623347#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 623340#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 623332#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 623309#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 618485#L1209 assume !(0 == start_simulation_~tmp~3#1); 618486#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 624984#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 624977#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 624974#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 624972#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 624971#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 624970#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 624966#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 609560#L1190-2 [2021-12-15 17:20:45,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,309 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2021-12-15 17:20:45,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343976181] [2021-12-15 17:20:45,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,309 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:45,319 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:45,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:45,347 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:45,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1467819355, now seen corresponding path program 1 times [2021-12-15 17:20:45,348 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717068194] [2021-12-15 17:20:45,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,349 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:45,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:45,366 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:45,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717068194] [2021-12-15 17:20:45,366 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717068194] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:45,367 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:45,367 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:45,367 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763810244] [2021-12-15 17:20:45,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:45,367 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:45,367 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:45,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:45,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:45,368 INFO L87 Difference]: Start difference. First operand 18950 states and 26765 transitions. cyclomatic complexity: 7817 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:45,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:45,480 INFO L93 Difference]: Finished difference Result 34435 states and 48323 transitions. [2021-12-15 17:20:45,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:45,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34435 states and 48323 transitions. [2021-12-15 17:20:45,607 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 34232 [2021-12-15 17:20:45,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34435 states to 34435 states and 48323 transitions. [2021-12-15 17:20:45,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34435 [2021-12-15 17:20:45,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34435 [2021-12-15 17:20:45,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34435 states and 48323 transitions. [2021-12-15 17:20:45,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:45,726 INFO L681 BuchiCegarLoop]: Abstraction has 34435 states and 48323 transitions. [2021-12-15 17:20:45,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34435 states and 48323 transitions. [2021-12-15 17:20:45,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34435 to 34419. [2021-12-15 17:20:46,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34419 states, 34419 states have (on average 1.4034980679275981) internal successors, (48307), 34418 states have internal predecessors, (48307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:46,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34419 states to 34419 states and 48307 transitions. [2021-12-15 17:20:46,272 INFO L704 BuchiCegarLoop]: Abstraction has 34419 states and 48307 transitions. [2021-12-15 17:20:46,272 INFO L587 BuchiCegarLoop]: Abstraction has 34419 states and 48307 transitions. [2021-12-15 17:20:46,272 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-15 17:20:46,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34419 states and 48307 transitions. [2021-12-15 17:20:46,364 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 34216 [2021-12-15 17:20:46,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:46,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:46,367 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:46,368 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:46,368 INFO L791 eck$LassoCheckResult]: Stem: 662811#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 662812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 662231#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 662232#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 663074#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 662530#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 662531#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 662658#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 662659#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 662444#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 662227#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 662228#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 662397#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 662398#L781 assume !(0 == ~M_E~0); 662910#L781-2 assume !(0 == ~T1_E~0); 663162#L786-1 assume !(0 == ~T2_E~0); 662192#L791-1 assume !(0 == ~T3_E~0); 662193#L796-1 assume !(0 == ~T4_E~0); 662740#L801-1 assume !(0 == ~T5_E~0); 662741#L806-1 assume !(0 == ~T6_E~0); 662771#L811-1 assume !(0 == ~T7_E~0); 662406#L816-1 assume !(0 == ~E_M~0); 662407#L821-1 assume !(0 == ~E_1~0); 662217#L826-1 assume !(0 == ~E_2~0); 662218#L831-1 assume !(0 == ~E_3~0); 662527#L836-1 assume !(0 == ~E_4~0); 662528#L841-1 assume !(0 == ~E_5~0); 662362#L846-1 assume !(0 == ~E_6~0); 662363#L851-1 assume 0 == ~E_7~0;~E_7~0 := 1; 663146#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 663037#L388 assume !(1 == ~m_pc~0); 663038#L388-2 is_master_triggered_~__retres1~0#1 := 0; 663215#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 663067#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 663068#L967 assume !(0 != activate_threads_~tmp~1#1); 663130#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 663131#L407 assume !(1 == ~t1_pc~0); 663135#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 663136#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 662144#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 662145#L975 assume !(0 != activate_threads_~tmp___0~0#1); 663033#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 663034#L426 assume !(1 == ~t2_pc~0); 663045#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 663046#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 663214#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 663113#L983 assume !(0 != activate_threads_~tmp___1~0#1); 663114#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 662572#L445 assume !(1 == ~t3_pc~0); 662573#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 662917#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 662378#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 662379#L991 assume !(0 != activate_threads_~tmp___2~0#1); 662830#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 662916#L464 assume !(1 == ~t4_pc~0); 663205#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 663204#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 663203#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 663202#L999 assume !(0 != activate_threads_~tmp___3~0#1); 663201#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 663200#L483 assume !(1 == ~t5_pc~0); 663024#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 663025#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 662715#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 662716#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 662476#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 662477#L502 assume !(1 == ~t6_pc~0); 662852#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 663198#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 663197#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 662695#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 662696#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 662952#L521 assume !(1 == ~t7_pc~0); 663048#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 663049#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 663194#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 663005#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 663006#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 663191#L869 assume !(1 == ~M_E~0); 663190#L869-2 assume !(1 == ~T1_E~0); 663189#L874-1 assume !(1 == ~T2_E~0); 663188#L879-1 assume !(1 == ~T3_E~0); 662623#L884-1 assume !(1 == ~T4_E~0); 662153#L889-1 assume !(1 == ~T5_E~0); 662154#L894-1 assume !(1 == ~T6_E~0); 662416#L899-1 assume !(1 == ~T7_E~0); 662818#L904-1 assume !(1 == ~E_M~0); 662562#L909-1 assume !(1 == ~E_1~0); 662563#L914-1 assume !(1 == ~E_2~0); 662758#L919-1 assume !(1 == ~E_3~0); 662487#L924-1 assume !(1 == ~E_4~0); 662324#L929-1 assume !(1 == ~E_5~0); 662325#L934-1 assume !(1 == ~E_6~0); 662541#L939-1 assume 1 == ~E_7~0;~E_7~0 := 2; 662542#L944-1 assume { :end_inline_reset_delta_events } true; 662950#L1190-2 [2021-12-15 17:20:46,368 INFO L793 eck$LassoCheckResult]: Loop: 662950#L1190-2 assume !false; 670209#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 670207#L756 assume !false; 670205#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 670203#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 670191#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 670186#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 670181#L653 assume !(0 != eval_~tmp~0#1); 670182#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 693578#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 693576#L781-3 assume !(0 == ~M_E~0); 693574#L781-5 assume !(0 == ~T1_E~0); 693572#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 693570#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 693567#L796-3 assume !(0 == ~T4_E~0); 693565#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 693563#L806-3 assume !(0 == ~T6_E~0); 693560#L811-3 assume !(0 == ~T7_E~0); 693558#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 693556#L821-3 assume !(0 == ~E_1~0); 693554#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 693552#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 693550#L836-3 assume !(0 == ~E_4~0); 693548#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 693546#L846-3 assume !(0 == ~E_6~0); 693505#L851-3 assume !(0 == ~E_7~0); 693506#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 696050#L388-27 assume !(1 == ~m_pc~0); 696048#L388-29 is_master_triggered_~__retres1~0#1 := 0; 696047#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 696046#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 696045#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 696044#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 696043#L407-27 assume !(1 == ~t1_pc~0); 696042#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 696041#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 696040#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 696039#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 696038#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 696037#L426-27 assume !(1 == ~t2_pc~0); 696035#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 696034#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 696033#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 696032#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 694950#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 662662#L445-27 assume !(1 == ~t3_pc~0); 662663#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 662210#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 662211#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 662639#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 662763#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 662468#L464-27 assume !(1 == ~t4_pc~0); 662208#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 662209#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 662274#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 662847#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 693641#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 690622#L483-27 assume !(1 == ~t5_pc~0); 690613#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 690604#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 690597#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 690589#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 690523#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 670672#L502-27 assume !(1 == ~t6_pc~0); 670667#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 670663#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 670661#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 670659#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 670657#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 670655#L521-27 assume 1 == ~t7_pc~0; 670654#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 670540#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 670538#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 670534#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 670532#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 670528#L869-3 assume !(1 == ~M_E~0); 670524#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 670522#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 670520#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 670518#L884-3 assume !(1 == ~T4_E~0); 670516#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 670514#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 670512#L899-3 assume !(1 == ~T7_E~0); 670510#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 670508#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 670506#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 670504#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 670502#L924-3 assume !(1 == ~E_4~0); 670500#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 670498#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 670497#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 670495#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 670488#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 670481#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 670480#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 670363#L1209 assume !(0 == start_simulation_~tmp~3#1); 670362#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 670263#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 670251#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 670244#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 670238#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 670231#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 670222#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 670218#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 662950#L1190-2 [2021-12-15 17:20:46,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:46,369 INFO L85 PathProgramCache]: Analyzing trace with hash -1450064635, now seen corresponding path program 1 times [2021-12-15 17:20:46,369 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:46,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058717803] [2021-12-15 17:20:46,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:46,369 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:46,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:46,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:46,404 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:46,404 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058717803] [2021-12-15 17:20:46,405 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058717803] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:46,405 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:46,405 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:46,405 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520985042] [2021-12-15 17:20:46,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:46,405 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:46,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:46,406 INFO L85 PathProgramCache]: Analyzing trace with hash 483142183, now seen corresponding path program 1 times [2021-12-15 17:20:46,406 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:46,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312526911] [2021-12-15 17:20:46,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:46,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:46,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:46,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:46,428 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:46,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312526911] [2021-12-15 17:20:46,428 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312526911] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:46,428 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:46,429 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:46,429 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029136453] [2021-12-15 17:20:46,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:46,429 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:46,429 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:46,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:46,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:46,430 INFO L87 Difference]: Start difference. First operand 34419 states and 48307 transitions. cyclomatic complexity: 13890 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:46,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:46,612 INFO L93 Difference]: Finished difference Result 50040 states and 70026 transitions. [2021-12-15 17:20:46,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:46,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50040 states and 70026 transitions. [2021-12-15 17:20:46,814 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 48392 [2021-12-15 17:20:46,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50040 states to 50040 states and 70026 transitions. [2021-12-15 17:20:46,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50040 [2021-12-15 17:20:46,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50040 [2021-12-15 17:20:46,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50040 states and 70026 transitions. [2021-12-15 17:20:47,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:47,024 INFO L681 BuchiCegarLoop]: Abstraction has 50040 states and 70026 transitions. [2021-12-15 17:20:47,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50040 states and 70026 transitions. [2021-12-15 17:20:47,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50040 to 34367. [2021-12-15 17:20:47,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34367 states, 34367 states have (on average 1.4027700992230918) internal successors, (48209), 34366 states have internal predecessors, (48209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:47,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34367 states to 34367 states and 48209 transitions. [2021-12-15 17:20:47,616 INFO L704 BuchiCegarLoop]: Abstraction has 34367 states and 48209 transitions. [2021-12-15 17:20:47,616 INFO L587 BuchiCegarLoop]: Abstraction has 34367 states and 48209 transitions. [2021-12-15 17:20:47,617 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-15 17:20:47,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34367 states and 48209 transitions. [2021-12-15 17:20:47,709 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 34216 [2021-12-15 17:20:47,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:47,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:47,711 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,712 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,712 INFO L791 eck$LassoCheckResult]: Stem: 747281#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 747282#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 746701#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 746702#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 747541#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 747002#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 747003#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 747134#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 747135#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 746914#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 746697#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 746698#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 746868#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 746869#L781 assume !(0 == ~M_E~0); 747376#L781-2 assume !(0 == ~T1_E~0); 747601#L786-1 assume !(0 == ~T2_E~0); 746659#L791-1 assume !(0 == ~T3_E~0); 746660#L796-1 assume !(0 == ~T4_E~0); 747213#L801-1 assume !(0 == ~T5_E~0); 747214#L806-1 assume !(0 == ~T6_E~0); 747240#L811-1 assume !(0 == ~T7_E~0); 746877#L816-1 assume !(0 == ~E_M~0); 746878#L821-1 assume !(0 == ~E_1~0); 746687#L826-1 assume !(0 == ~E_2~0); 746688#L831-1 assume !(0 == ~E_3~0); 746999#L836-1 assume !(0 == ~E_4~0); 747000#L841-1 assume !(0 == ~E_5~0); 746830#L846-1 assume !(0 == ~E_6~0); 746831#L851-1 assume !(0 == ~E_7~0); 746852#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 746853#L388 assume !(1 == ~m_pc~0); 746846#L388-2 is_master_triggered_~__retres1~0#1 := 0; 746847#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 747342#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 746705#L967 assume !(0 != activate_threads_~tmp~1#1); 746706#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 746636#L407 assume !(1 == ~t1_pc~0); 746637#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 746640#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 746615#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 746616#L975 assume !(0 != activate_threads_~tmp___0~0#1); 747489#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 746960#L426 assume !(1 == ~t2_pc~0); 746961#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 747515#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 747571#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 747566#L983 assume !(0 != activate_threads_~tmp___1~0#1); 747567#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 747047#L445 assume !(1 == ~t3_pc~0); 747048#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 747384#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 746848#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 746849#L991 assume !(0 != activate_threads_~tmp___2~0#1); 747302#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 747264#L464 assume !(1 == ~t4_pc~0); 746855#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 746726#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 746727#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 747057#L999 assume !(0 != activate_threads_~tmp___3~0#1); 747019#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 747020#L483 assume !(1 == ~t5_pc~0); 747262#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 747459#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 747188#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 747189#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 746945#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 746946#L502 assume !(1 == ~t6_pc~0); 746803#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 746755#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 746756#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 747170#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 747171#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 747422#L521 assume !(1 == ~t7_pc~0); 747484#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 746699#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 746700#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 746806#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 747431#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 747330#L869 assume !(1 == ~M_E~0); 747012#L869-2 assume !(1 == ~T1_E~0); 747013#L874-1 assume !(1 == ~T2_E~0); 747530#L879-1 assume !(1 == ~T3_E~0); 747531#L884-1 assume !(1 == ~T4_E~0); 746624#L889-1 assume !(1 == ~T5_E~0); 746625#L894-1 assume !(1 == ~T6_E~0); 746884#L899-1 assume !(1 == ~T7_E~0); 747626#L904-1 assume !(1 == ~E_M~0); 747625#L909-1 assume !(1 == ~E_1~0); 747623#L914-1 assume !(1 == ~E_2~0); 747620#L919-1 assume !(1 == ~E_3~0); 747619#L924-1 assume !(1 == ~E_4~0); 747618#L929-1 assume !(1 == ~E_5~0); 747617#L934-1 assume !(1 == ~E_6~0); 747616#L939-1 assume !(1 == ~E_7~0); 747016#L944-1 assume { :end_inline_reset_delta_events } true; 747420#L1190-2 [2021-12-15 17:20:47,712 INFO L793 eck$LassoCheckResult]: Loop: 747420#L1190-2 assume !false; 774237#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 774234#L756 assume !false; 774232#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 774230#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 774221#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 774219#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 774216#L653 assume !(0 != eval_~tmp~0#1); 774217#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 780483#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 780481#L781-3 assume !(0 == ~M_E~0); 780479#L781-5 assume !(0 == ~T1_E~0); 780477#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 780476#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 780475#L796-3 assume !(0 == ~T4_E~0); 778600#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 778599#L806-3 assume !(0 == ~T6_E~0); 778598#L811-3 assume !(0 == ~T7_E~0); 778596#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 778593#L821-3 assume !(0 == ~E_1~0); 778591#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 778589#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 778587#L836-3 assume !(0 == ~E_4~0); 778585#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 778583#L846-3 assume !(0 == ~E_6~0); 778581#L851-3 assume !(0 == ~E_7~0); 778579#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 778577#L388-27 assume 1 == ~m_pc~0; 778575#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 778572#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 778570#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 778567#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 778565#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 778563#L407-27 assume !(1 == ~t1_pc~0); 778561#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 778559#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 778557#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 778554#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 778552#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 778550#L426-27 assume !(1 == ~t2_pc~0); 778547#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 778545#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 778542#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 778540#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 778538#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 778536#L445-27 assume !(1 == ~t3_pc~0); 778398#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 778533#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 778532#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 778531#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 778529#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 778527#L464-27 assume !(1 == ~t4_pc~0); 778524#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 778522#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 778520#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 778518#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 778516#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 767087#L483-27 assume !(1 == ~t5_pc~0); 767083#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 767081#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 767056#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 767054#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 767052#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 763693#L502-27 assume !(1 == ~t6_pc~0); 763691#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 763689#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 763687#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 763685#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 763683#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 763681#L521-27 assume 1 == ~t7_pc~0; 763679#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 763680#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 763695#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 763668#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 763666#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 763664#L869-3 assume !(1 == ~M_E~0); 761355#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 763662#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 763660#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 763658#L884-3 assume !(1 == ~T4_E~0); 763656#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 763654#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 763652#L899-3 assume !(1 == ~T7_E~0); 763650#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 763648#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 763646#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 763644#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 763642#L924-3 assume !(1 == ~E_4~0); 763640#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 763638#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 763637#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 763635#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 763629#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 763622#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 763619#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 761381#L1209 assume !(0 == start_simulation_~tmp~3#1); 761382#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 774259#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 774252#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 774250#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 774248#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 774247#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 774246#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 774243#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 747420#L1190-2 [2021-12-15 17:20:47,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,713 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2021-12-15 17:20:47,713 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225353579] [2021-12-15 17:20:47,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,713 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:47,719 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:47,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:47,739 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:47,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,740 INFO L85 PathProgramCache]: Analyzing trace with hash -1969511322, now seen corresponding path program 1 times [2021-12-15 17:20:47,740 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444880553] [2021-12-15 17:20:47,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,741 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:47,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:47,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:47,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444880553] [2021-12-15 17:20:47,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444880553] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:47,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:47,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:47,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508725645] [2021-12-15 17:20:47,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:47,763 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:47,763 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:47,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:47,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:47,763 INFO L87 Difference]: Start difference. First operand 34367 states and 48209 transitions. cyclomatic complexity: 13844 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:47,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:47,960 INFO L93 Difference]: Finished difference Result 62599 states and 87065 transitions. [2021-12-15 17:20:47,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:20:47,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62599 states and 87065 transitions. [2021-12-15 17:20:48,265 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 62416 [2021-12-15 17:20:48,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62599 states to 62599 states and 87065 transitions. [2021-12-15 17:20:48,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62599 [2021-12-15 17:20:48,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62599 [2021-12-15 17:20:48,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62599 states and 87065 transitions. [2021-12-15 17:20:48,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:48,528 INFO L681 BuchiCegarLoop]: Abstraction has 62599 states and 87065 transitions. [2021-12-15 17:20:48,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62599 states and 87065 transitions. [2021-12-15 17:20:49,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62599 to 34559. [2021-12-15 17:20:49,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34559 states, 34559 states have (on average 1.4005324228131601) internal successors, (48401), 34558 states have internal predecessors, (48401), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:49,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34559 states to 34559 states and 48401 transitions. [2021-12-15 17:20:49,254 INFO L704 BuchiCegarLoop]: Abstraction has 34559 states and 48401 transitions. [2021-12-15 17:20:49,254 INFO L587 BuchiCegarLoop]: Abstraction has 34559 states and 48401 transitions. [2021-12-15 17:20:49,254 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-15 17:20:49,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34559 states and 48401 transitions. [2021-12-15 17:20:49,340 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 34408 [2021-12-15 17:20:49,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:49,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:49,342 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:49,342 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:49,342 INFO L791 eck$LassoCheckResult]: Stem: 844275#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 844276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 843683#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 843684#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 844543#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 843986#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 843987#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 844116#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 844117#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 843895#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 843679#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 843680#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 843851#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 843852#L781 assume !(0 == ~M_E~0); 844375#L781-2 assume !(0 == ~T1_E~0); 844632#L786-1 assume !(0 == ~T2_E~0); 843644#L791-1 assume !(0 == ~T3_E~0); 843645#L796-1 assume !(0 == ~T4_E~0); 844206#L801-1 assume !(0 == ~T5_E~0); 844207#L806-1 assume !(0 == ~T6_E~0); 844236#L811-1 assume !(0 == ~T7_E~0); 843857#L816-1 assume !(0 == ~E_M~0); 843858#L821-1 assume !(0 == ~E_1~0); 843669#L826-1 assume !(0 == ~E_2~0); 843670#L831-1 assume !(0 == ~E_3~0); 843983#L836-1 assume !(0 == ~E_4~0); 843984#L841-1 assume !(0 == ~E_5~0); 843814#L846-1 assume !(0 == ~E_6~0); 843815#L851-1 assume !(0 == ~E_7~0); 843834#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 843835#L388 assume !(1 == ~m_pc~0); 843828#L388-2 is_master_triggered_~__retres1~0#1 := 0; 843829#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 844343#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 843687#L967 assume !(0 != activate_threads_~tmp~1#1); 843688#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 843618#L407 assume !(1 == ~t1_pc~0); 843619#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 843625#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 843597#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 843598#L975 assume !(0 != activate_threads_~tmp___0~0#1); 844487#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 843943#L426 assume !(1 == ~t2_pc~0); 843944#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 844518#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 844588#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 844581#L983 assume !(0 != activate_threads_~tmp___1~0#1); 844582#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 844027#L445 assume !(1 == ~t3_pc~0); 844028#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 844384#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 843830#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 843831#L991 assume !(0 != activate_threads_~tmp___2~0#1); 844296#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 844261#L464 assume !(1 == ~t4_pc~0); 843837#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 843708#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 843709#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 844039#L999 assume !(0 != activate_threads_~tmp___3~0#1); 844001#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 844002#L483 assume !(1 == ~t5_pc~0); 844259#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 844460#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 844180#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 844181#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 843930#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 843931#L502 assume !(1 == ~t6_pc~0); 843786#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 843737#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 843738#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 844159#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 844160#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 844427#L521 assume !(1 == ~t7_pc~0); 844483#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 844521#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 844653#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 844476#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 844477#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844657#L869 assume !(1 == ~M_E~0); 844656#L869-2 assume !(1 == ~T1_E~0); 844574#L874-1 assume !(1 == ~T2_E~0); 844575#L879-1 assume !(1 == ~T3_E~0); 844078#L884-1 assume !(1 == ~T4_E~0); 844079#L889-1 assume !(1 == ~T5_E~0); 843867#L894-1 assume !(1 == ~T6_E~0); 843868#L899-1 assume !(1 == ~T7_E~0); 844655#L904-1 assume !(1 == ~E_M~0); 844654#L909-1 assume !(1 == ~E_1~0); 844222#L914-1 assume !(1 == ~E_2~0); 844223#L919-1 assume !(1 == ~E_3~0); 844652#L924-1 assume !(1 == ~E_4~0); 844651#L929-1 assume !(1 == ~E_5~0); 844650#L934-1 assume !(1 == ~E_6~0); 844649#L939-1 assume !(1 == ~E_7~0); 844000#L944-1 assume { :end_inline_reset_delta_events } true; 843847#L1190-2 [2021-12-15 17:20:49,343 INFO L793 eck$LassoCheckResult]: Loop: 843847#L1190-2 assume !false; 843859#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 843860#L756 assume !false; 844097#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 844620#L596 assume !(0 == ~m_st~0); 877610#L600 assume !(0 == ~t1_st~0); 877611#L604 assume !(0 == ~t2_st~0); 877613#L608 assume !(0 == ~t3_st~0); 877608#L612 assume !(0 == ~t4_st~0); 877609#L616 assume !(0 == ~t5_st~0); 877612#L620 assume !(0 == ~t6_st~0); 877606#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 877607#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 860830#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 860831#L653 assume !(0 != eval_~tmp~0#1); 877602#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 877600#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 877598#L781-3 assume !(0 == ~M_E~0); 877596#L781-5 assume !(0 == ~T1_E~0); 877594#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877592#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 877590#L796-3 assume !(0 == ~T4_E~0); 877588#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 877586#L806-3 assume !(0 == ~T6_E~0); 877584#L811-3 assume !(0 == ~T7_E~0); 877582#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 877580#L821-3 assume !(0 == ~E_1~0); 877578#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 877576#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 877574#L836-3 assume !(0 == ~E_4~0); 877572#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 877570#L846-3 assume !(0 == ~E_6~0); 877568#L851-3 assume !(0 == ~E_7~0); 877566#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 877564#L388-27 assume !(1 == ~m_pc~0); 877561#L388-29 is_master_triggered_~__retres1~0#1 := 0; 877558#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 877556#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 877554#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 877552#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 877550#L407-27 assume !(1 == ~t1_pc~0); 877548#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 877546#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 877544#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 877542#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 877540#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 877538#L426-27 assume !(1 == ~t2_pc~0); 877535#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 877532#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 877530#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 877528#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 877526#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 877524#L445-27 assume !(1 == ~t3_pc~0); 864687#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 877522#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 877520#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 877518#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 877516#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 877514#L464-27 assume !(1 == ~t4_pc~0); 877510#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 877508#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 877506#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 877504#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 877502#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 877500#L483-27 assume !(1 == ~t5_pc~0); 876500#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 877497#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 877495#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 877493#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 877491#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 877489#L502-27 assume !(1 == ~t6_pc~0); 876200#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 877487#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 877485#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 877483#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 877481#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 877479#L521-27 assume 1 == ~t7_pc~0; 877477#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 877478#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 877795#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 877794#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 844173#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844174#L869-3 assume !(1 == ~M_E~0); 844322#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 844323#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 844114#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 844115#L884-3 assume !(1 == ~T4_E~0); 844108#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 844109#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 844277#L899-3 assume !(1 == ~T7_E~0); 844278#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 878009#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 843739#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 843740#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 843785#L924-3 assume !(1 == ~E_4~0); 844307#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 844224#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 844225#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 844430#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 844470#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 843623#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 844055#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 844056#L1209 assume !(0 == start_simulation_~tmp~3#1); 877921#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 844124#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 843757#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 844188#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 844189#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 843650#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 843651#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 843846#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 843847#L1190-2 [2021-12-15 17:20:49,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:49,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2021-12-15 17:20:49,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:49,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994370013] [2021-12-15 17:20:49,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:49,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:49,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:49,350 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:49,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:49,365 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:49,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:49,365 INFO L85 PathProgramCache]: Analyzing trace with hash -903944265, now seen corresponding path program 1 times [2021-12-15 17:20:49,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:49,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970816539] [2021-12-15 17:20:49,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:49,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:49,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:49,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:49,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:49,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970816539] [2021-12-15 17:20:49,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970816539] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:49,412 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:49,412 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:49,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137114994] [2021-12-15 17:20:49,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:49,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:49,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:49,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:49,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:49,413 INFO L87 Difference]: Start difference. First operand 34559 states and 48401 transitions. cyclomatic complexity: 13844 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:49,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:49,764 INFO L93 Difference]: Finished difference Result 99576 states and 138388 transitions. [2021-12-15 17:20:49,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:49,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99576 states and 138388 transitions. [2021-12-15 17:20:50,586 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 99192 [2021-12-15 17:20:50,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99576 states to 99576 states and 138388 transitions. [2021-12-15 17:20:50,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99576 [2021-12-15 17:20:50,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99576 [2021-12-15 17:20:50,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99576 states and 138388 transitions. [2021-12-15 17:20:50,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:50,938 INFO L681 BuchiCegarLoop]: Abstraction has 99576 states and 138388 transitions. [2021-12-15 17:20:50,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99576 states and 138388 transitions. [2021-12-15 17:20:51,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99576 to 35906. [2021-12-15 17:20:51,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35906 states, 35906 states have (on average 1.3855066005681502) internal successors, (49748), 35905 states have internal predecessors, (49748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:51,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35906 states to 35906 states and 49748 transitions. [2021-12-15 17:20:51,423 INFO L704 BuchiCegarLoop]: Abstraction has 35906 states and 49748 transitions. [2021-12-15 17:20:51,423 INFO L587 BuchiCegarLoop]: Abstraction has 35906 states and 49748 transitions. [2021-12-15 17:20:51,423 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-15 17:20:51,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35906 states and 49748 transitions. [2021-12-15 17:20:51,519 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 35752 [2021-12-15 17:20:51,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:51,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:51,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:51,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:51,522 INFO L791 eck$LassoCheckResult]: Stem: 978415#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 978416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 977831#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 977832#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 978687#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 978132#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 978133#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 978259#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 978260#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 978046#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 977827#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 977828#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 977999#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 978000#L781 assume !(0 == ~M_E~0); 978505#L781-2 assume !(0 == ~T1_E~0); 978767#L786-1 assume !(0 == ~T2_E~0); 977789#L791-1 assume !(0 == ~T3_E~0); 977790#L796-1 assume !(0 == ~T4_E~0); 978335#L801-1 assume !(0 == ~T5_E~0); 978336#L806-1 assume !(0 == ~T6_E~0); 978372#L811-1 assume !(0 == ~T7_E~0); 978008#L816-1 assume !(0 == ~E_M~0); 978009#L821-1 assume !(0 == ~E_1~0); 977817#L826-1 assume !(0 == ~E_2~0); 977818#L831-1 assume !(0 == ~E_3~0); 978129#L836-1 assume !(0 == ~E_4~0); 978130#L841-1 assume !(0 == ~E_5~0); 977959#L846-1 assume !(0 == ~E_6~0); 977960#L851-1 assume !(0 == ~E_7~0); 977982#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 977983#L388 assume !(1 == ~m_pc~0); 977976#L388-2 is_master_triggered_~__retres1~0#1 := 0; 977977#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 978474#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 977835#L967 assume !(0 != activate_threads_~tmp~1#1); 977836#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 977766#L407 assume !(1 == ~t1_pc~0); 977767#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 977770#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 977745#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 977746#L975 assume !(0 != activate_threads_~tmp___0~0#1); 978624#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 978091#L426 assume !(1 == ~t2_pc~0); 978092#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 978656#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 978729#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 978723#L983 assume !(0 != activate_threads_~tmp___1~0#1); 978724#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 978175#L445 assume !(1 == ~t3_pc~0); 978176#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 978513#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 977978#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 977979#L991 assume !(0 != activate_threads_~tmp___2~0#1); 978434#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 978399#L464 assume !(1 == ~t4_pc~0); 977985#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 977856#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 977857#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 978186#L999 assume !(0 != activate_threads_~tmp___3~0#1); 978149#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 978150#L483 assume !(1 == ~t5_pc~0); 978397#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 978597#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 978311#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 978312#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 978077#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 978078#L502 assume !(1 == ~t6_pc~0); 977933#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 977885#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 977886#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 978294#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 978295#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 978559#L521 assume !(1 == ~t7_pc~0); 978620#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 978658#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 978787#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 978614#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 978571#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 978461#L869 assume !(1 == ~M_E~0); 978142#L869-2 assume !(1 == ~T1_E~0); 978143#L874-1 assume !(1 == ~T2_E~0); 978675#L879-1 assume !(1 == ~T3_E~0); 978676#L884-1 assume !(1 == ~T4_E~0); 977754#L889-1 assume !(1 == ~T5_E~0); 977755#L894-1 assume !(1 == ~T6_E~0); 978772#L899-1 assume !(1 == ~T7_E~0); 978773#L904-1 assume !(1 == ~E_M~0); 978788#L909-1 assume !(1 == ~E_1~0); 978355#L914-1 assume !(1 == ~E_2~0); 978356#L919-1 assume !(1 == ~E_3~0); 978785#L924-1 assume !(1 == ~E_4~0); 978784#L929-1 assume !(1 == ~E_5~0); 978783#L934-1 assume !(1 == ~E_6~0); 978782#L939-1 assume !(1 == ~E_7~0); 978146#L944-1 assume { :end_inline_reset_delta_events } true; 978557#L1190-2 [2021-12-15 17:20:51,523 INFO L793 eck$LassoCheckResult]: Loop: 978557#L1190-2 assume !false; 999924#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 999923#L756 assume !false; 999922#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 999921#L596 assume !(0 == ~m_st~0); 999917#L600 assume !(0 == ~t1_st~0); 999918#L604 assume !(0 == ~t2_st~0); 999920#L608 assume !(0 == ~t3_st~0); 999915#L612 assume !(0 == ~t4_st~0); 999916#L616 assume !(0 == ~t5_st~0); 999919#L620 assume !(0 == ~t6_st~0); 999913#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 999914#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 999907#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 999908#L653 assume !(0 != eval_~tmp~0#1); 1011164#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1011162#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1011158#L781-3 assume !(0 == ~M_E~0); 1011156#L781-5 assume !(0 == ~T1_E~0); 1011154#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1011152#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1011150#L796-3 assume !(0 == ~T4_E~0); 1011148#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1011146#L806-3 assume !(0 == ~T6_E~0); 1011144#L811-3 assume !(0 == ~T7_E~0); 1011142#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1011140#L821-3 assume !(0 == ~E_1~0); 1011138#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1011137#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1011133#L836-3 assume !(0 == ~E_4~0); 1011121#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1011119#L846-3 assume !(0 == ~E_6~0); 1011035#L851-3 assume !(0 == ~E_7~0); 1011036#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1011015#L388-27 assume !(1 == ~m_pc~0); 1011014#L388-29 is_master_triggered_~__retres1~0#1 := 0; 1011012#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1011010#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1011008#L967-27 assume !(0 != activate_threads_~tmp~1#1); 1011006#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1011005#L407-27 assume !(1 == ~t1_pc~0); 1011004#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1011003#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1011002#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1011000#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1010998#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1010997#L426-27 assume 1 == ~t2_pc~0; 1010996#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1010994#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1010993#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1010992#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1010991#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1010873#L445-27 assume !(1 == ~t3_pc~0); 1010872#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1010871#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1010870#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1010767#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1010766#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1010697#L464-27 assume !(1 == ~t4_pc~0); 1009716#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1009713#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1009711#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1009700#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1009699#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1000280#L483-27 assume !(1 == ~t5_pc~0); 1000281#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1000276#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1000277#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1000263#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1000264#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1000214#L502-27 assume !(1 == ~t6_pc~0); 1000209#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1000204#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1000198#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1000193#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1000188#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1000181#L521-27 assume !(1 == ~t7_pc~0); 1000171#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1000164#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1000156#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1000148#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1000142#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1000135#L869-3 assume !(1 == ~M_E~0); 1000127#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1000123#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1000119#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1000115#L884-3 assume !(1 == ~T4_E~0); 1000111#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1000107#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1000103#L899-3 assume !(1 == ~T7_E~0); 1000101#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1000097#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1000093#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1000089#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1000085#L924-3 assume !(1 == ~E_4~0); 1000081#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1000078#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1000075#L939-3 assume !(1 == ~E_7~0); 1000073#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1000026#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1000017#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1000012#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1000007#L1209 assume !(0 == start_simulation_~tmp~3#1); 1000003#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 999972#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 999963#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 999957#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 999951#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 999946#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 999938#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 999933#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 978557#L1190-2 [2021-12-15 17:20:51,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:51,523 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2021-12-15 17:20:51,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:51,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584828342] [2021-12-15 17:20:51,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:51,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:51,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:51,532 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:51,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:51,548 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:51,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:51,549 INFO L85 PathProgramCache]: Analyzing trace with hash 1844269369, now seen corresponding path program 1 times [2021-12-15 17:20:51,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:51,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750560097] [2021-12-15 17:20:51,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:51,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:51,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:51,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:51,571 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:51,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750560097] [2021-12-15 17:20:51,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750560097] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:51,572 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:51,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:51,572 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194225926] [2021-12-15 17:20:51,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:51,572 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:51,573 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:51,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:51,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:51,573 INFO L87 Difference]: Start difference. First operand 35906 states and 49748 transitions. cyclomatic complexity: 13844 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:52,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:52,090 INFO L93 Difference]: Finished difference Result 67466 states and 92508 transitions. [2021-12-15 17:20:52,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:52,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67466 states and 92508 transitions. [2021-12-15 17:20:52,330 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 67280 [2021-12-15 17:20:52,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67466 states to 67466 states and 92508 transitions. [2021-12-15 17:20:52,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67466 [2021-12-15 17:20:52,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67466 [2021-12-15 17:20:52,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67466 states and 92508 transitions. [2021-12-15 17:20:52,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:52,527 INFO L681 BuchiCegarLoop]: Abstraction has 67466 states and 92508 transitions. [2021-12-15 17:20:52,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67466 states and 92508 transitions. [2021-12-15 17:20:53,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67466 to 64234. [2021-12-15 17:20:53,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64234 states, 64234 states have (on average 1.3749104835445403) internal successors, (88316), 64233 states have internal predecessors, (88316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:53,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64234 states to 64234 states and 88316 transitions. [2021-12-15 17:20:53,381 INFO L704 BuchiCegarLoop]: Abstraction has 64234 states and 88316 transitions. [2021-12-15 17:20:53,381 INFO L587 BuchiCegarLoop]: Abstraction has 64234 states and 88316 transitions. [2021-12-15 17:20:53,381 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-15 17:20:53,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64234 states and 88316 transitions. [2021-12-15 17:20:53,569 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 64048 [2021-12-15 17:20:53,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:53,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:53,573 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:53,573 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:53,573 INFO L791 eck$LassoCheckResult]: Stem: 1081819#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1081820#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1081209#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1081210#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1082093#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1081515#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1081516#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1081649#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1081650#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1081426#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1081205#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1081206#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1081379#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1081380#L781 assume !(0 == ~M_E~0); 1081918#L781-2 assume !(0 == ~T1_E~0); 1082170#L786-1 assume !(0 == ~T2_E~0); 1081170#L791-1 assume !(0 == ~T3_E~0); 1081171#L796-1 assume !(0 == ~T4_E~0); 1081743#L801-1 assume !(0 == ~T5_E~0); 1081744#L806-1 assume !(0 == ~T6_E~0); 1081777#L811-1 assume !(0 == ~T7_E~0); 1081387#L816-1 assume !(0 == ~E_M~0); 1081388#L821-1 assume !(0 == ~E_1~0); 1081195#L826-1 assume !(0 == ~E_2~0); 1081196#L831-1 assume !(0 == ~E_3~0); 1081512#L836-1 assume !(0 == ~E_4~0); 1081513#L841-1 assume !(0 == ~E_5~0); 1081341#L846-1 assume !(0 == ~E_6~0); 1081342#L851-1 assume !(0 == ~E_7~0); 1081361#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1081362#L388 assume !(1 == ~m_pc~0); 1081355#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1081356#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1081881#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1081213#L967 assume !(0 != activate_threads_~tmp~1#1); 1081214#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1081144#L407 assume !(1 == ~t1_pc~0); 1081145#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1081151#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1081123#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1081124#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1082032#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1081472#L426 assume !(1 == ~t2_pc~0); 1081473#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1082060#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1082136#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1082128#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1082129#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1081560#L445 assume !(1 == ~t3_pc~0); 1081561#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1081923#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1081357#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1081358#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1081839#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1081804#L464 assume !(1 == ~t4_pc~0); 1081365#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1081234#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1081235#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1081573#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1081532#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1081533#L483 assume !(1 == ~t5_pc~0); 1081801#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1082000#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1081715#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1081716#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1081458#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1081459#L502 assume !(1 == ~t6_pc~0); 1081312#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1081263#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1081264#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1081689#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1081690#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1081966#L521 assume !(1 == ~t7_pc~0); 1082027#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1082062#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1082198#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1082020#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1081975#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1081870#L869 assume !(1 == ~M_E~0); 1081525#L869-2 assume !(1 == ~T1_E~0); 1081526#L874-1 assume !(1 == ~T2_E~0); 1082080#L879-1 assume !(1 == ~T3_E~0); 1082081#L884-1 assume !(1 == ~T4_E~0); 1081132#L889-1 assume !(1 == ~T5_E~0); 1081133#L894-1 assume !(1 == ~T6_E~0); 1082201#L899-1 assume !(1 == ~T7_E~0); 1082200#L904-1 assume !(1 == ~E_M~0); 1082199#L909-1 assume !(1 == ~E_1~0); 1081758#L914-1 assume !(1 == ~E_2~0); 1081759#L919-1 assume !(1 == ~E_3~0); 1082196#L924-1 assume !(1 == ~E_4~0); 1082195#L929-1 assume !(1 == ~E_5~0); 1082194#L934-1 assume !(1 == ~E_6~0); 1082191#L939-1 assume !(1 == ~E_7~0); 1081531#L944-1 assume { :end_inline_reset_delta_events } true; 1081964#L1190-2 [2021-12-15 17:20:53,573 INFO L793 eck$LassoCheckResult]: Loop: 1081964#L1190-2 assume !false; 1094797#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1094793#L756 assume !false; 1094786#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1094780#L596 assume !(0 == ~m_st~0); 1094781#L600 assume !(0 == ~t1_st~0); 1114503#L604 assume !(0 == ~t2_st~0); 1114501#L608 assume !(0 == ~t3_st~0); 1114499#L612 assume !(0 == ~t4_st~0); 1114497#L616 assume !(0 == ~t5_st~0); 1114495#L620 assume !(0 == ~t6_st~0); 1114492#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1114490#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1114488#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1114486#L653 assume !(0 != eval_~tmp~0#1); 1114484#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1114482#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1114480#L781-3 assume !(0 == ~M_E~0); 1114479#L781-5 assume !(0 == ~T1_E~0); 1114478#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1114476#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1114474#L796-3 assume !(0 == ~T4_E~0); 1114472#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1114470#L806-3 assume !(0 == ~T6_E~0); 1114468#L811-3 assume !(0 == ~T7_E~0); 1114466#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1114464#L821-3 assume !(0 == ~E_1~0); 1114462#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1114460#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1114458#L836-3 assume !(0 == ~E_4~0); 1114456#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1114454#L846-3 assume !(0 == ~E_6~0); 1114452#L851-3 assume !(0 == ~E_7~0); 1114449#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1114447#L388-27 assume 1 == ~m_pc~0; 1114444#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1114443#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1114442#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1114440#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1114439#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1114438#L407-27 assume !(1 == ~t1_pc~0); 1114437#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1114436#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1114435#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1114434#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1114433#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1114432#L426-27 assume 1 == ~t2_pc~0; 1114431#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1114429#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1114428#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1114427#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1114426#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1114425#L445-27 assume !(1 == ~t3_pc~0); 1107823#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1114424#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1114422#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1114420#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1114418#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1114416#L464-27 assume !(1 == ~t4_pc~0); 1114413#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1114409#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1114407#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1114405#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1114403#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1114401#L483-27 assume !(1 == ~t5_pc~0); 1092591#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1095618#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1095234#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1095232#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1095230#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1095070#L502-27 assume !(1 == ~t6_pc~0); 1095063#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1095056#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1095050#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1095044#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1095038#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1095032#L521-27 assume !(1 == ~t7_pc~0); 1095024#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1095018#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1095009#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1094998#L1023-27 assume !(0 != activate_threads_~tmp___6~0#1); 1094992#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1094985#L869-3 assume !(1 == ~M_E~0); 1094979#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1094975#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1094970#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1094962#L884-3 assume !(1 == ~T4_E~0); 1094956#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1094947#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1094939#L899-3 assume !(1 == ~T7_E~0); 1094932#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1094922#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1094915#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1094908#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1094902#L924-3 assume !(1 == ~E_4~0); 1094896#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1094891#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1094885#L939-3 assume !(1 == ~E_7~0); 1094880#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1094874#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1094868#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1094861#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1094855#L1209 assume !(0 == start_simulation_~tmp~3#1); 1094849#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1094844#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1094839#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1094835#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1094830#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1094825#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1094818#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1094812#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1081964#L1190-2 [2021-12-15 17:20:53,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:53,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 6 times [2021-12-15 17:20:53,574 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:53,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7522073] [2021-12-15 17:20:53,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:53,574 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:53,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:53,580 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:53,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:53,599 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:53,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:53,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1302658422, now seen corresponding path program 1 times [2021-12-15 17:20:53,600 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:53,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882272278] [2021-12-15 17:20:53,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:53,600 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:53,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:53,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:53,634 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:53,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882272278] [2021-12-15 17:20:53,634 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882272278] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:53,634 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:53,634 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:53,635 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674644290] [2021-12-15 17:20:53,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:53,635 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:53,635 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:53,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:53,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:53,636 INFO L87 Difference]: Start difference. First operand 64234 states and 88316 transitions. cyclomatic complexity: 24084 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:54,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:54,083 INFO L93 Difference]: Finished difference Result 124666 states and 170571 transitions. [2021-12-15 17:20:54,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:54,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124666 states and 170571 transitions. [2021-12-15 17:20:54,716 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 124480 [2021-12-15 17:20:55,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124666 states to 124666 states and 170571 transitions. [2021-12-15 17:20:55,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124666 [2021-12-15 17:20:55,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124666 [2021-12-15 17:20:55,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124666 states and 170571 transitions. [2021-12-15 17:20:55,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:55,606 INFO L681 BuchiCegarLoop]: Abstraction has 124666 states and 170571 transitions. [2021-12-15 17:20:55,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124666 states and 170571 transitions. [2021-12-15 17:20:56,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124666 to 65578. [2021-12-15 17:20:56,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65578 states, 65578 states have (on average 1.361355942541706) internal successors, (89275), 65577 states have internal predecessors, (89275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65578 states to 65578 states and 89275 transitions. [2021-12-15 17:20:56,361 INFO L704 BuchiCegarLoop]: Abstraction has 65578 states and 89275 transitions. [2021-12-15 17:20:56,361 INFO L587 BuchiCegarLoop]: Abstraction has 65578 states and 89275 transitions. [2021-12-15 17:20:56,361 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-15 17:20:56,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65578 states and 89275 transitions. [2021-12-15 17:20:56,907 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 65392 [2021-12-15 17:20:56,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:56,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:56,919 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,920 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,920 INFO L791 eck$LassoCheckResult]: Stem: 1270715#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1270716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1270123#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1270124#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1270995#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1270423#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1270424#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1270551#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1270552#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1270334#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1270119#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1270120#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1270288#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1270289#L781 assume !(0 == ~M_E~0); 1270818#L781-2 assume !(0 == ~T1_E~0); 1271072#L786-1 assume !(0 == ~T2_E~0); 1270081#L791-1 assume !(0 == ~T3_E~0); 1270082#L796-1 assume !(0 == ~T4_E~0); 1270636#L801-1 assume !(0 == ~T5_E~0); 1270637#L806-1 assume !(0 == ~T6_E~0); 1270672#L811-1 assume !(0 == ~T7_E~0); 1270296#L816-1 assume !(0 == ~E_M~0); 1270297#L821-1 assume !(0 == ~E_1~0); 1270109#L826-1 assume !(0 == ~E_2~0); 1270110#L831-1 assume !(0 == ~E_3~0); 1270420#L836-1 assume !(0 == ~E_4~0); 1270421#L841-1 assume !(0 == ~E_5~0); 1270251#L846-1 assume !(0 == ~E_6~0); 1270252#L851-1 assume !(0 == ~E_7~0); 1270273#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1270274#L388 assume !(1 == ~m_pc~0); 1270267#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1270268#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1271087#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1270127#L967 assume !(0 != activate_threads_~tmp~1#1); 1270128#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1270058#L407 assume !(1 == ~t1_pc~0); 1270059#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1270062#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1270037#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1270038#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1270927#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1270380#L426 assume !(1 == ~t2_pc~0); 1270381#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1270958#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1271034#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1271027#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1271028#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1270467#L445 assume !(1 == ~t3_pc~0); 1270468#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1270827#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1270269#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1270270#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1270735#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1270699#L464 assume !(1 == ~t4_pc~0); 1270276#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1270148#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1270149#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1270477#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1270441#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1270442#L483 assume !(1 == ~t5_pc~0); 1270697#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1270900#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1270608#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1270609#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1270365#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1270366#L502 assume !(1 == ~t6_pc~0); 1270225#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1270177#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1270178#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1270587#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1270588#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1270865#L521 assume !(1 == ~t7_pc~0); 1270923#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1270960#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1271091#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1270916#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1270917#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1271095#L869 assume !(1 == ~M_E~0); 1271094#L869-2 assume !(1 == ~T1_E~0); 1271022#L874-1 assume !(1 == ~T2_E~0); 1271023#L879-1 assume !(1 == ~T3_E~0); 1270518#L884-1 assume !(1 == ~T4_E~0); 1270519#L889-1 assume !(1 == ~T5_E~0); 1270303#L894-1 assume !(1 == ~T6_E~0); 1270304#L899-1 assume !(1 == ~T7_E~0); 1271080#L904-1 assume !(1 == ~E_M~0); 1271092#L909-1 assume !(1 == ~E_1~0); 1270657#L914-1 assume !(1 == ~E_2~0); 1270658#L919-1 assume !(1 == ~E_3~0); 1271090#L924-1 assume !(1 == ~E_4~0); 1271089#L929-1 assume !(1 == ~E_5~0); 1271088#L934-1 assume !(1 == ~E_6~0); 1271086#L939-1 assume !(1 == ~E_7~0); 1270438#L944-1 assume { :end_inline_reset_delta_events } true; 1270863#L1190-2 [2021-12-15 17:20:56,920 INFO L793 eck$LassoCheckResult]: Loop: 1270863#L1190-2 assume !false; 1278225#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1278217#L756 assume !false; 1278210#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1278202#L596 assume !(0 == ~m_st~0); 1278203#L600 assume !(0 == ~t1_st~0); 1292824#L604 assume !(0 == ~t2_st~0); 1292826#L608 assume !(0 == ~t3_st~0); 1292822#L612 assume !(0 == ~t4_st~0); 1292823#L616 assume !(0 == ~t5_st~0); 1292825#L620 assume !(0 == ~t6_st~0); 1292820#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1292821#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1292812#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1292813#L653 assume !(0 != eval_~tmp~0#1); 1298073#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1298072#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1298071#L781-3 assume !(0 == ~M_E~0); 1298070#L781-5 assume !(0 == ~T1_E~0); 1298069#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1298068#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1298067#L796-3 assume !(0 == ~T4_E~0); 1298066#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1298065#L806-3 assume !(0 == ~T6_E~0); 1298064#L811-3 assume !(0 == ~T7_E~0); 1298063#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1298062#L821-3 assume !(0 == ~E_1~0); 1298061#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1298060#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1298059#L836-3 assume !(0 == ~E_4~0); 1298058#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1298057#L846-3 assume !(0 == ~E_6~0); 1298056#L851-3 assume !(0 == ~E_7~0); 1298055#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1298049#L388-27 assume 1 == ~m_pc~0; 1298045#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1298042#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1298039#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1298035#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1298032#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1298029#L407-27 assume !(1 == ~t1_pc~0); 1298026#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1298023#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1298020#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1298017#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1298014#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1298010#L426-27 assume 1 == ~t2_pc~0; 1298006#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1298002#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1297999#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1297996#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1297993#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1297990#L445-27 assume !(1 == ~t3_pc~0); 1296563#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1297986#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1297983#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1297980#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1297977#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1297973#L464-27 assume !(1 == ~t4_pc~0); 1297969#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1297966#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1297963#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1297960#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1297957#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1277960#L483-27 assume !(1 == ~t5_pc~0); 1277958#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1277956#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1277954#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1277952#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1277950#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1277948#L502-27 assume !(1 == ~t6_pc~0); 1276637#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1277945#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1277943#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1277941#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1277940#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1277938#L521-27 assume 1 == ~t7_pc~0; 1277936#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1277937#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1278052#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1277920#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1277918#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1277916#L869-3 assume !(1 == ~M_E~0); 1277155#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1277913#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1277911#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1277909#L884-3 assume !(1 == ~T4_E~0); 1277907#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1277905#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1277903#L899-3 assume !(1 == ~T7_E~0); 1277901#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1277899#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1277897#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1277895#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1277894#L924-3 assume !(1 == ~E_4~0); 1277893#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1277889#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1277887#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1277884#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1277881#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1277879#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1277877#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1277875#L1209 assume !(0 == start_simulation_~tmp~3#1); 1277876#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1278294#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1278289#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1278284#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1278270#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1278258#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1278250#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1278242#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1270863#L1190-2 [2021-12-15 17:20:56,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,921 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 7 times [2021-12-15 17:20:56,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545159098] [2021-12-15 17:20:56,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,922 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:56,936 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:56,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:56,955 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:56,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,956 INFO L85 PathProgramCache]: Analyzing trace with hash -655427017, now seen corresponding path program 1 times [2021-12-15 17:20:56,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428578081] [2021-12-15 17:20:56,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,956 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,996 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,996 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428578081] [2021-12-15 17:20:56,996 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428578081] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,997 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:56,997 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570612632] [2021-12-15 17:20:56,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,997 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:56,997 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:56,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:56,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:56,998 INFO L87 Difference]: Start difference. First operand 65578 states and 89275 transitions. cyclomatic complexity: 23699 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,371 INFO L93 Difference]: Finished difference Result 120602 states and 163642 transitions. [2021-12-15 17:20:57,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:57,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120602 states and 163642 transitions. [2021-12-15 17:20:57,936 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 120352 [2021-12-15 17:20:58,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120602 states to 120602 states and 163642 transitions. [2021-12-15 17:20:58,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120602 [2021-12-15 17:20:58,344 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120602 [2021-12-15 17:20:58,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120602 states and 163642 transitions. [2021-12-15 17:20:58,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:58,413 INFO L681 BuchiCegarLoop]: Abstraction has 120602 states and 163642 transitions. [2021-12-15 17:20:58,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120602 states and 163642 transitions. [2021-12-15 17:20:59,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120602 to 66922. [2021-12-15 17:20:59,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66922 states, 66922 states have (on average 1.3483458354502256) internal successors, (90234), 66921 states have internal predecessors, (90234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:59,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66922 states to 66922 states and 90234 transitions. [2021-12-15 17:20:59,693 INFO L704 BuchiCegarLoop]: Abstraction has 66922 states and 90234 transitions. [2021-12-15 17:20:59,693 INFO L587 BuchiCegarLoop]: Abstraction has 66922 states and 90234 transitions. [2021-12-15 17:20:59,693 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-15 17:20:59,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66922 states and 90234 transitions. [2021-12-15 17:20:59,901 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 66736 [2021-12-15 17:20:59,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:59,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:59,905 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,906 INFO L791 eck$LassoCheckResult]: Stem: 1456904#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1456905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1456317#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1456318#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1457173#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1456617#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1456618#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1456747#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1456748#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1456528#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1456313#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1456314#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1456482#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1456483#L781 assume !(0 == ~M_E~0); 1456997#L781-2 assume !(0 == ~T1_E~0); 1457248#L786-1 assume !(0 == ~T2_E~0); 1456275#L791-1 assume !(0 == ~T3_E~0); 1456276#L796-1 assume !(0 == ~T4_E~0); 1456831#L801-1 assume !(0 == ~T5_E~0); 1456832#L806-1 assume !(0 == ~T6_E~0); 1456865#L811-1 assume !(0 == ~T7_E~0); 1456490#L816-1 assume !(0 == ~E_M~0); 1456491#L821-1 assume !(0 == ~E_1~0); 1456303#L826-1 assume !(0 == ~E_2~0); 1456304#L831-1 assume !(0 == ~E_3~0); 1456614#L836-1 assume !(0 == ~E_4~0); 1456615#L841-1 assume !(0 == ~E_5~0); 1456445#L846-1 assume !(0 == ~E_6~0); 1456446#L851-1 assume !(0 == ~E_7~0); 1456467#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1456468#L388 assume !(1 == ~m_pc~0); 1456461#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1456462#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1457267#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1456321#L967 assume !(0 != activate_threads_~tmp~1#1); 1456322#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1456252#L407 assume !(1 == ~t1_pc~0); 1456253#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1456256#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1456231#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1456232#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1457111#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1456572#L426 assume !(1 == ~t2_pc~0); 1456573#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1457142#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1457214#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1457207#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1457208#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1456661#L445 assume !(1 == ~t3_pc~0); 1456662#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1457004#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1456463#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1456464#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1456923#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1456890#L464 assume !(1 == ~t4_pc~0); 1456470#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1456342#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1456343#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1456671#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1456633#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1456634#L483 assume !(1 == ~t5_pc~0); 1456888#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1457078#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1456805#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1456806#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1456558#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1456559#L502 assume !(1 == ~t6_pc~0); 1456419#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1456371#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1456372#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1456785#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1456786#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1457045#L521 assume !(1 == ~t7_pc~0); 1457105#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1457144#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1457271#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1457098#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1457099#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1457275#L869 assume !(1 == ~M_E~0); 1457274#L869-2 assume !(1 == ~T1_E~0); 1457199#L874-1 assume !(1 == ~T2_E~0); 1457200#L879-1 assume !(1 == ~T3_E~0); 1456711#L884-1 assume !(1 == ~T4_E~0); 1456712#L889-1 assume !(1 == ~T5_E~0); 1456497#L894-1 assume !(1 == ~T6_E~0); 1456498#L899-1 assume !(1 == ~T7_E~0); 1457257#L904-1 assume !(1 == ~E_M~0); 1457272#L909-1 assume !(1 == ~E_1~0); 1456850#L914-1 assume !(1 == ~E_2~0); 1456851#L919-1 assume !(1 == ~E_3~0); 1457270#L924-1 assume !(1 == ~E_4~0); 1457269#L929-1 assume !(1 == ~E_5~0); 1457268#L934-1 assume !(1 == ~E_6~0); 1457266#L939-1 assume !(1 == ~E_7~0); 1456630#L944-1 assume { :end_inline_reset_delta_events } true; 1457043#L1190-2 [2021-12-15 17:20:59,906 INFO L793 eck$LassoCheckResult]: Loop: 1457043#L1190-2 assume !false; 1470975#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1470974#L756 assume !false; 1470973#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1470971#L596 assume !(0 == ~m_st~0); 1470972#L600 assume !(0 == ~t1_st~0); 1475741#L604 assume !(0 == ~t2_st~0); 1475743#L608 assume !(0 == ~t3_st~0); 1475739#L612 assume !(0 == ~t4_st~0); 1475740#L616 assume !(0 == ~t5_st~0); 1475742#L620 assume !(0 == ~t6_st~0); 1475737#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1475738#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1475731#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1475732#L653 assume !(0 != eval_~tmp~0#1); 1522690#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1522689#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1522688#L781-3 assume !(0 == ~M_E~0); 1522687#L781-5 assume !(0 == ~T1_E~0); 1522686#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1522685#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1522684#L796-3 assume !(0 == ~T4_E~0); 1522683#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1522682#L806-3 assume !(0 == ~T6_E~0); 1522681#L811-3 assume !(0 == ~T7_E~0); 1522680#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1522679#L821-3 assume !(0 == ~E_1~0); 1522678#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1522677#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1522676#L836-3 assume !(0 == ~E_4~0); 1522675#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1522674#L846-3 assume !(0 == ~E_6~0); 1522673#L851-3 assume !(0 == ~E_7~0); 1522672#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1522671#L388-27 assume 1 == ~m_pc~0; 1522669#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1522668#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1522667#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1522665#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1522664#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1522663#L407-27 assume !(1 == ~t1_pc~0); 1522662#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1522661#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1522660#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1522659#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1522658#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1522657#L426-27 assume !(1 == ~t2_pc~0); 1522655#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1522654#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1522653#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1522652#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1522651#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1468118#L445-27 assume !(1 == ~t3_pc~0); 1468116#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1468114#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1468112#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1468110#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1468108#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1468106#L464-27 assume !(1 == ~t4_pc~0); 1468102#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1468100#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1468098#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1468096#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1468094#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1468092#L483-27 assume !(1 == ~t5_pc~0); 1461962#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1468090#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1468088#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1468086#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1468084#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1468082#L502-27 assume !(1 == ~t6_pc~0); 1465413#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1468080#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1468078#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1468076#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1468074#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1468072#L521-27 assume 1 == ~t7_pc~0; 1468070#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1468071#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1468130#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1468126#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1468123#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1468121#L869-3 assume !(1 == ~M_E~0); 1468120#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1471204#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1471203#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1471202#L884-3 assume !(1 == ~T4_E~0); 1471201#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1471200#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1471199#L899-3 assume !(1 == ~T7_E~0); 1471198#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1471197#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1471196#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1471195#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1471194#L924-3 assume !(1 == ~E_4~0); 1471193#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1471192#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1471191#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1471189#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1471188#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1471187#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1471186#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1471156#L1209 assume !(0 == start_simulation_~tmp~3#1); 1471155#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1471153#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1471152#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1471151#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1471150#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1471149#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1471148#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1471147#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1457043#L1190-2 [2021-12-15 17:20:59,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,907 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 8 times [2021-12-15 17:20:59,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018825335] [2021-12-15 17:20:59,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,907 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:59,913 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:59,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:59,930 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:59,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1109001210, now seen corresponding path program 1 times [2021-12-15 17:20:59,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503106608] [2021-12-15 17:20:59,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:59,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:59,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:59,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503106608] [2021-12-15 17:20:59,961 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503106608] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:59,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:59,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:59,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762604866] [2021-12-15 17:20:59,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:59,962 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:59,962 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:59,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:59,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:59,963 INFO L87 Difference]: Start difference. First operand 66922 states and 90234 transitions. cyclomatic complexity: 23314 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:00,847 INFO L93 Difference]: Finished difference Result 178649 states and 239913 transitions. [2021-12-15 17:21:00,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:00,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178649 states and 239913 transitions. [2021-12-15 17:21:01,646 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 178192 [2021-12-15 17:21:02,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178649 states to 178649 states and 239913 transitions. [2021-12-15 17:21:02,071 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178649 [2021-12-15 17:21:02,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178649 [2021-12-15 17:21:02,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178649 states and 239913 transitions. [2021-12-15 17:21:02,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,290 INFO L681 BuchiCegarLoop]: Abstraction has 178649 states and 239913 transitions. [2021-12-15 17:21:02,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178649 states and 239913 transitions. [2021-12-15 17:21:03,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178649 to 69421. [2021-12-15 17:21:03,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69421 states, 69421 states have (on average 1.3358061681623716) internal successors, (92733), 69420 states have internal predecessors, (92733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69421 states to 69421 states and 92733 transitions. [2021-12-15 17:21:03,745 INFO L704 BuchiCegarLoop]: Abstraction has 69421 states and 92733 transitions. [2021-12-15 17:21:03,745 INFO L587 BuchiCegarLoop]: Abstraction has 69421 states and 92733 transitions. [2021-12-15 17:21:03,745 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-15 17:21:03,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69421 states and 92733 transitions. [2021-12-15 17:21:03,943 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 69232 [2021-12-15 17:21:03,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:03,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:03,947 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,947 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,947 INFO L791 eck$LassoCheckResult]: Stem: 1702508#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1702509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1701902#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1701903#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1702780#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1702214#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1702215#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1702343#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1702344#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1702120#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1701898#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1701899#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1702073#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1702074#L781 assume !(0 == ~M_E~0); 1702601#L781-2 assume !(0 == ~T1_E~0); 1702862#L786-1 assume !(0 == ~T2_E~0); 1701863#L791-1 assume !(0 == ~T3_E~0); 1701864#L796-1 assume !(0 == ~T4_E~0); 1702425#L801-1 assume !(0 == ~T5_E~0); 1702426#L806-1 assume !(0 == ~T6_E~0); 1702464#L811-1 assume !(0 == ~T7_E~0); 1702080#L816-1 assume !(0 == ~E_M~0); 1702081#L821-1 assume !(0 == ~E_1~0); 1701888#L826-1 assume !(0 == ~E_2~0); 1701889#L831-1 assume !(0 == ~E_3~0); 1702211#L836-1 assume !(0 == ~E_4~0); 1702212#L841-1 assume !(0 == ~E_5~0); 1702035#L846-1 assume !(0 == ~E_6~0); 1702036#L851-1 assume !(0 == ~E_7~0); 1702055#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1702056#L388 assume !(1 == ~m_pc~0); 1702049#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1702050#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1702773#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1701906#L967 assume !(0 != activate_threads_~tmp~1#1); 1701907#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1701837#L407 assume !(1 == ~t1_pc~0); 1701838#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1701844#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1701816#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1701817#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1702716#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1702169#L426 assume !(1 == ~t2_pc~0); 1702170#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1702743#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1702823#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1702816#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1702817#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1702259#L445 assume !(1 == ~t3_pc~0); 1702260#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1702608#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1702051#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1702052#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1702528#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1702492#L464 assume !(1 == ~t4_pc~0); 1702058#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1701928#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1701929#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1702271#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1702232#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1702233#L483 assume !(1 == ~t5_pc~0); 1702488#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1702688#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1702397#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1702398#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1702154#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1702155#L502 assume !(1 == ~t6_pc~0); 1702006#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1701957#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1701958#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1702378#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1702379#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1702651#L521 assume !(1 == ~t7_pc~0); 1702712#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1701900#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1701901#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1702009#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1702664#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1702555#L869 assume !(1 == ~M_E~0); 1702225#L869-2 assume !(1 == ~T1_E~0); 1702226#L874-1 assume !(1 == ~T2_E~0); 1702765#L879-1 assume !(1 == ~T3_E~0); 1702766#L884-1 assume !(1 == ~T4_E~0); 1701825#L889-1 assume !(1 == ~T5_E~0); 1701826#L894-1 assume !(1 == ~T6_E~0); 1702891#L899-1 assume !(1 == ~T7_E~0); 1702890#L904-1 assume !(1 == ~E_M~0); 1702889#L909-1 assume !(1 == ~E_1~0); 1702448#L914-1 assume !(1 == ~E_2~0); 1702449#L919-1 assume !(1 == ~E_3~0); 1702888#L924-1 assume !(1 == ~E_4~0); 1702887#L929-1 assume !(1 == ~E_5~0); 1702886#L934-1 assume !(1 == ~E_6~0); 1702885#L939-1 assume !(1 == ~E_7~0); 1702231#L944-1 assume { :end_inline_reset_delta_events } true; 1702650#L1190-2 [2021-12-15 17:21:03,948 INFO L793 eck$LassoCheckResult]: Loop: 1702650#L1190-2 assume !false; 1719310#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1719308#L756 assume !false; 1719306#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1719304#L596 assume !(0 == ~m_st~0); 1719305#L600 assume !(0 == ~t1_st~0); 1723573#L604 assume !(0 == ~t2_st~0); 1723571#L608 assume !(0 == ~t3_st~0); 1723569#L612 assume !(0 == ~t4_st~0); 1723567#L616 assume !(0 == ~t5_st~0); 1723565#L620 assume !(0 == ~t6_st~0); 1723561#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1723557#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1723554#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1723552#L653 assume !(0 != eval_~tmp~0#1); 1723538#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1723525#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1723518#L781-3 assume !(0 == ~M_E~0); 1723510#L781-5 assume !(0 == ~T1_E~0); 1723502#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1723494#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1723483#L796-3 assume !(0 == ~T4_E~0); 1723435#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1723427#L806-3 assume !(0 == ~T6_E~0); 1723417#L811-3 assume !(0 == ~T7_E~0); 1723408#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1723400#L821-3 assume !(0 == ~E_1~0); 1723392#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1723384#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1723373#L836-3 assume !(0 == ~E_4~0); 1723341#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1723334#L846-3 assume !(0 == ~E_6~0); 1723231#L851-3 assume !(0 == ~E_7~0); 1723227#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1723226#L388-27 assume 1 == ~m_pc~0; 1723224#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1723223#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1723222#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1723220#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1723219#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1723218#L407-27 assume !(1 == ~t1_pc~0); 1723217#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1723216#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1723215#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1723214#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1723213#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1723212#L426-27 assume 1 == ~t2_pc~0; 1723210#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1723208#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1723206#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1723204#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1722479#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1721593#L445-27 assume !(1 == ~t3_pc~0); 1721588#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1721583#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1721576#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1721575#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1721574#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1721061#L464-27 assume !(1 == ~t4_pc~0); 1721058#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1721056#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1721054#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1721052#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1721050#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1721047#L483-27 assume !(1 == ~t5_pc~0); 1720915#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1721044#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1721042#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1721040#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1721037#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1721035#L502-27 assume !(1 == ~t6_pc~0); 1718580#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1721032#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1721030#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1721028#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1721026#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1721024#L521-27 assume 1 == ~t7_pc~0; 1721022#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1721023#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1721149#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1720886#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1720884#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1720882#L869-3 assume !(1 == ~M_E~0); 1720878#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1720876#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1720874#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1720872#L884-3 assume !(1 == ~T4_E~0); 1720870#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1720868#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1720866#L899-3 assume !(1 == ~T7_E~0); 1720864#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1720862#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1720860#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1720858#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1720856#L924-3 assume !(1 == ~E_4~0); 1720854#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1720852#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1720850#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1720804#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1720792#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1720782#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1720771#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1719398#L1209 assume !(0 == start_simulation_~tmp~3#1); 1719397#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1719395#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1719391#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1719389#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1719387#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1719386#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1719385#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1719384#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1702650#L1190-2 [2021-12-15 17:21:03,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 9 times [2021-12-15 17:21:03,948 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611178696] [2021-12-15 17:21:03,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,948 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:03,954 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:03,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:03,986 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:03,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,986 INFO L85 PathProgramCache]: Analyzing trace with hash 731358393, now seen corresponding path program 1 times [2021-12-15 17:21:03,986 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532729792] [2021-12-15 17:21:03,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,987 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:04,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:04,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:04,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532729792] [2021-12-15 17:21:04,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532729792] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:04,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:04,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:04,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625527983] [2021-12-15 17:21:04,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:04,016 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:04,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:04,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:04,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:04,017 INFO L87 Difference]: Start difference. First operand 69421 states and 92733 transitions. cyclomatic complexity: 23314 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:04,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:04,751 INFO L93 Difference]: Finished difference Result 100413 states and 133236 transitions. [2021-12-15 17:21:04,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:04,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100413 states and 133236 transitions. [2021-12-15 17:21:05,182 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 100160 [2021-12-15 17:21:05,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100413 states to 100413 states and 133236 transitions. [2021-12-15 17:21:05,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100413 [2021-12-15 17:21:05,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100413 [2021-12-15 17:21:05,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100413 states and 133236 transitions. [2021-12-15 17:21:05,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:05,495 INFO L681 BuchiCegarLoop]: Abstraction has 100413 states and 133236 transitions. [2021-12-15 17:21:05,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100413 states and 133236 transitions. [2021-12-15 17:21:06,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100413 to 69613. [2021-12-15 17:21:06,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69613 states, 69613 states have (on average 1.3238331920761928) internal successors, (92156), 69612 states have internal predecessors, (92156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:06,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69613 states to 69613 states and 92156 transitions. [2021-12-15 17:21:06,623 INFO L704 BuchiCegarLoop]: Abstraction has 69613 states and 92156 transitions. [2021-12-15 17:21:06,623 INFO L587 BuchiCegarLoop]: Abstraction has 69613 states and 92156 transitions. [2021-12-15 17:21:06,623 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-15 17:21:06,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69613 states and 92156 transitions. [2021-12-15 17:21:06,793 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 69424 [2021-12-15 17:21:06,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:06,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:06,797 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,797 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,797 INFO L791 eck$LassoCheckResult]: Stem: 1872342#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1872343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1871750#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1871751#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1872636#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1872053#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1872054#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1872181#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1872182#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1871965#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1871746#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1871747#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1871919#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1871920#L781 assume !(0 == ~M_E~0); 1872444#L781-2 assume !(0 == ~T1_E~0); 1872719#L786-1 assume !(0 == ~T2_E~0); 1871711#L791-1 assume !(0 == ~T3_E~0); 1871712#L796-1 assume !(0 == ~T4_E~0); 1872270#L801-1 assume !(0 == ~T5_E~0); 1872271#L806-1 assume !(0 == ~T6_E~0); 1872302#L811-1 assume !(0 == ~T7_E~0); 1871927#L816-1 assume !(0 == ~E_M~0); 1871928#L821-1 assume !(0 == ~E_1~0); 1871736#L826-1 assume !(0 == ~E_2~0); 1871737#L831-1 assume !(0 == ~E_3~0); 1872050#L836-1 assume !(0 == ~E_4~0); 1872051#L841-1 assume !(0 == ~E_5~0); 1871883#L846-1 assume !(0 == ~E_6~0); 1871884#L851-1 assume !(0 == ~E_7~0); 1871903#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1871904#L388 assume !(1 == ~m_pc~0); 1871897#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1871898#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1872406#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1871754#L967 assume !(0 != activate_threads_~tmp~1#1); 1871755#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1871685#L407 assume !(1 == ~t1_pc~0); 1871686#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1871692#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1871664#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1871665#L975 assume !(0 != activate_threads_~tmp___0~0#1); 1872564#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1872009#L426 assume !(1 == ~t2_pc~0); 1872010#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1872601#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1872727#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1872672#L983 assume !(0 != activate_threads_~tmp___1~0#1); 1872673#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1872096#L445 assume !(1 == ~t3_pc~0); 1872097#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1872451#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1871899#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1871900#L991 assume !(0 != activate_threads_~tmp___2~0#1); 1872361#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1872327#L464 assume !(1 == ~t4_pc~0); 1871906#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1871775#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1871776#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1872109#L999 assume !(0 != activate_threads_~tmp___3~0#1); 1872068#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1872069#L483 assume !(1 == ~t5_pc~0); 1872325#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1872532#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1872241#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1872242#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 1871997#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1871998#L502 assume !(1 == ~t6_pc~0); 1871854#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1871804#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1871805#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1872221#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 1872222#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1872495#L521 assume !(1 == ~t7_pc~0); 1872560#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1872604#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1872744#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1872552#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 1872553#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1872749#L869 assume !(1 == ~M_E~0); 1872748#L869-2 assume !(1 == ~T1_E~0); 1872664#L874-1 assume !(1 == ~T2_E~0); 1872665#L879-1 assume !(1 == ~T3_E~0); 1872147#L884-1 assume !(1 == ~T4_E~0); 1872148#L889-1 assume !(1 == ~T5_E~0); 1871937#L894-1 assume !(1 == ~T6_E~0); 1871938#L899-1 assume !(1 == ~T7_E~0); 1872348#L904-1 assume !(1 == ~E_M~0); 1872086#L909-1 assume !(1 == ~E_1~0); 1872087#L914-1 assume !(1 == ~E_2~0); 1872743#L919-1 assume !(1 == ~E_3~0); 1872742#L924-1 assume !(1 == ~E_4~0); 1872741#L929-1 assume !(1 == ~E_5~0); 1872740#L934-1 assume !(1 == ~E_6~0); 1872736#L939-1 assume !(1 == ~E_7~0); 1872067#L944-1 assume { :end_inline_reset_delta_events } true; 1872493#L1190-2 [2021-12-15 17:21:06,797 INFO L793 eck$LassoCheckResult]: Loop: 1872493#L1190-2 assume !false; 1885745#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1885743#L756 assume !false; 1885740#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1885737#L596 assume !(0 == ~m_st~0); 1885738#L600 assume !(0 == ~t1_st~0); 1889354#L604 assume !(0 == ~t2_st~0); 1889353#L608 assume !(0 == ~t3_st~0); 1889352#L612 assume !(0 == ~t4_st~0); 1889351#L616 assume !(0 == ~t5_st~0); 1889350#L620 assume !(0 == ~t6_st~0); 1889348#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1889347#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1889346#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1889344#L653 assume !(0 != eval_~tmp~0#1); 1889343#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1889342#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1889341#L781-3 assume !(0 == ~M_E~0); 1889340#L781-5 assume !(0 == ~T1_E~0); 1889339#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1889338#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1889337#L796-3 assume !(0 == ~T4_E~0); 1889336#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1889335#L806-3 assume !(0 == ~T6_E~0); 1889334#L811-3 assume !(0 == ~T7_E~0); 1889333#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1889332#L821-3 assume !(0 == ~E_1~0); 1889331#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1889330#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1889329#L836-3 assume !(0 == ~E_4~0); 1889328#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1889327#L846-3 assume !(0 == ~E_6~0); 1889326#L851-3 assume !(0 == ~E_7~0); 1889325#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1889324#L388-27 assume 1 == ~m_pc~0; 1889322#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1889321#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1889320#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1889318#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1889317#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1889316#L407-27 assume !(1 == ~t1_pc~0); 1889315#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1889314#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1889313#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1889312#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 1889311#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1889310#L426-27 assume 1 == ~t2_pc~0; 1889308#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1889306#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1889304#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1889301#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1889298#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1887787#L445-27 assume !(1 == ~t3_pc~0); 1887784#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1887780#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1887778#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1887776#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 1887362#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1887345#L464-27 assume !(1 == ~t4_pc~0); 1887337#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1887330#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1887320#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1887313#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 1887305#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1886011#L483-27 assume !(1 == ~t5_pc~0); 1886009#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1886007#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1886005#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1886003#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 1886001#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1885994#L502-27 assume !(1 == ~t6_pc~0); 1885992#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1885989#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1885987#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1885983#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1885981#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1885979#L521-27 assume 1 == ~t7_pc~0; 1885977#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1885978#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1886279#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1886199#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1886197#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1885861#L869-3 assume !(1 == ~M_E~0); 1885857#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1885855#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1885853#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1885850#L884-3 assume !(1 == ~T4_E~0); 1885848#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1885846#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1885844#L899-3 assume !(1 == ~T7_E~0); 1885842#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1885840#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1885838#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1885837#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1885835#L924-3 assume !(1 == ~E_4~0); 1885833#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1885831#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1885829#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1885824#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1885821#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1885819#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1885817#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1885767#L1209 assume !(0 == start_simulation_~tmp~3#1); 1885766#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1885763#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1885761#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1885759#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1885757#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1885756#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1885755#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1885751#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1872493#L1190-2 [2021-12-15 17:21:06,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,797 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 10 times [2021-12-15 17:21:06,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848527723] [2021-12-15 17:21:06,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,798 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:06,806 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:06,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:06,823 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:06,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,824 INFO L85 PathProgramCache]: Analyzing trace with hash 715839675, now seen corresponding path program 1 times [2021-12-15 17:21:06,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,824 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382591637] [2021-12-15 17:21:06,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:06,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:06,857 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:06,857 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382591637] [2021-12-15 17:21:06,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382591637] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:06,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:06,858 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:06,858 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425586296] [2021-12-15 17:21:06,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:06,858 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:06,858 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:06,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:06,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:06,859 INFO L87 Difference]: Start difference. First operand 69613 states and 92156 transitions. cyclomatic complexity: 22545 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:07,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:07,283 INFO L93 Difference]: Finished difference Result 116661 states and 154835 transitions. [2021-12-15 17:21:07,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:07,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 116661 states and 154835 transitions. [2021-12-15 17:21:07,841 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 116408 [2021-12-15 17:21:08,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 116661 states to 116661 states and 154835 transitions. [2021-12-15 17:21:08,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116661 [2021-12-15 17:21:08,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116661 [2021-12-15 17:21:08,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116661 states and 154835 transitions. [2021-12-15 17:21:08,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:08,705 INFO L681 BuchiCegarLoop]: Abstraction has 116661 states and 154835 transitions. [2021-12-15 17:21:08,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116661 states and 154835 transitions. [2021-12-15 17:21:09,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116661 to 70909. [2021-12-15 17:21:09,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70909 states, 70909 states have (on average 1.312259374691506) internal successors, (93051), 70908 states have internal predecessors, (93051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:09,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70909 states to 70909 states and 93051 transitions. [2021-12-15 17:21:09,613 INFO L704 BuchiCegarLoop]: Abstraction has 70909 states and 93051 transitions. [2021-12-15 17:21:09,613 INFO L587 BuchiCegarLoop]: Abstraction has 70909 states and 93051 transitions. [2021-12-15 17:21:09,614 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-15 17:21:09,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70909 states and 93051 transitions. [2021-12-15 17:21:09,840 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 70720 [2021-12-15 17:21:09,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:09,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:09,844 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:09,844 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:09,845 INFO L791 eck$LassoCheckResult]: Stem: 2058637#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2058638#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2058038#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2058039#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2058911#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2058345#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2058346#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2058471#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2058472#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2058253#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2058034#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2058035#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2058207#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2058208#L781 assume !(0 == ~M_E~0); 2058734#L781-2 assume !(0 == ~T1_E~0); 2058988#L786-1 assume !(0 == ~T2_E~0); 2057996#L791-1 assume !(0 == ~T3_E~0); 2057997#L796-1 assume !(0 == ~T4_E~0); 2058559#L801-1 assume !(0 == ~T5_E~0); 2058560#L806-1 assume !(0 == ~T6_E~0); 2058595#L811-1 assume !(0 == ~T7_E~0); 2058215#L816-1 assume !(0 == ~E_M~0); 2058216#L821-1 assume !(0 == ~E_1~0); 2058024#L826-1 assume !(0 == ~E_2~0); 2058025#L831-1 assume !(0 == ~E_3~0); 2058342#L836-1 assume !(0 == ~E_4~0); 2058343#L841-1 assume !(0 == ~E_5~0); 2058169#L846-1 assume !(0 == ~E_6~0); 2058170#L851-1 assume !(0 == ~E_7~0); 2058191#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2058192#L388 assume !(1 == ~m_pc~0); 2058185#L388-2 is_master_triggered_~__retres1~0#1 := 0; 2058186#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2059010#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2058042#L967 assume !(0 != activate_threads_~tmp~1#1); 2058043#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2057973#L407 assume !(1 == ~t1_pc~0); 2057974#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2057977#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2057952#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2057953#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2058846#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2058302#L426 assume !(1 == ~t2_pc~0); 2058303#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2058879#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2058996#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2058947#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2058948#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2058387#L445 assume !(1 == ~t3_pc~0); 2058388#L445-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2058742#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2058187#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2058188#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2058658#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2058621#L464 assume !(1 == ~t4_pc~0); 2058194#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2058063#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2058064#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2058397#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2058362#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2058363#L483 assume !(1 == ~t5_pc~0); 2058619#L483-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2058819#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2058533#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2058534#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2058286#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2058287#L502 assume !(1 == ~t6_pc~0); 2058143#L502-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2058092#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2058093#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2058514#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2058515#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2058780#L521 assume !(1 == ~t7_pc~0); 2058842#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2058881#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2059016#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2058836#L1023 assume !(0 != activate_threads_~tmp___6~0#1); 2058791#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2058686#L869 assume !(1 == ~M_E~0); 2058355#L869-2 assume !(1 == ~T1_E~0); 2058356#L874-1 assume !(1 == ~T2_E~0); 2058899#L879-1 assume !(1 == ~T3_E~0); 2058900#L884-1 assume !(1 == ~T4_E~0); 2057961#L889-1 assume !(1 == ~T5_E~0); 2057962#L894-1 assume !(1 == ~T6_E~0); 2058999#L899-1 assume !(1 == ~T7_E~0); 2059000#L904-1 assume !(1 == ~E_M~0); 2059017#L909-1 assume !(1 == ~E_1~0); 2058577#L914-1 assume !(1 == ~E_2~0); 2058578#L919-1 assume !(1 == ~E_3~0); 2059014#L924-1 assume !(1 == ~E_4~0); 2059013#L929-1 assume !(1 == ~E_5~0); 2059012#L934-1 assume !(1 == ~E_6~0); 2059009#L939-1 assume !(1 == ~E_7~0); 2058359#L944-1 assume { :end_inline_reset_delta_events } true; 2058778#L1190-2 [2021-12-15 17:21:09,845 INFO L793 eck$LassoCheckResult]: Loop: 2058778#L1190-2 assume !false; 2093315#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2093314#L756 assume !false; 2093313#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2093311#L596 assume !(0 == ~m_st~0); 2093312#L600 assume !(0 == ~t1_st~0); 2093624#L604 assume !(0 == ~t2_st~0); 2093626#L608 assume !(0 == ~t3_st~0); 2093622#L612 assume !(0 == ~t4_st~0); 2093623#L616 assume !(0 == ~t5_st~0); 2093625#L620 assume !(0 == ~t6_st~0); 2093620#L624 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 2093621#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2093474#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2093475#L653 assume !(0 != eval_~tmp~0#1); 2103613#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2103610#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2103607#L781-3 assume !(0 == ~M_E~0); 2103604#L781-5 assume !(0 == ~T1_E~0); 2103601#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2103598#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2103595#L796-3 assume !(0 == ~T4_E~0); 2103592#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2103589#L806-3 assume !(0 == ~T6_E~0); 2103586#L811-3 assume !(0 == ~T7_E~0); 2103583#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2103580#L821-3 assume !(0 == ~E_1~0); 2103577#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2103574#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2103571#L836-3 assume !(0 == ~E_4~0); 2103568#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2103565#L846-3 assume !(0 == ~E_6~0); 2103562#L851-3 assume !(0 == ~E_7~0); 2103559#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2103556#L388-27 assume 1 == ~m_pc~0; 2103551#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2103548#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2103545#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2103540#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2103537#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2103534#L407-27 assume !(1 == ~t1_pc~0); 2103531#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2103528#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2103525#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2103522#L975-27 assume !(0 != activate_threads_~tmp___0~0#1); 2103519#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2103516#L426-27 assume 1 == ~t2_pc~0; 2103511#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2103505#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2103499#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2103493#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2103489#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2103485#L445-27 assume !(1 == ~t3_pc~0); 2103483#L445-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2103482#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2103480#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2103478#L991-27 assume !(0 != activate_threads_~tmp___2~0#1); 2103476#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2103474#L464-27 assume !(1 == ~t4_pc~0); 2103470#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2103468#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2103466#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2103464#L999-27 assume !(0 != activate_threads_~tmp___3~0#1); 2103462#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2103460#L483-27 assume !(1 == ~t5_pc~0); 2103457#L483-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2103456#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2103455#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2103454#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2103453#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2065658#L502-27 assume !(1 == ~t6_pc~0); 2065657#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2065656#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2065654#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2065652#L1015-27 assume !(0 != activate_threads_~tmp___5~0#1); 2065650#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2065648#L521-27 assume 1 == ~t7_pc~0; 2065646#L522-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2065647#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2065943#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2065860#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2065858#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2065855#L869-3 assume !(1 == ~M_E~0); 2065853#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2065851#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2065849#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2065847#L884-3 assume !(1 == ~T4_E~0); 2065845#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2065843#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2065841#L899-3 assume !(1 == ~T7_E~0); 2065839#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2065837#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2065835#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2065833#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2065831#L924-3 assume !(1 == ~E_4~0); 2065821#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2065813#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2065604#L939-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2065600#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2065597#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2065595#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2065594#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2065591#L1209 assume !(0 == start_simulation_~tmp~3#1); 2065592#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2093377#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2093376#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2093374#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2093372#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2093370#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2093368#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2093367#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 2058778#L1190-2 [2021-12-15 17:21:09,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:09,845 INFO L85 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 11 times [2021-12-15 17:21:09,845 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:09,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279354882] [2021-12-15 17:21:09,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:09,846 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:09,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:09,851 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:09,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:09,871 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:09,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:09,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1375371197, now seen corresponding path program 1 times [2021-12-15 17:21:09,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:09,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775205442] [2021-12-15 17:21:09,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:09,872 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:09,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:09,879 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:09,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:09,899 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:09,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:09,900 INFO L85 PathProgramCache]: Analyzing trace with hash -965324167, now seen corresponding path program 1 times [2021-12-15 17:21:09,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:09,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687410040] [2021-12-15 17:21:09,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:09,901 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:09,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:09,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:09,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:09,929 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687410040] [2021-12-15 17:21:09,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687410040] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:09,929 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:09,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:09,930 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113058486] [2021-12-15 17:21:09,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:12,013 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:21:12,017 INFO L158 Benchmark]: Toolchain (without parser) took 41556.57ms. Allocated memory was 115.3MB in the beginning and 14.4GB in the end (delta: 14.3GB). Free memory was 83.8MB in the beginning and 10.5GB in the end (delta: -10.4GB). Peak memory consumption was 4.5GB. Max. memory is 16.1GB. [2021-12-15 17:21:12,017 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 90.2MB. Free memory was 47.2MB in the beginning and 47.1MB in the end (delta: 42.1kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:21:12,017 INFO L158 Benchmark]: CACSL2BoogieTranslator took 315.43ms. Allocated memory is still 115.3MB. Free memory was 83.8MB in the beginning and 85.3MB in the end (delta: -1.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-15 17:21:12,018 INFO L158 Benchmark]: Boogie Procedure Inliner took 73.52ms. Allocated memory is still 115.3MB. Free memory was 85.3MB in the beginning and 78.7MB in the end (delta: 6.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-15 17:21:12,018 INFO L158 Benchmark]: Boogie Preprocessor took 80.93ms. Allocated memory is still 115.3MB. Free memory was 78.7MB in the beginning and 72.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-15 17:21:12,018 INFO L158 Benchmark]: RCFGBuilder took 1148.10ms. Allocated memory is still 115.3MB. Free memory was 72.4MB in the beginning and 54.3MB in the end (delta: 18.1MB). Peak memory consumption was 41.8MB. Max. memory is 16.1GB. [2021-12-15 17:21:12,018 INFO L158 Benchmark]: BuchiAutomizer took 39920.21ms. Allocated memory was 115.3MB in the beginning and 14.4GB in the end (delta: 14.3GB). Free memory was 53.8MB in the beginning and 10.5GB in the end (delta: -10.4GB). Peak memory consumption was 4.4GB. Max. memory is 16.1GB. [2021-12-15 17:21:12,019 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 90.2MB. Free memory was 47.2MB in the beginning and 47.1MB in the end (delta: 42.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 315.43ms. Allocated memory is still 115.3MB. Free memory was 83.8MB in the beginning and 85.3MB in the end (delta: -1.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 73.52ms. Allocated memory is still 115.3MB. Free memory was 85.3MB in the beginning and 78.7MB in the end (delta: 6.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 80.93ms. Allocated memory is still 115.3MB. Free memory was 78.7MB in the beginning and 72.4MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1148.10ms. Allocated memory is still 115.3MB. Free memory was 72.4MB in the beginning and 54.3MB in the end (delta: 18.1MB). Peak memory consumption was 41.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 39920.21ms. Allocated memory was 115.3MB in the beginning and 14.4GB in the end (delta: 14.3GB). Free memory was 53.8MB in the beginning and 10.5GB in the end (delta: -10.4GB). Peak memory consumption was 4.4GB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:21:12,043 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable