./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:30,519 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:30,544 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:30,585 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:30,586 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:30,589 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:30,590 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:30,593 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:30,595 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:30,598 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:30,599 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:30,600 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:30,601 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:30,603 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:30,605 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:30,609 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:30,611 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:30,612 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:30,614 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:30,616 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:30,619 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:30,619 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:30,621 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:30,622 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:30,626 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:30,626 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:30,626 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:30,628 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:30,628 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:30,629 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:30,630 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:30,631 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:30,632 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:30,633 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:30,635 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:30,635 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:30,636 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:30,636 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:30,636 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:30,637 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:30,637 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:30,638 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:30,675 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:30,675 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:30,676 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:30,676 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:30,677 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:30,677 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:30,678 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:30,678 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:30,678 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:30,678 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:30,679 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:30,679 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:30,679 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:30,680 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:30,680 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:30,680 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:30,680 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:30,680 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:30,681 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:30,681 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:30,681 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:30,681 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:30,681 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:30,681 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:30,682 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:30,682 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:30,682 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:30,682 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:30,682 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:30,683 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:30,683 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:30,683 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:30,684 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:30,684 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2021-12-15 17:20:30,944 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:30,970 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:30,972 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:30,973 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:30,974 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:30,975 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2021-12-15 17:20:31,039 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b3fecd2f3/ff7c0883ed9c4d48bbab241b470afbed/FLAGb957e40dc [2021-12-15 17:20:31,461 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:31,461 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2021-12-15 17:20:31,478 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b3fecd2f3/ff7c0883ed9c4d48bbab241b470afbed/FLAGb957e40dc [2021-12-15 17:20:31,493 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b3fecd2f3/ff7c0883ed9c4d48bbab241b470afbed [2021-12-15 17:20:31,496 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:31,498 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:31,500 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:31,500 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:31,503 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:31,503 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:31,504 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2c86f3d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31, skipping insertion in model container [2021-12-15 17:20:31,504 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:31,510 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:31,553 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:31,690 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2021-12-15 17:20:31,766 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:31,775 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:31,784 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2021-12-15 17:20:31,858 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:31,873 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:31,874 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31 WrapperNode [2021-12-15 17:20:31,874 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:31,875 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:31,875 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:31,875 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:31,881 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:31,891 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:31,966 INFO L137 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 157, statements flattened = 2358 [2021-12-15 17:20:31,967 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:31,967 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:31,968 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:31,968 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:31,975 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:31,975 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:31,983 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:31,983 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:32,008 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:32,027 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:32,032 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:32,043 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:32,044 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:32,044 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:32,044 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:32,045 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (1/1) ... [2021-12-15 17:20:32,073 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:32,094 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:32,113 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:32,135 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:32,152 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:32,152 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:32,153 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:32,153 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:32,297 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:32,298 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:33,536 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:33,552 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:33,552 INFO L301 CfgBuilder]: Removed 11 assume(true) statements. [2021-12-15 17:20:33,555 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:33 BoogieIcfgContainer [2021-12-15 17:20:33,555 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:33,556 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:33,556 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:33,563 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:33,563 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:33,563 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:31" (1/3) ... [2021-12-15 17:20:33,564 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4dc02f35 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:33, skipping insertion in model container [2021-12-15 17:20:33,564 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:33,565 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:31" (2/3) ... [2021-12-15 17:20:33,565 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4dc02f35 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:33, skipping insertion in model container [2021-12-15 17:20:33,565 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:33,565 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:33" (3/3) ... [2021-12-15 17:20:33,566 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2021-12-15 17:20:33,608 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:33,609 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:33,609 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:33,609 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:33,609 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:33,609 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:33,610 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:33,610 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:33,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2021-12-15 17:20:33,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,710 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,713 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,713 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:33,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:33,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2021-12-15 17:20:33,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:33,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:33,741 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,741 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:33,756 INFO L791 eck$LassoCheckResult]: Stem: 479#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 910#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25#L1266true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41#L590true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 845#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 430#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 974#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 163#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 474#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 132#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 277#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 960#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 258#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 550#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 484#L854true assume !(0 == ~M_E~0); 319#L854-2true assume !(0 == ~T1_E~0); 616#L859-1true assume !(0 == ~T2_E~0); 69#L864-1true assume !(0 == ~T3_E~0); 125#L869-1true assume !(0 == ~T4_E~0); 858#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 792#L879-1true assume !(0 == ~T6_E~0); 311#L884-1true assume !(0 == ~T7_E~0); 10#L889-1true assume !(0 == ~T8_E~0); 172#L894-1true assume !(0 == ~E_M~0); 970#L899-1true assume !(0 == ~E_1~0); 489#L904-1true assume !(0 == ~E_2~0); 268#L909-1true assume !(0 == ~E_3~0); 421#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 444#L919-1true assume !(0 == ~E_5~0); 218#L924-1true assume !(0 == ~E_6~0); 117#L929-1true assume !(0 == ~E_7~0); 812#L934-1true assume !(0 == ~E_8~0); 256#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19#L418true assume !(1 == ~m_pc~0); 893#L418-2true is_master_triggered_~__retres1~0#1 := 0; 692#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 898#L430true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 601#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 511#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 875#L437true assume 1 == ~t1_pc~0; 963#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 609#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 554#L449true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 191#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 803#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593#L456true assume !(1 == ~t2_pc~0); 419#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 864#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 364#L468true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 636#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 345#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67#L475true assume 1 == ~t3_pc~0; 290#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897#L487true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 773#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 193#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 688#L494true assume !(1 == ~t4_pc~0); 215#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 401#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 358#L506true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 944#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 441#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93#L513true assume 1 == ~t5_pc~0; 567#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 904#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241#L525true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 881#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53#L532true assume !(1 == ~t6_pc~0); 393#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 293#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 354#L544true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 829#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 176#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 641#L551true assume 1 == ~t7_pc~0; 650#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 447#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 669#L563true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 998#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 935#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 284#L570true assume 1 == ~t8_pc~0; 365#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 729#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 491#L582true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 361#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 64#L1125-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 613#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 42#L952-2true assume !(1 == ~T1_E~0); 577#L957-1true assume !(1 == ~T2_E~0); 885#L962-1true assume !(1 == ~T3_E~0); 376#L967-1true assume !(1 == ~T4_E~0); 847#L972-1true assume !(1 == ~T5_E~0); 642#L977-1true assume !(1 == ~T6_E~0); 941#L982-1true assume !(1 == ~T7_E~0); 128#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 133#L992-1true assume !(1 == ~E_M~0); 343#L997-1true assume !(1 == ~E_1~0); 797#L1002-1true assume !(1 == ~E_2~0); 334#L1007-1true assume !(1 == ~E_3~0); 11#L1012-1true assume !(1 == ~E_4~0); 547#L1017-1true assume !(1 == ~E_5~0); 336#L1022-1true assume !(1 == ~E_6~0); 355#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 800#L1032-1true assume !(1 == ~E_8~0); 468#L1037-1true assume { :end_inline_reset_delta_events } true; 569#L1303-2true [2021-12-15 17:20:33,767 INFO L793 eck$LassoCheckResult]: Loop: 569#L1303-2true assume !false; 602#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 890#L829true assume !true; 563#L844true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28#L590-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 455#L854-3true assume 0 == ~M_E~0;~M_E~0 := 1; 436#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 955#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 917#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 785#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 294#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 344#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 375#L884-3true assume !(0 == ~T7_E~0); 330#L889-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 112#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 480#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 130#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 309#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 99#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 123#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 707#L924-3true assume !(0 == ~E_6~0); 517#L929-3true assume 0 == ~E_7~0;~E_7~0 := 1; 422#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 644#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 552#L418-30true assume !(1 == ~m_pc~0); 370#L418-32true is_master_triggered_~__retres1~0#1 := 0; 564#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 304#L430-10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 817#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 217#L437-30true assume 1 == ~t1_pc~0; 458#L438-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 360#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 535#L449-10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 901#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 865#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 196#L456-30true assume !(1 == ~t2_pc~0); 884#L456-32true is_transmit2_triggered_~__retres1~2#1 := 0; 506#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 874#L468-10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 87#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 278#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743#L475-30true assume !(1 == ~t3_pc~0); 33#L475-32true is_transmit3_triggered_~__retres1~3#1 := 0; 435#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 796#L487-10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 888#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 207#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 989#L494-30true assume !(1 == ~t4_pc~0); 101#L494-32true is_transmit4_triggered_~__retres1~4#1 := 0; 4#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 716#L506-10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 909#L1093-30true assume !(0 != activate_threads_~tmp___3~0#1); 673#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 947#L513-30true assume !(1 == ~t5_pc~0); 281#L513-32true is_transmit5_triggered_~__retres1~5#1 := 0; 327#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 872#L525-10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 532#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 772#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 287#L532-30true assume 1 == ~t6_pc~0; 948#L533-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75#L544-10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 605#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 106#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135#L551-30true assume !(1 == ~t7_pc~0); 685#L551-32true is_transmit7_triggered_~__retres1~7#1 := 0; 620#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98#L563-10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12#L1117-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 194#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 736#L570-30true assume 1 == ~t8_pc~0; 611#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 134#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108#L582-10true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 232#L1125-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 949#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 732#L957-3true assume !(1 == ~T2_E~0); 745#L962-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 592#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 776#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 488#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 985#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 965#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 224#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 350#L997-3true assume !(1 == ~E_1~0); 222#L1002-3true assume 1 == ~E_2~0;~E_2~0 := 2; 445#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 119#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 171#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 310#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 335#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 27#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 416#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 141#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 744#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 91#L698-1true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 809#L1322true assume !(0 == start_simulation_~tmp~3#1); 244#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 62#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 733#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 852#L698-2true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 20#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 490#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 786#L1285true start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 647#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 569#L1303-2true [2021-12-15 17:20:33,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:33,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2021-12-15 17:20:33,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:33,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329345063] [2021-12-15 17:20:33,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:33,798 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:33,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:33,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:33,996 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:33,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329345063] [2021-12-15 17:20:33,997 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1329345063] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:33,997 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:33,998 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:33,999 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829023468] [2021-12-15 17:20:34,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,003 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:34,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,004 INFO L85 PathProgramCache]: Analyzing trace with hash -1450389818, now seen corresponding path program 1 times [2021-12-15 17:20:34,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121082040] [2021-12-15 17:20:34,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121082040] [2021-12-15 17:20:34,066 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121082040] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,066 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,066 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:34,067 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190898171] [2021-12-15 17:20:34,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,068 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,069 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:34,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:34,105 INFO L87 Difference]: Start difference. First operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,194 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2021-12-15 17:20:34,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:34,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2021-12-15 17:20:34,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:34,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 993 states and 1481 transitions. [2021-12-15 17:20:34,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:34,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:34,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1481 transitions. [2021-12-15 17:20:34,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,240 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2021-12-15 17:20:34,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1481 transitions. [2021-12-15 17:20:34,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:34,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1481 transitions. [2021-12-15 17:20:34,306 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2021-12-15 17:20:34,307 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2021-12-15 17:20:34,307 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:34,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1481 transitions. [2021-12-15 17:20:34,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:34,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,316 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,317 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,317 INFO L791 eck$LassoCheckResult]: Stem: 2766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2053#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2054#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2091#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2717#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2718#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2339#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2340#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2280#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2281#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2524#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2497#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2498#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2770#L854 assume !(0 == ~M_E~0); 2584#L854-2 assume !(0 == ~T1_E~0); 2585#L859-1 assume !(0 == ~T2_E~0); 2155#L864-1 assume !(0 == ~T3_E~0); 2156#L869-1 assume !(0 == ~T4_E~0); 2269#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2969#L879-1 assume !(0 == ~T6_E~0); 2572#L884-1 assume !(0 == ~T7_E~0); 2023#L889-1 assume !(0 == ~T8_E~0); 2024#L894-1 assume !(0 == ~E_M~0); 2354#L899-1 assume !(0 == ~E_1~0); 2777#L904-1 assume !(0 == ~E_2~0); 2513#L909-1 assume !(0 == ~E_3~0); 2514#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2708#L919-1 assume !(0 == ~E_5~0); 2434#L924-1 assume !(0 == ~E_6~0); 2252#L929-1 assume !(0 == ~E_7~0); 2253#L934-1 assume !(0 == ~E_8~0); 2494#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2041#L418 assume !(1 == ~m_pc~0); 2013#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2012#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2928#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2877#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2802#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2803#L437 assume 1 == ~t1_pc~0; 2986#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2885#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2838#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2389#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2390#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2868#L456 assume !(1 == ~t2_pc~0); 2305#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2304#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2643#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2644#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2619#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2149#L475 assume 1 == ~t3_pc~0; 2150#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2210#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2211#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2964#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2393#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2394#L494 assume !(1 == ~t4_pc~0); 2429#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2430#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2634#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2635#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2731#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2205#L513 assume 1 == ~t5_pc~0; 2206#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2431#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2468#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2166#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2167#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2118#L532 assume !(1 == ~t6_pc~0); 2119#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2270#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2549#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2628#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2359#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2360#L551 assume 1 == ~t7_pc~0; 2906#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2735#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2736#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2917#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2995#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2533#L570 assume 1 == ~t8_pc~0; 2534#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2645#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2779#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2639#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2143#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2144#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2092#L952-2 assume !(1 == ~T1_E~0); 2093#L957-1 assume !(1 == ~T2_E~0); 2850#L962-1 assume !(1 == ~T3_E~0); 2655#L967-1 assume !(1 == ~T4_E~0); 2656#L972-1 assume !(1 == ~T5_E~0); 2907#L977-1 assume !(1 == ~T6_E~0); 2908#L982-1 assume !(1 == ~T7_E~0); 2272#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2273#L992-1 assume !(1 == ~E_M~0); 2282#L997-1 assume !(1 == ~E_1~0); 2617#L1002-1 assume !(1 == ~E_2~0); 2605#L1007-1 assume !(1 == ~E_3~0); 2025#L1012-1 assume !(1 == ~E_4~0); 2026#L1017-1 assume !(1 == ~E_5~0); 2606#L1022-1 assume !(1 == ~E_6~0); 2607#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2629#L1032-1 assume !(1 == ~E_8~0); 2754#L1037-1 assume { :end_inline_reset_delta_events } true; 2755#L1303-2 [2021-12-15 17:20:34,318 INFO L793 eck$LassoCheckResult]: Loop: 2755#L1303-2 assume !false; 2845#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2036#L829 assume !false; 2799#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2414#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2342#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2745#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2723#L712 assume !(0 != eval_~tmp~0#1); 2724#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2060#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2061#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2726#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2727#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2993#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2967#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2550#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2551#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2618#L884-3 assume !(0 == ~T7_E~0); 2599#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2243#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2244#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2276#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2277#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2217#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2218#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2265#L924-3 assume !(0 == ~E_6~0); 2807#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2709#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2710#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2836#L418-30 assume 1 == ~m_pc~0; 2107#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2108#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2562#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2563#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2306#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2307#L437-30 assume !(1 == ~t1_pc~0); 2432#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2637#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2638#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2825#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2984#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2398#L456-30 assume !(1 == ~t2_pc~0); 2400#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2796#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2797#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2191#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2192#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2525#L475-30 assume 1 == ~t3_pc~0; 2900#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2074#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2725#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2970#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2416#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2417#L494-30 assume 1 == ~t4_pc~0; 2410#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2009#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2010#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2941#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2920#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2921#L513-30 assume !(1 == ~t5_pc~0); 2530#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2531#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2595#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2821#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2822#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2541#L532-30 assume !(1 == ~t6_pc~0); 2542#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2147#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2148#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2169#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2231#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2232#L551-30 assume 1 == ~t7_pc~0; 2284#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2344#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2216#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2027#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2028#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2395#L570-30 assume 1 == ~t8_pc~0; 2886#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2283#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2235#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2089#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2090#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2456#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2491#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2948#L957-3 assume !(1 == ~T2_E~0); 2949#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2866#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2867#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2775#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2776#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2998#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2444#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2445#L997-3 assume !(1 == ~E_1~0); 2440#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2441#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2256#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2257#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2353#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2571#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2058#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2059#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2296#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2297#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2201#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2202#L1322 assume !(0 == start_simulation_~tmp~3#1); 2470#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2137#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2138#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2950#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2042#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2043#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2778#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2910#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2755#L1303-2 [2021-12-15 17:20:34,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,320 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2021-12-15 17:20:34,320 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [576783184] [2021-12-15 17:20:34,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,321 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,412 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [576783184] [2021-12-15 17:20:34,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [576783184] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,413 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,413 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467185450] [2021-12-15 17:20:34,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,414 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:34,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,415 INFO L85 PathProgramCache]: Analyzing trace with hash -500294447, now seen corresponding path program 1 times [2021-12-15 17:20:34,415 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294993720] [2021-12-15 17:20:34,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,416 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,542 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,542 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294993720] [2021-12-15 17:20:34,543 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294993720] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,543 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,544 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,544 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888349377] [2021-12-15 17:20:34,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,545 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,546 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:34,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:34,547 INFO L87 Difference]: Start difference. First operand 993 states and 1481 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,569 INFO L93 Difference]: Finished difference Result 993 states and 1480 transitions. [2021-12-15 17:20:34,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:34,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1480 transitions. [2021-12-15 17:20:34,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:34,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1480 transitions. [2021-12-15 17:20:34,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:34,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:34,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1480 transitions. [2021-12-15 17:20:34,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,586 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2021-12-15 17:20:34,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1480 transitions. [2021-12-15 17:20:34,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:34,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1480 transitions. [2021-12-15 17:20:34,611 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2021-12-15 17:20:34,611 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2021-12-15 17:20:34,611 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:34,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1480 transitions. [2021-12-15 17:20:34,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:34,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,620 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,620 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,621 INFO L791 eck$LassoCheckResult]: Stem: 4759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4046#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4047#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4084#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4710#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4711#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4332#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4333#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4273#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4274#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4517#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4490#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4491#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4763#L854 assume !(0 == ~M_E~0); 4577#L854-2 assume !(0 == ~T1_E~0); 4578#L859-1 assume !(0 == ~T2_E~0); 4148#L864-1 assume !(0 == ~T3_E~0); 4149#L869-1 assume !(0 == ~T4_E~0); 4262#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4962#L879-1 assume !(0 == ~T6_E~0); 4565#L884-1 assume !(0 == ~T7_E~0); 4016#L889-1 assume !(0 == ~T8_E~0); 4017#L894-1 assume !(0 == ~E_M~0); 4347#L899-1 assume !(0 == ~E_1~0); 4770#L904-1 assume !(0 == ~E_2~0); 4506#L909-1 assume !(0 == ~E_3~0); 4507#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4701#L919-1 assume !(0 == ~E_5~0); 4427#L924-1 assume !(0 == ~E_6~0); 4245#L929-1 assume !(0 == ~E_7~0); 4246#L934-1 assume !(0 == ~E_8~0); 4487#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4034#L418 assume !(1 == ~m_pc~0); 4006#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4005#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4921#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4870#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4795#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4796#L437 assume 1 == ~t1_pc~0; 4979#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4878#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4831#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4382#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4383#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4861#L456 assume !(1 == ~t2_pc~0); 4298#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4297#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4636#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4637#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4612#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4142#L475 assume 1 == ~t3_pc~0; 4143#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4203#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4204#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4957#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4386#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4387#L494 assume !(1 == ~t4_pc~0); 4422#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4423#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4627#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4628#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4724#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4198#L513 assume 1 == ~t5_pc~0; 4199#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4424#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4461#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4159#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4160#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4111#L532 assume !(1 == ~t6_pc~0); 4112#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4263#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4542#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4621#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4352#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4353#L551 assume 1 == ~t7_pc~0; 4899#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4728#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4729#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4910#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 4988#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4526#L570 assume 1 == ~t8_pc~0; 4527#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4638#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4772#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4632#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4136#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4137#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 4085#L952-2 assume !(1 == ~T1_E~0); 4086#L957-1 assume !(1 == ~T2_E~0); 4843#L962-1 assume !(1 == ~T3_E~0); 4648#L967-1 assume !(1 == ~T4_E~0); 4649#L972-1 assume !(1 == ~T5_E~0); 4900#L977-1 assume !(1 == ~T6_E~0); 4901#L982-1 assume !(1 == ~T7_E~0); 4265#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4266#L992-1 assume !(1 == ~E_M~0); 4275#L997-1 assume !(1 == ~E_1~0); 4610#L1002-1 assume !(1 == ~E_2~0); 4598#L1007-1 assume !(1 == ~E_3~0); 4018#L1012-1 assume !(1 == ~E_4~0); 4019#L1017-1 assume !(1 == ~E_5~0); 4599#L1022-1 assume !(1 == ~E_6~0); 4600#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4622#L1032-1 assume !(1 == ~E_8~0); 4747#L1037-1 assume { :end_inline_reset_delta_events } true; 4748#L1303-2 [2021-12-15 17:20:34,622 INFO L793 eck$LassoCheckResult]: Loop: 4748#L1303-2 assume !false; 4838#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4029#L829 assume !false; 4792#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4407#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4335#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4738#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4716#L712 assume !(0 != eval_~tmp~0#1); 4717#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4053#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4054#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4719#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4720#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4986#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4960#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4543#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4544#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4611#L884-3 assume !(0 == ~T7_E~0); 4592#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4236#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4237#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4269#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4270#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4210#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4211#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4258#L924-3 assume !(0 == ~E_6~0); 4800#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4702#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4703#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4829#L418-30 assume 1 == ~m_pc~0; 4100#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4101#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4555#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4556#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4299#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4300#L437-30 assume !(1 == ~t1_pc~0); 4425#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4630#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4631#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4818#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4977#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4391#L456-30 assume 1 == ~t2_pc~0; 4392#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4789#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4790#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4184#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4185#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4518#L475-30 assume !(1 == ~t3_pc~0); 4066#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4067#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4718#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4963#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4409#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4410#L494-30 assume 1 == ~t4_pc~0; 4403#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4002#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4003#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4934#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 4913#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4914#L513-30 assume !(1 == ~t5_pc~0); 4523#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4524#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4588#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4814#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4815#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4534#L532-30 assume !(1 == ~t6_pc~0); 4535#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4140#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4141#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4162#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4224#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4225#L551-30 assume 1 == ~t7_pc~0; 4277#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4337#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4209#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4020#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4021#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4388#L570-30 assume !(1 == ~t8_pc~0); 4709#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4276#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4228#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4082#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4083#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4449#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4484#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4941#L957-3 assume !(1 == ~T2_E~0); 4942#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4859#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4860#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4768#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4769#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4991#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4437#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4438#L997-3 assume !(1 == ~E_1~0); 4433#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4434#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4249#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4250#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4346#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4564#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4051#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4052#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4289#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4290#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4194#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4195#L1322 assume !(0 == start_simulation_~tmp~3#1); 4463#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4130#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4131#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4943#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4035#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4036#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4771#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4903#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4748#L1303-2 [2021-12-15 17:20:34,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,626 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2021-12-15 17:20:34,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417716580] [2021-12-15 17:20:34,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,627 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,688 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417716580] [2021-12-15 17:20:34,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417716580] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,688 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,688 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,689 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825742580] [2021-12-15 17:20:34,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,689 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:34,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,690 INFO L85 PathProgramCache]: Analyzing trace with hash 630471762, now seen corresponding path program 1 times [2021-12-15 17:20:34,690 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805517533] [2021-12-15 17:20:34,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,691 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805517533] [2021-12-15 17:20:34,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805517533] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,771 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,771 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,771 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182937087] [2021-12-15 17:20:34,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,771 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,772 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:34,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:34,772 INFO L87 Difference]: Start difference. First operand 993 states and 1480 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,791 INFO L93 Difference]: Finished difference Result 993 states and 1479 transitions. [2021-12-15 17:20:34,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:34,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1479 transitions. [2021-12-15 17:20:34,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:34,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1479 transitions. [2021-12-15 17:20:34,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:34,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:34,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1479 transitions. [2021-12-15 17:20:34,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,805 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2021-12-15 17:20:34,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1479 transitions. [2021-12-15 17:20:34,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:34,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1479 transitions. [2021-12-15 17:20:34,820 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2021-12-15 17:20:34,820 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2021-12-15 17:20:34,821 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:34,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1479 transitions. [2021-12-15 17:20:34,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:34,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:34,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:34,828 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:34,829 INFO L791 eck$LassoCheckResult]: Stem: 6752#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6039#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6040#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6077#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6703#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6704#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6325#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6326#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6266#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6267#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6510#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6483#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6484#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6756#L854 assume !(0 == ~M_E~0); 6570#L854-2 assume !(0 == ~T1_E~0); 6571#L859-1 assume !(0 == ~T2_E~0); 6141#L864-1 assume !(0 == ~T3_E~0); 6142#L869-1 assume !(0 == ~T4_E~0); 6255#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6955#L879-1 assume !(0 == ~T6_E~0); 6558#L884-1 assume !(0 == ~T7_E~0); 6009#L889-1 assume !(0 == ~T8_E~0); 6010#L894-1 assume !(0 == ~E_M~0); 6340#L899-1 assume !(0 == ~E_1~0); 6763#L904-1 assume !(0 == ~E_2~0); 6499#L909-1 assume !(0 == ~E_3~0); 6500#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6694#L919-1 assume !(0 == ~E_5~0); 6420#L924-1 assume !(0 == ~E_6~0); 6238#L929-1 assume !(0 == ~E_7~0); 6239#L934-1 assume !(0 == ~E_8~0); 6480#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6027#L418 assume !(1 == ~m_pc~0); 5999#L418-2 is_master_triggered_~__retres1~0#1 := 0; 5998#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6914#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6863#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6788#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6789#L437 assume 1 == ~t1_pc~0; 6972#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6871#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6824#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6375#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6376#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6854#L456 assume !(1 == ~t2_pc~0); 6291#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6290#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6629#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6630#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6605#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6135#L475 assume 1 == ~t3_pc~0; 6136#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6196#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6197#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6950#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6379#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6380#L494 assume !(1 == ~t4_pc~0); 6415#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6416#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6620#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6621#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6717#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6191#L513 assume 1 == ~t5_pc~0; 6192#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6417#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6454#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6152#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6153#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6104#L532 assume !(1 == ~t6_pc~0); 6105#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6256#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6535#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6614#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6345#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6346#L551 assume 1 == ~t7_pc~0; 6892#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6721#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6722#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6903#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 6981#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6519#L570 assume 1 == ~t8_pc~0; 6520#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6631#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6765#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6625#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6129#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6130#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6078#L952-2 assume !(1 == ~T1_E~0); 6079#L957-1 assume !(1 == ~T2_E~0); 6836#L962-1 assume !(1 == ~T3_E~0); 6641#L967-1 assume !(1 == ~T4_E~0); 6642#L972-1 assume !(1 == ~T5_E~0); 6893#L977-1 assume !(1 == ~T6_E~0); 6894#L982-1 assume !(1 == ~T7_E~0); 6258#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6259#L992-1 assume !(1 == ~E_M~0); 6268#L997-1 assume !(1 == ~E_1~0); 6603#L1002-1 assume !(1 == ~E_2~0); 6591#L1007-1 assume !(1 == ~E_3~0); 6011#L1012-1 assume !(1 == ~E_4~0); 6012#L1017-1 assume !(1 == ~E_5~0); 6592#L1022-1 assume !(1 == ~E_6~0); 6593#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6615#L1032-1 assume !(1 == ~E_8~0); 6740#L1037-1 assume { :end_inline_reset_delta_events } true; 6741#L1303-2 [2021-12-15 17:20:34,829 INFO L793 eck$LassoCheckResult]: Loop: 6741#L1303-2 assume !false; 6831#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6022#L829 assume !false; 6785#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6400#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6328#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6731#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6709#L712 assume !(0 != eval_~tmp~0#1); 6710#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6046#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6047#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6712#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6713#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6979#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6953#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6536#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6537#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6604#L884-3 assume !(0 == ~T7_E~0); 6585#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6229#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6230#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6262#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6263#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6203#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6204#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6251#L924-3 assume !(0 == ~E_6~0); 6793#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6695#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6696#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6822#L418-30 assume 1 == ~m_pc~0; 6093#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6094#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6548#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6549#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6292#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6293#L437-30 assume !(1 == ~t1_pc~0); 6418#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6623#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6624#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6811#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6970#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6384#L456-30 assume 1 == ~t2_pc~0; 6385#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6782#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6783#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6177#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6178#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6511#L475-30 assume 1 == ~t3_pc~0; 6886#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6060#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6711#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6956#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6402#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6403#L494-30 assume !(1 == ~t4_pc~0); 6208#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 5995#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5996#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6927#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 6906#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6907#L513-30 assume !(1 == ~t5_pc~0); 6516#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 6517#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6581#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6807#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6808#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6527#L532-30 assume !(1 == ~t6_pc~0); 6528#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 6133#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6134#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6155#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6217#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6218#L551-30 assume 1 == ~t7_pc~0; 6270#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6330#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6202#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6013#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6014#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6381#L570-30 assume 1 == ~t8_pc~0; 6872#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6269#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6221#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6075#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6076#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6442#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6477#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6934#L957-3 assume !(1 == ~T2_E~0); 6935#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6852#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6853#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6761#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6762#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6984#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6430#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6431#L997-3 assume !(1 == ~E_1~0); 6426#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6427#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6242#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6243#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6339#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6557#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6044#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6045#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6282#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6283#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6187#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6188#L1322 assume !(0 == start_simulation_~tmp~3#1); 6456#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6123#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6124#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6936#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6028#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6029#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6764#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6896#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6741#L1303-2 [2021-12-15 17:20:34,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,830 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2021-12-15 17:20:34,831 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188970581] [2021-12-15 17:20:34,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,831 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188970581] [2021-12-15 17:20:34,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188970581] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,897 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871514093] [2021-12-15 17:20:34,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,898 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:34,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:34,899 INFO L85 PathProgramCache]: Analyzing trace with hash -1603750319, now seen corresponding path program 1 times [2021-12-15 17:20:34,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:34,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [859602654] [2021-12-15 17:20:34,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:34,901 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:34,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:34,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:34,951 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:34,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [859602654] [2021-12-15 17:20:34,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [859602654] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:34,951 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:34,955 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:34,955 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [60817607] [2021-12-15 17:20:34,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:34,956 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:34,956 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:34,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:34,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:34,957 INFO L87 Difference]: Start difference. First operand 993 states and 1479 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:34,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:34,979 INFO L93 Difference]: Finished difference Result 993 states and 1478 transitions. [2021-12-15 17:20:34,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:34,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1478 transitions. [2021-12-15 17:20:34,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:34,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1478 transitions. [2021-12-15 17:20:34,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:34,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:34,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1478 transitions. [2021-12-15 17:20:34,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:34,993 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2021-12-15 17:20:34,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1478 transitions. [2021-12-15 17:20:35,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:35,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1478 transitions. [2021-12-15 17:20:35,026 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2021-12-15 17:20:35,026 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2021-12-15 17:20:35,026 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:35,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1478 transitions. [2021-12-15 17:20:35,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,032 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,032 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,032 INFO L791 eck$LassoCheckResult]: Stem: 8745#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8032#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8033#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8070#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 8696#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8697#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8318#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8319#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8259#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8260#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8503#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8476#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8477#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8749#L854 assume !(0 == ~M_E~0); 8563#L854-2 assume !(0 == ~T1_E~0); 8564#L859-1 assume !(0 == ~T2_E~0); 8134#L864-1 assume !(0 == ~T3_E~0); 8135#L869-1 assume !(0 == ~T4_E~0); 8248#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8948#L879-1 assume !(0 == ~T6_E~0); 8551#L884-1 assume !(0 == ~T7_E~0); 8002#L889-1 assume !(0 == ~T8_E~0); 8003#L894-1 assume !(0 == ~E_M~0); 8333#L899-1 assume !(0 == ~E_1~0); 8756#L904-1 assume !(0 == ~E_2~0); 8492#L909-1 assume !(0 == ~E_3~0); 8493#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8687#L919-1 assume !(0 == ~E_5~0); 8413#L924-1 assume !(0 == ~E_6~0); 8231#L929-1 assume !(0 == ~E_7~0); 8232#L934-1 assume !(0 == ~E_8~0); 8473#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8020#L418 assume !(1 == ~m_pc~0); 7992#L418-2 is_master_triggered_~__retres1~0#1 := 0; 7991#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8907#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8856#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8781#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8782#L437 assume 1 == ~t1_pc~0; 8965#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8864#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8817#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8368#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 8369#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8847#L456 assume !(1 == ~t2_pc~0); 8284#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8283#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8622#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8623#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 8598#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8128#L475 assume 1 == ~t3_pc~0; 8129#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8189#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8190#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8943#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 8372#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8373#L494 assume !(1 == ~t4_pc~0); 8408#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8409#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8613#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8614#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 8710#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8184#L513 assume 1 == ~t5_pc~0; 8185#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8410#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8447#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8145#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 8146#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8097#L532 assume !(1 == ~t6_pc~0); 8098#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8249#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8528#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8607#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 8338#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8339#L551 assume 1 == ~t7_pc~0; 8885#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8714#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8715#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8896#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 8974#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8512#L570 assume 1 == ~t8_pc~0; 8513#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8624#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8758#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8618#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 8122#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8123#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 8071#L952-2 assume !(1 == ~T1_E~0); 8072#L957-1 assume !(1 == ~T2_E~0); 8829#L962-1 assume !(1 == ~T3_E~0); 8634#L967-1 assume !(1 == ~T4_E~0); 8635#L972-1 assume !(1 == ~T5_E~0); 8886#L977-1 assume !(1 == ~T6_E~0); 8887#L982-1 assume !(1 == ~T7_E~0); 8251#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8252#L992-1 assume !(1 == ~E_M~0); 8261#L997-1 assume !(1 == ~E_1~0); 8596#L1002-1 assume !(1 == ~E_2~0); 8584#L1007-1 assume !(1 == ~E_3~0); 8004#L1012-1 assume !(1 == ~E_4~0); 8005#L1017-1 assume !(1 == ~E_5~0); 8585#L1022-1 assume !(1 == ~E_6~0); 8586#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8608#L1032-1 assume !(1 == ~E_8~0); 8733#L1037-1 assume { :end_inline_reset_delta_events } true; 8734#L1303-2 [2021-12-15 17:20:35,033 INFO L793 eck$LassoCheckResult]: Loop: 8734#L1303-2 assume !false; 8824#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8015#L829 assume !false; 8778#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8393#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8321#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8724#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8702#L712 assume !(0 != eval_~tmp~0#1); 8703#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8039#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8040#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8705#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8706#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8972#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8946#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8529#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8530#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8597#L884-3 assume !(0 == ~T7_E~0); 8578#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8222#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8223#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8255#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8256#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8196#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8197#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8244#L924-3 assume !(0 == ~E_6~0); 8786#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8688#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8689#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8815#L418-30 assume 1 == ~m_pc~0; 8086#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8087#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8541#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8542#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8285#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8286#L437-30 assume !(1 == ~t1_pc~0); 8411#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 8616#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8617#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8804#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8963#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8377#L456-30 assume 1 == ~t2_pc~0; 8378#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8775#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8776#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8170#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8171#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8504#L475-30 assume !(1 == ~t3_pc~0); 8052#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 8053#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8704#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8949#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8395#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8396#L494-30 assume 1 == ~t4_pc~0; 8389#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7988#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7989#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8920#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 8899#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8900#L513-30 assume 1 == ~t5_pc~0; 8976#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8510#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8574#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8800#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8801#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8520#L532-30 assume !(1 == ~t6_pc~0); 8521#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 8126#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8127#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8148#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8210#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8211#L551-30 assume 1 == ~t7_pc~0; 8263#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8323#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8195#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8006#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8007#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8374#L570-30 assume 1 == ~t8_pc~0; 8865#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8262#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8214#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8068#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8069#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8435#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8470#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8927#L957-3 assume !(1 == ~T2_E~0); 8928#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8845#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8846#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8754#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8755#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8977#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8423#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8424#L997-3 assume !(1 == ~E_1~0); 8419#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8420#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8235#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8236#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8332#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8550#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8037#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8038#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8275#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8276#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8180#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8181#L1322 assume !(0 == start_simulation_~tmp~3#1); 8449#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8116#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8117#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8929#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 8021#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8022#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8757#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8889#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 8734#L1303-2 [2021-12-15 17:20:35,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,033 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2021-12-15 17:20:35,034 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641519182] [2021-12-15 17:20:35,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,034 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,070 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,070 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641519182] [2021-12-15 17:20:35,070 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641519182] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,071 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,071 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,071 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800018497] [2021-12-15 17:20:35,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,072 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,072 INFO L85 PathProgramCache]: Analyzing trace with hash 613340432, now seen corresponding path program 1 times [2021-12-15 17:20:35,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436803253] [2021-12-15 17:20:35,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,073 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,107 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436803253] [2021-12-15 17:20:35,108 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436803253] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,108 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,108 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,108 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253580960] [2021-12-15 17:20:35,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,109 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,109 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:35,110 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:35,110 INFO L87 Difference]: Start difference. First operand 993 states and 1478 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,128 INFO L93 Difference]: Finished difference Result 993 states and 1477 transitions. [2021-12-15 17:20:35,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:35,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1477 transitions. [2021-12-15 17:20:35,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1477 transitions. [2021-12-15 17:20:35,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:35,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:35,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1477 transitions. [2021-12-15 17:20:35,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,143 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2021-12-15 17:20:35,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1477 transitions. [2021-12-15 17:20:35,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:35,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1477 transitions. [2021-12-15 17:20:35,158 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2021-12-15 17:20:35,158 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2021-12-15 17:20:35,158 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:35,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1477 transitions. [2021-12-15 17:20:35,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,163 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,164 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,164 INFO L791 eck$LassoCheckResult]: Stem: 10738#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10025#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10026#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10063#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10689#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10690#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10311#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10312#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10252#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10253#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10496#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10469#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10470#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10742#L854 assume !(0 == ~M_E~0); 10556#L854-2 assume !(0 == ~T1_E~0); 10557#L859-1 assume !(0 == ~T2_E~0); 10127#L864-1 assume !(0 == ~T3_E~0); 10128#L869-1 assume !(0 == ~T4_E~0); 10241#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10941#L879-1 assume !(0 == ~T6_E~0); 10544#L884-1 assume !(0 == ~T7_E~0); 9995#L889-1 assume !(0 == ~T8_E~0); 9996#L894-1 assume !(0 == ~E_M~0); 10326#L899-1 assume !(0 == ~E_1~0); 10749#L904-1 assume !(0 == ~E_2~0); 10485#L909-1 assume !(0 == ~E_3~0); 10486#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10680#L919-1 assume !(0 == ~E_5~0); 10406#L924-1 assume !(0 == ~E_6~0); 10224#L929-1 assume !(0 == ~E_7~0); 10225#L934-1 assume !(0 == ~E_8~0); 10466#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10013#L418 assume !(1 == ~m_pc~0); 9985#L418-2 is_master_triggered_~__retres1~0#1 := 0; 9984#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10900#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10849#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10774#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10775#L437 assume 1 == ~t1_pc~0; 10958#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10857#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10810#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10361#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10362#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10840#L456 assume !(1 == ~t2_pc~0); 10277#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10276#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10615#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10616#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10591#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10121#L475 assume 1 == ~t3_pc~0; 10122#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10182#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10183#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10936#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10365#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10366#L494 assume !(1 == ~t4_pc~0); 10401#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10402#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10606#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10607#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10703#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10177#L513 assume 1 == ~t5_pc~0; 10178#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10403#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10440#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10138#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10139#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10090#L532 assume !(1 == ~t6_pc~0); 10091#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10242#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10521#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10600#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10331#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10332#L551 assume 1 == ~t7_pc~0; 10878#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10707#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10708#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10889#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 10967#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10505#L570 assume 1 == ~t8_pc~0; 10506#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10617#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10751#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10611#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10115#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10116#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10064#L952-2 assume !(1 == ~T1_E~0); 10065#L957-1 assume !(1 == ~T2_E~0); 10822#L962-1 assume !(1 == ~T3_E~0); 10627#L967-1 assume !(1 == ~T4_E~0); 10628#L972-1 assume !(1 == ~T5_E~0); 10879#L977-1 assume !(1 == ~T6_E~0); 10880#L982-1 assume !(1 == ~T7_E~0); 10244#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10245#L992-1 assume !(1 == ~E_M~0); 10254#L997-1 assume !(1 == ~E_1~0); 10589#L1002-1 assume !(1 == ~E_2~0); 10577#L1007-1 assume !(1 == ~E_3~0); 9997#L1012-1 assume !(1 == ~E_4~0); 9998#L1017-1 assume !(1 == ~E_5~0); 10578#L1022-1 assume !(1 == ~E_6~0); 10579#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10601#L1032-1 assume !(1 == ~E_8~0); 10726#L1037-1 assume { :end_inline_reset_delta_events } true; 10727#L1303-2 [2021-12-15 17:20:35,164 INFO L793 eck$LassoCheckResult]: Loop: 10727#L1303-2 assume !false; 10817#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10008#L829 assume !false; 10771#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10386#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10314#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10717#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10695#L712 assume !(0 != eval_~tmp~0#1); 10696#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10032#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10033#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10698#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10699#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10965#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10939#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10522#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10523#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10590#L884-3 assume !(0 == ~T7_E~0); 10571#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10215#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10216#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10248#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10249#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10189#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10190#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10237#L924-3 assume !(0 == ~E_6~0); 10779#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10681#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10682#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10808#L418-30 assume !(1 == ~m_pc~0); 10081#L418-32 is_master_triggered_~__retres1~0#1 := 0; 10080#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10534#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10535#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10278#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10279#L437-30 assume !(1 == ~t1_pc~0); 10404#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 10609#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10610#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10797#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10956#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10370#L456-30 assume 1 == ~t2_pc~0; 10371#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10768#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10769#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10163#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10164#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10497#L475-30 assume 1 == ~t3_pc~0; 10872#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10046#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10697#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10942#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10388#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10389#L494-30 assume !(1 == ~t4_pc~0); 10194#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9981#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9982#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10913#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 10892#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10893#L513-30 assume !(1 == ~t5_pc~0); 10502#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10503#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10567#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10793#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10794#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10513#L532-30 assume !(1 == ~t6_pc~0); 10514#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10119#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10120#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10141#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10203#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10204#L551-30 assume 1 == ~t7_pc~0; 10256#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10316#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10188#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9999#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10000#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10367#L570-30 assume !(1 == ~t8_pc~0); 10688#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 10255#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10207#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10061#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10062#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10428#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10463#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10920#L957-3 assume !(1 == ~T2_E~0); 10921#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10838#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10839#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10747#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10748#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10970#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10416#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10417#L997-3 assume !(1 == ~E_1~0); 10412#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10413#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10228#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10229#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10325#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10543#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10030#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10031#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10268#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10269#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10173#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10174#L1322 assume !(0 == start_simulation_~tmp~3#1); 10442#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10109#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10110#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10922#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10014#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10015#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10750#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10882#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10727#L1303-2 [2021-12-15 17:20:35,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2021-12-15 17:20:35,169 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472280158] [2021-12-15 17:20:35,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,170 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,195 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472280158] [2021-12-15 17:20:35,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472280158] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,195 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,196 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154811596] [2021-12-15 17:20:35,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,196 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,198 INFO L85 PathProgramCache]: Analyzing trace with hash -1695676973, now seen corresponding path program 1 times [2021-12-15 17:20:35,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950470480] [2021-12-15 17:20:35,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,244 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950470480] [2021-12-15 17:20:35,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950470480] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926531363] [2021-12-15 17:20:35,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,247 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,247 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:35,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:35,248 INFO L87 Difference]: Start difference. First operand 993 states and 1477 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,265 INFO L93 Difference]: Finished difference Result 993 states and 1476 transitions. [2021-12-15 17:20:35,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:35,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1476 transitions. [2021-12-15 17:20:35,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1476 transitions. [2021-12-15 17:20:35,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:35,276 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:35,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1476 transitions. [2021-12-15 17:20:35,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,278 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2021-12-15 17:20:35,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1476 transitions. [2021-12-15 17:20:35,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:35,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1476 transitions. [2021-12-15 17:20:35,293 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2021-12-15 17:20:35,293 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2021-12-15 17:20:35,293 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:35,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1476 transitions. [2021-12-15 17:20:35,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,298 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,298 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,299 INFO L791 eck$LassoCheckResult]: Stem: 12731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12732#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12018#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12019#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12056#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 12682#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12683#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12304#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12305#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12245#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12246#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12489#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12462#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12463#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12735#L854 assume !(0 == ~M_E~0); 12549#L854-2 assume !(0 == ~T1_E~0); 12550#L859-1 assume !(0 == ~T2_E~0); 12120#L864-1 assume !(0 == ~T3_E~0); 12121#L869-1 assume !(0 == ~T4_E~0); 12234#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12934#L879-1 assume !(0 == ~T6_E~0); 12537#L884-1 assume !(0 == ~T7_E~0); 11988#L889-1 assume !(0 == ~T8_E~0); 11989#L894-1 assume !(0 == ~E_M~0); 12319#L899-1 assume !(0 == ~E_1~0); 12742#L904-1 assume !(0 == ~E_2~0); 12478#L909-1 assume !(0 == ~E_3~0); 12479#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12673#L919-1 assume !(0 == ~E_5~0); 12399#L924-1 assume !(0 == ~E_6~0); 12217#L929-1 assume !(0 == ~E_7~0); 12218#L934-1 assume !(0 == ~E_8~0); 12459#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12006#L418 assume !(1 == ~m_pc~0); 11978#L418-2 is_master_triggered_~__retres1~0#1 := 0; 11977#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12893#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12842#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12767#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12768#L437 assume 1 == ~t1_pc~0; 12951#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12850#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12803#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12354#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 12355#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12833#L456 assume !(1 == ~t2_pc~0); 12270#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12269#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12608#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12609#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 12584#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12114#L475 assume 1 == ~t3_pc~0; 12115#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12175#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12176#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12929#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 12358#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12359#L494 assume !(1 == ~t4_pc~0); 12394#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12395#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12599#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12600#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 12696#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12170#L513 assume 1 == ~t5_pc~0; 12171#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12396#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12433#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12131#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 12132#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12083#L532 assume !(1 == ~t6_pc~0); 12084#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12235#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12514#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12593#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 12324#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12325#L551 assume 1 == ~t7_pc~0; 12871#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12700#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12701#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12882#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 12960#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12498#L570 assume 1 == ~t8_pc~0; 12499#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12610#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12744#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12604#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 12108#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12109#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 12057#L952-2 assume !(1 == ~T1_E~0); 12058#L957-1 assume !(1 == ~T2_E~0); 12815#L962-1 assume !(1 == ~T3_E~0); 12620#L967-1 assume !(1 == ~T4_E~0); 12621#L972-1 assume !(1 == ~T5_E~0); 12872#L977-1 assume !(1 == ~T6_E~0); 12873#L982-1 assume !(1 == ~T7_E~0); 12237#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12238#L992-1 assume !(1 == ~E_M~0); 12247#L997-1 assume !(1 == ~E_1~0); 12582#L1002-1 assume !(1 == ~E_2~0); 12570#L1007-1 assume !(1 == ~E_3~0); 11990#L1012-1 assume !(1 == ~E_4~0); 11991#L1017-1 assume !(1 == ~E_5~0); 12571#L1022-1 assume !(1 == ~E_6~0); 12572#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12594#L1032-1 assume !(1 == ~E_8~0); 12719#L1037-1 assume { :end_inline_reset_delta_events } true; 12720#L1303-2 [2021-12-15 17:20:35,299 INFO L793 eck$LassoCheckResult]: Loop: 12720#L1303-2 assume !false; 12810#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12001#L829 assume !false; 12764#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12379#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12307#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12710#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12688#L712 assume !(0 != eval_~tmp~0#1); 12689#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12025#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12026#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12691#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12692#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12958#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12932#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12515#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12516#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12583#L884-3 assume !(0 == ~T7_E~0); 12564#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12208#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12209#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12241#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12242#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12182#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12183#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12230#L924-3 assume !(0 == ~E_6~0); 12772#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12674#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12675#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12801#L418-30 assume 1 == ~m_pc~0; 12072#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12073#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12527#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12528#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12271#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12272#L437-30 assume !(1 == ~t1_pc~0); 12397#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 12602#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12603#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12790#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12949#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12363#L456-30 assume 1 == ~t2_pc~0; 12364#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12761#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12762#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12156#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12157#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12490#L475-30 assume 1 == ~t3_pc~0; 12865#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12039#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12690#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12935#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12381#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12382#L494-30 assume 1 == ~t4_pc~0; 12375#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11974#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11975#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12906#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 12885#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12886#L513-30 assume 1 == ~t5_pc~0; 12962#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12496#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12560#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12786#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12787#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12506#L532-30 assume !(1 == ~t6_pc~0); 12507#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 12112#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12113#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12134#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12196#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12197#L551-30 assume 1 == ~t7_pc~0; 12249#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12309#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12181#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11992#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11993#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12360#L570-30 assume 1 == ~t8_pc~0; 12851#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12248#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12200#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12054#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12055#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12421#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12456#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12913#L957-3 assume !(1 == ~T2_E~0); 12914#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12831#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12832#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12740#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12741#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12963#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12409#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12410#L997-3 assume !(1 == ~E_1~0); 12405#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12406#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12221#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12222#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12318#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12536#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12023#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12024#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12261#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12262#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12166#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12167#L1322 assume !(0 == start_simulation_~tmp~3#1); 12435#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12102#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12103#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12915#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 12007#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12008#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12743#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12875#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 12720#L1303-2 [2021-12-15 17:20:35,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,300 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2021-12-15 17:20:35,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345322881] [2021-12-15 17:20:35,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,327 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345322881] [2021-12-15 17:20:35,327 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345322881] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,327 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,327 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,328 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73047364] [2021-12-15 17:20:35,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,328 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,329 INFO L85 PathProgramCache]: Analyzing trace with hash -1524153841, now seen corresponding path program 1 times [2021-12-15 17:20:35,329 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,329 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006080532] [2021-12-15 17:20:35,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,359 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,359 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006080532] [2021-12-15 17:20:35,360 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006080532] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,360 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,360 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,360 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417353619] [2021-12-15 17:20:35,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,361 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,361 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:35,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:35,362 INFO L87 Difference]: Start difference. First operand 993 states and 1476 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,408 INFO L93 Difference]: Finished difference Result 993 states and 1475 transitions. [2021-12-15 17:20:35,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:35,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1475 transitions. [2021-12-15 17:20:35,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1475 transitions. [2021-12-15 17:20:35,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:35,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:35,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1475 transitions. [2021-12-15 17:20:35,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,424 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2021-12-15 17:20:35,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1475 transitions. [2021-12-15 17:20:35,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:35,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1475 transitions. [2021-12-15 17:20:35,439 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2021-12-15 17:20:35,440 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2021-12-15 17:20:35,440 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:35,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1475 transitions. [2021-12-15 17:20:35,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,445 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,446 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,446 INFO L791 eck$LassoCheckResult]: Stem: 14724#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14011#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14012#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14049#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14675#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14676#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14297#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14298#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14238#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14239#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14482#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14455#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14456#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14728#L854 assume !(0 == ~M_E~0); 14542#L854-2 assume !(0 == ~T1_E~0); 14543#L859-1 assume !(0 == ~T2_E~0); 14113#L864-1 assume !(0 == ~T3_E~0); 14114#L869-1 assume !(0 == ~T4_E~0); 14227#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14927#L879-1 assume !(0 == ~T6_E~0); 14530#L884-1 assume !(0 == ~T7_E~0); 13981#L889-1 assume !(0 == ~T8_E~0); 13982#L894-1 assume !(0 == ~E_M~0); 14312#L899-1 assume !(0 == ~E_1~0); 14735#L904-1 assume !(0 == ~E_2~0); 14471#L909-1 assume !(0 == ~E_3~0); 14472#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14666#L919-1 assume !(0 == ~E_5~0); 14392#L924-1 assume !(0 == ~E_6~0); 14210#L929-1 assume !(0 == ~E_7~0); 14211#L934-1 assume !(0 == ~E_8~0); 14452#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13999#L418 assume !(1 == ~m_pc~0); 13971#L418-2 is_master_triggered_~__retres1~0#1 := 0; 13970#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14886#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14835#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14760#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14761#L437 assume 1 == ~t1_pc~0; 14944#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14843#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14796#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14347#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14348#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14826#L456 assume !(1 == ~t2_pc~0); 14263#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14262#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14601#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14602#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14577#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14107#L475 assume 1 == ~t3_pc~0; 14108#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14168#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14169#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14922#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14351#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14352#L494 assume !(1 == ~t4_pc~0); 14387#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14388#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14592#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14593#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14689#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14163#L513 assume 1 == ~t5_pc~0; 14164#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14389#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14426#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14124#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14125#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14076#L532 assume !(1 == ~t6_pc~0); 14077#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14228#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14507#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14586#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14317#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14318#L551 assume 1 == ~t7_pc~0; 14864#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14693#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14694#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14875#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 14953#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14491#L570 assume 1 == ~t8_pc~0; 14492#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14603#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14737#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14597#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14101#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14102#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14050#L952-2 assume !(1 == ~T1_E~0); 14051#L957-1 assume !(1 == ~T2_E~0); 14808#L962-1 assume !(1 == ~T3_E~0); 14613#L967-1 assume !(1 == ~T4_E~0); 14614#L972-1 assume !(1 == ~T5_E~0); 14865#L977-1 assume !(1 == ~T6_E~0); 14866#L982-1 assume !(1 == ~T7_E~0); 14230#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14231#L992-1 assume !(1 == ~E_M~0); 14240#L997-1 assume !(1 == ~E_1~0); 14575#L1002-1 assume !(1 == ~E_2~0); 14563#L1007-1 assume !(1 == ~E_3~0); 13983#L1012-1 assume !(1 == ~E_4~0); 13984#L1017-1 assume !(1 == ~E_5~0); 14564#L1022-1 assume !(1 == ~E_6~0); 14565#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14587#L1032-1 assume !(1 == ~E_8~0); 14712#L1037-1 assume { :end_inline_reset_delta_events } true; 14713#L1303-2 [2021-12-15 17:20:35,446 INFO L793 eck$LassoCheckResult]: Loop: 14713#L1303-2 assume !false; 14803#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13994#L829 assume !false; 14757#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14372#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14300#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14703#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14681#L712 assume !(0 != eval_~tmp~0#1); 14682#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14018#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14019#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14684#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14685#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14951#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14925#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14508#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14509#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14576#L884-3 assume !(0 == ~T7_E~0); 14557#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14201#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14202#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14234#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14235#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14175#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14176#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14223#L924-3 assume !(0 == ~E_6~0); 14765#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14667#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14668#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14794#L418-30 assume 1 == ~m_pc~0; 14065#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14066#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14520#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14521#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14264#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14265#L437-30 assume !(1 == ~t1_pc~0); 14390#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 14595#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14596#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14783#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14942#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14356#L456-30 assume 1 == ~t2_pc~0; 14357#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14754#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14755#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14149#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14150#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14483#L475-30 assume 1 == ~t3_pc~0; 14858#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14032#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14683#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14928#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14374#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14375#L494-30 assume 1 == ~t4_pc~0; 14368#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13967#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13968#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14899#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 14878#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14879#L513-30 assume !(1 == ~t5_pc~0); 14488#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 14489#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14553#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14779#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14780#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14499#L532-30 assume !(1 == ~t6_pc~0); 14500#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 14105#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14106#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14127#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14189#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14190#L551-30 assume 1 == ~t7_pc~0; 14242#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14302#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14174#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13985#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13986#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14353#L570-30 assume !(1 == ~t8_pc~0); 14674#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 14241#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14193#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14047#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14048#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14414#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14449#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14906#L957-3 assume !(1 == ~T2_E~0); 14907#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14824#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14825#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14733#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14734#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14956#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14402#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14403#L997-3 assume !(1 == ~E_1~0); 14398#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14399#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14214#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14215#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14311#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14529#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14016#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14017#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14254#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14255#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14159#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14160#L1322 assume !(0 == start_simulation_~tmp~3#1); 14428#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14095#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14096#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14908#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 14000#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14001#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14736#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14868#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14713#L1303-2 [2021-12-15 17:20:35,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,447 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2021-12-15 17:20:35,448 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,448 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476646470] [2021-12-15 17:20:35,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,448 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,470 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476646470] [2021-12-15 17:20:35,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476646470] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,471 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,471 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,471 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809910000] [2021-12-15 17:20:35,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,472 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,472 INFO L85 PathProgramCache]: Analyzing trace with hash -1507022511, now seen corresponding path program 1 times [2021-12-15 17:20:35,472 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248734945] [2021-12-15 17:20:35,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,505 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248734945] [2021-12-15 17:20:35,505 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248734945] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,505 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71790466] [2021-12-15 17:20:35,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,506 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,506 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:35,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:35,507 INFO L87 Difference]: Start difference. First operand 993 states and 1475 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,528 INFO L93 Difference]: Finished difference Result 993 states and 1474 transitions. [2021-12-15 17:20:35,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:35,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1474 transitions. [2021-12-15 17:20:35,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1474 transitions. [2021-12-15 17:20:35,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2021-12-15 17:20:35,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2021-12-15 17:20:35,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1474 transitions. [2021-12-15 17:20:35,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,541 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2021-12-15 17:20:35,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1474 transitions. [2021-12-15 17:20:35,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2021-12-15 17:20:35,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1474 transitions. [2021-12-15 17:20:35,556 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2021-12-15 17:20:35,556 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2021-12-15 17:20:35,556 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:35,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1474 transitions. [2021-12-15 17:20:35,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2021-12-15 17:20:35,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,561 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,562 INFO L791 eck$LassoCheckResult]: Stem: 16717#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16718#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16004#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16005#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16042#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 16668#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16669#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16290#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16291#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16231#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16232#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16475#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16448#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16449#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16721#L854 assume !(0 == ~M_E~0); 16535#L854-2 assume !(0 == ~T1_E~0); 16536#L859-1 assume !(0 == ~T2_E~0); 16106#L864-1 assume !(0 == ~T3_E~0); 16107#L869-1 assume !(0 == ~T4_E~0); 16220#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16920#L879-1 assume !(0 == ~T6_E~0); 16523#L884-1 assume !(0 == ~T7_E~0); 15974#L889-1 assume !(0 == ~T8_E~0); 15975#L894-1 assume !(0 == ~E_M~0); 16305#L899-1 assume !(0 == ~E_1~0); 16728#L904-1 assume !(0 == ~E_2~0); 16464#L909-1 assume !(0 == ~E_3~0); 16465#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16659#L919-1 assume !(0 == ~E_5~0); 16385#L924-1 assume !(0 == ~E_6~0); 16203#L929-1 assume !(0 == ~E_7~0); 16204#L934-1 assume !(0 == ~E_8~0); 16445#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15992#L418 assume !(1 == ~m_pc~0); 15964#L418-2 is_master_triggered_~__retres1~0#1 := 0; 15963#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16879#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16828#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16753#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16754#L437 assume 1 == ~t1_pc~0; 16937#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16836#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16789#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16340#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 16341#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16819#L456 assume !(1 == ~t2_pc~0); 16256#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16255#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16594#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16595#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 16570#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16100#L475 assume 1 == ~t3_pc~0; 16101#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16161#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16162#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16915#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 16344#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16345#L494 assume !(1 == ~t4_pc~0); 16380#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16381#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16585#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16586#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 16682#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16156#L513 assume 1 == ~t5_pc~0; 16157#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16382#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16419#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16117#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 16118#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16069#L532 assume !(1 == ~t6_pc~0); 16070#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16221#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16500#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16579#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 16310#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16311#L551 assume 1 == ~t7_pc~0; 16857#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16686#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16687#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16868#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 16946#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16484#L570 assume 1 == ~t8_pc~0; 16485#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16596#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16730#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16590#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 16094#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16095#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 16043#L952-2 assume !(1 == ~T1_E~0); 16044#L957-1 assume !(1 == ~T2_E~0); 16801#L962-1 assume !(1 == ~T3_E~0); 16606#L967-1 assume !(1 == ~T4_E~0); 16607#L972-1 assume !(1 == ~T5_E~0); 16858#L977-1 assume !(1 == ~T6_E~0); 16859#L982-1 assume !(1 == ~T7_E~0); 16223#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16224#L992-1 assume !(1 == ~E_M~0); 16233#L997-1 assume !(1 == ~E_1~0); 16568#L1002-1 assume !(1 == ~E_2~0); 16556#L1007-1 assume !(1 == ~E_3~0); 15976#L1012-1 assume !(1 == ~E_4~0); 15977#L1017-1 assume !(1 == ~E_5~0); 16557#L1022-1 assume !(1 == ~E_6~0); 16558#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16580#L1032-1 assume !(1 == ~E_8~0); 16705#L1037-1 assume { :end_inline_reset_delta_events } true; 16706#L1303-2 [2021-12-15 17:20:35,562 INFO L793 eck$LassoCheckResult]: Loop: 16706#L1303-2 assume !false; 16796#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15987#L829 assume !false; 16750#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16365#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16293#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16696#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16674#L712 assume !(0 != eval_~tmp~0#1); 16675#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16011#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16012#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16677#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16678#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16944#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16918#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16501#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16502#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16569#L884-3 assume !(0 == ~T7_E~0); 16550#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16194#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16195#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16227#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16228#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16168#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16169#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16216#L924-3 assume !(0 == ~E_6~0); 16758#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16660#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16661#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16787#L418-30 assume 1 == ~m_pc~0; 16058#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16059#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16513#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16514#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16257#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16258#L437-30 assume 1 == ~t1_pc~0; 16384#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16588#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16589#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16776#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16935#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16349#L456-30 assume 1 == ~t2_pc~0; 16350#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16747#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16748#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16142#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16143#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16476#L475-30 assume 1 == ~t3_pc~0; 16851#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16025#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16676#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16921#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16367#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16368#L494-30 assume 1 == ~t4_pc~0; 16361#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15960#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15961#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16892#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 16871#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16872#L513-30 assume !(1 == ~t5_pc~0); 16481#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 16482#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16546#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16772#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16773#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16492#L532-30 assume !(1 == ~t6_pc~0); 16493#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 16098#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16099#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16120#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16182#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16183#L551-30 assume 1 == ~t7_pc~0; 16235#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16295#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16167#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15978#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15979#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16346#L570-30 assume 1 == ~t8_pc~0; 16837#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16234#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16186#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16040#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16041#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16407#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16442#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16899#L957-3 assume !(1 == ~T2_E~0); 16900#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16817#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16818#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16726#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16727#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16949#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16395#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16396#L997-3 assume !(1 == ~E_1~0); 16391#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16392#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16207#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16208#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16304#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16522#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16009#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16010#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16247#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16248#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16152#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 16153#L1322 assume !(0 == start_simulation_~tmp~3#1); 16421#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16088#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16089#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16901#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 15993#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15994#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16729#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16861#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 16706#L1303-2 [2021-12-15 17:20:35,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,563 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2021-12-15 17:20:35,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557160137] [2021-12-15 17:20:35,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,595 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557160137] [2021-12-15 17:20:35,595 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557160137] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,595 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996623463] [2021-12-15 17:20:35,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,596 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1695255281, now seen corresponding path program 1 times [2021-12-15 17:20:35,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789202705] [2021-12-15 17:20:35,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,626 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,626 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789202705] [2021-12-15 17:20:35,626 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [789202705] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,627 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,627 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,627 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784225411] [2021-12-15 17:20:35,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,627 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,628 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:35,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:35,628 INFO L87 Difference]: Start difference. First operand 993 states and 1474 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,707 INFO L93 Difference]: Finished difference Result 1806 states and 2671 transitions. [2021-12-15 17:20:35,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:35,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1806 states and 2671 transitions. [2021-12-15 17:20:35,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2021-12-15 17:20:35,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1806 states to 1806 states and 2671 transitions. [2021-12-15 17:20:35,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1806 [2021-12-15 17:20:35,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1806 [2021-12-15 17:20:35,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1806 states and 2671 transitions. [2021-12-15 17:20:35,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,729 INFO L681 BuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2021-12-15 17:20:35,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1806 states and 2671 transitions. [2021-12-15 17:20:35,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1806 to 1806. [2021-12-15 17:20:35,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1806 states to 1806 states and 2671 transitions. [2021-12-15 17:20:35,760 INFO L704 BuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2021-12-15 17:20:35,761 INFO L587 BuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2021-12-15 17:20:35,761 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:35,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1806 states and 2671 transitions. [2021-12-15 17:20:35,776 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2021-12-15 17:20:35,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,778 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,778 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,778 INFO L791 eck$LassoCheckResult]: Stem: 19540#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 18813#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18814#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18851#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 19488#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19489#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19101#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19102#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19041#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19042#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19291#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19264#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19265#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19545#L854 assume !(0 == ~M_E~0); 19352#L854-2 assume !(0 == ~T1_E~0); 19353#L859-1 assume !(0 == ~T2_E~0); 18915#L864-1 assume !(0 == ~T3_E~0); 18916#L869-1 assume !(0 == ~T4_E~0); 19030#L874-1 assume !(0 == ~T5_E~0); 19776#L879-1 assume !(0 == ~T6_E~0); 19340#L884-1 assume !(0 == ~T7_E~0); 18783#L889-1 assume !(0 == ~T8_E~0); 18784#L894-1 assume !(0 == ~E_M~0); 19116#L899-1 assume !(0 == ~E_1~0); 19552#L904-1 assume !(0 == ~E_2~0); 19280#L909-1 assume !(0 == ~E_3~0); 19281#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19479#L919-1 assume !(0 == ~E_5~0); 19198#L924-1 assume !(0 == ~E_6~0); 19013#L929-1 assume !(0 == ~E_7~0); 19014#L934-1 assume !(0 == ~E_8~0); 19261#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18801#L418 assume !(1 == ~m_pc~0); 18773#L418-2 is_master_triggered_~__retres1~0#1 := 0; 18772#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19723#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19662#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19578#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19579#L437 assume 1 == ~t1_pc~0; 19799#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19672#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19619#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19151#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 19152#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19653#L456 assume !(1 == ~t2_pc~0); 19067#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19066#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19413#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19414#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 19389#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18909#L475 assume 1 == ~t3_pc~0; 18910#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18971#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18972#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19768#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 19155#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19156#L494 assume !(1 == ~t4_pc~0); 19193#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19194#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19404#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19405#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 19502#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18966#L513 assume 1 == ~t5_pc~0; 18967#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19195#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19234#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18926#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 18927#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18878#L532 assume !(1 == ~t6_pc~0); 18879#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19031#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19316#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19398#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 19121#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19122#L551 assume 1 == ~t7_pc~0; 19696#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19507#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19508#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19711#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 19811#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19300#L570 assume 1 == ~t8_pc~0; 19301#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19415#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19554#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19409#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 18903#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18904#L952 assume !(1 == ~M_E~0); 19676#L952-2 assume !(1 == ~T1_E~0); 19944#L957-1 assume !(1 == ~T2_E~0); 19942#L962-1 assume !(1 == ~T3_E~0); 19940#L967-1 assume !(1 == ~T4_E~0); 19939#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19697#L977-1 assume !(1 == ~T6_E~0); 19698#L982-1 assume !(1 == ~T7_E~0); 19033#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19034#L992-1 assume !(1 == ~E_M~0); 19043#L997-1 assume !(1 == ~E_1~0); 19387#L1002-1 assume !(1 == ~E_2~0); 19375#L1007-1 assume !(1 == ~E_3~0); 18785#L1012-1 assume !(1 == ~E_4~0); 18786#L1017-1 assume !(1 == ~E_5~0); 19851#L1022-1 assume !(1 == ~E_6~0); 19849#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19847#L1032-1 assume !(1 == ~E_8~0); 19846#L1037-1 assume { :end_inline_reset_delta_events } true; 19628#L1303-2 [2021-12-15 17:20:35,779 INFO L793 eck$LassoCheckResult]: Loop: 19628#L1303-2 assume !false; 19629#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19837#L829 assume !false; 19575#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19178#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19104#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19827#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19825#L712 assume !(0 != eval_~tmp~0#1); 19626#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18820#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18821#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19823#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20236#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20235#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20234#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20233#L874-3 assume !(0 == ~T5_E~0); 20232#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20231#L884-3 assume !(0 == ~T7_E~0); 20230#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20229#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20228#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20227#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20226#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20225#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20224#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20223#L924-3 assume !(0 == ~E_6~0); 20222#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20221#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20220#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20219#L418-30 assume 1 == ~m_pc~0; 20217#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20216#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20215#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20214#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20213#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20212#L437-30 assume !(1 == ~t1_pc~0); 20210#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 20209#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20208#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20207#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20206#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20205#L456-30 assume 1 == ~t2_pc~0; 20203#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20202#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20201#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20200#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20199#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20198#L475-30 assume !(1 == ~t3_pc~0); 20196#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 20195#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20194#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20193#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20192#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20191#L494-30 assume 1 == ~t4_pc~0; 20189#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20188#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20187#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20186#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 20185#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20184#L513-30 assume 1 == ~t5_pc~0; 20182#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20181#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20180#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20179#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20178#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20177#L532-30 assume 1 == ~t6_pc~0; 20176#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20174#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20173#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20172#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20171#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20170#L551-30 assume 1 == ~t7_pc~0; 20168#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20167#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20166#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20165#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20164#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20163#L570-30 assume !(1 == ~t8_pc~0); 20160#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 20157#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20155#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20153#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20151#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20149#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19257#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20145#L957-3 assume !(1 == ~T2_E~0); 20143#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20141#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20139#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19769#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20136#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20133#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20131#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20129#L997-3 assume !(1 == ~E_1~0); 20127#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20125#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20123#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20120#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20118#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20116#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20114#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20113#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20104#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20103#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20102#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20101#L1322 assume !(0 == start_simulation_~tmp~3#1); 19566#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20099#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19749#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19750#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 20089#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20088#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19773#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19774#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 19628#L1303-2 [2021-12-15 17:20:35,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,779 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2021-12-15 17:20:35,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131569717] [2021-12-15 17:20:35,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131569717] [2021-12-15 17:20:35,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131569717] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,819 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,819 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509741516] [2021-12-15 17:20:35,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,820 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1301437970, now seen corresponding path program 1 times [2021-12-15 17:20:35,821 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745016459] [2021-12-15 17:20:35,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,822 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745016459] [2021-12-15 17:20:35,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745016459] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76655335] [2021-12-15 17:20:35,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,858 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,858 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:35,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:35,859 INFO L87 Difference]: Start difference. First operand 1806 states and 2671 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,988 INFO L93 Difference]: Finished difference Result 3286 states and 4848 transitions. [2021-12-15 17:20:35,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:35,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3286 states and 4848 transitions. [2021-12-15 17:20:36,006 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2021-12-15 17:20:36,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3286 states to 3286 states and 4848 transitions. [2021-12-15 17:20:36,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3286 [2021-12-15 17:20:36,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3286 [2021-12-15 17:20:36,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3286 states and 4848 transitions. [2021-12-15 17:20:36,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,031 INFO L681 BuchiCegarLoop]: Abstraction has 3286 states and 4848 transitions. [2021-12-15 17:20:36,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3286 states and 4848 transitions. [2021-12-15 17:20:36,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3286 to 3284. [2021-12-15 17:20:36,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3284 states to 3284 states and 4846 transitions. [2021-12-15 17:20:36,098 INFO L704 BuchiCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2021-12-15 17:20:36,098 INFO L587 BuchiCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2021-12-15 17:20:36,098 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:36,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3284 states and 4846 transitions. [2021-12-15 17:20:36,108 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2021-12-15 17:20:36,108 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,110 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,110 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,111 INFO L791 eck$LassoCheckResult]: Stem: 24659#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 23917#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23918#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23956#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 24606#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24607#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24207#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24208#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24147#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24148#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24402#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24375#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24376#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24663#L854 assume !(0 == ~M_E~0); 24464#L854-2 assume !(0 == ~T1_E~0); 24465#L859-1 assume !(0 == ~T2_E~0); 24020#L864-1 assume !(0 == ~T3_E~0); 24021#L869-1 assume !(0 == ~T4_E~0); 24136#L874-1 assume !(0 == ~T5_E~0); 24917#L879-1 assume !(0 == ~T6_E~0); 24452#L884-1 assume !(0 == ~T7_E~0); 23885#L889-1 assume !(0 == ~T8_E~0); 23886#L894-1 assume !(0 == ~E_M~0); 24224#L899-1 assume !(0 == ~E_1~0); 24670#L904-1 assume !(0 == ~E_2~0); 24391#L909-1 assume !(0 == ~E_3~0); 24392#L914-1 assume !(0 == ~E_4~0); 24596#L919-1 assume !(0 == ~E_5~0); 24309#L924-1 assume !(0 == ~E_6~0); 24118#L929-1 assume !(0 == ~E_7~0); 24119#L934-1 assume !(0 == ~E_8~0); 24372#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23905#L418 assume !(1 == ~m_pc~0); 23875#L418-2 is_master_triggered_~__retres1~0#1 := 0; 23874#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24860#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24790#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24697#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24698#L437 assume 1 == ~t1_pc~0; 24948#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24798#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24741#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24260#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 24261#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24780#L456 assume !(1 == ~t2_pc~0); 24173#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24172#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24528#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24529#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 24503#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24014#L475 assume 1 == ~t3_pc~0; 24015#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24076#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24077#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24908#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 24264#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24265#L494 assume !(1 == ~t4_pc~0); 24304#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24305#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24519#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24520#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 24620#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24070#L513 assume 1 == ~t5_pc~0; 24071#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24306#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24345#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24031#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 24032#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23983#L532 assume !(1 == ~t6_pc~0); 23984#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24137#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24429#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24513#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 24230#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24231#L551 assume 1 == ~t7_pc~0; 24824#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24624#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24625#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24841#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 24968#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24413#L570 assume 1 == ~t8_pc~0; 24414#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24530#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24672#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24524#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 24008#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24009#L952 assume !(1 == ~M_E~0); 24802#L952-2 assume !(1 == ~T1_E~0); 24760#L957-1 assume !(1 == ~T2_E~0); 24761#L962-1 assume !(1 == ~T3_E~0); 24542#L967-1 assume !(1 == ~T4_E~0); 24543#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25157#L977-1 assume !(1 == ~T6_E~0); 25155#L982-1 assume !(1 == ~T7_E~0); 25153#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24149#L992-1 assume !(1 == ~E_M~0); 24150#L997-1 assume !(1 == ~E_1~0); 25100#L1002-1 assume !(1 == ~E_2~0); 24485#L1007-1 assume !(1 == ~E_3~0); 24486#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25065#L1017-1 assume !(1 == ~E_5~0); 25042#L1022-1 assume !(1 == ~E_6~0); 25027#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25025#L1032-1 assume !(1 == ~E_8~0); 25015#L1037-1 assume { :end_inline_reset_delta_events } true; 25008#L1303-2 [2021-12-15 17:20:36,111 INFO L793 eck$LassoCheckResult]: Loop: 25008#L1303-2 assume !false; 25003#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25001#L829 assume !false; 25000#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24995#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24990#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24989#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 24987#L712 assume !(0 != eval_~tmp~0#1); 24986#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24985#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24983#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24984#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25660#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25658#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25656#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25654#L874-3 assume !(0 == ~T5_E~0); 25652#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25650#L884-3 assume !(0 == ~T7_E~0); 25648#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25646#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25644#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25642#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25640#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25638#L914-3 assume !(0 == ~E_4~0); 25636#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25634#L924-3 assume !(0 == ~E_6~0); 25632#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25630#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25628#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25626#L418-30 assume 1 == ~m_pc~0; 25623#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25620#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25618#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25616#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25614#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25612#L437-30 assume !(1 == ~t1_pc~0); 25609#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 25606#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25604#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25602#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25600#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25598#L456-30 assume 1 == ~t2_pc~0; 25595#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25592#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25590#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25588#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25586#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25584#L475-30 assume !(1 == ~t3_pc~0); 25581#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 25578#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25576#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25574#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25572#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25570#L494-30 assume !(1 == ~t4_pc~0); 25568#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 25564#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25562#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25560#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 25558#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25556#L513-30 assume 1 == ~t5_pc~0; 25553#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25550#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25548#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25546#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25544#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25542#L532-30 assume !(1 == ~t6_pc~0); 25539#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 25536#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25534#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25532#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25530#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25528#L551-30 assume 1 == ~t7_pc~0; 25525#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25522#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25520#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25518#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25515#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25511#L570-30 assume !(1 == ~t8_pc~0); 25507#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 25503#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25500#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25497#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25494#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25490#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24368#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25485#L957-3 assume !(1 == ~T2_E~0); 25482#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25479#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25476#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25472#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25470#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25468#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25466#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25464#L997-3 assume !(1 == ~E_1~0); 25462#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25452#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25447#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25439#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25434#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25429#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25137#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25135#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25109#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25107#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25106#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25104#L1322 assume !(0 == start_simulation_~tmp~3#1); 24684#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25063#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25054#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25041#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 25039#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25026#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25024#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25014#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 25008#L1303-2 [2021-12-15 17:20:36,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2021-12-15 17:20:36,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963172898] [2021-12-15 17:20:36,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,157 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,157 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963172898] [2021-12-15 17:20:36,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963172898] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,158 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,158 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:36,158 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824682740] [2021-12-15 17:20:36,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,158 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1857591446, now seen corresponding path program 1 times [2021-12-15 17:20:36,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425798274] [2021-12-15 17:20:36,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,160 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,188 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425798274] [2021-12-15 17:20:36,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425798274] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,189 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742832015] [2021-12-15 17:20:36,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,189 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,190 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:36,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:36,191 INFO L87 Difference]: Start difference. First operand 3284 states and 4846 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,456 INFO L93 Difference]: Finished difference Result 9426 states and 13840 transitions. [2021-12-15 17:20:36,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:36,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9426 states and 13840 transitions. [2021-12-15 17:20:36,503 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9048 [2021-12-15 17:20:36,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9426 states to 9426 states and 13840 transitions. [2021-12-15 17:20:36,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9426 [2021-12-15 17:20:36,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9426 [2021-12-15 17:20:36,556 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9426 states and 13840 transitions. [2021-12-15 17:20:36,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,571 INFO L681 BuchiCegarLoop]: Abstraction has 9426 states and 13840 transitions. [2021-12-15 17:20:36,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9426 states and 13840 transitions. [2021-12-15 17:20:36,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9426 to 3404. [2021-12-15 17:20:36,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3404 states to 3404 states and 4966 transitions. [2021-12-15 17:20:36,749 INFO L704 BuchiCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2021-12-15 17:20:36,749 INFO L587 BuchiCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2021-12-15 17:20:36,749 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:36,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3404 states and 4966 transitions. [2021-12-15 17:20:36,760 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3250 [2021-12-15 17:20:36,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,762 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,763 INFO L791 eck$LassoCheckResult]: Stem: 37380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 37381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 36639#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36640#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36677#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 37328#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37329#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36928#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36929#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36868#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36869#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37120#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37093#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37094#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37385#L854 assume !(0 == ~M_E~0); 37183#L854-2 assume !(0 == ~T1_E~0); 37184#L859-1 assume !(0 == ~T2_E~0); 36741#L864-1 assume !(0 == ~T3_E~0); 36742#L869-1 assume !(0 == ~T4_E~0); 36856#L874-1 assume !(0 == ~T5_E~0); 37648#L879-1 assume !(0 == ~T6_E~0); 37170#L884-1 assume !(0 == ~T7_E~0); 36608#L889-1 assume !(0 == ~T8_E~0); 36609#L894-1 assume !(0 == ~E_M~0); 36945#L899-1 assume !(0 == ~E_1~0); 37394#L904-1 assume !(0 == ~E_2~0); 37110#L909-1 assume !(0 == ~E_3~0); 37111#L914-1 assume !(0 == ~E_4~0); 37318#L919-1 assume !(0 == ~E_5~0); 37027#L924-1 assume !(0 == ~E_6~0); 36843#L929-1 assume !(0 == ~E_7~0); 36844#L934-1 assume !(0 == ~E_8~0); 37090#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36627#L418 assume !(1 == ~m_pc~0); 36600#L418-2 is_master_triggered_~__retres1~0#1 := 0; 37593#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37594#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37515#L1061 assume !(0 != activate_threads_~tmp~1#1); 37424#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37425#L437 assume 1 == ~t1_pc~0; 37676#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37525#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37469#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36978#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 36979#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37506#L456 assume !(1 == ~t2_pc~0); 36893#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36892#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37245#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37246#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 37221#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36735#L475 assume 1 == ~t3_pc~0; 36736#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36798#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36799#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37637#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 36982#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36983#L494 assume !(1 == ~t4_pc~0); 37022#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37023#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37236#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37237#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 37342#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36791#L513 assume 1 == ~t5_pc~0; 36792#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37024#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37063#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36752#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 36753#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36704#L532 assume !(1 == ~t6_pc~0); 36705#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36857#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37146#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37230#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 36948#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36949#L551 assume 1 == ~t7_pc~0; 37555#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37346#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37347#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37577#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 37699#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37130#L570 assume 1 == ~t8_pc~0; 37131#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37248#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37395#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37243#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 36733#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36734#L952 assume !(1 == ~M_E~0); 37530#L952-2 assume !(1 == ~T1_E~0); 37487#L957-1 assume !(1 == ~T2_E~0); 37488#L962-1 assume !(1 == ~T3_E~0); 37263#L967-1 assume !(1 == ~T4_E~0); 37264#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37826#L977-1 assume !(1 == ~T6_E~0); 37704#L982-1 assume !(1 == ~T7_E~0); 37705#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36870#L992-1 assume !(1 == ~E_M~0); 36871#L997-1 assume !(1 == ~E_1~0); 37650#L1002-1 assume !(1 == ~E_2~0); 37651#L1007-1 assume !(1 == ~E_3~0); 37808#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 37806#L1017-1 assume !(1 == ~E_5~0); 37804#L1022-1 assume !(1 == ~E_6~0); 37800#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37798#L1032-1 assume !(1 == ~E_8~0); 37788#L1037-1 assume { :end_inline_reset_delta_events } true; 37781#L1303-2 [2021-12-15 17:20:36,763 INFO L793 eck$LassoCheckResult]: Loop: 37781#L1303-2 assume !false; 37776#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37774#L829 assume !false; 37773#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37768#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37763#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37762#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37760#L712 assume !(0 != eval_~tmp~0#1); 37759#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37758#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37756#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37757#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39083#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39081#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39079#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39077#L874-3 assume !(0 == ~T5_E~0); 39075#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39073#L884-3 assume !(0 == ~T7_E~0); 39071#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39069#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39067#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39065#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39063#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39061#L914-3 assume !(0 == ~E_4~0); 39059#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39057#L924-3 assume !(0 == ~E_6~0); 39055#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39053#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39042#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39041#L418-30 assume !(1 == ~m_pc~0); 39040#L418-32 is_master_triggered_~__retres1~0#1 := 0; 39038#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39036#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39034#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 39031#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39029#L437-30 assume !(1 == ~t1_pc~0); 39025#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 39023#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39021#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39019#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39017#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39015#L456-30 assume 1 == ~t2_pc~0; 39011#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39009#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39007#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39005#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39003#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39001#L475-30 assume !(1 == ~t3_pc~0); 38997#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 38995#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38993#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38991#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38989#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38987#L494-30 assume 1 == ~t4_pc~0; 38983#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38981#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38979#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38977#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 38975#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38973#L513-30 assume 1 == ~t5_pc~0; 38969#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38967#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38965#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38963#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38961#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38959#L532-30 assume !(1 == ~t6_pc~0); 38955#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 38953#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38951#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38949#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38947#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38945#L551-30 assume 1 == ~t7_pc~0; 38941#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38939#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38937#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38935#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38933#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38931#L570-30 assume 1 == ~t8_pc~0; 38928#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38925#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38923#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38921#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38911#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38908#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37086#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38902#L957-3 assume !(1 == ~T2_E~0); 38899#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38896#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38792#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38787#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38785#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38783#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38781#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38779#L997-3 assume !(1 == ~E_1~0); 38777#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38774#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38772#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38769#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38767#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38765#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38763#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38760#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38750#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38748#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38746#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 38744#L1322 assume !(0 == start_simulation_~tmp~3#1); 37410#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38731#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38721#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38719#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 38717#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38715#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37797#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 37787#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 37781#L1303-2 [2021-12-15 17:20:36,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,764 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2021-12-15 17:20:36,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958618458] [2021-12-15 17:20:36,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,790 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958618458] [2021-12-15 17:20:36,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958618458] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,791 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,791 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:36,791 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255070755] [2021-12-15 17:20:36,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,791 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,792 INFO L85 PathProgramCache]: Analyzing trace with hash 1723741911, now seen corresponding path program 1 times [2021-12-15 17:20:36,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862049307] [2021-12-15 17:20:36,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,821 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862049307] [2021-12-15 17:20:36,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862049307] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,822 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,822 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,822 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187997513] [2021-12-15 17:20:36,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,823 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,823 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:36,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:36,823 INFO L87 Difference]: Start difference. First operand 3404 states and 4966 transitions. cyclomatic complexity: 1566 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,913 INFO L93 Difference]: Finished difference Result 6338 states and 9180 transitions. [2021-12-15 17:20:36,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:36,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6338 states and 9180 transitions. [2021-12-15 17:20:36,947 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6181 [2021-12-15 17:20:36,974 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6338 states to 6338 states and 9180 transitions. [2021-12-15 17:20:36,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6338 [2021-12-15 17:20:36,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6338 [2021-12-15 17:20:36,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6338 states and 9180 transitions. [2021-12-15 17:20:36,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,991 INFO L681 BuchiCegarLoop]: Abstraction has 6338 states and 9180 transitions. [2021-12-15 17:20:36,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6338 states and 9180 transitions. [2021-12-15 17:20:37,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6338 to 6330. [2021-12-15 17:20:37,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6330 states, 6330 states have (on average 1.4489731437598736) internal successors, (9172), 6329 states have internal predecessors, (9172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6330 states to 6330 states and 9172 transitions. [2021-12-15 17:20:37,166 INFO L704 BuchiCegarLoop]: Abstraction has 6330 states and 9172 transitions. [2021-12-15 17:20:37,166 INFO L587 BuchiCegarLoop]: Abstraction has 6330 states and 9172 transitions. [2021-12-15 17:20:37,166 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:37,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6330 states and 9172 transitions. [2021-12-15 17:20:37,187 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6173 [2021-12-15 17:20:37,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:37,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:37,189 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,189 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,189 INFO L791 eck$LassoCheckResult]: Stem: 47166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 47167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 46388#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46389#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46426#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 47100#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47101#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46679#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46680#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46617#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46618#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46876#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46847#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46848#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47170#L854 assume !(0 == ~M_E~0); 46944#L854-2 assume !(0 == ~T1_E~0); 46945#L859-1 assume !(0 == ~T2_E~0); 46489#L864-1 assume !(0 == ~T3_E~0); 46490#L869-1 assume !(0 == ~T4_E~0); 46606#L874-1 assume !(0 == ~T5_E~0); 47475#L879-1 assume !(0 == ~T6_E~0); 46932#L884-1 assume !(0 == ~T7_E~0); 46357#L889-1 assume !(0 == ~T8_E~0); 46358#L894-1 assume !(0 == ~E_M~0); 46696#L899-1 assume !(0 == ~E_1~0); 47177#L904-1 assume !(0 == ~E_2~0); 46864#L909-1 assume !(0 == ~E_3~0); 46865#L914-1 assume !(0 == ~E_4~0); 47087#L919-1 assume !(0 == ~E_5~0); 46781#L924-1 assume !(0 == ~E_6~0); 46588#L929-1 assume !(0 == ~E_7~0); 46589#L934-1 assume !(0 == ~E_8~0); 46844#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46376#L418 assume !(1 == ~m_pc~0); 46347#L418-2 is_master_triggered_~__retres1~0#1 := 0; 47388#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47389#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47306#L1061 assume !(0 != activate_threads_~tmp~1#1); 47205#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47206#L437 assume !(1 == ~t1_pc~0); 47457#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47314#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47252#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46732#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 46733#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47296#L456 assume !(1 == ~t2_pc~0); 46642#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46641#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47007#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47008#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 46982#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46483#L475 assume 1 == ~t3_pc~0; 46484#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46545#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46546#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47459#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 46736#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46737#L494 assume !(1 == ~t4_pc~0); 46776#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46777#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46997#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46998#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 47115#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46539#L513 assume 1 == ~t5_pc~0; 46540#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46778#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46817#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46500#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 46501#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46453#L532 assume !(1 == ~t6_pc~0); 46454#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46607#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46905#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46991#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 46702#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46703#L551 assume 1 == ~t7_pc~0; 47343#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47123#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47124#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47366#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 47550#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46888#L570 assume 1 == ~t8_pc~0; 46889#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47009#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47179#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47002#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 46477#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46478#L952 assume !(1 == ~M_E~0); 47318#L952-2 assume !(1 == ~T1_E~0); 49323#L957-1 assume !(1 == ~T2_E~0); 47520#L962-1 assume !(1 == ~T3_E~0); 47022#L967-1 assume !(1 == ~T4_E~0); 47023#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47344#L977-1 assume !(1 == ~T6_E~0); 47345#L982-1 assume !(1 == ~T7_E~0); 47553#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46619#L992-1 assume !(1 == ~E_M~0); 46620#L997-1 assume !(1 == ~E_1~0); 46980#L1002-1 assume !(1 == ~E_2~0); 47478#L1007-1 assume !(1 == ~E_3~0); 49087#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49054#L1017-1 assume !(1 == ~E_5~0); 49022#L1022-1 assume !(1 == ~E_6~0); 48997#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 48401#L1032-1 assume !(1 == ~E_8~0); 48384#L1037-1 assume { :end_inline_reset_delta_events } true; 48371#L1303-2 [2021-12-15 17:20:37,189 INFO L793 eck$LassoCheckResult]: Loop: 48371#L1303-2 assume !false; 48361#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48358#L829 assume !false; 48357#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48351#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 48337#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 48335#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48332#L712 assume !(0 != eval_~tmp~0#1); 48327#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48328#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48323#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48324#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51016#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51013#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51010#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51008#L874-3 assume !(0 == ~T5_E~0); 51006#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51004#L884-3 assume !(0 == ~T7_E~0); 51002#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51000#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50998#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50996#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50994#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50991#L914-3 assume !(0 == ~E_4~0); 50989#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50987#L924-3 assume !(0 == ~E_6~0); 50985#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50983#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50981#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50978#L418-30 assume !(1 == ~m_pc~0); 50976#L418-32 is_master_triggered_~__retres1~0#1 := 0; 50973#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50970#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50967#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 50964#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50961#L437-30 assume !(1 == ~t1_pc~0); 50959#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 50957#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50955#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50953#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50951#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49562#L456-30 assume 1 == ~t2_pc~0; 49559#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49557#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49555#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49554#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49553#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49551#L475-30 assume !(1 == ~t3_pc~0); 49548#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 49546#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49544#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49542#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49540#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49538#L494-30 assume !(1 == ~t4_pc~0); 49536#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 49532#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49530#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49528#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 49526#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49524#L513-30 assume 1 == ~t5_pc~0; 49521#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49520#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49519#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49518#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49517#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49516#L532-30 assume !(1 == ~t6_pc~0); 49514#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 49512#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49510#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49508#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49506#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49505#L551-30 assume 1 == ~t7_pc~0; 49502#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49500#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49498#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49495#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49373#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49371#L570-30 assume !(1 == ~t8_pc~0); 49368#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 49366#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49364#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49362#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49360#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49276#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48270#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48269#L957-3 assume !(1 == ~T2_E~0); 48268#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48262#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48263#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49155#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49153#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49151#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49115#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49113#L997-3 assume !(1 == ~E_1~0); 49111#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49109#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49108#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49105#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49104#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49103#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49102#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49101#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49075#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49052#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49050#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 49048#L1322 assume !(0 == start_simulation_~tmp~3#1); 48213#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49005#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 48996#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 48995#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 48994#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48992#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48400#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 48383#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 48371#L1303-2 [2021-12-15 17:20:37,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,190 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2021-12-15 17:20:37,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020571383] [2021-12-15 17:20:37,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,190 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,226 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020571383] [2021-12-15 17:20:37,226 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020571383] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,226 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,226 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,227 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070289644] [2021-12-15 17:20:37,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,228 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,228 INFO L85 PathProgramCache]: Analyzing trace with hash -417433255, now seen corresponding path program 1 times [2021-12-15 17:20:37,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650935425] [2021-12-15 17:20:37,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,260 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,260 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [650935425] [2021-12-15 17:20:37,260 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [650935425] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,261 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,261 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190587467] [2021-12-15 17:20:37,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,261 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:37,261 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:37,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:37,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:37,262 INFO L87 Difference]: Start difference. First operand 6330 states and 9172 transitions. cyclomatic complexity: 2850 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:37,478 INFO L93 Difference]: Finished difference Result 15078 states and 21642 transitions. [2021-12-15 17:20:37,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:37,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15078 states and 21642 transitions. [2021-12-15 17:20:37,633 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14890 [2021-12-15 17:20:37,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15078 states to 15078 states and 21642 transitions. [2021-12-15 17:20:37,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15078 [2021-12-15 17:20:37,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15078 [2021-12-15 17:20:37,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15078 states and 21642 transitions. [2021-12-15 17:20:37,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:37,717 INFO L681 BuchiCegarLoop]: Abstraction has 15078 states and 21642 transitions. [2021-12-15 17:20:37,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15078 states and 21642 transitions. [2021-12-15 17:20:37,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15078 to 12142. [2021-12-15 17:20:37,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12142 states, 12142 states have (on average 1.4396310327787845) internal successors, (17480), 12141 states have internal predecessors, (17480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12142 states to 12142 states and 17480 transitions. [2021-12-15 17:20:37,946 INFO L704 BuchiCegarLoop]: Abstraction has 12142 states and 17480 transitions. [2021-12-15 17:20:37,946 INFO L587 BuchiCegarLoop]: Abstraction has 12142 states and 17480 transitions. [2021-12-15 17:20:37,946 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:37,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12142 states and 17480 transitions. [2021-12-15 17:20:38,048 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11982 [2021-12-15 17:20:38,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,051 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,051 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,051 INFO L791 eck$LassoCheckResult]: Stem: 68552#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 68553#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 67806#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67807#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67843#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 68496#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68497#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68095#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68096#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68032#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68033#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68283#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68253#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68254#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68556#L854 assume !(0 == ~M_E~0); 68351#L854-2 assume !(0 == ~T1_E~0); 68352#L859-1 assume !(0 == ~T2_E~0); 67905#L864-1 assume !(0 == ~T3_E~0); 67906#L869-1 assume !(0 == ~T4_E~0); 68019#L874-1 assume !(0 == ~T5_E~0); 68806#L879-1 assume !(0 == ~T6_E~0); 68334#L884-1 assume !(0 == ~T7_E~0); 67775#L889-1 assume !(0 == ~T8_E~0); 67776#L894-1 assume !(0 == ~E_M~0); 68109#L899-1 assume !(0 == ~E_1~0); 68564#L904-1 assume !(0 == ~E_2~0); 68270#L909-1 assume !(0 == ~E_3~0); 68271#L914-1 assume !(0 == ~E_4~0); 68484#L919-1 assume !(0 == ~E_5~0); 68188#L924-1 assume !(0 == ~E_6~0); 68004#L929-1 assume !(0 == ~E_7~0); 68005#L934-1 assume !(0 == ~E_8~0); 68252#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67794#L418 assume !(1 == ~m_pc~0); 67765#L418-2 is_master_triggered_~__retres1~0#1 := 0; 68751#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68752#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68680#L1061 assume !(0 != activate_threads_~tmp~1#1); 68588#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68589#L437 assume !(1 == ~t1_pc~0); 68796#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68689#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68632#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68144#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 68145#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68671#L456 assume !(1 == ~t2_pc~0); 68060#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68059#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68411#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68412#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 68384#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67900#L475 assume !(1 == ~t3_pc~0); 67901#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67960#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67961#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68797#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 68148#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68149#L494 assume !(1 == ~t4_pc~0); 68184#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68185#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68402#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68403#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 68510#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67955#L513 assume 1 == ~t5_pc~0; 67956#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68187#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68223#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67916#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 67917#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67872#L532 assume !(1 == ~t6_pc~0); 67873#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68020#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68312#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68393#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 68114#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68115#L551 assume 1 == ~t7_pc~0; 68716#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68514#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68515#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68732#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 68846#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68292#L570 assume 1 == ~t8_pc~0; 68293#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68413#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68565#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68406#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 67894#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67895#L952 assume !(1 == ~M_E~0); 68695#L952-2 assume !(1 == ~T1_E~0); 68649#L957-1 assume !(1 == ~T2_E~0); 68650#L962-1 assume !(1 == ~T3_E~0); 68426#L967-1 assume !(1 == ~T4_E~0); 68427#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75390#L977-1 assume !(1 == ~T6_E~0); 68851#L982-1 assume !(1 == ~T7_E~0); 68852#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 68034#L992-1 assume !(1 == ~E_M~0); 68035#L997-1 assume !(1 == ~E_1~0); 68808#L1002-1 assume !(1 == ~E_2~0); 68809#L1007-1 assume !(1 == ~E_3~0); 67777#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 67778#L1017-1 assume !(1 == ~E_5~0); 68625#L1022-1 assume !(1 == ~E_6~0); 68394#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 68395#L1032-1 assume !(1 == ~E_8~0); 68541#L1037-1 assume { :end_inline_reset_delta_events } true; 68542#L1303-2 [2021-12-15 17:20:38,052 INFO L793 eck$LassoCheckResult]: Loop: 68542#L1303-2 assume !false; 68643#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67789#L829 assume !false; 68585#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 68169#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 68098#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 68524#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 68502#L712 assume !(0 != eval_~tmp~0#1); 68503#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79897#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79896#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 79895#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 79894#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79893#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79892#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79891#L874-3 assume !(0 == ~T5_E~0); 79890#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79889#L884-3 assume !(0 == ~T7_E~0); 68362#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67993#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67994#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68026#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68027#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67967#L914-3 assume !(0 == ~E_4~0); 67968#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 68015#L924-3 assume !(0 == ~E_6~0); 68593#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68485#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68486#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68629#L418-30 assume 1 == ~m_pc~0; 67859#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 67860#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79887#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 79886#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68056#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68057#L437-30 assume !(1 == ~t1_pc~0); 68186#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 68404#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68405#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68616#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68829#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68153#L456-30 assume !(1 == ~t2_pc~0); 68155#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 68582#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68583#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 67941#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67942#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79511#L475-30 assume !(1 == ~t3_pc~0); 70605#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 79083#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79082#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 79081#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 79080#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79079#L494-30 assume 1 == ~t4_pc~0; 79077#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79076#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79075#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79074#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 79073#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79072#L513-30 assume !(1 == ~t5_pc~0); 79071#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 79069#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79068#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79067#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 79066#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79065#L532-30 assume !(1 == ~t6_pc~0); 79063#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 79062#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79061#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79060#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 79059#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79058#L551-30 assume !(1 == ~t7_pc~0); 79057#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 79055#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 79054#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79053#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 79052#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79051#L570-30 assume !(1 == ~t8_pc~0); 79049#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 79046#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 79045#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79044#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68210#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68211#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 68247#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68776#L957-3 assume !(1 == ~T2_E~0); 68777#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68667#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68668#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68561#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68562#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 68856#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 68196#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68197#L997-3 assume !(1 == ~E_1~0); 68194#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68195#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68002#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68003#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68108#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68333#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 67811#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67812#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 68049#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 68050#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 67951#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 67952#L1322 assume !(0 == start_simulation_~tmp~3#1); 68225#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 67888#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 67889#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 68778#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 67795#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 67796#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68563#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 68721#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 68542#L1303-2 [2021-12-15 17:20:38,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,053 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2021-12-15 17:20:38,053 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514015255] [2021-12-15 17:20:38,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,122 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,122 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514015255] [2021-12-15 17:20:38,123 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514015255] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,123 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,123 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,123 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342828705] [2021-12-15 17:20:38,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,124 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,127 INFO L85 PathProgramCache]: Analyzing trace with hash -543518312, now seen corresponding path program 1 times [2021-12-15 17:20:38,127 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39079437] [2021-12-15 17:20:38,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,143 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39079437] [2021-12-15 17:20:38,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39079437] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,202 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387195589] [2021-12-15 17:20:38,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,203 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,204 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:38,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:38,205 INFO L87 Difference]: Start difference. First operand 12142 states and 17480 transitions. cyclomatic complexity: 5346 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,496 INFO L93 Difference]: Finished difference Result 28438 states and 40634 transitions. [2021-12-15 17:20:38,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:38,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28438 states and 40634 transitions. [2021-12-15 17:20:38,655 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 28215 [2021-12-15 17:20:38,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28438 states to 28438 states and 40634 transitions. [2021-12-15 17:20:38,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28438 [2021-12-15 17:20:38,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28438 [2021-12-15 17:20:38,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28438 states and 40634 transitions. [2021-12-15 17:20:38,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,997 INFO L681 BuchiCegarLoop]: Abstraction has 28438 states and 40634 transitions. [2021-12-15 17:20:39,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28438 states and 40634 transitions. [2021-12-15 17:20:39,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28438 to 22883. [2021-12-15 17:20:39,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22883 states, 22883 states have (on average 1.4331599877638421) internal successors, (32795), 22882 states have internal predecessors, (32795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22883 states to 22883 states and 32795 transitions. [2021-12-15 17:20:39,476 INFO L704 BuchiCegarLoop]: Abstraction has 22883 states and 32795 transitions. [2021-12-15 17:20:39,476 INFO L587 BuchiCegarLoop]: Abstraction has 22883 states and 32795 transitions. [2021-12-15 17:20:39,476 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:39,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22883 states and 32795 transitions. [2021-12-15 17:20:39,557 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22716 [2021-12-15 17:20:39,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:39,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:39,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,560 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,560 INFO L791 eck$LassoCheckResult]: Stem: 109175#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 109176#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 108397#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 108398#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108434#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 109108#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109109#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108686#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108687#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 108622#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 108623#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 108882#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 108854#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 108855#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 109181#L854 assume !(0 == ~M_E~0); 108952#L854-2 assume !(0 == ~T1_E~0); 108953#L859-1 assume !(0 == ~T2_E~0); 108496#L864-1 assume !(0 == ~T3_E~0); 108497#L869-1 assume !(0 == ~T4_E~0); 108611#L874-1 assume !(0 == ~T5_E~0); 109482#L879-1 assume !(0 == ~T6_E~0); 108938#L884-1 assume !(0 == ~T7_E~0); 108364#L889-1 assume !(0 == ~T8_E~0); 108365#L894-1 assume !(0 == ~E_M~0); 108701#L899-1 assume !(0 == ~E_1~0); 109188#L904-1 assume !(0 == ~E_2~0); 108869#L909-1 assume !(0 == ~E_3~0); 108870#L914-1 assume !(0 == ~E_4~0); 109096#L919-1 assume !(0 == ~E_5~0); 108786#L924-1 assume !(0 == ~E_6~0); 108593#L929-1 assume !(0 == ~E_7~0); 108594#L934-1 assume !(0 == ~E_8~0); 108851#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108385#L418 assume !(1 == ~m_pc~0); 108354#L418-2 is_master_triggered_~__retres1~0#1 := 0; 109405#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109406#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 109326#L1061 assume !(0 != activate_threads_~tmp~1#1); 109219#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109220#L437 assume !(1 == ~t1_pc~0); 109467#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 109334#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109273#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 108739#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 108740#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109316#L456 assume !(1 == ~t2_pc~0); 108651#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 108650#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109022#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 109023#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 108995#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108491#L475 assume !(1 == ~t3_pc~0); 108492#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 108550#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108551#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109468#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 108743#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108744#L494 assume !(1 == ~t4_pc~0); 108781#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 108782#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109013#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 109014#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 109123#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108545#L513 assume !(1 == ~t5_pc~0); 108546#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 108783#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108821#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 108507#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 108508#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 108461#L532 assume !(1 == ~t6_pc~0); 108462#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 108612#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 108911#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109006#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 108706#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 108707#L551 assume 1 == ~t7_pc~0; 109366#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 109130#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109131#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 109386#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 109553#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108893#L570 assume 1 == ~t8_pc~0; 108894#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 109024#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 109190#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 109018#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 108485#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108486#L952 assume !(1 == ~M_E~0); 109338#L952-2 assume !(1 == ~T1_E~0); 109295#L957-1 assume !(1 == ~T2_E~0); 109296#L962-1 assume !(1 == ~T3_E~0); 109037#L967-1 assume !(1 == ~T4_E~0); 109038#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117929#L977-1 assume !(1 == ~T6_E~0); 109555#L982-1 assume !(1 == ~T7_E~0); 109556#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 108624#L992-1 assume !(1 == ~E_M~0); 108625#L997-1 assume !(1 == ~E_1~0); 109484#L1002-1 assume !(1 == ~E_2~0); 109485#L1007-1 assume !(1 == ~E_3~0); 108366#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 108367#L1017-1 assume !(1 == ~E_5~0); 109267#L1022-1 assume !(1 == ~E_6~0); 109007#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 109008#L1032-1 assume !(1 == ~E_8~0); 109159#L1037-1 assume { :end_inline_reset_delta_events } true; 109160#L1303-2 [2021-12-15 17:20:39,560 INFO L793 eck$LassoCheckResult]: Loop: 109160#L1303-2 assume !false; 119556#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119552#L829 assume !false; 119551#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 119479#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 119466#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 119460#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 119453#L712 assume !(0 != eval_~tmp~0#1); 119454#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121701#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121700#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 121699#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 121698#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 121697#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121696#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121695#L874-3 assume !(0 == ~T5_E~0); 121694#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 121693#L884-3 assume !(0 == ~T7_E~0); 121692#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 121691#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 121690#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121689#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121688#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 121687#L914-3 assume !(0 == ~E_4~0); 121686#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121685#L924-3 assume !(0 == ~E_6~0); 121684#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 121683#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 121682#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121681#L418-30 assume !(1 == ~m_pc~0); 121680#L418-32 is_master_triggered_~__retres1~0#1 := 0; 121678#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121676#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121674#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 121672#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121671#L437-30 assume !(1 == ~t1_pc~0); 121670#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 121669#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121668#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121664#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 121663#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121662#L456-30 assume !(1 == ~t2_pc~0); 121661#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 121659#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121658#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121657#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 121656#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109451#L475-30 assume !(1 == ~t3_pc~0); 109452#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 120620#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120615#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 120612#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 120609#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120606#L494-30 assume !(1 == ~t4_pc~0); 120603#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 120599#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120597#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 120594#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 120591#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120587#L513-30 assume !(1 == ~t5_pc~0); 114867#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 120582#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120578#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 120573#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 120571#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120569#L532-30 assume !(1 == ~t6_pc~0); 120565#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 120561#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 120557#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 120551#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 120545#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 120540#L551-30 assume !(1 == ~t7_pc~0); 120535#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 120530#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120525#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 120522#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 120519#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 120443#L570-30 assume !(1 == ~t8_pc~0); 120435#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 120429#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 120422#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 120416#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 120410#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120404#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 118031#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 120391#L957-3 assume !(1 == ~T2_E~0); 120384#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 120378#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 120372#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 118019#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 120360#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 120352#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 120347#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 120344#L997-3 assume !(1 == ~E_1~0); 120315#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 120311#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 120293#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119257#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 120280#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 120274#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 120268#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 120263#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 120212#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 120203#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 120194#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 109839#L1322 assume !(0 == start_simulation_~tmp~3#1); 109840#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 119682#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 119673#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 119671#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 119669#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 119667#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 119665#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 119662#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 109160#L1303-2 [2021-12-15 17:20:39,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,561 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2021-12-15 17:20:39,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002095457] [2021-12-15 17:20:39,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,595 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002095457] [2021-12-15 17:20:39,595 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002095457] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,595 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149659439] [2021-12-15 17:20:39,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,596 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:39,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1790010852, now seen corresponding path program 1 times [2021-12-15 17:20:39,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393254548] [2021-12-15 17:20:39,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,621 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,621 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393254548] [2021-12-15 17:20:39,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393254548] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,622 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512568170] [2021-12-15 17:20:39,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,623 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:39,623 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:39,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:39,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:39,624 INFO L87 Difference]: Start difference. First operand 22883 states and 32795 transitions. cyclomatic complexity: 9920 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:40,131 INFO L93 Difference]: Finished difference Result 53212 states and 75754 transitions. [2021-12-15 17:20:40,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:40,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53212 states and 75754 transitions. [2021-12-15 17:20:40,410 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 52918 [2021-12-15 17:20:40,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53212 states to 53212 states and 75754 transitions. [2021-12-15 17:20:40,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53212 [2021-12-15 17:20:40,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53212 [2021-12-15 17:20:40,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53212 states and 75754 transitions. [2021-12-15 17:20:40,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:40,889 INFO L681 BuchiCegarLoop]: Abstraction has 53212 states and 75754 transitions. [2021-12-15 17:20:40,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53212 states and 75754 transitions. [2021-12-15 17:20:41,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53212 to 43150. [2021-12-15 17:20:41,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43150 states, 43150 states have (on average 1.4276709154113558) internal successors, (61604), 43149 states have internal predecessors, (61604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43150 states to 43150 states and 61604 transitions. [2021-12-15 17:20:41,607 INFO L704 BuchiCegarLoop]: Abstraction has 43150 states and 61604 transitions. [2021-12-15 17:20:41,607 INFO L587 BuchiCegarLoop]: Abstraction has 43150 states and 61604 transitions. [2021-12-15 17:20:41,607 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:41,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43150 states and 61604 transitions. [2021-12-15 17:20:41,893 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 42968 [2021-12-15 17:20:41,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:41,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:41,897 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,897 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,897 INFO L791 eck$LassoCheckResult]: Stem: 185276#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 185277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 184499#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 184500#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 184537#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 185212#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 185213#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 184788#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 184789#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 184725#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 184726#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 184981#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 184954#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 184955#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 185281#L854 assume !(0 == ~M_E~0); 185049#L854-2 assume !(0 == ~T1_E~0); 185050#L859-1 assume !(0 == ~T2_E~0); 184601#L864-1 assume !(0 == ~T3_E~0); 184602#L869-1 assume !(0 == ~T4_E~0); 184714#L874-1 assume !(0 == ~T5_E~0); 185574#L879-1 assume !(0 == ~T6_E~0); 185036#L884-1 assume !(0 == ~T7_E~0); 184469#L889-1 assume !(0 == ~T8_E~0); 184470#L894-1 assume !(0 == ~E_M~0); 184805#L899-1 assume !(0 == ~E_1~0); 185289#L904-1 assume !(0 == ~E_2~0); 184969#L909-1 assume !(0 == ~E_3~0); 184970#L914-1 assume !(0 == ~E_4~0); 185198#L919-1 assume !(0 == ~E_5~0); 184889#L924-1 assume !(0 == ~E_6~0); 184697#L929-1 assume !(0 == ~E_7~0); 184698#L934-1 assume !(0 == ~E_8~0); 184951#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 184488#L418 assume !(1 == ~m_pc~0); 184459#L418-2 is_master_triggered_~__retres1~0#1 := 0; 185497#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185498#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 185418#L1061 assume !(0 != activate_threads_~tmp~1#1); 185315#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185316#L437 assume !(1 == ~t1_pc~0); 185558#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 185427#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185368#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 184842#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 184843#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185409#L456 assume !(1 == ~t2_pc~0); 184751#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 184750#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185115#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 185116#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 185087#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 184596#L475 assume !(1 == ~t3_pc~0); 184597#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 184655#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 184656#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 185559#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 184846#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184847#L494 assume !(1 == ~t4_pc~0); 184885#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 184886#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 185104#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 185105#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 185227#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 184651#L513 assume !(1 == ~t5_pc~0); 184652#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 184887#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 184925#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 184612#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 184613#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 184564#L532 assume !(1 == ~t6_pc~0); 184565#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 184715#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 185009#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 185097#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 184810#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 184811#L551 assume !(1 == ~t7_pc~0); 185292#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 185231#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 185232#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 185474#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 185643#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 184992#L570 assume 1 == ~t8_pc~0; 184993#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 185117#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 185291#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 185110#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 184590#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184591#L952 assume !(1 == ~M_E~0); 185431#L952-2 assume !(1 == ~T1_E~0); 185387#L957-1 assume !(1 == ~T2_E~0); 185388#L962-1 assume !(1 == ~T3_E~0); 185133#L967-1 assume !(1 == ~T4_E~0); 185134#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215611#L977-1 assume !(1 == ~T6_E~0); 185646#L982-1 assume !(1 == ~T7_E~0); 185647#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 184727#L992-1 assume !(1 == ~E_M~0); 184728#L997-1 assume !(1 == ~E_1~0); 185577#L1002-1 assume !(1 == ~E_2~0); 185578#L1007-1 assume !(1 == ~E_3~0); 184471#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 184472#L1017-1 assume !(1 == ~E_5~0); 185073#L1022-1 assume !(1 == ~E_6~0); 185074#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 185579#L1032-1 assume !(1 == ~E_8~0); 185260#L1037-1 assume { :end_inline_reset_delta_events } true; 185261#L1303-2 [2021-12-15 17:20:41,898 INFO L793 eck$LassoCheckResult]: Loop: 185261#L1303-2 assume !false; 222849#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 222846#L829 assume !false; 222844#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 219962#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 219956#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 219939#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 219921#L712 assume !(0 != eval_~tmp~0#1); 219922#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 227600#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 227598#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 227596#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 227594#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 227592#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 227589#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 227588#L874-3 assume !(0 == ~T5_E~0); 227586#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 227584#L884-3 assume !(0 == ~T7_E~0); 227583#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 227581#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 227580#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 227574#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 227573#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 227571#L914-3 assume !(0 == ~E_4~0); 227569#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 227568#L924-3 assume !(0 == ~E_6~0); 227566#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 227564#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 227563#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227562#L418-30 assume !(1 == ~m_pc~0); 227561#L418-32 is_master_triggered_~__retres1~0#1 := 0; 227559#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227557#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 227538#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 227532#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 227529#L437-30 assume !(1 == ~t1_pc~0); 227398#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 227378#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 227377#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 227291#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 227290#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 227289#L456-30 assume 1 == ~t2_pc~0; 227287#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 227285#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227283#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 227193#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 226976#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224796#L475-30 assume !(1 == ~t3_pc~0); 224794#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 224792#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224789#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 224787#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 224785#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224783#L494-30 assume !(1 == ~t4_pc~0); 224781#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 224778#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224777#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 224775#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 224773#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 185649#L513-30 assume !(1 == ~t5_pc~0); 185650#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 223014#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223012#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 223010#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223008#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223006#L532-30 assume 1 == ~t6_pc~0; 223003#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 223000#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222998#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222996#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 222994#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 222992#L551-30 assume !(1 == ~t7_pc~0); 192890#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 222990#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 222988#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222986#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 222984#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 222982#L570-30 assume 1 == ~t8_pc~0; 222979#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 222976#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 222974#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 222972#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 222970#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 222968#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 215723#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 222965#L957-3 assume !(1 == ~T2_E~0); 222963#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 222961#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 222959#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215711#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 222956#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 222954#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 222952#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 222950#L997-3 assume !(1 == ~E_1~0); 222948#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 222946#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 222944#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 218449#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 222941#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 222939#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 222937#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 222936#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 222887#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 222886#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 222885#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 222882#L1322 assume !(0 == start_simulation_~tmp~3#1); 222880#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 222876#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 222867#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 222865#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 222863#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222860#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 222858#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 222856#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 185261#L1303-2 [2021-12-15 17:20:41,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,898 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2021-12-15 17:20:41,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024368782] [2021-12-15 17:20:41,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,930 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024368782] [2021-12-15 17:20:41,930 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024368782] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,930 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015414172] [2021-12-15 17:20:41,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,931 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:41,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,932 INFO L85 PathProgramCache]: Analyzing trace with hash 2074472409, now seen corresponding path program 1 times [2021-12-15 17:20:41,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420104267] [2021-12-15 17:20:41,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420104267] [2021-12-15 17:20:41,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1420104267] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624950930] [2021-12-15 17:20:41,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:41,963 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:41,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:41,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:41,964 INFO L87 Difference]: Start difference. First operand 43150 states and 61604 transitions. cyclomatic complexity: 18462 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:42,759 INFO L93 Difference]: Finished difference Result 99777 states and 141605 transitions. [2021-12-15 17:20:42,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:42,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99777 states and 141605 transitions. [2021-12-15 17:20:43,424 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 99340 [2021-12-15 17:20:43,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99777 states to 99777 states and 141605 transitions. [2021-12-15 17:20:43,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99777 [2021-12-15 17:20:43,916 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99777 [2021-12-15 17:20:43,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99777 states and 141605 transitions. [2021-12-15 17:20:43,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,986 INFO L681 BuchiCegarLoop]: Abstraction has 99777 states and 141605 transitions. [2021-12-15 17:20:44,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99777 states and 141605 transitions. [2021-12-15 17:20:44,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99777 to 81285. [2021-12-15 17:20:44,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81285 states, 81285 states have (on average 1.4230546841360645) internal successors, (115673), 81284 states have internal predecessors, (115673), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:45,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81285 states to 81285 states and 115673 transitions. [2021-12-15 17:20:45,152 INFO L704 BuchiCegarLoop]: Abstraction has 81285 states and 115673 transitions. [2021-12-15 17:20:45,152 INFO L587 BuchiCegarLoop]: Abstraction has 81285 states and 115673 transitions. [2021-12-15 17:20:45,152 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:45,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81285 states and 115673 transitions. [2021-12-15 17:20:45,403 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 81072 [2021-12-15 17:20:45,403 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:45,403 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:45,408 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,408 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,408 INFO L791 eck$LassoCheckResult]: Stem: 328200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 328201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 327437#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 327438#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 327472#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 328143#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 328144#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 327730#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 327731#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 327664#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 327665#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 327928#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 327899#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 327900#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 328205#L854 assume !(0 == ~M_E~0); 327993#L854-2 assume !(0 == ~T1_E~0); 327994#L859-1 assume !(0 == ~T2_E~0); 327536#L864-1 assume !(0 == ~T3_E~0); 327537#L869-1 assume !(0 == ~T4_E~0); 327651#L874-1 assume !(0 == ~T5_E~0); 328499#L879-1 assume !(0 == ~T6_E~0); 327977#L884-1 assume !(0 == ~T7_E~0); 327405#L889-1 assume !(0 == ~T8_E~0); 327406#L894-1 assume !(0 == ~E_M~0); 327744#L899-1 assume !(0 == ~E_1~0); 328213#L904-1 assume !(0 == ~E_2~0); 327919#L909-1 assume !(0 == ~E_3~0); 327920#L914-1 assume !(0 == ~E_4~0); 328129#L919-1 assume !(0 == ~E_5~0); 327830#L924-1 assume !(0 == ~E_6~0); 327638#L929-1 assume !(0 == ~E_7~0); 327639#L934-1 assume !(0 == ~E_8~0); 327898#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 327423#L418 assume !(1 == ~m_pc~0); 327398#L418-2 is_master_triggered_~__retres1~0#1 := 0; 328432#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 328433#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 328344#L1061 assume !(0 != activate_threads_~tmp~1#1); 328241#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 328242#L437 assume !(1 == ~t1_pc~0); 328488#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 328354#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 328292#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 327783#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 327784#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 328338#L456 assume !(1 == ~t2_pc~0); 327692#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 327691#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328054#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 328055#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 328028#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 327531#L475 assume !(1 == ~t3_pc~0); 327532#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 327593#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 327594#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 328489#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 327787#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 327788#L494 assume !(1 == ~t4_pc~0); 327825#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 327826#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 328046#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 328047#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 328157#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 327589#L513 assume !(1 == ~t5_pc~0); 327590#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 327829#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 327868#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 327547#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 327548#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 327501#L532 assume !(1 == ~t6_pc~0); 327502#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 327652#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 327955#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 328038#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 327749#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 327750#L551 assume !(1 == ~t7_pc~0); 328215#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 328161#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 328162#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 328405#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 328568#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 327938#L570 assume !(1 == ~t8_pc~0); 327939#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 328464#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 328214#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 328052#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 327529#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 327530#L952 assume !(1 == ~M_E~0); 328362#L952-2 assume !(1 == ~T1_E~0); 328315#L957-1 assume !(1 == ~T2_E~0); 328316#L962-1 assume !(1 == ~T3_E~0); 328068#L967-1 assume !(1 == ~T4_E~0); 328069#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 351607#L977-1 assume !(1 == ~T6_E~0); 351606#L982-1 assume !(1 == ~T7_E~0); 351605#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 351604#L992-1 assume !(1 == ~E_M~0); 351603#L997-1 assume !(1 == ~E_1~0); 351602#L1002-1 assume !(1 == ~E_2~0); 351601#L1007-1 assume !(1 == ~E_3~0); 351600#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 327408#L1017-1 assume !(1 == ~E_5~0); 328285#L1022-1 assume !(1 == ~E_6~0); 328039#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 328040#L1032-1 assume !(1 == ~E_8~0); 328188#L1037-1 assume { :end_inline_reset_delta_events } true; 328189#L1303-2 [2021-12-15 17:20:45,409 INFO L793 eck$LassoCheckResult]: Loop: 328189#L1303-2 assume !false; 360739#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 360738#L829 assume !false; 360735#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 360721#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 360715#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 360713#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 355892#L712 assume !(0 != eval_~tmp~0#1); 355893#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 367006#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 367001#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 366996#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 366990#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 366981#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 366973#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 366965#L874-3 assume !(0 == ~T5_E~0); 366957#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 366950#L884-3 assume !(0 == ~T7_E~0); 366943#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 366938#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 366933#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 366927#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 366922#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 366647#L914-3 assume !(0 == ~E_4~0); 366562#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 366561#L924-3 assume !(0 == ~E_6~0); 366560#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 366559#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 366557#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 366556#L418-30 assume 1 == ~m_pc~0; 366555#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 366553#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 366551#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 366548#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 366547#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 366546#L437-30 assume !(1 == ~t1_pc~0); 366545#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 366544#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366542#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 366540#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 366538#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 366536#L456-30 assume 1 == ~t2_pc~0; 366533#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 366531#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 366529#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 366527#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 366525#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 366523#L475-30 assume !(1 == ~t3_pc~0); 365905#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 366520#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 366518#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 366516#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 366514#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 366512#L494-30 assume 1 == ~t4_pc~0; 366509#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 366507#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 366505#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 366503#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 366499#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 366497#L513-30 assume !(1 == ~t5_pc~0); 358711#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 366494#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 366491#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 366489#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 366487#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 366485#L532-30 assume !(1 == ~t6_pc~0); 366441#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 366414#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 366406#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 366398#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 366390#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 361163#L551-30 assume !(1 == ~t7_pc~0); 361162#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 361160#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 361158#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 361156#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 361154#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 361152#L570-30 assume !(1 == ~t8_pc~0); 335632#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 361148#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 361146#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 361144#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 361142#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 361138#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 351831#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 361135#L957-3 assume !(1 == ~T2_E~0); 361133#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 361131#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 361129#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 355432#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 361127#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 361125#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 361123#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 361121#L997-3 assume !(1 == ~E_1~0); 361119#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 361117#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 361115#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 351788#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 361112#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 361110#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 361108#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 361106#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 361088#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 361086#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 361084#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 361083#L1322 assume !(0 == start_simulation_~tmp~3#1); 361081#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 361075#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 361066#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 361064#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 361061#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 361059#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 361057#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 361055#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 328189#L1303-2 [2021-12-15 17:20:45,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2021-12-15 17:20:45,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803120086] [2021-12-15 17:20:45,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,410 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:45,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:45,444 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:45,444 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803120086] [2021-12-15 17:20:45,444 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803120086] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:45,444 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:45,444 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:45,445 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408515741] [2021-12-15 17:20:45,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:45,445 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:45,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,446 INFO L85 PathProgramCache]: Analyzing trace with hash 1619460951, now seen corresponding path program 1 times [2021-12-15 17:20:45,446 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607278648] [2021-12-15 17:20:45,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,446 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:45,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:45,479 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:45,480 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607278648] [2021-12-15 17:20:45,480 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607278648] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:45,480 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:45,480 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:45,480 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429350958] [2021-12-15 17:20:45,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:45,481 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:45,481 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:45,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:45,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:45,482 INFO L87 Difference]: Start difference. First operand 81285 states and 115673 transitions. cyclomatic complexity: 34396 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:46,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:46,028 INFO L93 Difference]: Finished difference Result 62166 states and 88267 transitions. [2021-12-15 17:20:46,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:46,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62166 states and 88267 transitions. [2021-12-15 17:20:46,310 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 62000 [2021-12-15 17:20:46,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62166 states to 62166 states and 88267 transitions. [2021-12-15 17:20:46,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62166 [2021-12-15 17:20:46,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62166 [2021-12-15 17:20:46,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62166 states and 88267 transitions. [2021-12-15 17:20:46,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:46,628 INFO L681 BuchiCegarLoop]: Abstraction has 62166 states and 88267 transitions. [2021-12-15 17:20:46,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62166 states and 88267 transitions. [2021-12-15 17:20:47,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62166 to 43073. [2021-12-15 17:20:47,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43073 states, 43073 states have (on average 1.4201471919764121) internal successors, (61170), 43072 states have internal predecessors, (61170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:47,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43073 states to 43073 states and 61170 transitions. [2021-12-15 17:20:47,434 INFO L704 BuchiCegarLoop]: Abstraction has 43073 states and 61170 transitions. [2021-12-15 17:20:47,435 INFO L587 BuchiCegarLoop]: Abstraction has 43073 states and 61170 transitions. [2021-12-15 17:20:47,435 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:20:47,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43073 states and 61170 transitions. [2021-12-15 17:20:47,573 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 42928 [2021-12-15 17:20:47,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:47,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:47,576 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,576 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,576 INFO L791 eck$LassoCheckResult]: Stem: 471681#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 471682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 470897#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 470898#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 470935#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 471617#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 471618#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 471184#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 471185#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 471126#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 471127#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 471391#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 471361#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 471362#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 471686#L854 assume !(0 == ~M_E~0); 471460#L854-2 assume !(0 == ~T1_E~0); 471461#L859-1 assume !(0 == ~T2_E~0); 470999#L864-1 assume !(0 == ~T3_E~0); 471000#L869-1 assume !(0 == ~T4_E~0); 471114#L874-1 assume !(0 == ~T5_E~0); 471976#L879-1 assume !(0 == ~T6_E~0); 471447#L884-1 assume !(0 == ~T7_E~0); 470866#L889-1 assume !(0 == ~T8_E~0); 470867#L894-1 assume !(0 == ~E_M~0); 471201#L899-1 assume !(0 == ~E_1~0); 471693#L904-1 assume !(0 == ~E_2~0); 471378#L909-1 assume !(0 == ~E_3~0); 471379#L914-1 assume !(0 == ~E_4~0); 471604#L919-1 assume !(0 == ~E_5~0); 471291#L924-1 assume !(0 == ~E_6~0); 471096#L929-1 assume !(0 == ~E_7~0); 471097#L934-1 assume !(0 == ~E_8~0); 471358#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 470886#L418 assume !(1 == ~m_pc~0); 470857#L418-2 is_master_triggered_~__retres1~0#1 := 0; 472034#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 472037#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 471828#L1061 assume !(0 != activate_threads_~tmp~1#1); 471725#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 471726#L437 assume !(1 == ~t1_pc~0); 471962#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 471838#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 471774#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 471242#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 471243#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 471818#L456 assume !(1 == ~t2_pc~0); 471150#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 471149#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 471522#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 471523#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 471497#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 470994#L475 assume !(1 == ~t3_pc~0); 470995#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 471054#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 471055#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 471964#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 471246#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 471247#L494 assume !(1 == ~t4_pc~0); 471286#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 471287#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 471512#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 471513#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 471632#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 471049#L513 assume !(1 == ~t5_pc~0); 471050#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 471288#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 471330#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 471010#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 471011#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 470962#L532 assume !(1 == ~t6_pc~0); 470963#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 471115#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 471421#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 471506#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 471208#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 471209#L551 assume !(1 == ~t7_pc~0); 471696#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 471637#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 471638#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 471885#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 472056#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 471405#L570 assume !(1 == ~t8_pc~0); 471406#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 471934#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 471695#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 471518#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 470988#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 470989#L952 assume !(1 == ~M_E~0); 470936#L952-2 assume !(1 == ~T1_E~0); 470937#L957-1 assume !(1 == ~T2_E~0); 471797#L962-1 assume !(1 == ~T3_E~0); 471537#L967-1 assume !(1 == ~T4_E~0); 471538#L972-1 assume !(1 == ~T5_E~0); 471867#L977-1 assume !(1 == ~T6_E~0); 471868#L982-1 assume !(1 == ~T7_E~0); 471118#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 471119#L992-1 assume !(1 == ~E_M~0); 471128#L997-1 assume !(1 == ~E_1~0); 471495#L1002-1 assume !(1 == ~E_2~0); 471483#L1007-1 assume !(1 == ~E_3~0); 470868#L1012-1 assume !(1 == ~E_4~0); 470869#L1017-1 assume !(1 == ~E_5~0); 471484#L1022-1 assume !(1 == ~E_6~0); 471485#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 471507#L1032-1 assume !(1 == ~E_8~0); 471666#L1037-1 assume { :end_inline_reset_delta_events } true; 471667#L1303-2 [2021-12-15 17:20:47,577 INFO L793 eck$LassoCheckResult]: Loop: 471667#L1303-2 assume !false; 490073#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 490070#L829 assume !false; 490068#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 490056#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 490050#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 490047#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 490044#L712 assume !(0 != eval_~tmp~0#1); 490045#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 513834#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 513832#L854-3 assume !(0 == ~M_E~0); 471627#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 471628#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 472046#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 471970#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 471971#L874-3 assume !(0 == ~T5_E~0); 513672#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 513671#L884-3 assume !(0 == ~T7_E~0); 513670#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 513669#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 513668#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 513667#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 513666#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 512985#L914-3 assume !(0 == ~E_4~0); 512984#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 512981#L924-3 assume !(0 == ~E_6~0); 512979#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 512977#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 512975#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 512972#L418-30 assume !(1 == ~m_pc~0); 512969#L418-32 is_master_triggered_~__retres1~0#1 := 0; 512965#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 512961#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 512958#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 512953#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 512947#L437-30 assume !(1 == ~t1_pc~0); 512941#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 512935#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 512928#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 512922#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 512918#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 512912#L456-30 assume !(1 == ~t2_pc~0); 512908#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 512902#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 512898#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 512894#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 512878#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 512874#L475-30 assume !(1 == ~t3_pc~0); 490485#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 512870#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 512439#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 512237#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 512236#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 512235#L494-30 assume 1 == ~t4_pc~0; 512231#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 512229#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 512228#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 512227#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 512225#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 512224#L513-30 assume !(1 == ~t5_pc~0); 483615#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 512223#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 512222#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 512221#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 512219#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 512217#L532-30 assume 1 == ~t6_pc~0; 512213#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 512210#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 512208#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 512206#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 511408#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 488032#L551-30 assume !(1 == ~t7_pc~0); 488030#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 488028#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 488025#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 488023#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 488021#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488019#L570-30 assume !(1 == ~t8_pc~0); 483296#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 488016#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 488013#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 488011#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 488009#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 488007#L952-3 assume !(1 == ~M_E~0); 488005#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 488003#L957-3 assume !(1 == ~T2_E~0); 488002#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 487999#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 487997#L972-3 assume !(1 == ~T5_E~0); 487995#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 487993#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 487991#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 487990#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 487986#L997-3 assume !(1 == ~E_1~0); 487984#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 487982#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 487981#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 487977#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 487976#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 487973#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 487971#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 487969#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 487955#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 487951#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 486142#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 482112#L1322 assume !(0 == start_simulation_~tmp~3#1); 482113#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 490133#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 490124#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 490122#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 490120#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 490119#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 490117#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 490115#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 471667#L1303-2 [2021-12-15 17:20:47,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,577 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2021-12-15 17:20:47,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427770558] [2021-12-15 17:20:47,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,578 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:47,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:47,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:47,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427770558] [2021-12-15 17:20:47,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1427770558] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:47,610 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:47,611 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:47,611 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [572645812] [2021-12-15 17:20:47,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:47,611 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:47,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,612 INFO L85 PathProgramCache]: Analyzing trace with hash -2133812840, now seen corresponding path program 1 times [2021-12-15 17:20:47,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133895425] [2021-12-15 17:20:47,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:47,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:47,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:47,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133895425] [2021-12-15 17:20:47,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133895425] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:47,641 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:47,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:47,641 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017013830] [2021-12-15 17:20:47,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:47,642 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:47,642 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:47,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:47,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:47,643 INFO L87 Difference]: Start difference. First operand 43073 states and 61170 transitions. cyclomatic complexity: 18101 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:48,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:48,152 INFO L93 Difference]: Finished difference Result 68587 states and 97364 transitions. [2021-12-15 17:20:48,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:48,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68587 states and 97364 transitions. [2021-12-15 17:20:48,403 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 68336 [2021-12-15 17:20:48,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68587 states to 68587 states and 97364 transitions. [2021-12-15 17:20:48,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68587 [2021-12-15 17:20:48,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68587 [2021-12-15 17:20:48,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68587 states and 97364 transitions. [2021-12-15 17:20:48,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:48,604 INFO L681 BuchiCegarLoop]: Abstraction has 68587 states and 97364 transitions. [2021-12-15 17:20:48,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68587 states and 97364 transitions. [2021-12-15 17:20:49,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68587 to 48433. [2021-12-15 17:20:49,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48433 states, 48433 states have (on average 1.4218611277434807) internal successors, (68865), 48432 states have internal predecessors, (68865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:49,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48433 states to 48433 states and 68865 transitions. [2021-12-15 17:20:49,351 INFO L704 BuchiCegarLoop]: Abstraction has 48433 states and 68865 transitions. [2021-12-15 17:20:49,351 INFO L587 BuchiCegarLoop]: Abstraction has 48433 states and 68865 transitions. [2021-12-15 17:20:49,351 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:20:49,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48433 states and 68865 transitions. [2021-12-15 17:20:49,490 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48208 [2021-12-15 17:20:49,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:49,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:49,493 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:49,493 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:49,493 INFO L791 eck$LassoCheckResult]: Stem: 583347#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 583348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 582571#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 582572#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 582606#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 583282#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 583283#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 582862#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 582863#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 582799#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 582800#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 583061#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 583029#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 583030#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 583350#L854 assume !(0 == ~M_E~0); 583126#L854-2 assume !(0 == ~T1_E~0); 583127#L859-1 assume !(0 == ~T2_E~0); 582670#L864-1 assume !(0 == ~T3_E~0); 582671#L869-1 assume !(0 == ~T4_E~0); 582785#L874-1 assume !(0 == ~T5_E~0); 583656#L879-1 assume !(0 == ~T6_E~0); 583109#L884-1 assume !(0 == ~T7_E~0); 582536#L889-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 582537#L894-1 assume !(0 == ~E_M~0); 582875#L899-1 assume !(0 == ~E_1~0); 583359#L904-1 assume !(0 == ~E_2~0); 583360#L909-1 assume !(0 == ~E_3~0); 583268#L914-1 assume !(0 == ~E_4~0); 583269#L919-1 assume !(0 == ~E_5~0); 582960#L924-1 assume !(0 == ~E_6~0); 582961#L929-1 assume !(0 == ~E_7~0); 583668#L934-1 assume !(0 == ~E_8~0); 583669#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 582555#L418 assume !(1 == ~m_pc~0); 582556#L418-2 is_master_triggered_~__retres1~0#1 := 0; 583779#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 583777#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 583774#L1061 assume !(0 != activate_threads_~tmp~1#1); 583773#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 583702#L437 assume !(1 == ~t1_pc~0); 583703#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 583501#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 583502#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 582913#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 582914#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 583483#L456 assume !(1 == ~t2_pc~0); 583484#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 583693#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 583694#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 583533#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 583534#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 582665#L475 assume !(1 == ~t3_pc~0); 582666#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 582727#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 582728#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 583642#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 583643#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 583578#L494 assume !(1 == ~t4_pc~0); 583579#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 583240#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 583241#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 583736#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 583737#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 582723#L513 assume !(1 == ~t5_pc~0); 582724#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 583714#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 583715#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 582681#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 582682#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 582635#L532 assume !(1 == ~t6_pc~0); 582636#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 583087#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 583088#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 583676#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 583677#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 583538#L551 assume !(1 == ~t7_pc~0); 583539#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 583304#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 583305#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 583772#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 583733#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 583071#L570 assume !(1 == ~t8_pc~0); 583072#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 583612#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 583613#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 583770#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 583769#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 583768#L952 assume !(1 == ~M_E~0); 583767#L952-2 assume !(1 == ~T1_E~0); 583766#L957-1 assume !(1 == ~T2_E~0); 583765#L962-1 assume !(1 == ~T3_E~0); 583764#L967-1 assume !(1 == ~T4_E~0); 583763#L972-1 assume !(1 == ~T5_E~0); 583762#L977-1 assume !(1 == ~T6_E~0); 583761#L982-1 assume !(1 == ~T7_E~0); 583760#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 582791#L992-1 assume !(1 == ~E_M~0); 582801#L997-1 assume !(1 == ~E_1~0); 583157#L1002-1 assume !(1 == ~E_2~0); 583145#L1007-1 assume !(1 == ~E_3~0); 582539#L1012-1 assume !(1 == ~E_4~0); 582540#L1017-1 assume !(1 == ~E_5~0); 583148#L1022-1 assume !(1 == ~E_6~0); 583149#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 583172#L1032-1 assume !(1 == ~E_8~0); 583334#L1037-1 assume { :end_inline_reset_delta_events } true; 583335#L1303-2 [2021-12-15 17:20:49,495 INFO L793 eck$LassoCheckResult]: Loop: 583335#L1303-2 assume !false; 603754#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 603748#L829 assume !false; 603742#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 603731#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 603722#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 603716#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 603710#L712 assume !(0 != eval_~tmp~0#1); 603704#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 603699#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 603692#L854-3 assume !(0 == ~M_E~0); 603687#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 603681#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 603676#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 603672#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 603667#L874-3 assume !(0 == ~T5_E~0); 603662#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 603649#L884-3 assume !(0 == ~T7_E~0); 603643#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 603642#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 603641#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 603640#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 603639#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 603638#L914-3 assume !(0 == ~E_4~0); 603637#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 603636#L924-3 assume !(0 == ~E_6~0); 603635#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 603634#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 603633#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 603632#L418-30 assume !(1 == ~m_pc~0); 603631#L418-32 is_master_triggered_~__retres1~0#1 := 0; 603629#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 603627#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 603625#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 603623#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 603622#L437-30 assume !(1 == ~t1_pc~0); 603621#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 603620#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 603619#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 603618#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 603617#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 603616#L456-30 assume !(1 == ~t2_pc~0); 603615#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 603613#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 603612#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 603611#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 603610#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 595859#L475-30 assume !(1 == ~t3_pc~0); 595860#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 595851#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 595852#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 595843#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 595844#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 595805#L494-30 assume 1 == ~t4_pc~0; 595807#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 595752#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 595753#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 595728#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 595729#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 595467#L513-30 assume !(1 == ~t5_pc~0); 595462#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 595456#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 595451#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 595446#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 595442#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 595438#L532-30 assume 1 == ~t6_pc~0; 595432#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 595427#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 595422#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 595417#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 595412#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 592356#L551-30 assume !(1 == ~t7_pc~0); 592355#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 592353#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 592354#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 595389#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 595387#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 592337#L570-30 assume !(1 == ~t8_pc~0); 592336#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 592335#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 592334#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 592333#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 592332#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 592331#L952-3 assume !(1 == ~M_E~0); 592330#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 592329#L957-3 assume !(1 == ~T2_E~0); 592328#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 592327#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 592326#L972-3 assume !(1 == ~T5_E~0); 592325#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 592324#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 592322#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 592321#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 592319#L997-3 assume !(1 == ~E_1~0); 592317#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 592315#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 592313#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 592311#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 592309#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 592307#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 592305#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 592303#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 592217#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 592215#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 592213#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 590766#L1322 assume !(0 == start_simulation_~tmp~3#1); 590767#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 603838#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 603827#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 603826#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 603825#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 603814#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 603777#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 603768#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 583335#L1303-2 [2021-12-15 17:20:49,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:49,496 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2021-12-15 17:20:49,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:49,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527408332] [2021-12-15 17:20:49,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:49,497 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:49,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:49,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:49,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:49,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527408332] [2021-12-15 17:20:49,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527408332] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:49,538 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:49,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:49,538 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818978575] [2021-12-15 17:20:49,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:49,540 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:49,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:49,540 INFO L85 PathProgramCache]: Analyzing trace with hash -2133812840, now seen corresponding path program 2 times [2021-12-15 17:20:49,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:49,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942715542] [2021-12-15 17:20:49,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:49,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:49,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:49,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:49,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:49,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942715542] [2021-12-15 17:20:49,567 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942715542] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:49,567 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:49,567 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:49,567 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227415311] [2021-12-15 17:20:49,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:49,568 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:49,568 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:49,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:49,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:49,569 INFO L87 Difference]: Start difference. First operand 48433 states and 68865 transitions. cyclomatic complexity: 20436 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:49,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:49,740 INFO L93 Difference]: Finished difference Result 43073 states and 61008 transitions. [2021-12-15 17:20:49,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:49,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43073 states and 61008 transitions. [2021-12-15 17:20:49,945 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 42928 [2021-12-15 17:20:50,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43073 states to 43073 states and 61008 transitions. [2021-12-15 17:20:50,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43073 [2021-12-15 17:20:50,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43073 [2021-12-15 17:20:50,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43073 states and 61008 transitions. [2021-12-15 17:20:50,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:50,119 INFO L681 BuchiCegarLoop]: Abstraction has 43073 states and 61008 transitions. [2021-12-15 17:20:50,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43073 states and 61008 transitions. [2021-12-15 17:20:50,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43073 to 43073. [2021-12-15 17:20:50,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43073 states, 43073 states have (on average 1.416386135165881) internal successors, (61008), 43072 states have internal predecessors, (61008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:50,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43073 states to 43073 states and 61008 transitions. [2021-12-15 17:20:50,851 INFO L704 BuchiCegarLoop]: Abstraction has 43073 states and 61008 transitions. [2021-12-15 17:20:50,851 INFO L587 BuchiCegarLoop]: Abstraction has 43073 states and 61008 transitions. [2021-12-15 17:20:50,851 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:20:50,851 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43073 states and 61008 transitions. [2021-12-15 17:20:50,952 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 42928 [2021-12-15 17:20:50,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:50,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:50,953 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:50,953 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:50,954 INFO L791 eck$LassoCheckResult]: Stem: 674841#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 674842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 674084#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 674085#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 674118#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 674777#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 674778#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 674373#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 674374#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 674307#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 674308#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 674563#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 674534#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 674535#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 674845#L854 assume !(0 == ~M_E~0); 674632#L854-2 assume !(0 == ~T1_E~0); 674633#L859-1 assume !(0 == ~T2_E~0); 674182#L864-1 assume !(0 == ~T3_E~0); 674183#L869-1 assume !(0 == ~T4_E~0); 674295#L874-1 assume !(0 == ~T5_E~0); 675140#L879-1 assume !(0 == ~T6_E~0); 674615#L884-1 assume !(0 == ~T7_E~0); 674052#L889-1 assume !(0 == ~T8_E~0); 674053#L894-1 assume !(0 == ~E_M~0); 674386#L899-1 assume !(0 == ~E_1~0); 674854#L904-1 assume !(0 == ~E_2~0); 674554#L909-1 assume !(0 == ~E_3~0); 674555#L914-1 assume !(0 == ~E_4~0); 674766#L919-1 assume !(0 == ~E_5~0); 674472#L924-1 assume !(0 == ~E_6~0); 674282#L929-1 assume !(0 == ~E_7~0); 674283#L934-1 assume !(0 == ~E_8~0); 674533#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 674070#L418 assume !(1 == ~m_pc~0); 674045#L418-2 is_master_triggered_~__retres1~0#1 := 0; 675069#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 675070#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 674982#L1061 assume !(0 != activate_threads_~tmp~1#1); 674883#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 674884#L437 assume !(1 == ~t1_pc~0); 675124#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 674992#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 674930#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 674426#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 674427#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 674976#L456 assume !(1 == ~t2_pc~0); 674333#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 674332#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 674688#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 674689#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 674662#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 674177#L475 assume !(1 == ~t3_pc~0); 674178#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 674238#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 674239#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 675126#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 674430#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 674431#L494 assume !(1 == ~t4_pc~0); 674468#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 674469#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 674679#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 674680#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 674792#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 674234#L513 assume !(1 == ~t5_pc~0); 674235#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 674471#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 674507#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 674193#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 674194#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 674147#L532 assume !(1 == ~t6_pc~0); 674148#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 674296#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 674592#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 674672#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 674392#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 674393#L551 assume !(1 == ~t7_pc~0); 674856#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 674796#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 674797#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 675040#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 675195#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 674576#L570 assume !(1 == ~t8_pc~0); 674577#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 675098#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 674855#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 674685#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 674175#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 674176#L952 assume !(1 == ~M_E~0); 674119#L952-2 assume !(1 == ~T1_E~0); 674120#L957-1 assume !(1 == ~T2_E~0); 674954#L962-1 assume !(1 == ~T3_E~0); 674702#L967-1 assume !(1 == ~T4_E~0); 674703#L972-1 assume !(1 == ~T5_E~0); 675021#L977-1 assume !(1 == ~T6_E~0); 675022#L982-1 assume !(1 == ~T7_E~0); 674298#L987-1 assume !(1 == ~T8_E~0); 674299#L992-1 assume !(1 == ~E_M~0); 674309#L997-1 assume !(1 == ~E_1~0); 674660#L1002-1 assume !(1 == ~E_2~0); 674648#L1007-1 assume !(1 == ~E_3~0); 674054#L1012-1 assume !(1 == ~E_4~0); 674055#L1017-1 assume !(1 == ~E_5~0); 674651#L1022-1 assume !(1 == ~E_6~0); 674652#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 674673#L1032-1 assume !(1 == ~E_8~0); 674828#L1037-1 assume { :end_inline_reset_delta_events } true; 674829#L1303-2 [2021-12-15 17:20:50,954 INFO L793 eck$LassoCheckResult]: Loop: 674829#L1303-2 assume !false; 691251#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 691248#L829 assume !false; 691212#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 691170#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 691164#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 691159#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 691152#L712 assume !(0 != eval_~tmp~0#1); 691153#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 716836#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 716834#L854-3 assume !(0 == ~M_E~0); 716832#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 716830#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 716726#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 716724#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 716723#L874-3 assume !(0 == ~T5_E~0); 716714#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 716712#L884-3 assume !(0 == ~T7_E~0); 716710#L889-3 assume !(0 == ~T8_E~0); 716708#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 716706#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 716704#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 716703#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 716701#L914-3 assume !(0 == ~E_4~0); 716699#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 716697#L924-3 assume !(0 == ~E_6~0); 716688#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 716687#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 716686#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 716685#L418-30 assume 1 == ~m_pc~0; 716683#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 716681#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 716679#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 716677#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 716676#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 716675#L437-30 assume !(1 == ~t1_pc~0); 716674#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 716673#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 716672#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 716671#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 716670#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 716669#L456-30 assume 1 == ~t2_pc~0; 716667#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 716666#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 716665#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 716652#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 716651#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 706055#L475-30 assume !(1 == ~t3_pc~0); 706054#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 706053#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 706052#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 706051#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 706049#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 706047#L494-30 assume 1 == ~t4_pc~0; 706044#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 706042#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 706041#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 706040#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 706038#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 697985#L513-30 assume !(1 == ~t5_pc~0); 697973#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 697967#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 697959#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 697776#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 697655#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 697652#L532-30 assume 1 == ~t6_pc~0; 697650#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 697634#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 697623#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 697612#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 697605#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 691303#L551-30 assume !(1 == ~t7_pc~0); 691301#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 691299#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 691297#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 691295#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 691293#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 691291#L570-30 assume !(1 == ~t8_pc~0); 686864#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 691287#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 691285#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 691283#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 691281#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 691279#L952-3 assume !(1 == ~M_E~0); 691278#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 691276#L957-3 assume !(1 == ~T2_E~0); 691274#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 691272#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 691270#L972-3 assume !(1 == ~T5_E~0); 691268#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 691265#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 691261#L987-3 assume !(1 == ~T8_E~0); 691257#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 691254#L997-3 assume !(1 == ~E_1~0); 691249#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 691246#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 691245#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 691244#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 691243#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 691242#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 691241#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 691240#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 691192#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 691190#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 691161#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 691155#L1322 assume !(0 == start_simulation_~tmp~3#1); 691156#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 691353#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 691345#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 691310#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 691307#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 691305#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 691263#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 691259#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 674829#L1303-2 [2021-12-15 17:20:50,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:50,955 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2021-12-15 17:20:50,955 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:50,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760336523] [2021-12-15 17:20:50,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:50,955 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:50,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:50,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:50,983 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:50,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760336523] [2021-12-15 17:20:50,983 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760336523] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:50,983 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:50,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:50,983 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443128690] [2021-12-15 17:20:50,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:50,984 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:50,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:50,984 INFO L85 PathProgramCache]: Analyzing trace with hash -557978412, now seen corresponding path program 1 times [2021-12-15 17:20:50,984 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:50,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116854583] [2021-12-15 17:20:50,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:50,985 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:50,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:51,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:51,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:51,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116854583] [2021-12-15 17:20:51,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116854583] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:51,008 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:51,008 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:51,008 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915047228] [2021-12-15 17:20:51,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:51,008 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:51,008 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:51,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:51,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:51,009 INFO L87 Difference]: Start difference. First operand 43073 states and 61008 transitions. cyclomatic complexity: 17939 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:51,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:51,276 INFO L93 Difference]: Finished difference Result 66851 states and 94434 transitions. [2021-12-15 17:20:51,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:51,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66851 states and 94434 transitions. [2021-12-15 17:20:51,545 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 66576 [2021-12-15 17:20:52,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66851 states to 66851 states and 94434 transitions. [2021-12-15 17:20:52,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66851 [2021-12-15 17:20:52,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66851 [2021-12-15 17:20:52,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66851 states and 94434 transitions. [2021-12-15 17:20:52,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:52,199 INFO L681 BuchiCegarLoop]: Abstraction has 66851 states and 94434 transitions. [2021-12-15 17:20:52,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66851 states and 94434 transitions. [2021-12-15 17:20:52,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66851 to 48401. [2021-12-15 17:20:52,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48401 states, 48401 states have (on average 1.4138344249085764) internal successors, (68431), 48400 states have internal predecessors, (68431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:52,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48401 states to 48401 states and 68431 transitions. [2021-12-15 17:20:52,645 INFO L704 BuchiCegarLoop]: Abstraction has 48401 states and 68431 transitions. [2021-12-15 17:20:52,645 INFO L587 BuchiCegarLoop]: Abstraction has 48401 states and 68431 transitions. [2021-12-15 17:20:52,645 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:20:52,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48401 states and 68431 transitions. [2021-12-15 17:20:52,764 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48176 [2021-12-15 17:20:52,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:52,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:52,766 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:52,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:52,767 INFO L791 eck$LassoCheckResult]: Stem: 784799#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 784800#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 784016#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 784017#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 784053#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 784733#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 784734#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 784304#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 784305#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 784244#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 784245#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 784507#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 784475#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 784476#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 784804#L854 assume !(0 == ~M_E~0); 784572#L854-2 assume !(0 == ~T1_E~0); 784573#L859-1 assume !(0 == ~T2_E~0); 784116#L864-1 assume !(0 == ~T3_E~0); 784117#L869-1 assume !(0 == ~T4_E~0); 784231#L874-1 assume !(0 == ~T5_E~0); 785122#L879-1 assume !(0 == ~T6_E~0); 784559#L884-1 assume !(0 == ~T7_E~0); 783986#L889-1 assume !(0 == ~T8_E~0); 783987#L894-1 assume !(0 == ~E_M~0); 784320#L899-1 assume !(0 == ~E_1~0); 784813#L904-1 assume !(0 == ~E_2~0); 784492#L909-1 assume !(0 == ~E_3~0); 784493#L914-1 assume !(0 == ~E_4~0); 784721#L919-1 assume !(0 == ~E_5~0); 784406#L924-1 assume !(0 == ~E_6~0); 784213#L929-1 assume 0 == ~E_7~0;~E_7~0 := 1; 784214#L934-1 assume !(0 == ~E_8~0); 785139#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 784003#L418 assume !(1 == ~m_pc~0); 784004#L418-2 is_master_triggered_~__retres1~0#1 := 0; 785186#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 785245#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 785242#L1061 assume !(0 != activate_threads_~tmp~1#1); 785241#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 785175#L437 assume !(1 == ~t1_pc~0); 785176#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 784972#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 784973#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 784359#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 784360#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 784952#L456 assume !(1 == ~t2_pc~0); 784953#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 785171#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 785172#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 784998#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 784999#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 784111#L475 assume !(1 == ~t3_pc~0); 784112#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 784171#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 784172#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 785106#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 785107#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 785036#L494 assume !(1 == ~t4_pc~0); 785037#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 784692#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 784693#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 785240#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 784750#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 784751#L513 assume !(1 == ~t5_pc~0); 784403#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 784404#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 785239#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 784127#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 784128#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 785238#L532 assume !(1 == ~t6_pc~0); 784234#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 784233#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 784621#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 784622#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 784325#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 784326#L551 assume !(1 == ~t7_pc~0); 785237#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 784755#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 784756#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 785236#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 785202#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 785203#L570 assume !(1 == ~t8_pc~0); 785111#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 785112#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 785235#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 784634#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 784105#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784106#L952 assume !(1 == ~M_E~0); 784054#L952-2 assume !(1 == ~T1_E~0); 784055#L957-1 assume !(1 == ~T2_E~0); 785180#L962-1 assume !(1 == ~T3_E~0); 785181#L967-1 assume !(1 == ~T4_E~0); 785162#L972-1 assume !(1 == ~T5_E~0); 785163#L977-1 assume !(1 == ~T6_E~0); 785233#L982-1 assume !(1 == ~T7_E~0); 785232#L987-1 assume !(1 == ~T8_E~0); 784246#L992-1 assume !(1 == ~E_M~0); 784247#L997-1 assume !(1 == ~E_1~0); 785124#L1002-1 assume !(1 == ~E_2~0); 785125#L1007-1 assume !(1 == ~E_3~0); 783988#L1012-1 assume !(1 == ~E_4~0); 783989#L1017-1 assume !(1 == ~E_5~0); 784595#L1022-1 assume !(1 == ~E_6~0); 784596#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 784624#L1032-1 assume !(1 == ~E_8~0); 784786#L1037-1 assume { :end_inline_reset_delta_events } true; 784787#L1303-2 [2021-12-15 17:20:52,767 INFO L793 eck$LassoCheckResult]: Loop: 784787#L1303-2 assume !false; 824424#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 824418#L829 assume !false; 824416#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 824222#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 824212#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 824207#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 824201#L712 assume !(0 != eval_~tmp~0#1); 824202#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 827999#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 827994#L854-3 assume !(0 == ~M_E~0); 827989#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 827983#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 827978#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 827973#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 827966#L874-3 assume !(0 == ~T5_E~0); 827961#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 827956#L884-3 assume !(0 == ~T7_E~0); 827950#L889-3 assume !(0 == ~T8_E~0); 827945#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 827940#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 827937#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 827932#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 827927#L914-3 assume !(0 == ~E_4~0); 827923#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 827919#L924-3 assume !(0 == ~E_6~0); 827906#L929-3 assume !(0 == ~E_7~0); 827907#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 832330#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 832053#L418-30 assume !(1 == ~m_pc~0); 832050#L418-32 is_master_triggered_~__retres1~0#1 := 0; 832048#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 832044#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 832042#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 832039#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 832037#L437-30 assume !(1 == ~t1_pc~0); 832034#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 832032#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 832030#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 832028#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 832026#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 832024#L456-30 assume 1 == ~t2_pc~0; 832021#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 832019#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 832017#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 832014#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 831325#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 827687#L475-30 assume !(1 == ~t3_pc~0); 827686#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 827685#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 827684#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 827683#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 827682#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 827681#L494-30 assume 1 == ~t4_pc~0; 827679#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 827677#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 827676#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 827675#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 827674#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 827670#L513-30 assume !(1 == ~t5_pc~0); 806374#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 827667#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 827665#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 827662#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 827660#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 827658#L532-30 assume !(1 == ~t6_pc~0); 827654#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 827652#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 827650#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 827648#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 827646#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 827644#L551-30 assume !(1 == ~t7_pc~0); 819216#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 827640#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 827638#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 827636#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 827634#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 827632#L570-30 assume !(1 == ~t8_pc~0); 797338#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 827629#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 827627#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 827625#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 827623#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 827621#L952-3 assume !(1 == ~M_E~0); 827619#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 827616#L957-3 assume !(1 == ~T2_E~0); 827614#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 827612#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 827610#L972-3 assume !(1 == ~T5_E~0); 827608#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 827606#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 827605#L987-3 assume !(1 == ~T8_E~0); 827603#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 827601#L997-3 assume !(1 == ~E_1~0); 827599#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 827597#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 827595#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 827592#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 827590#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 827588#L1027-3 assume !(1 == ~E_7~0); 827585#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 827583#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 827559#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 827557#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 825778#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 809682#L1322 assume !(0 == start_simulation_~tmp~3#1); 809683#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 824471#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 824462#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 824460#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 824458#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 824456#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 824444#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 824436#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 784787#L1303-2 [2021-12-15 17:20:52,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:52,767 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2021-12-15 17:20:52,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:52,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405414014] [2021-12-15 17:20:52,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:52,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:52,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:52,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:52,792 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:52,792 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405414014] [2021-12-15 17:20:52,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405414014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:52,792 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:52,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:52,792 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936680270] [2021-12-15 17:20:52,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:52,793 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:52,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:52,793 INFO L85 PathProgramCache]: Analyzing trace with hash 655610136, now seen corresponding path program 1 times [2021-12-15 17:20:52,793 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:52,794 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327110394] [2021-12-15 17:20:52,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:52,794 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:52,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:52,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:52,821 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:52,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327110394] [2021-12-15 17:20:52,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1327110394] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:52,822 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:52,822 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:52,822 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509342906] [2021-12-15 17:20:52,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:52,823 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:52,823 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:52,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:52,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:52,824 INFO L87 Difference]: Start difference. First operand 48401 states and 68431 transitions. cyclomatic complexity: 20034 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:53,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:53,328 INFO L93 Difference]: Finished difference Result 61153 states and 86110 transitions. [2021-12-15 17:20:53,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:53,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61153 states and 86110 transitions. [2021-12-15 17:20:53,526 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 60960 [2021-12-15 17:20:53,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61153 states to 61153 states and 86110 transitions. [2021-12-15 17:20:53,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61153 [2021-12-15 17:20:53,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61153 [2021-12-15 17:20:53,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61153 states and 86110 transitions. [2021-12-15 17:20:53,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:53,712 INFO L681 BuchiCegarLoop]: Abstraction has 61153 states and 86110 transitions. [2021-12-15 17:20:53,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61153 states and 86110 transitions. [2021-12-15 17:20:54,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61153 to 43073. [2021-12-15 17:20:54,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43073 states, 43073 states have (on average 1.4070531423397488) internal successors, (60606), 43072 states have internal predecessors, (60606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:54,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43073 states to 43073 states and 60606 transitions. [2021-12-15 17:20:54,111 INFO L704 BuchiCegarLoop]: Abstraction has 43073 states and 60606 transitions. [2021-12-15 17:20:54,111 INFO L587 BuchiCegarLoop]: Abstraction has 43073 states and 60606 transitions. [2021-12-15 17:20:54,111 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:20:54,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43073 states and 60606 transitions. [2021-12-15 17:20:54,422 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 42928 [2021-12-15 17:20:54,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:54,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:54,425 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:54,425 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:54,425 INFO L791 eck$LassoCheckResult]: Stem: 894348#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 894349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 893578#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 893579#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 893615#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 894283#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 894284#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 893864#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 893865#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 893805#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 893806#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 894062#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 894032#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 894033#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 894353#L854 assume !(0 == ~M_E~0); 894128#L854-2 assume !(0 == ~T1_E~0); 894129#L859-1 assume !(0 == ~T2_E~0); 893678#L864-1 assume !(0 == ~T3_E~0); 893679#L869-1 assume !(0 == ~T4_E~0); 893794#L874-1 assume !(0 == ~T5_E~0); 894654#L879-1 assume !(0 == ~T6_E~0); 894114#L884-1 assume !(0 == ~T7_E~0); 893550#L889-1 assume !(0 == ~T8_E~0); 893551#L894-1 assume !(0 == ~E_M~0); 893880#L899-1 assume !(0 == ~E_1~0); 894360#L904-1 assume !(0 == ~E_2~0); 894050#L909-1 assume !(0 == ~E_3~0); 894051#L914-1 assume !(0 == ~E_4~0); 894271#L919-1 assume !(0 == ~E_5~0); 893967#L924-1 assume !(0 == ~E_6~0); 893775#L929-1 assume !(0 == ~E_7~0); 893776#L934-1 assume !(0 == ~E_8~0); 894029#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 893567#L418 assume !(1 == ~m_pc~0); 893541#L418-2 is_master_triggered_~__retres1~0#1 := 0; 894575#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 894576#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 894492#L1061 assume !(0 != activate_threads_~tmp~1#1); 894391#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 894392#L437 assume !(1 == ~t1_pc~0); 894638#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 894502#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 894435#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 893920#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 893921#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 894483#L456 assume !(1 == ~t2_pc~0); 893830#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 893829#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894188#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 894189#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 894164#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 893673#L475 assume !(1 == ~t3_pc~0); 893674#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 893733#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 893734#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 894639#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 893924#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 893925#L494 assume !(1 == ~t4_pc~0); 893963#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 893964#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 894178#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 894179#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 894298#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 893728#L513 assume !(1 == ~t5_pc~0); 893729#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 893965#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 894001#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 893689#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 893690#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 893642#L532 assume !(1 == ~t6_pc~0); 893643#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 893795#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 894090#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 894173#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 893886#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 893887#L551 assume !(1 == ~t7_pc~0); 894363#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 894304#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 894305#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 894551#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 894725#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 894073#L570 assume !(1 == ~t8_pc~0); 894074#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 894603#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 894362#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 894184#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 893667#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 893668#L952 assume !(1 == ~M_E~0); 893616#L952-2 assume !(1 == ~T1_E~0); 893617#L957-1 assume !(1 == ~T2_E~0); 894461#L962-1 assume !(1 == ~T3_E~0); 894203#L967-1 assume !(1 == ~T4_E~0); 894204#L972-1 assume !(1 == ~T5_E~0); 894532#L977-1 assume !(1 == ~T6_E~0); 894533#L982-1 assume !(1 == ~T7_E~0); 893797#L987-1 assume !(1 == ~T8_E~0); 893798#L992-1 assume !(1 == ~E_M~0); 893807#L997-1 assume !(1 == ~E_1~0); 894161#L1002-1 assume !(1 == ~E_2~0); 894148#L1007-1 assume !(1 == ~E_3~0); 893552#L1012-1 assume !(1 == ~E_4~0); 893553#L1017-1 assume !(1 == ~E_5~0); 894149#L1022-1 assume !(1 == ~E_6~0); 894150#L1027-1 assume !(1 == ~E_7~0); 894174#L1032-1 assume !(1 == ~E_8~0); 894333#L1037-1 assume { :end_inline_reset_delta_events } true; 894334#L1303-2 [2021-12-15 17:20:54,425 INFO L793 eck$LassoCheckResult]: Loop: 894334#L1303-2 assume !false; 921243#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 921242#L829 assume !false; 921241#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 921231#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 921225#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 921222#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 921220#L712 assume !(0 != eval_~tmp~0#1); 921221#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 936268#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 936266#L854-3 assume !(0 == ~M_E~0); 936264#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 936262#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 936260#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 936257#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 936254#L874-3 assume !(0 == ~T5_E~0); 936252#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 936250#L884-3 assume !(0 == ~T7_E~0); 936248#L889-3 assume !(0 == ~T8_E~0); 936246#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 936245#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 936244#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 936241#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 936239#L914-3 assume !(0 == ~E_4~0); 936238#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 936237#L924-3 assume !(0 == ~E_6~0); 936235#L929-3 assume !(0 == ~E_7~0); 936233#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 936232#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 936230#L418-30 assume 1 == ~m_pc~0; 936228#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 936229#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936323#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 936221#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 936220#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 936219#L437-30 assume !(1 == ~t1_pc~0); 936218#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 936217#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 936216#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 894706#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 894696#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 893929#L456-30 assume !(1 == ~t2_pc~0); 893931#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 894384#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894385#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 893714#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 893715#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 894063#L475-30 assume !(1 == ~t3_pc~0); 893594#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 893595#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 894292#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 894655#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 893949#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 893950#L494-30 assume 1 == ~t4_pc~0; 894752#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 936144#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 936142#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 894707#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 894555#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 894556#L513-30 assume !(1 == ~t5_pc~0); 931992#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 931990#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 931988#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 931986#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 931983#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 931981#L532-30 assume !(1 == ~t6_pc~0); 931978#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 931976#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 931974#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 931973#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 931972#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 915560#L551-30 assume !(1 == ~t7_pc~0); 915557#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 915555#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 915553#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 915551#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 915534#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 911217#L570-30 assume !(1 == ~t8_pc~0); 911215#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 911213#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 911211#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 911209#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 911207#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 911205#L952-3 assume !(1 == ~M_E~0); 911204#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 911202#L957-3 assume !(1 == ~T2_E~0); 911200#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 911198#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 911196#L972-3 assume !(1 == ~T5_E~0); 911194#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 911192#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 911190#L987-3 assume !(1 == ~T8_E~0); 911188#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 911186#L997-3 assume !(1 == ~E_1~0); 911184#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 911182#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 911180#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 911178#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 911176#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 911174#L1027-3 assume !(1 == ~E_7~0); 911172#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 911170#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 911144#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 911142#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 911140#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 911136#L1322 assume !(0 == start_simulation_~tmp~3#1); 911137#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 921318#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 921309#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 921307#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 921305#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 921303#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 921301#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 921298#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 894334#L1303-2 [2021-12-15 17:20:54,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:54,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2021-12-15 17:20:54,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:54,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673438174] [2021-12-15 17:20:54,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:54,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:54,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:54,437 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:54,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:54,508 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:54,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:54,509 INFO L85 PathProgramCache]: Analyzing trace with hash 767655574, now seen corresponding path program 1 times [2021-12-15 17:20:54,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:54,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610774013] [2021-12-15 17:20:54,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:54,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:54,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:54,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:54,537 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:54,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610774013] [2021-12-15 17:20:54,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610774013] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:54,538 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:54,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:54,538 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96001168] [2021-12-15 17:20:54,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:54,539 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:54,539 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:54,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:54,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:54,540 INFO L87 Difference]: Start difference. First operand 43073 states and 60606 transitions. cyclomatic complexity: 17537 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:54,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:54,693 INFO L93 Difference]: Finished difference Result 48433 states and 68171 transitions. [2021-12-15 17:20:54,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:54,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48433 states and 68171 transitions. [2021-12-15 17:20:54,880 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48208 [2021-12-15 17:20:54,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48433 states to 48433 states and 68171 transitions. [2021-12-15 17:20:54,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48433 [2021-12-15 17:20:55,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48433 [2021-12-15 17:20:55,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48433 states and 68171 transitions. [2021-12-15 17:20:55,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:55,056 INFO L681 BuchiCegarLoop]: Abstraction has 48433 states and 68171 transitions. [2021-12-15 17:20:55,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48433 states and 68171 transitions. [2021-12-15 17:20:55,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48433 to 48433. [2021-12-15 17:20:55,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48433 states, 48433 states have (on average 1.407532054590878) internal successors, (68171), 48432 states have internal predecessors, (68171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:55,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48433 states to 48433 states and 68171 transitions. [2021-12-15 17:20:55,510 INFO L704 BuchiCegarLoop]: Abstraction has 48433 states and 68171 transitions. [2021-12-15 17:20:55,510 INFO L587 BuchiCegarLoop]: Abstraction has 48433 states and 68171 transitions. [2021-12-15 17:20:55,510 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-15 17:20:55,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48433 states and 68171 transitions. [2021-12-15 17:20:55,637 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48208 [2021-12-15 17:20:55,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:55,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:55,639 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:55,639 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:55,640 INFO L791 eck$LassoCheckResult]: Stem: 985869#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 985870#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 985093#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 985094#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 985129#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 985805#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 985806#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 985381#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 985382#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 985321#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 985322#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 985580#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 985554#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 985555#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 985872#L854 assume !(0 == ~M_E~0); 985649#L854-2 assume !(0 == ~T1_E~0); 985650#L859-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 985192#L864-1 assume !(0 == ~T3_E~0); 985193#L869-1 assume !(0 == ~T4_E~0); 985307#L874-1 assume !(0 == ~T5_E~0); 986169#L879-1 assume !(0 == ~T6_E~0); 986170#L884-1 assume !(0 == ~T7_E~0); 985062#L889-1 assume !(0 == ~T8_E~0); 985063#L894-1 assume !(0 == ~E_M~0); 986258#L899-1 assume !(0 == ~E_1~0); 985879#L904-1 assume !(0 == ~E_2~0); 985570#L909-1 assume !(0 == ~E_3~0); 985571#L914-1 assume !(0 == ~E_4~0); 985823#L919-1 assume !(0 == ~E_5~0); 985824#L924-1 assume !(0 == ~E_6~0); 985292#L929-1 assume !(0 == ~E_7~0); 985293#L934-1 assume !(0 == ~E_8~0); 986289#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 985080#L418 assume !(1 == ~m_pc~0); 985081#L418-2 is_master_triggered_~__retres1~0#1 := 0; 986288#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 986286#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 986283#L1061 assume !(0 != activate_threads_~tmp~1#1); 986282#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 986213#L437 assume !(1 == ~t1_pc~0); 986214#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 986022#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 986023#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 985436#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 985437#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 986000#L456 assume !(1 == ~t2_pc~0); 986001#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 986207#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 986208#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 986045#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 986046#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 985187#L475 assume !(1 == ~t3_pc~0); 985188#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 985250#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 985251#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 986156#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 986157#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 986085#L494 assume !(1 == ~t4_pc~0); 986086#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 985763#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 985764#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 986246#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 986247#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985243#L513 assume !(1 == ~t5_pc~0); 985244#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 986225#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 986226#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 985203#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 985204#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 986281#L532 assume !(1 == ~t6_pc~0); 985310#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 985309#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 985695#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 985696#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 986192#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 986051#L551 assume !(1 == ~t7_pc~0); 985882#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 985827#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 985828#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 986277#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 986241#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 985591#L570 assume !(1 == ~t8_pc~0); 985592#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 986120#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 985881#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 985708#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 985183#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 985184#L952 assume !(1 == ~M_E~0); 985130#L952-2 assume !(1 == ~T1_E~0); 985131#L957-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 985978#L962-1 assume !(1 == ~T3_E~0); 985723#L967-1 assume !(1 == ~T4_E~0); 985724#L972-1 assume !(1 == ~T5_E~0); 986052#L977-1 assume !(1 == ~T6_E~0); 986053#L982-1 assume !(1 == ~T7_E~0); 985312#L987-1 assume !(1 == ~T8_E~0); 985313#L992-1 assume !(1 == ~E_M~0); 985323#L997-1 assume !(1 == ~E_1~0); 985681#L1002-1 assume !(1 == ~E_2~0); 985668#L1007-1 assume !(1 == ~E_3~0); 985064#L1012-1 assume !(1 == ~E_4~0); 985065#L1017-1 assume !(1 == ~E_5~0); 985669#L1022-1 assume !(1 == ~E_6~0); 985670#L1027-1 assume !(1 == ~E_7~0); 985697#L1032-1 assume !(1 == ~E_8~0); 985851#L1037-1 assume { :end_inline_reset_delta_events } true; 985852#L1303-2 [2021-12-15 17:20:55,640 INFO L793 eck$LassoCheckResult]: Loop: 985852#L1303-2 assume !false; 1000472#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1000470#L829 assume !false; 1000468#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1000457#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1000451#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1000449#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1000447#L712 assume !(0 != eval_~tmp~0#1); 1000448#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1008884#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1008881#L854-3 assume !(0 == ~M_E~0); 1008878#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1008874#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1008875#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1009179#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1009177#L874-3 assume !(0 == ~T5_E~0); 1009174#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1009172#L884-3 assume !(0 == ~T7_E~0); 1009170#L889-3 assume !(0 == ~T8_E~0); 1009168#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1009166#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1009165#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1009164#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1009163#L914-3 assume !(0 == ~E_4~0); 1009162#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1009160#L924-3 assume !(0 == ~E_6~0); 1009158#L929-3 assume !(0 == ~E_7~0); 1009156#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1009154#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1009151#L418-30 assume !(1 == ~m_pc~0); 1009148#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1009144#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1009140#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1009136#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1009132#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1009128#L437-30 assume !(1 == ~t1_pc~0); 1009124#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1009120#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1009117#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1009113#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1009072#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1009071#L456-30 assume !(1 == ~t2_pc~0); 1009011#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1009008#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1009006#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1009004#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1009002#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1008999#L475-30 assume !(1 == ~t3_pc~0); 1008602#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1008984#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1008977#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1008970#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1008963#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1008954#L494-30 assume !(1 == ~t4_pc~0); 1008931#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1008924#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1008918#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1008912#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1008906#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1007330#L513-30 assume !(1 == ~t5_pc~0); 1007327#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1007325#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1007323#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1007321#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1007319#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1007318#L532-30 assume 1 == ~t6_pc~0; 1007317#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1007315#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1007312#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1007311#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1007309#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1007307#L551-30 assume !(1 == ~t7_pc~0); 1000874#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 998966#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 998962#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 998960#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 998958#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 998956#L570-30 assume !(1 == ~t8_pc~0); 990220#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 998952#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 998949#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 998947#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 998945#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 998943#L952-3 assume !(1 == ~M_E~0); 998941#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 998939#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 998937#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 998935#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 998933#L972-3 assume !(1 == ~T5_E~0); 998931#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 998869#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 998862#L987-3 assume !(1 == ~T8_E~0); 998853#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 998846#L997-3 assume !(1 == ~E_1~0); 998839#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 998833#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 998683#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 998679#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 998674#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 998669#L1027-3 assume !(1 == ~E_7~0); 998668#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 998667#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 998658#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 998657#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 998656#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 998654#L1322 assume !(0 == start_simulation_~tmp~3#1); 998655#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1000633#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1000625#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1000624#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1000620#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1000618#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1000616#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1000615#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 985852#L1303-2 [2021-12-15 17:20:55,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:55,641 INFO L85 PathProgramCache]: Analyzing trace with hash 743043657, now seen corresponding path program 1 times [2021-12-15 17:20:55,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:55,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387050272] [2021-12-15 17:20:55,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:55,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:55,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:55,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:55,663 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:55,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387050272] [2021-12-15 17:20:55,664 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387050272] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:55,664 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:55,664 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:55,664 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802393840] [2021-12-15 17:20:55,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:55,665 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:55,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:55,665 INFO L85 PathProgramCache]: Analyzing trace with hash 961723607, now seen corresponding path program 1 times [2021-12-15 17:20:55,665 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:55,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56301625] [2021-12-15 17:20:55,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:55,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:55,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:55,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:55,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:55,689 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56301625] [2021-12-15 17:20:55,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56301625] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:55,690 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:55,690 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:55,690 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784381258] [2021-12-15 17:20:55,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:55,690 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:55,691 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:55,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:55,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:55,691 INFO L87 Difference]: Start difference. First operand 48433 states and 68171 transitions. cyclomatic complexity: 19742 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:56,080 INFO L93 Difference]: Finished difference Result 63233 states and 88809 transitions. [2021-12-15 17:20:56,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:56,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63233 states and 88809 transitions. [2021-12-15 17:20:56,301 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 63056 [2021-12-15 17:20:56,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63233 states to 63233 states and 88809 transitions. [2021-12-15 17:20:56,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63233 [2021-12-15 17:20:56,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63233 [2021-12-15 17:20:56,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63233 states and 88809 transitions. [2021-12-15 17:20:56,513 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:56,513 INFO L681 BuchiCegarLoop]: Abstraction has 63233 states and 88809 transitions. [2021-12-15 17:20:56,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63233 states and 88809 transitions. [2021-12-15 17:20:56,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63233 to 43073. [2021-12-15 17:20:56,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43073 states, 43073 states have (on average 1.4055440763355234) internal successors, (60541), 43072 states have internal predecessors, (60541), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43073 states to 43073 states and 60541 transitions. [2021-12-15 17:20:56,947 INFO L704 BuchiCegarLoop]: Abstraction has 43073 states and 60541 transitions. [2021-12-15 17:20:56,947 INFO L587 BuchiCegarLoop]: Abstraction has 43073 states and 60541 transitions. [2021-12-15 17:20:56,948 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-15 17:20:56,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43073 states and 60541 transitions. [2021-12-15 17:20:57,054 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 42928 [2021-12-15 17:20:57,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,056 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,056 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,056 INFO L791 eck$LassoCheckResult]: Stem: 1097541#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1097542#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1096770#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1096771#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1096803#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1097472#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1097473#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1097058#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1097059#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1096995#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1096996#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1097248#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1097219#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1097220#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1097545#L854 assume !(0 == ~M_E~0); 1097315#L854-2 assume !(0 == ~T1_E~0); 1097316#L859-1 assume !(0 == ~T2_E~0); 1096866#L864-1 assume !(0 == ~T3_E~0); 1096867#L869-1 assume !(0 == ~T4_E~0); 1096983#L874-1 assume !(0 == ~T5_E~0); 1097850#L879-1 assume !(0 == ~T6_E~0); 1097298#L884-1 assume !(0 == ~T7_E~0); 1096738#L889-1 assume !(0 == ~T8_E~0); 1096739#L894-1 assume !(0 == ~E_M~0); 1097071#L899-1 assume !(0 == ~E_1~0); 1097553#L904-1 assume !(0 == ~E_2~0); 1097238#L909-1 assume !(0 == ~E_3~0); 1097239#L914-1 assume !(0 == ~E_4~0); 1097459#L919-1 assume !(0 == ~E_5~0); 1097154#L924-1 assume !(0 == ~E_6~0); 1096969#L929-1 assume !(0 == ~E_7~0); 1096970#L934-1 assume !(0 == ~E_8~0); 1097218#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1096756#L418 assume !(1 == ~m_pc~0); 1096731#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1097771#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1097772#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1097690#L1061 assume !(0 != activate_threads_~tmp~1#1); 1097588#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1097589#L437 assume !(1 == ~t1_pc~0); 1097835#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1097700#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1097635#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1097108#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1097109#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1097684#L456 assume !(1 == ~t2_pc~0); 1097020#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1097019#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1097375#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1097376#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1097349#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1096861#L475 assume !(1 == ~t3_pc~0); 1096862#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1096924#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1096925#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1097837#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1097112#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1097113#L494 assume !(1 == ~t4_pc~0); 1097150#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1097151#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1097366#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1097367#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1097488#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1096920#L513 assume !(1 == ~t5_pc~0); 1096921#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1097153#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1097190#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1096877#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1096878#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1096832#L532 assume !(1 == ~t6_pc~0); 1096833#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1096984#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1097276#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1097360#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1097076#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1097077#L551 assume !(1 == ~t7_pc~0); 1097555#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1097493#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1097494#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1097750#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1097908#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1097260#L570 assume !(1 == ~t8_pc~0); 1097261#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1097803#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1097554#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1097372#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1096859#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1096860#L952 assume !(1 == ~M_E~0); 1096804#L952-2 assume !(1 == ~T1_E~0); 1096805#L957-1 assume !(1 == ~T2_E~0); 1097662#L962-1 assume !(1 == ~T3_E~0); 1097389#L967-1 assume !(1 == ~T4_E~0); 1097390#L972-1 assume !(1 == ~T5_E~0); 1097730#L977-1 assume !(1 == ~T6_E~0); 1097731#L982-1 assume !(1 == ~T7_E~0); 1096986#L987-1 assume !(1 == ~T8_E~0); 1096987#L992-1 assume !(1 == ~E_M~0); 1096997#L997-1 assume !(1 == ~E_1~0); 1097347#L1002-1 assume !(1 == ~E_2~0); 1097335#L1007-1 assume !(1 == ~E_3~0); 1096740#L1012-1 assume !(1 == ~E_4~0); 1096741#L1017-1 assume !(1 == ~E_5~0); 1097338#L1022-1 assume !(1 == ~E_6~0); 1097339#L1027-1 assume !(1 == ~E_7~0); 1097361#L1032-1 assume !(1 == ~E_8~0); 1097529#L1037-1 assume { :end_inline_reset_delta_events } true; 1097530#L1303-2 [2021-12-15 17:20:57,057 INFO L793 eck$LassoCheckResult]: Loop: 1097530#L1303-2 assume !false; 1129486#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1129484#L829 assume !false; 1129482#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1129471#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1129465#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1129463#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1129461#L712 assume !(0 != eval_~tmp~0#1); 1129462#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1139748#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1139747#L854-3 assume !(0 == ~M_E~0); 1139746#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1139745#L859-3 assume !(0 == ~T2_E~0); 1139744#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1139743#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1139742#L874-3 assume !(0 == ~T5_E~0); 1139741#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1139740#L884-3 assume !(0 == ~T7_E~0); 1139739#L889-3 assume !(0 == ~T8_E~0); 1139738#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1139737#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1139736#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1139735#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1139734#L914-3 assume !(0 == ~E_4~0); 1139733#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1139732#L924-3 assume !(0 == ~E_6~0); 1139731#L929-3 assume !(0 == ~E_7~0); 1139730#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1139729#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1139728#L418-30 assume !(1 == ~m_pc~0); 1139725#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1139724#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1139723#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1139722#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1139720#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1139719#L437-30 assume !(1 == ~t1_pc~0); 1139718#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1139717#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1139716#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1139715#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1139714#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1139713#L456-30 assume !(1 == ~t2_pc~0); 1139712#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1139710#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1139709#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1139708#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1139707#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1139706#L475-30 assume !(1 == ~t3_pc~0); 1137778#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1139705#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1139704#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1139703#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1139702#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1139701#L494-30 assume 1 == ~t4_pc~0; 1139699#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1139698#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1139697#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1139696#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1139695#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1139694#L513-30 assume !(1 == ~t5_pc~0); 1138436#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1139693#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1139692#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1139691#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1139690#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1139689#L532-30 assume !(1 == ~t6_pc~0); 1139687#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1139686#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1139685#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1139684#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1139683#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1139682#L551-30 assume !(1 == ~t7_pc~0); 1134873#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1139681#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1096926#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1096927#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1139506#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1129573#L570-30 assume !(1 == ~t8_pc~0); 1129571#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1129569#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1129567#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1129564#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1129562#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1129560#L952-3 assume !(1 == ~M_E~0); 1129558#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1129556#L957-3 assume !(1 == ~T2_E~0); 1129554#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1129553#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1129551#L972-3 assume !(1 == ~T5_E~0); 1129549#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1129547#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1129545#L987-3 assume !(1 == ~T8_E~0); 1129543#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1129542#L997-3 assume !(1 == ~E_1~0); 1129540#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1129538#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1129536#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1129534#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1129533#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1129532#L1027-3 assume !(1 == ~E_7~0); 1129531#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1129530#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1129521#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1129520#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1129519#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1129518#L1322 assume !(0 == start_simulation_~tmp~3#1); 1129517#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1129511#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1129502#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1129500#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1129498#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1129495#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1129493#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1129491#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1097530#L1303-2 [2021-12-15 17:20:57,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2021-12-15 17:20:57,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509898481] [2021-12-15 17:20:57,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,058 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:57,066 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:20:57,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:20:57,097 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:20:57,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,098 INFO L85 PathProgramCache]: Analyzing trace with hash 920889495, now seen corresponding path program 1 times [2021-12-15 17:20:57,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142214729] [2021-12-15 17:20:57,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,099 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,264 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142214729] [2021-12-15 17:20:57,264 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142214729] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852347804] [2021-12-15 17:20:57,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,265 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,266 INFO L87 Difference]: Start difference. First operand 43073 states and 60541 transitions. cyclomatic complexity: 17472 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,473 INFO L93 Difference]: Finished difference Result 64817 states and 90650 transitions. [2021-12-15 17:20:57,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,475 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64817 states and 90650 transitions. [2021-12-15 17:20:57,724 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 64592 [2021-12-15 17:20:57,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64817 states to 64817 states and 90650 transitions. [2021-12-15 17:20:57,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64817 [2021-12-15 17:20:57,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64817 [2021-12-15 17:20:57,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64817 states and 90650 transitions. [2021-12-15 17:20:57,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,965 INFO L681 BuchiCegarLoop]: Abstraction has 64817 states and 90650 transitions. [2021-12-15 17:20:58,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64817 states and 90650 transitions. [2021-12-15 17:20:58,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64817 to 64657. [2021-12-15 17:20:58,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64657 states, 64657 states have (on average 1.3985492676740336) internal successors, (90426), 64656 states have internal predecessors, (90426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:59,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64657 states to 64657 states and 90426 transitions. [2021-12-15 17:20:59,119 INFO L704 BuchiCegarLoop]: Abstraction has 64657 states and 90426 transitions. [2021-12-15 17:20:59,119 INFO L587 BuchiCegarLoop]: Abstraction has 64657 states and 90426 transitions. [2021-12-15 17:20:59,119 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-15 17:20:59,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64657 states and 90426 transitions. [2021-12-15 17:20:59,291 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 64432 [2021-12-15 17:20:59,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:59,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:59,293 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,293 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,293 INFO L791 eck$LassoCheckResult]: Stem: 1205442#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1205443#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1204667#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1204668#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1204700#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1205379#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1205380#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1204956#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1204957#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1204893#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1204894#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1205156#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1205125#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1205126#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1205447#L854 assume !(0 == ~M_E~0); 1205223#L854-2 assume !(0 == ~T1_E~0); 1205224#L859-1 assume !(0 == ~T2_E~0); 1204764#L864-1 assume !(0 == ~T3_E~0); 1204765#L869-1 assume !(0 == ~T4_E~0); 1204878#L874-1 assume !(0 == ~T5_E~0); 1205764#L879-1 assume !(0 == ~T6_E~0); 1205207#L884-1 assume !(0 == ~T7_E~0); 1204634#L889-1 assume !(0 == ~T8_E~0); 1204635#L894-1 assume !(0 == ~E_M~0); 1204970#L899-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1205454#L904-1 assume !(0 == ~E_2~0); 1205455#L909-1 assume !(0 == ~E_3~0); 1205367#L914-1 assume !(0 == ~E_4~0); 1205368#L919-1 assume !(0 == ~E_5~0); 1205056#L924-1 assume !(0 == ~E_6~0); 1205057#L929-1 assume !(0 == ~E_7~0); 1205781#L934-1 assume !(0 == ~E_8~0); 1205782#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1204651#L418 assume !(1 == ~m_pc~0); 1204652#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1205879#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1205877#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1205874#L1061 assume !(0 != activate_threads_~tmp~1#1); 1205873#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1205813#L437 assume !(1 == ~t1_pc~0); 1205814#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1205599#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1205600#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1205007#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1205008#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1205580#L456 assume !(1 == ~t2_pc~0); 1205581#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1205805#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1205806#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1205625#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1205626#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1204759#L475 assume !(1 == ~t3_pc~0); 1204760#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1204820#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1204821#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1205747#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1205748#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1205675#L494 assume !(1 == ~t4_pc~0); 1205676#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1205336#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1205337#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1205847#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1205848#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1204816#L513 assume !(1 == ~t5_pc~0); 1204817#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1205828#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1205829#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1204775#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1204776#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1204729#L532 assume !(1 == ~t6_pc~0); 1204730#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1205185#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1205186#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1205789#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1205790#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1205631#L551 assume !(1 == ~t7_pc~0); 1205632#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1205402#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1205403#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1205872#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1205842#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1205843#L570 assume !(1 == ~t8_pc~0); 1205753#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1205754#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1205457#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1205458#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1204757#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1204758#L952 assume !(1 == ~M_E~0); 1204701#L952-2 assume !(1 == ~T1_E~0); 1204702#L957-1 assume !(1 == ~T2_E~0); 1205819#L962-1 assume !(1 == ~T3_E~0); 1205820#L967-1 assume !(1 == ~T4_E~0); 1205798#L972-1 assume !(1 == ~T5_E~0); 1205799#L977-1 assume !(1 == ~T6_E~0); 1205846#L982-1 assume !(1 == ~T7_E~0); 1204884#L987-1 assume !(1 == ~T8_E~0); 1204885#L992-1 assume !(1 == ~E_M~0); 1204895#L997-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1205251#L1002-1 assume !(1 == ~E_2~0); 1205239#L1007-1 assume !(1 == ~E_3~0); 1204636#L1012-1 assume !(1 == ~E_4~0); 1204637#L1017-1 assume !(1 == ~E_5~0); 1205242#L1022-1 assume !(1 == ~E_6~0); 1205243#L1027-1 assume !(1 == ~E_7~0); 1205266#L1032-1 assume !(1 == ~E_8~0); 1205430#L1037-1 assume { :end_inline_reset_delta_events } true; 1205431#L1303-2 [2021-12-15 17:20:59,294 INFO L793 eck$LassoCheckResult]: Loop: 1205431#L1303-2 assume !false; 1216143#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1216140#L829 assume !false; 1216139#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1216030#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1216017#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1216010#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1216000#L712 assume !(0 != eval_~tmp~0#1); 1216001#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1227504#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1227502#L854-3 assume !(0 == ~M_E~0); 1227500#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1227498#L859-3 assume !(0 == ~T2_E~0); 1227496#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1227494#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1227492#L874-3 assume !(0 == ~T5_E~0); 1227490#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1227487#L884-3 assume !(0 == ~T7_E~0); 1227485#L889-3 assume !(0 == ~T8_E~0); 1227481#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1227477#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1227474#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1227471#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1227468#L914-3 assume !(0 == ~E_4~0); 1227464#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1227460#L924-3 assume !(0 == ~E_6~0); 1227456#L929-3 assume !(0 == ~E_7~0); 1227453#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1227450#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1227446#L418-30 assume 1 == ~m_pc~0; 1227442#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1227438#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1227434#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1227430#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1227427#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1227422#L437-30 assume !(1 == ~t1_pc~0); 1227419#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1227416#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1227413#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1227410#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1227407#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1227404#L456-30 assume !(1 == ~t2_pc~0); 1227402#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1227399#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1227397#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1227395#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1227394#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1227393#L475-30 assume !(1 == ~t3_pc~0); 1227154#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1227389#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1227386#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1227382#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1227378#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1227373#L494-30 assume 1 == ~t4_pc~0; 1227368#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1227364#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1227360#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1227356#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1227352#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1227346#L513-30 assume !(1 == ~t5_pc~0); 1218792#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1227336#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1227331#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1227327#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1227324#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1227321#L532-30 assume !(1 == ~t6_pc~0); 1227316#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1227313#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1227309#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1227305#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1227301#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1219745#L551-30 assume !(1 == ~t7_pc~0); 1219743#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1219741#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1219738#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1219736#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1219724#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1216546#L570-30 assume !(1 == ~t8_pc~0); 1216544#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1216542#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1216540#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1216538#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1216536#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1216534#L952-3 assume !(1 == ~M_E~0); 1216532#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1216530#L957-3 assume !(1 == ~T2_E~0); 1216528#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1216526#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1216524#L972-3 assume !(1 == ~T5_E~0); 1216522#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1216520#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1216518#L987-3 assume !(1 == ~T8_E~0); 1216516#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1216515#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1216513#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1216512#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1216511#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1216509#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1216508#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1216507#L1027-3 assume !(1 == ~E_7~0); 1216506#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1216505#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1216399#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1216393#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1216387#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1216382#L1322 assume !(0 == start_simulation_~tmp~3#1); 1216379#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1216213#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1216197#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1216191#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1216183#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1216176#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1216170#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1216162#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1205431#L1303-2 [2021-12-15 17:20:59,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1215057335, now seen corresponding path program 1 times [2021-12-15 17:20:59,294 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21264564] [2021-12-15 17:20:59,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,295 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:59,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:59,317 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:59,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21264564] [2021-12-15 17:20:59,317 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21264564] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:59,317 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:59,317 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:59,317 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [713642706] [2021-12-15 17:20:59,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:59,318 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:59,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,318 INFO L85 PathProgramCache]: Analyzing trace with hash -1521754926, now seen corresponding path program 1 times [2021-12-15 17:20:59,318 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,318 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821955364] [2021-12-15 17:20:59,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,319 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:59,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:59,343 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:59,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821955364] [2021-12-15 17:20:59,344 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821955364] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:59,344 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:59,344 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:59,344 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794639236] [2021-12-15 17:20:59,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:59,344 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:59,345 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:59,345 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:59,345 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:59,345 INFO L87 Difference]: Start difference. First operand 64657 states and 90426 transitions. cyclomatic complexity: 25773 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:59,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:59,493 INFO L93 Difference]: Finished difference Result 43073 states and 60107 transitions. [2021-12-15 17:20:59,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:59,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43073 states and 60107 transitions. [2021-12-15 17:20:59,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 42928 [2021-12-15 17:20:59,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43073 states to 43073 states and 60107 transitions. [2021-12-15 17:20:59,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43073 [2021-12-15 17:20:59,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43073 [2021-12-15 17:20:59,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43073 states and 60107 transitions. [2021-12-15 17:20:59,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:59,794 INFO L681 BuchiCegarLoop]: Abstraction has 43073 states and 60107 transitions. [2021-12-15 17:20:59,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43073 states and 60107 transitions. [2021-12-15 17:21:00,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43073 to 43073. [2021-12-15 17:21:00,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43073 states, 43073 states have (on average 1.3954681587073108) internal successors, (60107), 43072 states have internal predecessors, (60107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43073 states to 43073 states and 60107 transitions. [2021-12-15 17:21:00,154 INFO L704 BuchiCegarLoop]: Abstraction has 43073 states and 60107 transitions. [2021-12-15 17:21:00,154 INFO L587 BuchiCegarLoop]: Abstraction has 43073 states and 60107 transitions. [2021-12-15 17:21:00,155 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-15 17:21:00,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43073 states and 60107 transitions. [2021-12-15 17:21:00,584 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 42928 [2021-12-15 17:21:00,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:00,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:00,586 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,586 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,586 INFO L791 eck$LassoCheckResult]: Stem: 1313163#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1313164#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1312402#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1312403#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1312438#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1313106#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1313107#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1312688#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1312689#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1312628#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1312629#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1312884#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1312853#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1312854#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1313166#L854 assume !(0 == ~M_E~0); 1312946#L854-2 assume !(0 == ~T1_E~0); 1312947#L859-1 assume !(0 == ~T2_E~0); 1312501#L864-1 assume !(0 == ~T3_E~0); 1312502#L869-1 assume !(0 == ~T4_E~0); 1312616#L874-1 assume !(0 == ~T5_E~0); 1313458#L879-1 assume !(0 == ~T6_E~0); 1312933#L884-1 assume !(0 == ~T7_E~0); 1312373#L889-1 assume !(0 == ~T8_E~0); 1312374#L894-1 assume !(0 == ~E_M~0); 1312704#L899-1 assume !(0 == ~E_1~0); 1313173#L904-1 assume !(0 == ~E_2~0); 1312872#L909-1 assume !(0 == ~E_3~0); 1312873#L914-1 assume !(0 == ~E_4~0); 1313093#L919-1 assume !(0 == ~E_5~0); 1312786#L924-1 assume !(0 == ~E_6~0); 1312602#L929-1 assume !(0 == ~E_7~0); 1312603#L934-1 assume !(0 == ~E_8~0); 1312850#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1312391#L418 assume !(1 == ~m_pc~0); 1312364#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1313384#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1313385#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1313298#L1061 assume !(0 != activate_threads_~tmp~1#1); 1313203#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1313204#L437 assume !(1 == ~t1_pc~0); 1313444#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1313307#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1313250#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1312739#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1312740#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1313290#L456 assume !(1 == ~t2_pc~0); 1312653#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1312652#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1313009#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1313010#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1312984#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1312496#L475 assume !(1 == ~t3_pc~0); 1312497#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1312559#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1312560#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1313445#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1312743#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1312744#L494 assume !(1 == ~t4_pc~0); 1312781#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1312782#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1312999#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1313000#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1313121#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1312552#L513 assume !(1 == ~t5_pc~0); 1312553#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1312783#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1312822#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1312512#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1312513#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1312465#L532 assume !(1 == ~t6_pc~0); 1312466#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1312617#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1312911#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1312994#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1312707#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1312708#L551 assume !(1 == ~t7_pc~0); 1313176#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1313125#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1313126#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1313361#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1313519#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1312895#L570 assume !(1 == ~t8_pc~0); 1312896#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1313411#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1313175#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1313007#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1312492#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1312493#L952 assume !(1 == ~M_E~0); 1312439#L952-2 assume !(1 == ~T1_E~0); 1312440#L957-1 assume !(1 == ~T2_E~0); 1313269#L962-1 assume !(1 == ~T3_E~0); 1313024#L967-1 assume !(1 == ~T4_E~0); 1313025#L972-1 assume !(1 == ~T5_E~0); 1313339#L977-1 assume !(1 == ~T6_E~0); 1313340#L982-1 assume !(1 == ~T7_E~0); 1312619#L987-1 assume !(1 == ~T8_E~0); 1312620#L992-1 assume !(1 == ~E_M~0); 1312630#L997-1 assume !(1 == ~E_1~0); 1312982#L1002-1 assume !(1 == ~E_2~0); 1312970#L1007-1 assume !(1 == ~E_3~0); 1312375#L1012-1 assume !(1 == ~E_4~0); 1312376#L1017-1 assume !(1 == ~E_5~0); 1312971#L1022-1 assume !(1 == ~E_6~0); 1312972#L1027-1 assume !(1 == ~E_7~0); 1312995#L1032-1 assume !(1 == ~E_8~0); 1313148#L1037-1 assume { :end_inline_reset_delta_events } true; 1313149#L1303-2 [2021-12-15 17:21:00,587 INFO L793 eck$LassoCheckResult]: Loop: 1313149#L1303-2 assume !false; 1329169#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1329145#L829 assume !false; 1329141#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1328984#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1328972#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1328964#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1328955#L712 assume !(0 != eval_~tmp~0#1); 1328956#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1332962#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1332960#L854-3 assume !(0 == ~M_E~0); 1332957#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1332955#L859-3 assume !(0 == ~T2_E~0); 1332953#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1332951#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1332949#L874-3 assume !(0 == ~T5_E~0); 1332947#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1332945#L884-3 assume !(0 == ~T7_E~0); 1332943#L889-3 assume !(0 == ~T8_E~0); 1332941#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1332936#L899-3 assume !(0 == ~E_1~0); 1332932#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1332931#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1332930#L914-3 assume !(0 == ~E_4~0); 1332929#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1332928#L924-3 assume !(0 == ~E_6~0); 1332927#L929-3 assume !(0 == ~E_7~0); 1332926#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1332924#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1332923#L418-30 assume 1 == ~m_pc~0; 1332921#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1332920#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1332916#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1332912#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1332910#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1332907#L437-30 assume !(1 == ~t1_pc~0); 1332905#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1332903#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1332901#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1332899#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1332897#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1332895#L456-30 assume 1 == ~t2_pc~0; 1332892#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1332890#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1332887#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1332885#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1332883#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1332881#L475-30 assume !(1 == ~t3_pc~0); 1328040#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1332878#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1332877#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1332874#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1332872#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1332870#L494-30 assume !(1 == ~t4_pc~0); 1332868#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1332865#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1332863#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1332860#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1332858#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1332856#L513-30 assume !(1 == ~t5_pc~0); 1332328#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1332853#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1332852#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1332851#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1332850#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1332849#L532-30 assume 1 == ~t6_pc~0; 1332848#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1332845#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1332842#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1332840#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1332838#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1329503#L551-30 assume !(1 == ~t7_pc~0); 1329501#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1329499#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1329497#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1329495#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1329494#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1329493#L570-30 assume !(1 == ~t8_pc~0); 1319591#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1329490#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1329488#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1329486#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1329472#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1329468#L952-3 assume !(1 == ~M_E~0); 1329466#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1329464#L957-3 assume !(1 == ~T2_E~0); 1329462#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1329459#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1329457#L972-3 assume !(1 == ~T5_E~0); 1329455#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1329453#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1329451#L987-3 assume !(1 == ~T8_E~0); 1329449#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1329447#L997-3 assume !(1 == ~E_1~0); 1329445#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1329443#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1329440#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1329438#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1329436#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1329434#L1027-3 assume !(1 == ~E_7~0); 1329432#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1329431#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1329417#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1329415#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1329413#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1329411#L1322 assume !(0 == start_simulation_~tmp~3#1); 1329364#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1329251#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1329243#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1329241#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1329239#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1329230#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1329209#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1329199#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1313149#L1303-2 [2021-12-15 17:21:00,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:00,588 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2021-12-15 17:21:00,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:00,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145404838] [2021-12-15 17:21:00,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:00,588 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:00,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:00,596 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:00,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:00,626 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:00,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:00,627 INFO L85 PathProgramCache]: Analyzing trace with hash -994719919, now seen corresponding path program 1 times [2021-12-15 17:21:00,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:00,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706371250] [2021-12-15 17:21:00,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:00,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:00,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:00,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:00,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:00,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706371250] [2021-12-15 17:21:00,662 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706371250] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:00,662 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:00,662 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:00,662 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834934635] [2021-12-15 17:21:00,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:00,663 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:00,663 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:00,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:00,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:00,664 INFO L87 Difference]: Start difference. First operand 43073 states and 60107 transitions. cyclomatic complexity: 17038 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:00,984 INFO L93 Difference]: Finished difference Result 78641 states and 108507 transitions. [2021-12-15 17:21:00,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:21:00,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78641 states and 108507 transitions. [2021-12-15 17:21:01,323 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 78464 [2021-12-15 17:21:01,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78641 states to 78641 states and 108507 transitions. [2021-12-15 17:21:01,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78641 [2021-12-15 17:21:01,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78641 [2021-12-15 17:21:01,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78641 states and 108507 transitions. [2021-12-15 17:21:01,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:01,659 INFO L681 BuchiCegarLoop]: Abstraction has 78641 states and 108507 transitions. [2021-12-15 17:21:01,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78641 states and 108507 transitions. [2021-12-15 17:21:02,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78641 to 43265. [2021-12-15 17:21:02,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43265 states, 43265 states have (on average 1.393713163064833) internal successors, (60299), 43264 states have internal predecessors, (60299), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43265 states to 43265 states and 60299 transitions. [2021-12-15 17:21:02,660 INFO L704 BuchiCegarLoop]: Abstraction has 43265 states and 60299 transitions. [2021-12-15 17:21:02,661 INFO L587 BuchiCegarLoop]: Abstraction has 43265 states and 60299 transitions. [2021-12-15 17:21:02,661 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-15 17:21:02,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43265 states and 60299 transitions. [2021-12-15 17:21:02,783 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 43120 [2021-12-15 17:21:02,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,785 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,785 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,786 INFO L791 eck$LassoCheckResult]: Stem: 1434889#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1434890#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1434131#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1434132#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1434168#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1434830#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1434831#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1434417#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1434418#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1434358#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1434359#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1434616#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1434587#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1434588#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1434894#L854 assume !(0 == ~M_E~0); 1434677#L854-2 assume !(0 == ~T1_E~0); 1434678#L859-1 assume !(0 == ~T2_E~0); 1434231#L864-1 assume !(0 == ~T3_E~0); 1434232#L869-1 assume !(0 == ~T4_E~0); 1434347#L874-1 assume !(0 == ~T5_E~0); 1435189#L879-1 assume !(0 == ~T6_E~0); 1434664#L884-1 assume !(0 == ~T7_E~0); 1434103#L889-1 assume !(0 == ~T8_E~0); 1434104#L894-1 assume !(0 == ~E_M~0); 1434433#L899-1 assume !(0 == ~E_1~0); 1434901#L904-1 assume !(0 == ~E_2~0); 1434603#L909-1 assume !(0 == ~E_3~0); 1434604#L914-1 assume !(0 == ~E_4~0); 1434816#L919-1 assume !(0 == ~E_5~0); 1434521#L924-1 assume !(0 == ~E_6~0); 1434331#L929-1 assume !(0 == ~E_7~0); 1434332#L934-1 assume !(0 == ~E_8~0); 1434584#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1434120#L418 assume !(1 == ~m_pc~0); 1434094#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1435113#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1435114#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1435031#L1061 assume !(0 != activate_threads_~tmp~1#1); 1434930#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1434931#L437 assume !(1 == ~t1_pc~0); 1435174#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1435040#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1434980#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1434474#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1434475#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1435022#L456 assume !(1 == ~t2_pc~0); 1434384#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1434383#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1434736#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1434737#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1434711#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1434226#L475 assume !(1 == ~t3_pc~0); 1434227#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1434287#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1434288#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1435177#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1434478#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1434479#L494 assume !(1 == ~t4_pc~0); 1434517#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1434518#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1434726#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1434727#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1434845#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1434282#L513 assume !(1 == ~t5_pc~0); 1434283#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1434519#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1434556#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1434242#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1434243#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1434195#L532 assume !(1 == ~t6_pc~0); 1434196#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1434348#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1434641#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1434721#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1434440#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1434441#L551 assume !(1 == ~t7_pc~0); 1434904#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1434849#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1434850#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1435087#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1435251#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1434625#L570 assume !(1 == ~t8_pc~0); 1434626#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1435145#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1434903#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1434732#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1434220#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1434221#L952 assume !(1 == ~M_E~0); 1434169#L952-2 assume !(1 == ~T1_E~0); 1434170#L957-1 assume !(1 == ~T2_E~0); 1435001#L962-1 assume !(1 == ~T3_E~0); 1434749#L967-1 assume !(1 == ~T4_E~0); 1434750#L972-1 assume !(1 == ~T5_E~0); 1435068#L977-1 assume !(1 == ~T6_E~0); 1435069#L982-1 assume !(1 == ~T7_E~0); 1434350#L987-1 assume !(1 == ~T8_E~0); 1434351#L992-1 assume !(1 == ~E_M~0); 1434360#L997-1 assume !(1 == ~E_1~0); 1434709#L1002-1 assume !(1 == ~E_2~0); 1434697#L1007-1 assume !(1 == ~E_3~0); 1434105#L1012-1 assume !(1 == ~E_4~0); 1434106#L1017-1 assume !(1 == ~E_5~0); 1434698#L1022-1 assume !(1 == ~E_6~0); 1434699#L1027-1 assume !(1 == ~E_7~0); 1434722#L1032-1 assume !(1 == ~E_8~0); 1434874#L1037-1 assume { :end_inline_reset_delta_events } true; 1434875#L1303-2 [2021-12-15 17:21:02,786 INFO L793 eck$LassoCheckResult]: Loop: 1434875#L1303-2 assume !false; 1472198#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1472192#L829 assume !false; 1472135#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1472124#L650 assume !(0 == ~m_st~0); 1472125#L654 assume !(0 == ~t1_st~0); 1472128#L658 assume !(0 == ~t2_st~0); 1472122#L662 assume !(0 == ~t3_st~0); 1472123#L666 assume !(0 == ~t4_st~0); 1472127#L670 assume !(0 == ~t5_st~0); 1472120#L674 assume !(0 == ~t6_st~0); 1472121#L678 assume !(0 == ~t7_st~0); 1472126#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1472129#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1450841#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1450842#L712 assume !(0 != eval_~tmp~0#1); 1472568#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1472564#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1472565#L854-3 assume !(0 == ~M_E~0); 1472560#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1472561#L859-3 assume !(0 == ~T2_E~0); 1472556#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1472557#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1472552#L874-3 assume !(0 == ~T5_E~0); 1472553#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1472548#L884-3 assume !(0 == ~T7_E~0); 1472549#L889-3 assume !(0 == ~T8_E~0); 1472544#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1472545#L899-3 assume !(0 == ~E_1~0); 1472540#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1472541#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1472536#L914-3 assume !(0 == ~E_4~0); 1472537#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1472532#L924-3 assume !(0 == ~E_6~0); 1472533#L929-3 assume !(0 == ~E_7~0); 1472527#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1472528#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1472518#L418-30 assume 1 == ~m_pc~0; 1472519#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1472506#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1472507#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1472496#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1472497#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1472490#L437-30 assume !(1 == ~t1_pc~0); 1472491#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1472484#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1472485#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1472478#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1472479#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1472470#L456-30 assume 1 == ~t2_pc~0; 1472471#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1472461#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1472462#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1472421#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1472422#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1472363#L475-30 assume !(1 == ~t3_pc~0); 1472362#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1472360#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1472358#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1472356#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1472354#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1472352#L494-30 assume 1 == ~t4_pc~0; 1472348#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1472346#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1472344#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1472342#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1472340#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1472338#L513-30 assume !(1 == ~t5_pc~0); 1452988#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1472336#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1472334#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1472332#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1472330#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1472328#L532-30 assume !(1 == ~t6_pc~0); 1472324#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1472322#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1472320#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1472318#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1472316#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1472314#L551-30 assume !(1 == ~t7_pc~0); 1457675#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1472312#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1472310#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1472308#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1472306#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1472303#L570-30 assume !(1 == ~t8_pc~0); 1472302#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1472301#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1472300#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1472299#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1472298#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1472297#L952-3 assume !(1 == ~M_E~0); 1472296#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1472295#L957-3 assume !(1 == ~T2_E~0); 1472294#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1472293#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1472292#L972-3 assume !(1 == ~T5_E~0); 1472291#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1472290#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1472289#L987-3 assume !(1 == ~T8_E~0); 1472288#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1472287#L997-3 assume !(1 == ~E_1~0); 1472286#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1472285#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1472284#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1472283#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1472282#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1472281#L1027-3 assume !(1 == ~E_7~0); 1472280#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1472279#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1472270#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1472266#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1472263#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1472258#L1322 assume !(0 == start_simulation_~tmp~3#1); 1472254#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1472252#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1472241#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1472237#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1472232#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1472227#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1472222#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1472218#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1434875#L1303-2 [2021-12-15 17:21:02,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2021-12-15 17:21:02,787 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020864551] [2021-12-15 17:21:02,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,788 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:02,796 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:02,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:02,823 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:02,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1559330683, now seen corresponding path program 1 times [2021-12-15 17:21:02,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,824 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612286949] [2021-12-15 17:21:02,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,824 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,854 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612286949] [2021-12-15 17:21:02,854 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1612286949] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,854 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:02,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021768668] [2021-12-15 17:21:02,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,855 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:02,855 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:02,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:02,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:02,856 INFO L87 Difference]: Start difference. First operand 43265 states and 60299 transitions. cyclomatic complexity: 17038 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:03,214 INFO L93 Difference]: Finished difference Result 84929 states and 117438 transitions. [2021-12-15 17:21:03,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-15 17:21:03,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84929 states and 117438 transitions. [2021-12-15 17:21:03,548 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 84704 [2021-12-15 17:21:03,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84929 states to 84929 states and 117438 transitions. [2021-12-15 17:21:03,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84929 [2021-12-15 17:21:03,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84929 [2021-12-15 17:21:03,825 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84929 states and 117438 transitions. [2021-12-15 17:21:03,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:03,870 INFO L681 BuchiCegarLoop]: Abstraction has 84929 states and 117438 transitions. [2021-12-15 17:21:03,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84929 states and 117438 transitions. [2021-12-15 17:21:04,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84929 to 44804. [2021-12-15 17:21:04,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44804 states, 44804 states have (on average 1.3801892688152844) internal successors, (61838), 44803 states have internal predecessors, (61838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:04,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44804 states to 44804 states and 61838 transitions. [2021-12-15 17:21:04,837 INFO L704 BuchiCegarLoop]: Abstraction has 44804 states and 61838 transitions. [2021-12-15 17:21:04,837 INFO L587 BuchiCegarLoop]: Abstraction has 44804 states and 61838 transitions. [2021-12-15 17:21:04,837 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-15 17:21:04,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44804 states and 61838 transitions. [2021-12-15 17:21:04,960 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 44656 [2021-12-15 17:21:04,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:04,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:04,962 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,962 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,962 INFO L791 eck$LassoCheckResult]: Stem: 1563107#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1563108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1562339#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1562340#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1562375#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1563047#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1563048#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1562622#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1562623#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1562563#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1562564#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1562819#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1562791#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1562792#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1563112#L854 assume !(0 == ~M_E~0); 1562884#L854-2 assume !(0 == ~T1_E~0); 1562885#L859-1 assume !(0 == ~T2_E~0); 1562438#L864-1 assume !(0 == ~T3_E~0); 1562439#L869-1 assume !(0 == ~T4_E~0); 1562552#L874-1 assume !(0 == ~T5_E~0); 1563415#L879-1 assume !(0 == ~T6_E~0); 1562868#L884-1 assume !(0 == ~T7_E~0); 1562311#L889-1 assume !(0 == ~T8_E~0); 1562312#L894-1 assume !(0 == ~E_M~0); 1562640#L899-1 assume !(0 == ~E_1~0); 1563120#L904-1 assume !(0 == ~E_2~0); 1562806#L909-1 assume !(0 == ~E_3~0); 1562807#L914-1 assume !(0 == ~E_4~0); 1563033#L919-1 assume !(0 == ~E_5~0); 1562728#L924-1 assume !(0 == ~E_6~0); 1562535#L929-1 assume !(0 == ~E_7~0); 1562536#L934-1 assume !(0 == ~E_8~0); 1562788#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1562328#L418 assume !(1 == ~m_pc~0); 1562302#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1563348#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1563349#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1563261#L1061 assume !(0 != activate_threads_~tmp~1#1); 1563150#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1563151#L437 assume !(1 == ~t1_pc~0); 1563403#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1563269#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1563203#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1562681#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1562682#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1563253#L456 assume !(1 == ~t2_pc~0); 1562587#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1562586#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1562949#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1562950#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1562923#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1562433#L475 assume !(1 == ~t3_pc~0); 1562434#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1562492#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1562493#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1563404#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1562685#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1562686#L494 assume !(1 == ~t4_pc~0); 1562723#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1562724#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1562938#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1562939#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1563063#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1562487#L513 assume !(1 == ~t5_pc~0); 1562488#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1562725#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1562762#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1562449#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1562450#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1562402#L532 assume !(1 == ~t6_pc~0); 1562403#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1562553#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1562845#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1562932#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1562647#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1562648#L551 assume !(1 == ~t7_pc~0); 1563123#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1563068#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1563069#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1563324#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1563471#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1562829#L570 assume !(1 == ~t8_pc~0); 1562830#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1563375#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1563122#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1562944#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1562427#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1562428#L952 assume !(1 == ~M_E~0); 1562376#L952-2 assume !(1 == ~T1_E~0); 1562377#L957-1 assume !(1 == ~T2_E~0); 1563232#L962-1 assume !(1 == ~T3_E~0); 1562965#L967-1 assume !(1 == ~T4_E~0); 1562966#L972-1 assume !(1 == ~T5_E~0); 1563299#L977-1 assume !(1 == ~T6_E~0); 1563300#L982-1 assume !(1 == ~T7_E~0); 1562555#L987-1 assume !(1 == ~T8_E~0); 1562556#L992-1 assume !(1 == ~E_M~0); 1562565#L997-1 assume !(1 == ~E_1~0); 1562921#L1002-1 assume !(1 == ~E_2~0); 1562909#L1007-1 assume !(1 == ~E_3~0); 1562313#L1012-1 assume !(1 == ~E_4~0); 1562314#L1017-1 assume !(1 == ~E_5~0); 1562910#L1022-1 assume !(1 == ~E_6~0); 1562911#L1027-1 assume !(1 == ~E_7~0); 1562933#L1032-1 assume !(1 == ~E_8~0); 1563093#L1037-1 assume { :end_inline_reset_delta_events } true; 1563094#L1303-2 [2021-12-15 17:21:04,963 INFO L793 eck$LassoCheckResult]: Loop: 1563094#L1303-2 assume !false; 1605454#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1605453#L829 assume !false; 1605452#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1605446#L650 assume !(0 == ~m_st~0); 1605447#L654 assume !(0 == ~t1_st~0); 1605450#L658 assume !(0 == ~t2_st~0); 1605444#L662 assume !(0 == ~t3_st~0); 1605445#L666 assume !(0 == ~t4_st~0); 1605449#L670 assume !(0 == ~t5_st~0); 1605442#L674 assume !(0 == ~t6_st~0); 1605443#L678 assume !(0 == ~t7_st~0); 1605448#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1605451#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1606674#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1606673#L712 assume !(0 != eval_~tmp~0#1); 1606672#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1606671#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1606670#L854-3 assume !(0 == ~M_E~0); 1606668#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1606667#L859-3 assume !(0 == ~T2_E~0); 1606666#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1606665#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1606664#L874-3 assume !(0 == ~T5_E~0); 1606663#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1606662#L884-3 assume !(0 == ~T7_E~0); 1606661#L889-3 assume !(0 == ~T8_E~0); 1606660#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1606659#L899-3 assume !(0 == ~E_1~0); 1606658#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1606657#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1606656#L914-3 assume !(0 == ~E_4~0); 1606655#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1606654#L924-3 assume !(0 == ~E_6~0); 1606653#L929-3 assume !(0 == ~E_7~0); 1606652#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1606651#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1606650#L418-30 assume 1 == ~m_pc~0; 1606648#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1606649#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1606669#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1606643#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1606642#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1606641#L437-30 assume !(1 == ~t1_pc~0); 1606640#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1606639#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1606638#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1606637#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1606636#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1606635#L456-30 assume 1 == ~t2_pc~0; 1606633#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1606632#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1606631#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1606036#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1606033#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1606034#L475-30 assume !(1 == ~t3_pc~0); 1601592#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1606606#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1606604#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1606602#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1606601#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1605823#L494-30 assume !(1 == ~t4_pc~0); 1605824#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1605793#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1605794#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1605607#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1605605#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1605603#L513-30 assume !(1 == ~t5_pc~0); 1605098#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1605601#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1605600#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1605599#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1605598#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1605597#L532-30 assume !(1 == ~t6_pc~0); 1605595#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1605594#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1605592#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1605569#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1605549#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1605547#L551-30 assume !(1 == ~t7_pc~0); 1599363#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1605541#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1605532#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1605525#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1605518#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1605508#L570-30 assume !(1 == ~t8_pc~0); 1605507#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1605506#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1605505#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1605504#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1605503#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1605502#L952-3 assume !(1 == ~M_E~0); 1605501#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1605500#L957-3 assume !(1 == ~T2_E~0); 1605499#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1605498#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1605497#L972-3 assume !(1 == ~T5_E~0); 1605496#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1605495#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1605494#L987-3 assume !(1 == ~T8_E~0); 1605493#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1605492#L997-3 assume !(1 == ~E_1~0); 1605491#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1605490#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1605489#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1605488#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1605487#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1605486#L1027-3 assume !(1 == ~E_7~0); 1605485#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1605484#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1605475#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1605474#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1605473#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1605472#L1322 assume !(0 == start_simulation_~tmp~3#1); 1605471#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1605469#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1605461#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1605460#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1605459#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1605458#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1605457#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1605456#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1563094#L1303-2 [2021-12-15 17:21:04,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:04,964 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 5 times [2021-12-15 17:21:04,964 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:04,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705273859] [2021-12-15 17:21:04,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:04,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:04,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:04,991 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:04,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:05,023 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:05,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:05,025 INFO L85 PathProgramCache]: Analyzing trace with hash -1707104452, now seen corresponding path program 1 times [2021-12-15 17:21:05,025 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:05,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043347199] [2021-12-15 17:21:05,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:05,026 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:05,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:05,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:05,093 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:05,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043347199] [2021-12-15 17:21:05,093 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043347199] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:05,093 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:05,093 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:05,093 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083547331] [2021-12-15 17:21:05,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:05,094 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:05,094 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:05,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:05,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:05,095 INFO L87 Difference]: Start difference. First operand 44804 states and 61838 transitions. cyclomatic complexity: 17038 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:05,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:05,382 INFO L93 Difference]: Finished difference Result 57316 states and 79245 transitions. [2021-12-15 17:21:05,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:05,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57316 states and 79245 transitions. [2021-12-15 17:21:05,618 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 57168 [2021-12-15 17:21:05,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57316 states to 57316 states and 79245 transitions. [2021-12-15 17:21:05,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57316 [2021-12-15 17:21:05,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57316 [2021-12-15 17:21:05,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57316 states and 79245 transitions. [2021-12-15 17:21:05,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:05,842 INFO L681 BuchiCegarLoop]: Abstraction has 57316 states and 79245 transitions. [2021-12-15 17:21:05,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57316 states and 79245 transitions. [2021-12-15 17:21:06,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57316 to 44900. [2021-12-15 17:21:06,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44900 states, 44900 states have (on average 1.368663697104677) internal successors, (61453), 44899 states have internal predecessors, (61453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:06,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44900 states to 44900 states and 61453 transitions. [2021-12-15 17:21:06,718 INFO L704 BuchiCegarLoop]: Abstraction has 44900 states and 61453 transitions. [2021-12-15 17:21:06,718 INFO L587 BuchiCegarLoop]: Abstraction has 44900 states and 61453 transitions. [2021-12-15 17:21:06,718 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-15 17:21:06,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44900 states and 61453 transitions. [2021-12-15 17:21:06,829 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 44752 [2021-12-15 17:21:06,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:06,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:06,830 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,831 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,831 INFO L791 eck$LassoCheckResult]: Stem: 1665264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1665265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1664474#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1664475#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1664510#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1665201#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1665202#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1664759#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1664760#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1664701#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1664702#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1664966#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1664935#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1664936#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1665267#L854 assume !(0 == ~M_E~0); 1665033#L854-2 assume !(0 == ~T1_E~0); 1665034#L859-1 assume !(0 == ~T2_E~0); 1664573#L864-1 assume !(0 == ~T3_E~0); 1664574#L869-1 assume !(0 == ~T4_E~0); 1664689#L874-1 assume !(0 == ~T5_E~0); 1665617#L879-1 assume !(0 == ~T6_E~0); 1665020#L884-1 assume !(0 == ~T7_E~0); 1664445#L889-1 assume !(0 == ~T8_E~0); 1664446#L894-1 assume !(0 == ~E_M~0); 1664776#L899-1 assume !(0 == ~E_1~0); 1665275#L904-1 assume !(0 == ~E_2~0); 1664952#L909-1 assume !(0 == ~E_3~0); 1664953#L914-1 assume !(0 == ~E_4~0); 1665184#L919-1 assume !(0 == ~E_5~0); 1664867#L924-1 assume !(0 == ~E_6~0); 1664673#L929-1 assume !(0 == ~E_7~0); 1664674#L934-1 assume !(0 == ~E_8~0); 1664932#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1664463#L418 assume !(1 == ~m_pc~0); 1664436#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1665527#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1665528#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1665424#L1061 assume !(0 != activate_threads_~tmp~1#1); 1665304#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1665305#L437 assume !(1 == ~t1_pc~0); 1665597#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1665435#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1665366#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1664818#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1664819#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1665416#L456 assume !(1 == ~t2_pc~0); 1664726#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1664725#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1665096#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1665097#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1665070#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1664568#L475 assume !(1 == ~t3_pc~0); 1664569#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1664629#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1664630#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1665599#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1664822#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1664823#L494 assume !(1 == ~t4_pc~0); 1664861#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1664862#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1665741#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1665740#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1665219#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1664624#L513 assume !(1 == ~t5_pc~0); 1664625#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1664863#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1664904#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1664584#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1664585#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1664537#L532 assume !(1 == ~t6_pc~0); 1664538#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1664690#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1664995#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1665080#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1664784#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1664785#L551 assume !(1 == ~t7_pc~0); 1665279#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1665223#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1665224#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1665502#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1665708#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1664978#L570 assume !(1 == ~t8_pc~0); 1664979#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1665560#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1665278#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1665092#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1664562#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1664563#L952 assume !(1 == ~M_E~0); 1664511#L952-2 assume !(1 == ~T1_E~0); 1664512#L957-1 assume !(1 == ~T2_E~0); 1665393#L962-1 assume !(1 == ~T3_E~0); 1665111#L967-1 assume !(1 == ~T4_E~0); 1665112#L972-1 assume !(1 == ~T5_E~0); 1665474#L977-1 assume !(1 == ~T6_E~0); 1665475#L982-1 assume !(1 == ~T7_E~0); 1664693#L987-1 assume !(1 == ~T8_E~0); 1664694#L992-1 assume !(1 == ~E_M~0); 1664703#L997-1 assume !(1 == ~E_1~0); 1665068#L1002-1 assume !(1 == ~E_2~0); 1665056#L1007-1 assume !(1 == ~E_3~0); 1664447#L1012-1 assume !(1 == ~E_4~0); 1664448#L1017-1 assume !(1 == ~E_5~0); 1665057#L1022-1 assume !(1 == ~E_6~0); 1665058#L1027-1 assume !(1 == ~E_7~0); 1665081#L1032-1 assume !(1 == ~E_8~0); 1665250#L1037-1 assume { :end_inline_reset_delta_events } true; 1665251#L1303-2 [2021-12-15 17:21:06,831 INFO L793 eck$LassoCheckResult]: Loop: 1665251#L1303-2 assume !false; 1686227#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1684168#L829 assume !false; 1686224#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1686222#L650 assume !(0 == ~m_st~0); 1686220#L654 assume !(0 == ~t1_st~0); 1686219#L658 assume !(0 == ~t2_st~0); 1686217#L662 assume !(0 == ~t3_st~0); 1686215#L666 assume !(0 == ~t4_st~0); 1686213#L670 assume !(0 == ~t5_st~0); 1686211#L674 assume !(0 == ~t6_st~0); 1686209#L678 assume !(0 == ~t7_st~0); 1686206#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1686204#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1686202#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1686200#L712 assume !(0 != eval_~tmp~0#1); 1686197#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1686195#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1686193#L854-3 assume !(0 == ~M_E~0); 1686191#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1686189#L859-3 assume !(0 == ~T2_E~0); 1686187#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1686185#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1686183#L874-3 assume !(0 == ~T5_E~0); 1686181#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1686179#L884-3 assume !(0 == ~T7_E~0); 1686177#L889-3 assume !(0 == ~T8_E~0); 1686175#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1686173#L899-3 assume !(0 == ~E_1~0); 1686168#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1686165#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1686163#L914-3 assume !(0 == ~E_4~0); 1686161#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1686159#L924-3 assume !(0 == ~E_6~0); 1686157#L929-3 assume !(0 == ~E_7~0); 1686155#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1686153#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1686150#L418-30 assume !(1 == ~m_pc~0); 1686147#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1686142#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1686138#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1686134#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1686130#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1686128#L437-30 assume !(1 == ~t1_pc~0); 1686126#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1686124#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1686122#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1686120#L1069-30 assume !(0 != activate_threads_~tmp___0~0#1); 1686118#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1686116#L456-30 assume !(1 == ~t2_pc~0); 1686111#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1685990#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1685991#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1685651#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1685652#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1685601#L475-30 assume !(1 == ~t3_pc~0); 1683573#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1685592#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1685593#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1685542#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1685543#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1685510#L494-30 assume 1 == ~t4_pc~0; 1685512#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1685493#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1685494#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1685466#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1685465#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1685438#L513-30 assume !(1 == ~t5_pc~0); 1679524#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1685410#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1685411#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1685330#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1685331#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1685197#L532-30 assume 1 == ~t6_pc~0; 1685199#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1685178#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1685179#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1685156#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1685157#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1684362#L551-30 assume !(1 == ~t7_pc~0); 1684360#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1684358#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1684357#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1684355#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1684353#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1684351#L570-30 assume !(1 == ~t8_pc~0); 1683168#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1684348#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1684346#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1684344#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1684342#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1684340#L952-3 assume !(1 == ~M_E~0); 1684338#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1684336#L957-3 assume !(1 == ~T2_E~0); 1684334#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1684332#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1684330#L972-3 assume !(1 == ~T5_E~0); 1684328#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1684326#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1684324#L987-3 assume !(1 == ~T8_E~0); 1684322#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1684320#L997-3 assume !(1 == ~E_1~0); 1684318#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1684316#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1684314#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1684312#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1684311#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1684310#L1027-3 assume !(1 == ~E_7~0); 1684309#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1684308#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1684290#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1684288#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1684286#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1684282#L1322 assume !(0 == start_simulation_~tmp~3#1); 1684283#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1686341#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1686297#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1686291#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1686244#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1686234#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1686232#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1686230#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1665251#L1303-2 [2021-12-15 17:21:06,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 6 times [2021-12-15 17:21:06,832 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902669651] [2021-12-15 17:21:06,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,832 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:06,840 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:06,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:06,872 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:06,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,873 INFO L85 PathProgramCache]: Analyzing trace with hash 421277886, now seen corresponding path program 1 times [2021-12-15 17:21:06,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918496723] [2021-12-15 17:21:06,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:06,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:06,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:06,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918496723] [2021-12-15 17:21:06,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918496723] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:06,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:06,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:06,896 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588378231] [2021-12-15 17:21:06,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:06,896 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:06,896 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:06,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:06,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:06,897 INFO L87 Difference]: Start difference. First operand 44900 states and 61453 transitions. cyclomatic complexity: 16557 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:07,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:07,140 INFO L93 Difference]: Finished difference Result 85012 states and 114909 transitions. [2021-12-15 17:21:07,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:07,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85012 states and 114909 transitions. [2021-12-15 17:21:07,499 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 84832 [2021-12-15 17:21:07,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85012 states to 85012 states and 114909 transitions. [2021-12-15 17:21:07,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 85012 [2021-12-15 17:21:07,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 85012 [2021-12-15 17:21:07,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85012 states and 114909 transitions. [2021-12-15 17:21:07,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:07,831 INFO L681 BuchiCegarLoop]: Abstraction has 85012 states and 114909 transitions. [2021-12-15 17:21:07,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85012 states and 114909 transitions. [2021-12-15 17:21:08,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85012 to 81172. [2021-12-15 17:21:08,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81172 states, 81172 states have (on average 1.3545187995860641) internal successors, (109949), 81171 states have internal predecessors, (109949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:09,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81172 states to 81172 states and 109949 transitions. [2021-12-15 17:21:09,111 INFO L704 BuchiCegarLoop]: Abstraction has 81172 states and 109949 transitions. [2021-12-15 17:21:09,111 INFO L587 BuchiCegarLoop]: Abstraction has 81172 states and 109949 transitions. [2021-12-15 17:21:09,111 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-15 17:21:09,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81172 states and 109949 transitions. [2021-12-15 17:21:09,362 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 80992 [2021-12-15 17:21:09,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:09,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:09,364 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:09,364 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:09,365 INFO L791 eck$LassoCheckResult]: Stem: 1795165#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1795166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1794391#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1794392#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1794427#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1795101#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1795102#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1794671#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1794672#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1794615#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1794616#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1794874#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1794845#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1794846#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1795170#L854 assume !(0 == ~M_E~0); 1794937#L854-2 assume !(0 == ~T1_E~0); 1794938#L859-1 assume !(0 == ~T2_E~0); 1794489#L864-1 assume !(0 == ~T3_E~0); 1794490#L869-1 assume !(0 == ~T4_E~0); 1794604#L874-1 assume !(0 == ~T5_E~0); 1795483#L879-1 assume !(0 == ~T6_E~0); 1794923#L884-1 assume !(0 == ~T7_E~0); 1794363#L889-1 assume !(0 == ~T8_E~0); 1794364#L894-1 assume !(0 == ~E_M~0); 1794688#L899-1 assume !(0 == ~E_1~0); 1795178#L904-1 assume !(0 == ~E_2~0); 1794862#L909-1 assume !(0 == ~E_3~0); 1794863#L914-1 assume !(0 == ~E_4~0); 1795087#L919-1 assume !(0 == ~E_5~0); 1794775#L924-1 assume !(0 == ~E_6~0); 1794587#L929-1 assume !(0 == ~E_7~0); 1794588#L934-1 assume !(0 == ~E_8~0); 1794842#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1794380#L418 assume !(1 == ~m_pc~0); 1794354#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1795407#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1795408#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1795317#L1061 assume !(0 != activate_threads_~tmp~1#1); 1795209#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1795210#L437 assume !(1 == ~t1_pc~0); 1795470#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1795326#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1795263#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1794728#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1794729#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1795308#L456 assume !(1 == ~t2_pc~0); 1794639#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1794638#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1795003#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1795004#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1794976#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1794484#L475 assume !(1 == ~t3_pc~0); 1794485#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1794544#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1794545#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1795474#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1794732#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1794733#L494 assume !(1 == ~t4_pc~0); 1794770#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1794771#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1795585#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1795584#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1795119#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1794539#L513 assume !(1 == ~t5_pc~0); 1794540#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1794772#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1794811#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1794500#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1794501#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1794454#L532 assume !(1 == ~t6_pc~0); 1794455#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1794605#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1794900#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1794988#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1794695#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1794696#L551 assume !(1 == ~t7_pc~0); 1795181#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1795123#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1795124#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1795386#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1795554#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1794884#L570 assume !(1 == ~t8_pc~0); 1794885#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1795440#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1795180#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1794999#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1794478#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1794479#L952 assume !(1 == ~M_E~0); 1794428#L952-2 assume !(1 == ~T1_E~0); 1794429#L957-1 assume !(1 == ~T2_E~0); 1795285#L962-1 assume !(1 == ~T3_E~0); 1795018#L967-1 assume !(1 == ~T4_E~0); 1795019#L972-1 assume !(1 == ~T5_E~0); 1795360#L977-1 assume !(1 == ~T6_E~0); 1795361#L982-1 assume !(1 == ~T7_E~0); 1794607#L987-1 assume !(1 == ~T8_E~0); 1794608#L992-1 assume !(1 == ~E_M~0); 1794617#L997-1 assume !(1 == ~E_1~0); 1794974#L1002-1 assume !(1 == ~E_2~0); 1794959#L1007-1 assume !(1 == ~E_3~0); 1794365#L1012-1 assume !(1 == ~E_4~0); 1794366#L1017-1 assume !(1 == ~E_5~0); 1794961#L1022-1 assume !(1 == ~E_6~0); 1794962#L1027-1 assume !(1 == ~E_7~0); 1794989#L1032-1 assume !(1 == ~E_8~0); 1795150#L1037-1 assume { :end_inline_reset_delta_events } true; 1795151#L1303-2 [2021-12-15 17:21:09,365 INFO L793 eck$LassoCheckResult]: Loop: 1795151#L1303-2 assume !false; 1809586#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1809584#L829 assume !false; 1809582#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1809579#L650 assume !(0 == ~m_st~0); 1809580#L654 assume !(0 == ~t1_st~0); 1831981#L658 assume !(0 == ~t2_st~0); 1831980#L662 assume !(0 == ~t3_st~0); 1831979#L666 assume !(0 == ~t4_st~0); 1831978#L670 assume !(0 == ~t5_st~0); 1831977#L674 assume !(0 == ~t6_st~0); 1831976#L678 assume !(0 == ~t7_st~0); 1831974#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1831973#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1831972#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1831971#L712 assume !(0 != eval_~tmp~0#1); 1831970#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1831969#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1831968#L854-3 assume !(0 == ~M_E~0); 1831967#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1831966#L859-3 assume !(0 == ~T2_E~0); 1831965#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1831964#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1831963#L874-3 assume !(0 == ~T5_E~0); 1831962#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1831961#L884-3 assume !(0 == ~T7_E~0); 1831960#L889-3 assume !(0 == ~T8_E~0); 1831959#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1831958#L899-3 assume !(0 == ~E_1~0); 1831957#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1831956#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1831955#L914-3 assume !(0 == ~E_4~0); 1831954#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1831953#L924-3 assume !(0 == ~E_6~0); 1831952#L929-3 assume !(0 == ~E_7~0); 1831951#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1831950#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1831949#L418-30 assume 1 == ~m_pc~0; 1831946#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1831947#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1831930#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1831931#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1832423#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1832422#L437-30 assume !(1 == ~t1_pc~0); 1832421#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1832420#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1832419#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1832418#L1069-30 assume !(0 != activate_threads_~tmp___0~0#1); 1832417#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1832416#L456-30 assume !(1 == ~t2_pc~0); 1832415#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1832411#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1832409#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1832407#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1832405#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1832403#L475-30 assume !(1 == ~t3_pc~0); 1816744#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1832318#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1832313#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1832306#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1832305#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1832304#L494-30 assume !(1 == ~t4_pc~0); 1832302#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1832303#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1832300#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1832296#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 1832288#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1809750#L513-30 assume !(1 == ~t5_pc~0); 1809748#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1809745#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1809743#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1809741#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1809740#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1809739#L532-30 assume 1 == ~t6_pc~0; 1809738#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1809735#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1809734#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1809733#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1809732#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1809730#L551-30 assume !(1 == ~t7_pc~0); 1809131#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1809725#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1809723#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1809721#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1809719#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1809714#L570-30 assume !(1 == ~t8_pc~0); 1804393#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1809711#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1809709#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1809707#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1809705#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1809703#L952-3 assume !(1 == ~M_E~0); 1809701#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1809699#L957-3 assume !(1 == ~T2_E~0); 1809697#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1809695#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1809693#L972-3 assume !(1 == ~T5_E~0); 1809691#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1809689#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1809687#L987-3 assume !(1 == ~T8_E~0); 1809684#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1809682#L997-3 assume !(1 == ~E_1~0); 1809680#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1809678#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1809676#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1809674#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1809673#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1809671#L1027-3 assume !(1 == ~E_7~0); 1809669#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1809667#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1809664#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1809662#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1809661#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1809658#L1322 assume !(0 == start_simulation_~tmp~3#1); 1809656#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1809653#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1809651#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1809650#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1809649#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1809648#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1809646#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1809644#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1795151#L1303-2 [2021-12-15 17:21:09,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:09,366 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 7 times [2021-12-15 17:21:09,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:09,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589624875] [2021-12-15 17:21:09,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:09,367 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:09,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:09,374 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:09,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:09,404 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:09,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:09,405 INFO L85 PathProgramCache]: Analyzing trace with hash 690784702, now seen corresponding path program 1 times [2021-12-15 17:21:09,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:09,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511255687] [2021-12-15 17:21:09,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:09,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:09,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:09,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:09,458 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:09,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511255687] [2021-12-15 17:21:09,458 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511255687] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:09,459 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:09,459 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:09,459 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736327208] [2021-12-15 17:21:09,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:09,459 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:09,459 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:09,460 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:09,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:09,460 INFO L87 Difference]: Start difference. First operand 81172 states and 109949 transitions. cyclomatic complexity: 28781 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:10,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:10,632 INFO L93 Difference]: Finished difference Result 219377 states and 296680 transitions. [2021-12-15 17:21:10,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:10,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219377 states and 296680 transitions. [2021-12-15 17:21:11,534 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 218944 [2021-12-15 17:21:12,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219377 states to 219377 states and 296680 transitions. [2021-12-15 17:21:12,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219377 [2021-12-15 17:21:12,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219377 [2021-12-15 17:21:12,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 219377 states and 296680 transitions. [2021-12-15 17:21:12,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:12,891 INFO L681 BuchiCegarLoop]: Abstraction has 219377 states and 296680 transitions. [2021-12-15 17:21:12,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219377 states and 296680 transitions. [2021-12-15 17:21:13,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219377 to 84055. [2021-12-15 17:21:13,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84055 states, 84055 states have (on average 1.342359169591339) internal successors, (112832), 84054 states have internal predecessors, (112832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:13,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84055 states to 84055 states and 112832 transitions. [2021-12-15 17:21:13,895 INFO L704 BuchiCegarLoop]: Abstraction has 84055 states and 112832 transitions. [2021-12-15 17:21:13,895 INFO L587 BuchiCegarLoop]: Abstraction has 84055 states and 112832 transitions. [2021-12-15 17:21:13,895 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-15 17:21:13,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84055 states and 112832 transitions. [2021-12-15 17:21:14,636 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 83872 [2021-12-15 17:21:14,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:14,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:14,639 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:14,639 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:14,640 INFO L791 eck$LassoCheckResult]: Stem: 2095715#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2095716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2094954#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2094955#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2094990#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2095656#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2095657#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2095236#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2095237#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2095179#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2095180#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2095439#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2095411#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2095412#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2095720#L854 assume !(0 == ~M_E~0); 2095501#L854-2 assume !(0 == ~T1_E~0); 2095502#L859-1 assume !(0 == ~T2_E~0); 2095052#L864-1 assume !(0 == ~T3_E~0); 2095053#L869-1 assume !(0 == ~T4_E~0); 2095167#L874-1 assume !(0 == ~T5_E~0); 2096044#L879-1 assume !(0 == ~T6_E~0); 2095488#L884-1 assume !(0 == ~T7_E~0); 2094926#L889-1 assume !(0 == ~T8_E~0); 2094927#L894-1 assume !(0 == ~E_M~0); 2095254#L899-1 assume !(0 == ~E_1~0); 2095727#L904-1 assume !(0 == ~E_2~0); 2095428#L909-1 assume !(0 == ~E_3~0); 2095429#L914-1 assume !(0 == ~E_4~0); 2095642#L919-1 assume !(0 == ~E_5~0); 2095344#L924-1 assume !(0 == ~E_6~0); 2095150#L929-1 assume !(0 == ~E_7~0); 2095151#L934-1 assume !(0 == ~E_8~0); 2095408#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2094943#L418 assume !(1 == ~m_pc~0); 2094917#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2095960#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2095961#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2095867#L1061 assume !(0 != activate_threads_~tmp~1#1); 2095759#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2095760#L437 assume !(1 == ~t1_pc~0); 2096031#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2095876#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2095806#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2095295#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2095296#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2095856#L456 assume !(1 == ~t2_pc~0); 2095203#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2095639#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2096085#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2095904#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2095535#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2095047#L475 assume !(1 == ~t3_pc~0); 2095048#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2095107#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2095108#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2096033#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2095299#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2095300#L494 assume !(1 == ~t4_pc~0); 2095338#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2095339#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2095612#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2096146#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2095672#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2095102#L513 assume !(1 == ~t5_pc~0); 2095103#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2095340#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2095381#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2095063#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2095064#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2095017#L532 assume !(1 == ~t6_pc~0); 2095018#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2095168#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2095465#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2095546#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2095262#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2095263#L551 assume !(1 == ~t7_pc~0); 2095731#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2095676#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2095677#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2095933#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2096124#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2095449#L570 assume !(1 == ~t8_pc~0); 2095450#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2095992#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2095730#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2095557#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2095041#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2095042#L952 assume !(1 == ~M_E~0); 2094991#L952-2 assume !(1 == ~T1_E~0); 2094992#L957-1 assume !(1 == ~T2_E~0); 2095833#L962-1 assume !(1 == ~T3_E~0); 2095574#L967-1 assume !(1 == ~T4_E~0); 2095575#L972-1 assume !(1 == ~T5_E~0); 2095908#L977-1 assume !(1 == ~T6_E~0); 2095909#L982-1 assume !(1 == ~T7_E~0); 2095171#L987-1 assume !(1 == ~T8_E~0); 2095172#L992-1 assume !(1 == ~E_M~0); 2095181#L997-1 assume !(1 == ~E_1~0); 2095533#L1002-1 assume !(1 == ~E_2~0); 2095521#L1007-1 assume !(1 == ~E_3~0); 2094928#L1012-1 assume !(1 == ~E_4~0); 2094929#L1017-1 assume !(1 == ~E_5~0); 2095522#L1022-1 assume !(1 == ~E_6~0); 2095523#L1027-1 assume !(1 == ~E_7~0); 2095547#L1032-1 assume !(1 == ~E_8~0); 2095699#L1037-1 assume { :end_inline_reset_delta_events } true; 2095700#L1303-2 [2021-12-15 17:21:14,655 INFO L793 eck$LassoCheckResult]: Loop: 2095700#L1303-2 assume !false; 2110971#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2110962#L829 assume !false; 2110954#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2110942#L650 assume !(0 == ~m_st~0); 2110943#L654 assume !(0 == ~t1_st~0); 2114940#L658 assume !(0 == ~t2_st~0); 2114939#L662 assume !(0 == ~t3_st~0); 2114938#L666 assume !(0 == ~t4_st~0); 2114937#L670 assume !(0 == ~t5_st~0); 2114936#L674 assume !(0 == ~t6_st~0); 2114935#L678 assume !(0 == ~t7_st~0); 2114933#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 2114932#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2114931#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2114930#L712 assume !(0 != eval_~tmp~0#1); 2114929#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2114928#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2114927#L854-3 assume !(0 == ~M_E~0); 2114926#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2114925#L859-3 assume !(0 == ~T2_E~0); 2114924#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2114923#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2114922#L874-3 assume !(0 == ~T5_E~0); 2114921#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2114920#L884-3 assume !(0 == ~T7_E~0); 2114919#L889-3 assume !(0 == ~T8_E~0); 2114918#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2114916#L899-3 assume !(0 == ~E_1~0); 2114914#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2114912#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2114910#L914-3 assume !(0 == ~E_4~0); 2114908#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2114906#L924-3 assume !(0 == ~E_6~0); 2114903#L929-3 assume !(0 == ~E_7~0); 2114901#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2114899#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2114898#L418-30 assume 1 == ~m_pc~0; 2114896#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2114895#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2114894#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2114892#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2114891#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2114890#L437-30 assume !(1 == ~t1_pc~0); 2114889#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2114888#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2114887#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2114886#L1069-30 assume !(0 != activate_threads_~tmp___0~0#1); 2114885#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2114884#L456-30 assume 1 == ~t2_pc~0; 2114882#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2114880#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2114878#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2114876#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2114874#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2111883#L475-30 assume !(1 == ~t3_pc~0); 2111882#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2111881#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2111880#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2111879#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2111878#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2111877#L494-30 assume !(1 == ~t4_pc~0); 2111875#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2111873#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2111871#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2111869#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2111868#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2111867#L513-30 assume !(1 == ~t5_pc~0); 2111711#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2111866#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2111865#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2111863#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2111861#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2111859#L532-30 assume !(1 == ~t6_pc~0); 2111856#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2111854#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2111852#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2111848#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2111845#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2111842#L551-30 assume !(1 == ~t7_pc~0); 2108775#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2111836#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2111825#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2111823#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2111821#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2111817#L570-30 assume !(1 == ~t8_pc~0); 2103977#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2111808#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2111748#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2111611#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2111608#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2111606#L952-3 assume !(1 == ~M_E~0); 2111601#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2111595#L957-3 assume !(1 == ~T2_E~0); 2111590#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2111584#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2111579#L972-3 assume !(1 == ~T5_E~0); 2111574#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2111569#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2111563#L987-3 assume !(1 == ~T8_E~0); 2111558#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2111552#L997-3 assume !(1 == ~E_1~0); 2111547#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2111542#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2111537#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2111533#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2111528#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2111524#L1027-3 assume !(1 == ~E_7~0); 2111519#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2111514#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2111508#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2111503#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2111498#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2111493#L1322 assume !(0 == start_simulation_~tmp~3#1); 2111489#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2111485#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2111478#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2111467#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2111450#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2111442#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2111435#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2111427#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2095700#L1303-2 [2021-12-15 17:21:14,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:14,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 8 times [2021-12-15 17:21:14,656 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:14,657 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058471449] [2021-12-15 17:21:14,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:14,657 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:14,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:14,666 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:14,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:14,694 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:14,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:14,695 INFO L85 PathProgramCache]: Analyzing trace with hash 26999998, now seen corresponding path program 1 times [2021-12-15 17:21:14,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:14,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108122730] [2021-12-15 17:21:14,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:14,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:14,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:14,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:14,740 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:14,740 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108122730] [2021-12-15 17:21:14,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108122730] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:14,740 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:14,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:14,740 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012231369] [2021-12-15 17:21:14,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:14,741 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:14,741 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:14,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:14,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:14,742 INFO L87 Difference]: Start difference. First operand 84055 states and 112832 transitions. cyclomatic complexity: 28781 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:15,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:15,290 INFO L93 Difference]: Finished difference Result 155287 states and 208319 transitions. [2021-12-15 17:21:15,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:15,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155287 states and 208319 transitions. [2021-12-15 17:21:15,974 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 155040 [2021-12-15 17:21:16,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155287 states to 155287 states and 208319 transitions. [2021-12-15 17:21:16,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155287 [2021-12-15 17:21:17,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155287 [2021-12-15 17:21:17,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155287 states and 208319 transitions. [2021-12-15 17:21:17,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:17,229 INFO L681 BuchiCegarLoop]: Abstraction has 155287 states and 208319 transitions. [2021-12-15 17:21:17,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155287 states and 208319 transitions. [2021-12-15 17:21:18,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155287 to 85591. [2021-12-15 17:21:18,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85591 states, 85591 states have (on average 1.3309693776214788) internal successors, (113919), 85590 states have internal predecessors, (113919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:18,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85591 states to 85591 states and 113919 transitions. [2021-12-15 17:21:18,363 INFO L704 BuchiCegarLoop]: Abstraction has 85591 states and 113919 transitions. [2021-12-15 17:21:18,363 INFO L587 BuchiCegarLoop]: Abstraction has 85591 states and 113919 transitions. [2021-12-15 17:21:18,363 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-15 17:21:18,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85591 states and 113919 transitions. [2021-12-15 17:21:18,621 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 85408 [2021-12-15 17:21:18,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:18,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:18,622 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:18,622 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:18,623 INFO L791 eck$LassoCheckResult]: Stem: 2335080#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2335081#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2334310#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2334311#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2334347#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2335014#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2335015#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2334590#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2334591#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2334532#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2334533#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2334795#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2334764#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2334765#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2335085#L854 assume !(0 == ~M_E~0); 2334859#L854-2 assume !(0 == ~T1_E~0); 2334860#L859-1 assume !(0 == ~T2_E~0); 2334409#L864-1 assume !(0 == ~T3_E~0); 2334410#L869-1 assume !(0 == ~T4_E~0); 2334521#L874-1 assume !(0 == ~T5_E~0); 2335392#L879-1 assume !(0 == ~T6_E~0); 2334845#L884-1 assume !(0 == ~T7_E~0); 2334282#L889-1 assume !(0 == ~T8_E~0); 2334283#L894-1 assume !(0 == ~E_M~0); 2334607#L899-1 assume !(0 == ~E_1~0); 2335092#L904-1 assume !(0 == ~E_2~0); 2334781#L909-1 assume !(0 == ~E_3~0); 2334782#L914-1 assume !(0 == ~E_4~0); 2334999#L919-1 assume !(0 == ~E_5~0); 2334697#L924-1 assume !(0 == ~E_6~0); 2334505#L929-1 assume !(0 == ~E_7~0); 2334506#L934-1 assume !(0 == ~E_8~0); 2334761#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2334299#L418 assume !(1 == ~m_pc~0); 2334273#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2335311#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2335312#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2335227#L1061 assume !(0 != activate_threads_~tmp~1#1); 2335120#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2335121#L437 assume !(1 == ~t1_pc~0); 2335375#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2335236#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2335169#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2334647#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2334648#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2335218#L456 assume !(1 == ~t2_pc~0); 2334557#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2334996#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2334919#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2334920#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2334893#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2334404#L475 assume !(1 == ~t3_pc~0); 2334405#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2334463#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2334464#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2335378#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2334651#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2334652#L494 assume !(1 == ~t4_pc~0); 2334693#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2334694#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2335493#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2335492#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2335033#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2334458#L513 assume !(1 == ~t5_pc~0); 2334459#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2334695#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2334734#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2334420#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2334421#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2334374#L532 assume !(1 == ~t6_pc~0); 2334375#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2334522#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2334822#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2334903#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2334614#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2334615#L551 assume !(1 == ~t7_pc~0); 2335095#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2335037#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2335038#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2335288#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2335469#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2334806#L570 assume !(1 == ~t8_pc~0); 2334807#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2335340#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2335094#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2334914#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2334398#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2334399#L952 assume !(1 == ~M_E~0); 2334348#L952-2 assume !(1 == ~T1_E~0); 2334349#L957-1 assume !(1 == ~T2_E~0); 2335195#L962-1 assume !(1 == ~T3_E~0); 2334932#L967-1 assume !(1 == ~T4_E~0); 2334933#L972-1 assume !(1 == ~T5_E~0); 2335265#L977-1 assume !(1 == ~T6_E~0); 2335266#L982-1 assume !(1 == ~T7_E~0); 2334524#L987-1 assume !(1 == ~T8_E~0); 2334525#L992-1 assume !(1 == ~E_M~0); 2334534#L997-1 assume !(1 == ~E_1~0); 2334891#L1002-1 assume !(1 == ~E_2~0); 2334879#L1007-1 assume !(1 == ~E_3~0); 2334284#L1012-1 assume !(1 == ~E_4~0); 2334285#L1017-1 assume !(1 == ~E_5~0); 2334882#L1022-1 assume !(1 == ~E_6~0); 2334883#L1027-1 assume !(1 == ~E_7~0); 2334904#L1032-1 assume !(1 == ~E_8~0); 2335065#L1037-1 assume { :end_inline_reset_delta_events } true; 2335066#L1303-2 [2021-12-15 17:21:18,623 INFO L793 eck$LassoCheckResult]: Loop: 2335066#L1303-2 assume !false; 2356096#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2356095#L829 assume !false; 2356094#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2356092#L650 assume !(0 == ~m_st~0); 2356093#L654 assume !(0 == ~t1_st~0); 2358351#L658 assume !(0 == ~t2_st~0); 2358347#L662 assume !(0 == ~t3_st~0); 2358348#L666 assume !(0 == ~t4_st~0); 2358350#L670 assume !(0 == ~t5_st~0); 2358345#L674 assume !(0 == ~t6_st~0); 2358346#L678 assume !(0 == ~t7_st~0); 2358349#L682 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 2358352#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2358327#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2358328#L712 assume !(0 != eval_~tmp~0#1); 2412502#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2413983#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2413982#L854-3 assume !(0 == ~M_E~0); 2413981#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2413980#L859-3 assume !(0 == ~T2_E~0); 2413979#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2413978#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2413977#L874-3 assume !(0 == ~T5_E~0); 2413976#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2413975#L884-3 assume !(0 == ~T7_E~0); 2413974#L889-3 assume !(0 == ~T8_E~0); 2413973#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2413972#L899-3 assume !(0 == ~E_1~0); 2413971#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2413970#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2413969#L914-3 assume !(0 == ~E_4~0); 2413968#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2413967#L924-3 assume !(0 == ~E_6~0); 2413966#L929-3 assume !(0 == ~E_7~0); 2413965#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2413964#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2413963#L418-30 assume 1 == ~m_pc~0; 2413961#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2413960#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2413959#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2413957#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2413956#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2413955#L437-30 assume !(1 == ~t1_pc~0); 2413954#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2413953#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2413952#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2413951#L1069-30 assume !(0 != activate_threads_~tmp___0~0#1); 2413950#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2413949#L456-30 assume !(1 == ~t2_pc~0); 2413948#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2413946#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2413944#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2413942#L1077-30 assume !(0 != activate_threads_~tmp___1~0#1); 2413940#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2351745#L475-30 assume !(1 == ~t3_pc~0); 2351744#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2351743#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2351742#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2351741#L1085-30 assume !(0 != activate_threads_~tmp___2~0#1); 2351740#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2351739#L494-30 assume 1 == ~t4_pc~0; 2351738#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2351736#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2351734#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2351732#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2351730#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2351729#L513-30 assume !(1 == ~t5_pc~0); 2343115#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2351728#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2351727#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2351726#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2351725#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2351724#L532-30 assume 1 == ~t6_pc~0; 2351723#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2351721#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2351720#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2351719#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2351718#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2344608#L551-30 assume !(1 == ~t7_pc~0); 2344609#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2344600#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2344601#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2344592#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2344593#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2344585#L570-30 assume !(1 == ~t8_pc~0); 2344583#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2344581#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2344579#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2344577#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2344575#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2344572#L952-3 assume !(1 == ~M_E~0); 2344573#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2356285#L957-3 assume !(1 == ~T2_E~0); 2356284#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2356283#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2356282#L972-3 assume !(1 == ~T5_E~0); 2356281#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2356280#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2356279#L987-3 assume !(1 == ~T8_E~0); 2356278#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2356277#L997-3 assume !(1 == ~E_1~0); 2356276#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2356275#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2356274#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2356273#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2356272#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2356271#L1027-3 assume !(1 == ~E_7~0); 2356270#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2356269#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2356268#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2356267#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2356266#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2356265#L1322 assume !(0 == start_simulation_~tmp~3#1); 2356264#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2356262#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2356261#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2356260#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2356259#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2356258#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2356257#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2356256#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2335066#L1303-2 [2021-12-15 17:21:18,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:18,625 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 9 times [2021-12-15 17:21:18,625 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:18,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338995804] [2021-12-15 17:21:18,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:18,626 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:18,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:18,634 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:18,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:18,659 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:18,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:18,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1786279807, now seen corresponding path program 1 times [2021-12-15 17:21:18,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:18,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822259723] [2021-12-15 17:21:18,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:18,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:18,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:18,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:18,704 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:18,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822259723] [2021-12-15 17:21:18,704 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822259723] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:18,704 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:18,704 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:18,704 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [11587135] [2021-12-15 17:21:18,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:18,705 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:18,705 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:18,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:18,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:18,706 INFO L87 Difference]: Start difference. First operand 85591 states and 113919 transitions. cyclomatic complexity: 28332 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)