./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:31,466 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:31,468 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:31,511 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:31,512 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:31,513 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:31,514 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:31,516 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:31,518 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:31,519 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:31,520 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:31,521 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:31,521 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:31,522 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:31,523 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:31,525 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:31,525 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:31,526 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:31,528 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:31,529 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:31,531 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:31,532 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:31,533 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:31,534 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:31,536 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:31,536 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:31,537 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:31,537 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:31,538 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:31,539 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:31,539 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:31,540 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:31,541 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:31,541 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:31,542 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:31,542 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:31,543 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:31,543 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:31,543 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:31,544 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:31,545 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:31,546 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:31,565 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:31,565 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:31,566 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:31,566 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:31,567 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:31,567 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:31,568 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:31,568 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:31,568 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:31,568 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:31,568 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:31,569 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:31,569 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:31,569 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:31,569 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:31,570 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:31,570 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:31,570 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:31,570 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:31,571 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:31,571 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:31,571 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:31,571 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:31,571 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:31,572 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:31,572 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:31,572 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:31,572 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:31,573 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:31,573 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:31,573 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:31,573 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:31,574 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:31,574 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2021-12-15 17:20:31,812 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:31,834 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:31,836 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:31,837 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:31,838 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:31,839 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-12-15 17:20:31,898 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5ee691971/ef60d15065e24cf79612f0df20c5ee46/FLAG7b32f61dc [2021-12-15 17:20:32,266 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:32,267 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-12-15 17:20:32,278 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5ee691971/ef60d15065e24cf79612f0df20c5ee46/FLAG7b32f61dc [2021-12-15 17:20:32,662 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5ee691971/ef60d15065e24cf79612f0df20c5ee46 [2021-12-15 17:20:32,664 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:32,665 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:32,669 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:32,669 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:32,672 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:32,672 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:32" (1/1) ... [2021-12-15 17:20:32,674 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6ec0e54 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:32, skipping insertion in model container [2021-12-15 17:20:32,674 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:32" (1/1) ... [2021-12-15 17:20:32,680 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:32,714 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:32,870 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2021-12-15 17:20:33,000 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:33,018 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:33,035 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2021-12-15 17:20:33,091 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:33,106 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:33,107 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33 WrapperNode [2021-12-15 17:20:33,107 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:33,108 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:33,108 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:33,108 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:33,115 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,126 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,216 INFO L137 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 182, statements flattened = 2757 [2021-12-15 17:20:33,216 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:33,217 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:33,217 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:33,217 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:33,224 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,224 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,233 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,233 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,260 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,298 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,310 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,344 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:33,346 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:33,346 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:33,347 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:33,347 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,363 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:33,375 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:33,388 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:33,414 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:33,435 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:33,435 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:33,435 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:33,436 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:33,596 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:33,597 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:34,831 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:34,862 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:34,865 INFO L301 CfgBuilder]: Removed 12 assume(true) statements. [2021-12-15 17:20:34,868 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:34 BoogieIcfgContainer [2021-12-15 17:20:34,869 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:34,871 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:34,871 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:34,873 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:34,874 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:34,874 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:32" (1/3) ... [2021-12-15 17:20:34,875 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@22c5b069 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:34, skipping insertion in model container [2021-12-15 17:20:34,875 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:34,876 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33" (2/3) ... [2021-12-15 17:20:34,877 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@22c5b069 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:34, skipping insertion in model container [2021-12-15 17:20:34,877 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:34,877 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:34" (3/3) ... [2021-12-15 17:20:34,878 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2021-12-15 17:20:34,915 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:34,915 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:34,916 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:34,916 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:34,916 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:34,916 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:34,916 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:34,916 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:34,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2021-12-15 17:20:35,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,025 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,025 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,025 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:35,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2021-12-15 17:20:35,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,048 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,048 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,056 INFO L791 eck$LassoCheckResult]: Stem: 548#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1061#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 500#L1391true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 867#L651true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 751#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 400#L658-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 772#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 716#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 275#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 811#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 623#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1030#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 106#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 335#L703-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1020#L939true assume !(0 == ~M_E~0); 531#L939-2true assume !(0 == ~T1_E~0); 745#L944-1true assume !(0 == ~T2_E~0); 356#L949-1true assume !(0 == ~T3_E~0); 354#L954-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1069#L959-1true assume !(0 == ~T5_E~0); 773#L964-1true assume !(0 == ~T6_E~0); 187#L969-1true assume !(0 == ~T7_E~0); 888#L974-1true assume !(0 == ~T8_E~0); 703#L979-1true assume !(0 == ~T9_E~0); 1096#L984-1true assume !(0 == ~E_M~0); 282#L989-1true assume !(0 == ~E_1~0); 510#L994-1true assume 0 == ~E_2~0;~E_2~0 := 1; 214#L999-1true assume !(0 == ~E_3~0); 670#L1004-1true assume !(0 == ~E_4~0); 40#L1009-1true assume !(0 == ~E_5~0); 209#L1014-1true assume !(0 == ~E_6~0); 630#L1019-1true assume !(0 == ~E_7~0); 938#L1024-1true assume !(0 == ~E_8~0); 170#L1029-1true assume !(0 == ~E_9~0); 222#L1034-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 953#L460true assume 1 == ~m_pc~0; 3#L461true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 596#L471true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1051#L472true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024#L1167true assume !(0 != activate_threads_~tmp~1#1); 346#L1167-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 493#L479true assume 1 == ~t1_pc~0; 336#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1040#L490true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 891#L491true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 177#L1175true assume !(0 != activate_threads_~tmp___0~0#1); 388#L1175-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98#L498true assume !(1 == ~t2_pc~0); 639#L498-2true is_transmit2_triggered_~__retres1~2#1 := 0; 334#L509true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 831#L510true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 671#L1183true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 587#L1183-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1120#L517true assume 1 == ~t3_pc~0; 899#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1063#L528true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 383#L529true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 195#L1191true assume !(0 != activate_threads_~tmp___2~0#1); 641#L1191-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 812#L536true assume !(1 == ~t4_pc~0); 1098#L536-2true is_transmit4_triggered_~__retres1~4#1 := 0; 762#L547true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1087#L548true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 373#L1199true assume !(0 != activate_threads_~tmp___3~0#1); 1085#L1199-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 559#L555true assume 1 == ~t5_pc~0; 1165#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 700#L566true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55#L567true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 171#L1207true assume !(0 != activate_threads_~tmp___4~0#1); 109#L1207-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59#L574true assume !(1 == ~t6_pc~0); 632#L574-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1102#L585true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112#L586true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 665#L1215true assume !(0 != activate_threads_~tmp___5~0#1); 1093#L1215-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 968#L593true assume 1 == ~t7_pc~0; 1138#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 778#L604true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1084#L605true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1078#L1223true assume !(0 != activate_threads_~tmp___6~0#1); 902#L1223-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 280#L612true assume !(1 == ~t8_pc~0); 1017#L612-2true is_transmit8_triggered_~__retres1~8#1 := 0; 892#L623true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 474#L624true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 807#L1231true assume !(0 != activate_threads_~tmp___7~0#1); 444#L1231-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 499#L631true assume 1 == ~t9_pc~0; 456#L632true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54#L642true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39#L643true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 337#L1239true assume !(0 != activate_threads_~tmp___8~0#1); 1050#L1239-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 643#L1047true assume !(1 == ~M_E~0); 26#L1047-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L1052-1true assume !(1 == ~T2_E~0); 18#L1057-1true assume !(1 == ~T3_E~0); 161#L1062-1true assume !(1 == ~T4_E~0); 774#L1067-1true assume !(1 == ~T5_E~0); 348#L1072-1true assume !(1 == ~T6_E~0); 611#L1077-1true assume !(1 == ~T7_E~0); 104#L1082-1true assume !(1 == ~T8_E~0); 419#L1087-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 6#L1092-1true assume !(1 == ~E_M~0); 19#L1097-1true assume !(1 == ~E_1~0); 942#L1102-1true assume !(1 == ~E_2~0); 495#L1107-1true assume !(1 == ~E_3~0); 440#L1112-1true assume !(1 == ~E_4~0); 475#L1117-1true assume !(1 == ~E_5~0); 1153#L1122-1true assume !(1 == ~E_6~0); 384#L1127-1true assume 1 == ~E_7~0;~E_7~0 := 2; 224#L1132-1true assume !(1 == ~E_8~0); 946#L1137-1true assume !(1 == ~E_9~0); 160#L1142-1true assume { :end_inline_reset_delta_events } true; 90#L1428-2true [2021-12-15 17:20:35,058 INFO L793 eck$LassoCheckResult]: Loop: 90#L1428-2true assume !false; 437#L1429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 971#L914true assume false; 216#L929true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 494#L651-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 759#L939-3true assume !(0 == ~M_E~0); 117#L939-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 144#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 5#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 719#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 360#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 41#L964-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 268#L969-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 143#L974-3true assume !(0 == ~T8_E~0); 1055#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 414#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1142#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 174#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 969#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 538#L1004-3true assume 0 == ~E_4~0;~E_4~0 := 1; 82#L1009-3true assume 0 == ~E_5~0;~E_5~0 := 1; 617#L1014-3true assume !(0 == ~E_6~0); 401#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1113#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 391#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 362#L1034-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 922#L460-33true assume !(1 == ~m_pc~0); 571#L460-35true is_master_triggered_~__retres1~0#1 := 0; 550#L471-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226#L472-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9#L1167-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 501#L1167-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190#L479-33true assume 1 == ~t1_pc~0; 934#L480-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 172#L490-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 605#L491-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 870#L1175-33true assume !(0 != activate_threads_~tmp___0~0#1); 992#L1175-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194#L498-33true assume !(1 == ~t2_pc~0); 61#L498-35true is_transmit2_triggered_~__retres1~2#1 := 0; 321#L509-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130#L510-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 429#L1183-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118#L1183-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1000#L517-33true assume !(1 == ~t3_pc~0); 1111#L517-35true is_transmit3_triggered_~__retres1~3#1 := 0; 737#L528-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1091#L529-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 525#L1191-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 666#L1191-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 250#L536-33true assume 1 == ~t4_pc~0; 598#L537-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 290#L547-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418#L548-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 709#L1199-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 813#L1199-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L555-33true assume !(1 == ~t5_pc~0); 800#L555-35true is_transmit5_triggered_~__retres1~5#1 := 0; 470#L566-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 166#L567-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 490#L1207-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1034#L1207-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17#L574-33true assume 1 == ~t6_pc~0; 722#L575-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 846#L585-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#L586-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 572#L1215-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 332#L1215-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51#L593-33true assume 1 == ~t7_pc~0; 399#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 954#L604-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103#L605-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 549#L1223-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 695#L1223-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1119#L612-33true assume 1 == ~t8_pc~0; 919#L613-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 853#L623-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1088#L624-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 610#L1231-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102#L1231-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1162#L631-33true assume !(1 == ~t9_pc~0); 497#L631-35true is_transmit9_triggered_~__retres1~9#1 := 0; 73#L642-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 404#L643-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 208#L1239-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 131#L1239-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227#L1047-3true assume !(1 == ~M_E~0); 771#L1047-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1173#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 677#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1167#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 79#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1025#L1072-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 295#L1077-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 199#L1082-3true assume !(1 == ~T8_E~0); 248#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 434#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1178#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 382#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 952#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 728#L1112-3true assume 1 == ~E_4~0;~E_4~0 := 2; 196#L1117-3true assume 1 == ~E_5~0;~E_5~0 := 2; 735#L1122-3true assume !(1 == ~E_6~0); 228#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 509#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1080#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 486#L1142-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 133#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 492#L768-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 487#L769-1true start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 307#L1447true assume !(0 == start_simulation_~tmp~3#1); 702#L1447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1140#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 732#L768-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 511#L769-2true stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 213#L1402true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 85#L1409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 533#L1410true start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 349#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 90#L1428-2true [2021-12-15 17:20:35,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,064 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2021-12-15 17:20:35,071 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,071 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607063157] [2021-12-15 17:20:35,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,073 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,260 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,260 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607063157] [2021-12-15 17:20:35,261 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607063157] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,269 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388618967] [2021-12-15 17:20:35,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,276 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1744542878, now seen corresponding path program 1 times [2021-12-15 17:20:35,278 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586714546] [2021-12-15 17:20:35,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,330 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586714546] [2021-12-15 17:20:35,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586714546] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,331 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,331 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:35,331 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1314411926] [2021-12-15 17:20:35,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,333 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,344 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:35,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:35,373 INFO L87 Difference]: Start difference. First operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,427 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions. [2021-12-15 17:20:35,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:35,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions. [2021-12-15 17:20:35,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:35,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1170 states and 1742 transitions. [2021-12-15 17:20:35,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:35,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:35,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1742 transitions. [2021-12-15 17:20:35,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,473 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2021-12-15 17:20:35,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1742 transitions. [2021-12-15 17:20:35,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:35,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1742 transitions. [2021-12-15 17:20:35,549 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2021-12-15 17:20:35,549 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2021-12-15 17:20:35,549 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:35,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1742 transitions. [2021-12-15 17:20:35,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:35,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,557 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,558 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,558 INFO L791 eck$LassoCheckResult]: Stem: 3232#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3182#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3183#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3401#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3068#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3069#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3378#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2877#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2878#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3306#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3307#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2376#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2377#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2580#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2968#L939 assume !(0 == ~M_E~0); 3212#L939-2 assume !(0 == ~T1_E~0); 3213#L944-1 assume !(0 == ~T2_E~0); 2997#L949-1 assume !(0 == ~T3_E~0); 2995#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2996#L959-1 assume !(0 == ~T5_E~0); 3415#L964-1 assume !(0 == ~T6_E~0); 2728#L969-1 assume !(0 == ~T7_E~0); 2729#L974-1 assume !(0 == ~T8_E~0); 3366#L979-1 assume !(0 == ~T9_E~0); 3367#L984-1 assume !(0 == ~E_M~0); 2889#L989-1 assume !(0 == ~E_1~0); 2890#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2778#L999-1 assume !(0 == ~E_3~0); 2779#L1004-1 assume !(0 == ~E_4~0); 2444#L1009-1 assume !(0 == ~E_5~0); 2445#L1014-1 assume !(0 == ~E_6~0); 2772#L1019-1 assume !(0 == ~E_7~0); 3311#L1024-1 assume !(0 == ~E_8~0); 2701#L1029-1 assume !(0 == ~E_9~0); 2702#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2792#L460 assume 1 == ~m_pc~0; 2360#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2361#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3277#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3516#L1167 assume !(0 != activate_threads_~tmp~1#1); 2985#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2986#L479 assume 1 == ~t1_pc~0; 2969#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2970#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2713#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2714#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L498 assume !(1 == ~t2_pc~0); 2563#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2966#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2967#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3344#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3268#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3269#L517 assume 1 == ~t3_pc~0; 3477#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3478#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2746#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2747#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3322#L536 assume !(1 == ~t4_pc~0); 3030#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3029#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3406#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3022#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3023#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3242#L555 assume 1 == ~t5_pc~0; 3243#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3312#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2475#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2476#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2583#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2483#L574 assume !(1 == ~t6_pc~0); 2484#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3115#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2588#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2589#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3340#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3500#L593 assume 1 == ~t7_pc~0; 3501#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2720#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3418#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3521#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3481#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2884#L612 assume !(1 == ~t8_pc~0); 2885#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3294#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3152#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3153#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3117#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3118#L631 assume 1 == ~t9_pc~0; 3136#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2474#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2442#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2443#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2972#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3323#L1047 assume !(1 == ~M_E~0); 2412#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2413#L1052-1 assume !(1 == ~T2_E~0); 2395#L1057-1 assume !(1 == ~T3_E~0); 2396#L1062-1 assume !(1 == ~T4_E~0); 2685#L1067-1 assume !(1 == ~T5_E~0); 2988#L1072-1 assume !(1 == ~T6_E~0); 2989#L1077-1 assume !(1 == ~T7_E~0); 2576#L1082-1 assume !(1 == ~T8_E~0); 2577#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2370#L1092-1 assume !(1 == ~E_M~0); 2371#L1097-1 assume !(1 == ~E_1~0); 2397#L1102-1 assume !(1 == ~E_2~0); 3178#L1107-1 assume !(1 == ~E_3~0); 3113#L1112-1 assume !(1 == ~E_4~0); 3114#L1117-1 assume !(1 == ~E_5~0); 3154#L1122-1 assume !(1 == ~E_6~0); 3041#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2797#L1132-1 assume !(1 == ~E_8~0); 2798#L1137-1 assume !(1 == ~E_9~0); 2684#L1142-1 assume { :end_inline_reset_delta_events } true; 2544#L1428-2 [2021-12-15 17:20:35,559 INFO L793 eck$LassoCheckResult]: Loop: 2544#L1428-2 assume !false; 2545#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2619#L914 assume !false; 3109#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3110#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2381#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2382#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3341#L783 assume !(0 != eval_~tmp~0#1); 2781#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2782#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3177#L939-3 assume !(0 == ~M_E~0); 2600#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2601#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2366#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2367#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3003#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2446#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2447#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2653#L974-3 assume !(0 == ~T8_E~0); 2654#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3084#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3085#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2707#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2708#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3219#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2530#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2531#L1014-3 assume !(0 == ~E_6~0); 3070#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3071#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3052#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3004#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3005#L460-33 assume 1 == ~m_pc~0; 3042#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3043#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2799#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2374#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2375#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2736#L479-33 assume !(1 == ~t1_pc~0); 2737#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2703#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3288#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 3461#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2744#L498-33 assume 1 == ~t2_pc~0; 2745#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2490#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2626#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2627#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2602#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2603#L517-33 assume !(1 == ~t3_pc~0); 3509#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3392#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3393#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3205#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3206#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2831#L536-33 assume 1 == ~t4_pc~0; 2832#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2901#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2902#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3092#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3371#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2421#L555-33 assume !(1 == ~t5_pc~0); 2422#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3147#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2694#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2695#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3174#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2387#L574-33 assume 1 == ~t6_pc~0; 2388#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3383#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2709#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2710#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2963#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2463#L593-33 assume !(1 == ~t7_pc~0); 2464#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2919#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2574#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2575#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3234#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3361#L612-33 assume 1 == ~t8_pc~0; 3488#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3452#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3453#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3295#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2570#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2571#L631-33 assume 1 == ~t9_pc~0; 3413#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2512#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2513#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2767#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2624#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2625#L1047-3 assume !(1 == ~M_E~0); 2800#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3414#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3346#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3347#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2525#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2526#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2908#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2753#L1082-3 assume !(1 == ~T8_E~0); 2754#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2827#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3108#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3038#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3039#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3384#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2748#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2749#L1122-3 assume !(1 == ~E_6~0); 2801#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2802#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3191#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3168#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2628#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2506#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3169#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2926#L1447 assume !(0 == start_simulation_~tmp~3#1); 2927#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3365#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2667#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3192#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2777#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2534#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2535#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2990#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2544#L1428-2 [2021-12-15 17:20:35,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,560 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2021-12-15 17:20:35,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328233633] [2021-12-15 17:20:35,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,606 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,606 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328233633] [2021-12-15 17:20:35,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328233633] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,606 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,607 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,607 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072029954] [2021-12-15 17:20:35,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,608 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,608 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 1 times [2021-12-15 17:20:35,609 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802040298] [2021-12-15 17:20:35,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,609 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,739 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802040298] [2021-12-15 17:20:35,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802040298] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,740 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,741 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,741 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839989605] [2021-12-15 17:20:35,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,742 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,742 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:35,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:35,743 INFO L87 Difference]: Start difference. First operand 1170 states and 1742 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,766 INFO L93 Difference]: Finished difference Result 1170 states and 1741 transitions. [2021-12-15 17:20:35,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:35,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1741 transitions. [2021-12-15 17:20:35,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:35,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1741 transitions. [2021-12-15 17:20:35,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:35,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:35,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1741 transitions. [2021-12-15 17:20:35,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,784 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2021-12-15 17:20:35,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1741 transitions. [2021-12-15 17:20:35,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:35,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1741 transitions. [2021-12-15 17:20:35,802 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2021-12-15 17:20:35,803 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2021-12-15 17:20:35,803 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:35,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1741 transitions. [2021-12-15 17:20:35,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:35,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:35,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:35,810 INFO L791 eck$LassoCheckResult]: Stem: 5579#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5529#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5530#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5748#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5415#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5416#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5725#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5224#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5225#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5653#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5654#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4723#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4724#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4927#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5315#L939 assume !(0 == ~M_E~0); 5559#L939-2 assume !(0 == ~T1_E~0); 5560#L944-1 assume !(0 == ~T2_E~0); 5344#L949-1 assume !(0 == ~T3_E~0); 5342#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5343#L959-1 assume !(0 == ~T5_E~0); 5762#L964-1 assume !(0 == ~T6_E~0); 5075#L969-1 assume !(0 == ~T7_E~0); 5076#L974-1 assume !(0 == ~T8_E~0); 5715#L979-1 assume !(0 == ~T9_E~0); 5716#L984-1 assume !(0 == ~E_M~0); 5236#L989-1 assume !(0 == ~E_1~0); 5237#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5125#L999-1 assume !(0 == ~E_3~0); 5126#L1004-1 assume !(0 == ~E_4~0); 4791#L1009-1 assume !(0 == ~E_5~0); 4792#L1014-1 assume !(0 == ~E_6~0); 5121#L1019-1 assume !(0 == ~E_7~0); 5658#L1024-1 assume !(0 == ~E_8~0); 5048#L1029-1 assume !(0 == ~E_9~0); 5049#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5139#L460 assume 1 == ~m_pc~0; 4710#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4711#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5624#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5863#L1167 assume !(0 != activate_threads_~tmp~1#1); 5332#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5333#L479 assume 1 == ~t1_pc~0; 5316#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5317#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5820#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5060#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 5061#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4909#L498 assume !(1 == ~t2_pc~0); 4910#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5313#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5314#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5691#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5615#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5616#L517 assume 1 == ~t3_pc~0; 5824#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5825#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5387#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5093#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 5094#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5669#L536 assume !(1 == ~t4_pc~0); 5377#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5376#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5753#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5369#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 5370#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5589#L555 assume 1 == ~t5_pc~0; 5590#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5659#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4822#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4823#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 4930#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4830#L574 assume !(1 == ~t6_pc~0); 4831#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5462#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4935#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4936#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 5687#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5847#L593 assume 1 == ~t7_pc~0; 5848#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5067#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5765#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5868#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 5828#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5231#L612 assume !(1 == ~t8_pc~0); 5232#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5641#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5500#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5501#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 5466#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5467#L631 assume 1 == ~t9_pc~0; 5483#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4821#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4789#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4790#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 5319#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5670#L1047 assume !(1 == ~M_E~0); 4759#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4760#L1052-1 assume !(1 == ~T2_E~0); 4742#L1057-1 assume !(1 == ~T3_E~0); 4743#L1062-1 assume !(1 == ~T4_E~0); 5032#L1067-1 assume !(1 == ~T5_E~0); 5335#L1072-1 assume !(1 == ~T6_E~0); 5336#L1077-1 assume !(1 == ~T7_E~0); 4923#L1082-1 assume !(1 == ~T8_E~0); 4924#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4719#L1092-1 assume !(1 == ~E_M~0); 4720#L1097-1 assume !(1 == ~E_1~0); 4744#L1102-1 assume !(1 == ~E_2~0); 5525#L1107-1 assume !(1 == ~E_3~0); 5460#L1112-1 assume !(1 == ~E_4~0); 5461#L1117-1 assume !(1 == ~E_5~0); 5502#L1122-1 assume !(1 == ~E_6~0); 5388#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5144#L1132-1 assume !(1 == ~E_8~0); 5145#L1137-1 assume !(1 == ~E_9~0); 5031#L1142-1 assume { :end_inline_reset_delta_events } true; 4894#L1428-2 [2021-12-15 17:20:35,811 INFO L793 eck$LassoCheckResult]: Loop: 4894#L1428-2 assume !false; 4895#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4966#L914 assume !false; 5456#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5457#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4728#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4729#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5688#L783 assume !(0 != eval_~tmp~0#1); 5128#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5129#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5524#L939-3 assume !(0 == ~M_E~0); 4949#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4950#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4713#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4714#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5350#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4793#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4794#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5000#L974-3 assume !(0 == ~T8_E~0); 5001#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5431#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5432#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5054#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5055#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5566#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4877#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4878#L1014-3 assume !(0 == ~E_6~0); 5417#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5418#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5399#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5351#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5352#L460-33 assume !(1 == ~m_pc~0); 5392#L460-35 is_master_triggered_~__retres1~0#1 := 0; 5391#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5146#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4721#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4722#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5083#L479-33 assume !(1 == ~t1_pc~0); 5084#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 5050#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5051#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5635#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 5808#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5088#L498-33 assume 1 == ~t2_pc~0; 5089#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4834#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4971#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4972#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4947#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4948#L517-33 assume !(1 == ~t3_pc~0); 5856#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5739#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5740#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5552#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5553#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5175#L536-33 assume 1 == ~t4_pc~0; 5176#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5248#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5249#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5439#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5718#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4768#L555-33 assume !(1 == ~t5_pc~0); 4769#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 5494#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5041#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5042#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5521#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4737#L574-33 assume 1 == ~t6_pc~0; 4738#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5730#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5056#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5057#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5310#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4813#L593-33 assume !(1 == ~t7_pc~0); 4814#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 5267#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4921#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4922#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5581#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5708#L612-33 assume 1 == ~t8_pc~0; 5835#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5799#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5800#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5642#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4917#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4918#L631-33 assume 1 == ~t9_pc~0; 5760#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4861#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4862#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5114#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4973#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4974#L1047-3 assume !(1 == ~M_E~0); 5147#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5761#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5693#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5694#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4872#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4873#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5255#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5100#L1082-3 assume !(1 == ~T8_E~0); 5101#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5174#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5455#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5385#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5386#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5731#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5095#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5096#L1122-3 assume !(1 == ~E_6~0); 5148#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5149#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5538#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5515#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4975#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4853#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5516#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 5273#L1447 assume !(0 == start_simulation_~tmp~3#1); 5274#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5712#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5014#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5539#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 5124#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4881#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4882#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5337#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 4894#L1428-2 [2021-12-15 17:20:35,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,812 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2021-12-15 17:20:35,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245168095] [2021-12-15 17:20:35,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,813 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245168095] [2021-12-15 17:20:35,852 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245168095] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,852 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150539200] [2021-12-15 17:20:35,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,853 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:35,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:35,854 INFO L85 PathProgramCache]: Analyzing trace with hash 1367214863, now seen corresponding path program 1 times [2021-12-15 17:20:35,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:35,854 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589908429] [2021-12-15 17:20:35,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:35,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:35,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:35,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:35,920 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:35,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589908429] [2021-12-15 17:20:35,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589908429] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:35,921 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:35,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:35,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970780030] [2021-12-15 17:20:35,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:35,921 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:35,922 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:35,922 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:35,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:35,922 INFO L87 Difference]: Start difference. First operand 1170 states and 1741 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:35,955 INFO L93 Difference]: Finished difference Result 1170 states and 1740 transitions. [2021-12-15 17:20:35,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:35,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1740 transitions. [2021-12-15 17:20:35,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:35,971 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1740 transitions. [2021-12-15 17:20:35,971 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:35,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:35,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1740 transitions. [2021-12-15 17:20:35,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:35,974 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2021-12-15 17:20:35,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1740 transitions. [2021-12-15 17:20:35,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:35,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:35,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1740 transitions. [2021-12-15 17:20:35,993 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2021-12-15 17:20:35,993 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2021-12-15 17:20:35,993 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:35,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1740 transitions. [2021-12-15 17:20:35,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:35,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:35,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,004 INFO L791 eck$LassoCheckResult]: Stem: 7926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7927#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7876#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7877#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8095#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 7764#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7765#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8072#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7571#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7572#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8000#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8001#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7070#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7071#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7274#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7662#L939 assume !(0 == ~M_E~0); 7906#L939-2 assume !(0 == ~T1_E~0); 7907#L944-1 assume !(0 == ~T2_E~0); 7691#L949-1 assume !(0 == ~T3_E~0); 7689#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7690#L959-1 assume !(0 == ~T5_E~0); 8109#L964-1 assume !(0 == ~T6_E~0); 7422#L969-1 assume !(0 == ~T7_E~0); 7423#L974-1 assume !(0 == ~T8_E~0); 8062#L979-1 assume !(0 == ~T9_E~0); 8063#L984-1 assume !(0 == ~E_M~0); 7585#L989-1 assume !(0 == ~E_1~0); 7586#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7472#L999-1 assume !(0 == ~E_3~0); 7473#L1004-1 assume !(0 == ~E_4~0); 7138#L1009-1 assume !(0 == ~E_5~0); 7139#L1014-1 assume !(0 == ~E_6~0); 7468#L1019-1 assume !(0 == ~E_7~0); 8005#L1024-1 assume !(0 == ~E_8~0); 7395#L1029-1 assume !(0 == ~E_9~0); 7396#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7488#L460 assume 1 == ~m_pc~0; 7057#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7058#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7971#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8210#L1167 assume !(0 != activate_threads_~tmp~1#1); 7679#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7680#L479 assume 1 == ~t1_pc~0; 7663#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7664#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8167#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7408#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 7409#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7256#L498 assume !(1 == ~t2_pc~0); 7257#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7660#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7661#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8038#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7962#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7963#L517 assume 1 == ~t3_pc~0; 8172#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8173#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7734#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7440#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 7441#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8016#L536 assume !(1 == ~t4_pc~0); 7724#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7723#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8100#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7716#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 7717#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7938#L555 assume 1 == ~t5_pc~0; 7939#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8006#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7171#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7172#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 7279#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7177#L574 assume !(1 == ~t6_pc~0); 7178#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7809#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7282#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7283#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 8034#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8194#L593 assume 1 == ~t7_pc~0; 8195#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7414#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8114#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8215#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 8175#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7578#L612 assume !(1 == ~t8_pc~0); 7579#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7988#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7847#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7848#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 7813#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7814#L631 assume 1 == ~t9_pc~0; 7830#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7168#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7136#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7137#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 7666#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8017#L1047 assume !(1 == ~M_E~0); 7108#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7109#L1052-1 assume !(1 == ~T2_E~0); 7089#L1057-1 assume !(1 == ~T3_E~0); 7090#L1062-1 assume !(1 == ~T4_E~0); 7379#L1067-1 assume !(1 == ~T5_E~0); 7682#L1072-1 assume !(1 == ~T6_E~0); 7683#L1077-1 assume !(1 == ~T7_E~0); 7270#L1082-1 assume !(1 == ~T8_E~0); 7271#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7066#L1092-1 assume !(1 == ~E_M~0); 7067#L1097-1 assume !(1 == ~E_1~0); 7091#L1102-1 assume !(1 == ~E_2~0); 7872#L1107-1 assume !(1 == ~E_3~0); 7807#L1112-1 assume !(1 == ~E_4~0); 7808#L1117-1 assume !(1 == ~E_5~0); 7849#L1122-1 assume !(1 == ~E_6~0); 7735#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7491#L1132-1 assume !(1 == ~E_8~0); 7492#L1137-1 assume !(1 == ~E_9~0); 7378#L1142-1 assume { :end_inline_reset_delta_events } true; 7241#L1428-2 [2021-12-15 17:20:36,004 INFO L793 eck$LassoCheckResult]: Loop: 7241#L1428-2 assume !false; 7242#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7313#L914 assume !false; 7803#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7804#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7077#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7078#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8035#L783 assume !(0 != eval_~tmp~0#1); 7475#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7476#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7871#L939-3 assume !(0 == ~M_E~0); 7296#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7297#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7060#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7061#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7697#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7142#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7143#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7347#L974-3 assume !(0 == ~T8_E~0); 7348#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7778#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7779#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7401#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7402#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7913#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7224#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7225#L1014-3 assume !(0 == ~E_6~0); 7762#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7763#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7744#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7698#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7699#L460-33 assume 1 == ~m_pc~0; 7736#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7737#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7493#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7068#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7069#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7429#L479-33 assume !(1 == ~t1_pc~0); 7430#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7397#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7398#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7980#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 8155#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7438#L498-33 assume 1 == ~t2_pc~0; 7439#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7184#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7318#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7319#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7294#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7295#L517-33 assume !(1 == ~t3_pc~0); 8203#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8086#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8087#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7899#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7900#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7525#L536-33 assume 1 == ~t4_pc~0; 7526#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7595#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7596#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7786#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8065#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7115#L555-33 assume !(1 == ~t5_pc~0); 7116#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7841#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7388#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7389#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7868#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7086#L574-33 assume !(1 == ~t6_pc~0); 7088#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8077#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7403#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7404#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7657#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7162#L593-33 assume !(1 == ~t7_pc~0); 7163#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7618#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7268#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7269#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7928#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8055#L612-33 assume 1 == ~t8_pc~0; 8182#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8146#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8147#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7989#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7264#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7265#L631-33 assume !(1 == ~t9_pc~0); 7875#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 7208#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7209#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7461#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7320#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7321#L1047-3 assume !(1 == ~M_E~0); 7494#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8108#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8040#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8041#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7219#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7220#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7602#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7447#L1082-3 assume !(1 == ~T8_E~0); 7448#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7521#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7802#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7732#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7733#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8078#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7442#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7443#L1122-3 assume !(1 == ~E_6~0); 7495#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7496#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7885#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7862#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7325#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7200#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7863#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7620#L1447 assume !(0 == start_simulation_~tmp~3#1); 7621#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8059#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7361#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7886#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7471#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7228#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7229#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7684#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7241#L1428-2 [2021-12-15 17:20:36,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2021-12-15 17:20:36,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985722941] [2021-12-15 17:20:36,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,007 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,070 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,070 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985722941] [2021-12-15 17:20:36,071 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985722941] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,071 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,071 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,074 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58403551] [2021-12-15 17:20:36,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,075 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,076 INFO L85 PathProgramCache]: Analyzing trace with hash -466631152, now seen corresponding path program 1 times [2021-12-15 17:20:36,076 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128799798] [2021-12-15 17:20:36,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,077 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,124 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128799798] [2021-12-15 17:20:36,124 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128799798] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,124 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,124 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:36,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115154342] [2021-12-15 17:20:36,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,125 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,126 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:36,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:36,126 INFO L87 Difference]: Start difference. First operand 1170 states and 1740 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,146 INFO L93 Difference]: Finished difference Result 1170 states and 1739 transitions. [2021-12-15 17:20:36,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:36,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1739 transitions. [2021-12-15 17:20:36,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1739 transitions. [2021-12-15 17:20:36,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:36,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:36,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1739 transitions. [2021-12-15 17:20:36,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,161 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2021-12-15 17:20:36,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1739 transitions. [2021-12-15 17:20:36,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:36,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1739 transitions. [2021-12-15 17:20:36,178 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2021-12-15 17:20:36,178 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2021-12-15 17:20:36,178 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:36,178 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1739 transitions. [2021-12-15 17:20:36,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,202 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,202 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,203 INFO L791 eck$LassoCheckResult]: Stem: 10275#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10225#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10226#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10444#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 10111#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10112#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10421#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9920#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9921#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10347#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10348#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9419#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9420#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9623#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10011#L939 assume !(0 == ~M_E~0); 10255#L939-2 assume !(0 == ~T1_E~0); 10256#L944-1 assume !(0 == ~T2_E~0); 10040#L949-1 assume !(0 == ~T3_E~0); 10038#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10039#L959-1 assume !(0 == ~T5_E~0); 10458#L964-1 assume !(0 == ~T6_E~0); 9771#L969-1 assume !(0 == ~T7_E~0); 9772#L974-1 assume !(0 == ~T8_E~0); 10409#L979-1 assume !(0 == ~T9_E~0); 10410#L984-1 assume !(0 == ~E_M~0); 9932#L989-1 assume !(0 == ~E_1~0); 9933#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9821#L999-1 assume !(0 == ~E_3~0); 9822#L1004-1 assume !(0 == ~E_4~0); 9487#L1009-1 assume !(0 == ~E_5~0); 9488#L1014-1 assume !(0 == ~E_6~0); 9813#L1019-1 assume !(0 == ~E_7~0); 10354#L1024-1 assume !(0 == ~E_8~0); 9744#L1029-1 assume !(0 == ~E_9~0); 9745#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9835#L460 assume 1 == ~m_pc~0; 9403#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9404#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10320#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10559#L1167 assume !(0 != activate_threads_~tmp~1#1); 10028#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10029#L479 assume 1 == ~t1_pc~0; 10012#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10013#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10516#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9756#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 9757#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9605#L498 assume !(1 == ~t2_pc~0); 9606#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10009#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10010#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10387#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10310#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10311#L517 assume 1 == ~t3_pc~0; 10518#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10519#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10083#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9789#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 9790#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10363#L536 assume !(1 == ~t4_pc~0); 10073#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10072#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10449#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10065#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 10066#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10283#L555 assume 1 == ~t5_pc~0; 10284#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10355#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9518#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9519#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 9626#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9526#L574 assume !(1 == ~t6_pc~0); 9527#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10158#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9631#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9632#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 10381#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10543#L593 assume 1 == ~t7_pc~0; 10544#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9763#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10461#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10564#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 10524#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9927#L612 assume !(1 == ~t8_pc~0); 9928#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10337#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10195#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10196#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 10160#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10161#L631 assume 1 == ~t9_pc~0; 10179#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9517#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9485#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9486#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 10015#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10366#L1047 assume !(1 == ~M_E~0); 9455#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9456#L1052-1 assume !(1 == ~T2_E~0); 9438#L1057-1 assume !(1 == ~T3_E~0); 9439#L1062-1 assume !(1 == ~T4_E~0); 9728#L1067-1 assume !(1 == ~T5_E~0); 10031#L1072-1 assume !(1 == ~T6_E~0); 10032#L1077-1 assume !(1 == ~T7_E~0); 9619#L1082-1 assume !(1 == ~T8_E~0); 9620#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9411#L1092-1 assume !(1 == ~E_M~0); 9412#L1097-1 assume !(1 == ~E_1~0); 9440#L1102-1 assume !(1 == ~E_2~0); 10221#L1107-1 assume !(1 == ~E_3~0); 10156#L1112-1 assume !(1 == ~E_4~0); 10157#L1117-1 assume !(1 == ~E_5~0); 10197#L1122-1 assume !(1 == ~E_6~0); 10084#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9838#L1132-1 assume !(1 == ~E_8~0); 9839#L1137-1 assume !(1 == ~E_9~0); 9727#L1142-1 assume { :end_inline_reset_delta_events } true; 9587#L1428-2 [2021-12-15 17:20:36,203 INFO L793 eck$LassoCheckResult]: Loop: 9587#L1428-2 assume !false; 9588#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9662#L914 assume !false; 10152#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10153#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9424#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9425#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10384#L783 assume !(0 != eval_~tmp~0#1); 9824#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9825#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10220#L939-3 assume !(0 == ~M_E~0); 9643#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9644#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9409#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9410#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10046#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9489#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9490#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9696#L974-3 assume !(0 == ~T8_E~0); 9697#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10127#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10128#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9750#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9751#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10262#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9573#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9574#L1014-3 assume !(0 == ~E_6~0); 10113#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10114#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10095#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10047#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10048#L460-33 assume 1 == ~m_pc~0; 10085#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10086#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9842#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9417#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9418#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9778#L479-33 assume !(1 == ~t1_pc~0); 9779#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9746#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9747#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10331#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 10504#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9787#L498-33 assume 1 == ~t2_pc~0; 9788#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9533#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9667#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9668#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9645#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9646#L517-33 assume !(1 == ~t3_pc~0); 10552#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 10435#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10436#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10248#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10249#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9874#L536-33 assume 1 == ~t4_pc~0; 9875#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9944#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9945#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10135#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10414#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9464#L555-33 assume !(1 == ~t5_pc~0); 9465#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 10190#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9737#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9738#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10217#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9435#L574-33 assume 1 == ~t6_pc~0; 9436#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10426#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9752#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9753#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10006#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9511#L593-33 assume !(1 == ~t7_pc~0); 9512#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9967#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9617#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9618#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10277#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10404#L612-33 assume 1 == ~t8_pc~0; 10531#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10495#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10496#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10338#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9615#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9616#L631-33 assume !(1 == ~t9_pc~0); 10224#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9557#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9558#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9812#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9669#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9670#L1047-3 assume !(1 == ~M_E~0); 9843#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10457#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10389#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10390#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9568#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9569#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9951#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9796#L1082-3 assume !(1 == ~T8_E~0); 9797#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9870#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10151#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10081#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10082#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10427#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9791#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9792#L1122-3 assume !(1 == ~E_6~0); 9844#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9845#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10234#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10211#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9674#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9552#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10212#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9969#L1447 assume !(0 == start_simulation_~tmp~3#1); 9970#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10408#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9710#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10235#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 9820#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9577#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9578#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10033#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 9587#L1428-2 [2021-12-15 17:20:36,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,204 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2021-12-15 17:20:36,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726042105] [2021-12-15 17:20:36,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,205 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,231 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726042105] [2021-12-15 17:20:36,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726042105] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,232 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,232 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,232 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679916250] [2021-12-15 17:20:36,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,232 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,233 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 1 times [2021-12-15 17:20:36,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,233 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930892734] [2021-12-15 17:20:36,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930892734] [2021-12-15 17:20:36,266 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930892734] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,266 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,266 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051076142] [2021-12-15 17:20:36,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,267 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,267 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:36,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:36,268 INFO L87 Difference]: Start difference. First operand 1170 states and 1739 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,285 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2021-12-15 17:20:36,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:36,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1738 transitions. [2021-12-15 17:20:36,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1738 transitions. [2021-12-15 17:20:36,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:36,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:36,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1738 transitions. [2021-12-15 17:20:36,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,301 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2021-12-15 17:20:36,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1738 transitions. [2021-12-15 17:20:36,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:36,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1738 transitions. [2021-12-15 17:20:36,319 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2021-12-15 17:20:36,319 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2021-12-15 17:20:36,319 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:36,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1738 transitions. [2021-12-15 17:20:36,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,326 INFO L791 eck$LassoCheckResult]: Stem: 12622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12572#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12573#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12791#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 12458#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12459#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12768#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12267#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12268#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12694#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12695#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11766#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11767#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11970#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12358#L939 assume !(0 == ~M_E~0); 12602#L939-2 assume !(0 == ~T1_E~0); 12603#L944-1 assume !(0 == ~T2_E~0); 12387#L949-1 assume !(0 == ~T3_E~0); 12385#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12386#L959-1 assume !(0 == ~T5_E~0); 12805#L964-1 assume !(0 == ~T6_E~0); 12118#L969-1 assume !(0 == ~T7_E~0); 12119#L974-1 assume !(0 == ~T8_E~0); 12756#L979-1 assume !(0 == ~T9_E~0); 12757#L984-1 assume !(0 == ~E_M~0); 12279#L989-1 assume !(0 == ~E_1~0); 12280#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12168#L999-1 assume !(0 == ~E_3~0); 12169#L1004-1 assume !(0 == ~E_4~0); 11834#L1009-1 assume !(0 == ~E_5~0); 11835#L1014-1 assume !(0 == ~E_6~0); 12160#L1019-1 assume !(0 == ~E_7~0); 12701#L1024-1 assume !(0 == ~E_8~0); 12091#L1029-1 assume !(0 == ~E_9~0); 12092#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12182#L460 assume 1 == ~m_pc~0; 11750#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11751#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12667#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12906#L1167 assume !(0 != activate_threads_~tmp~1#1); 12375#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12376#L479 assume 1 == ~t1_pc~0; 12359#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12360#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12863#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12103#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 12104#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11952#L498 assume !(1 == ~t2_pc~0); 11953#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12356#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12357#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12734#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12657#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12658#L517 assume 1 == ~t3_pc~0; 12865#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12866#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12430#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12136#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 12137#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12710#L536 assume !(1 == ~t4_pc~0); 12420#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12419#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12796#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12412#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 12413#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12630#L555 assume 1 == ~t5_pc~0; 12631#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12702#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11865#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11866#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 11973#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11873#L574 assume !(1 == ~t6_pc~0); 11874#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12505#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11978#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11979#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 12728#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12890#L593 assume 1 == ~t7_pc~0; 12891#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12110#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12808#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12911#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 12871#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12274#L612 assume !(1 == ~t8_pc~0); 12275#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12684#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12542#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12543#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 12507#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12508#L631 assume 1 == ~t9_pc~0; 12526#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11864#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11832#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11833#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 12362#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12713#L1047 assume !(1 == ~M_E~0); 11802#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11803#L1052-1 assume !(1 == ~T2_E~0); 11785#L1057-1 assume !(1 == ~T3_E~0); 11786#L1062-1 assume !(1 == ~T4_E~0); 12075#L1067-1 assume !(1 == ~T5_E~0); 12378#L1072-1 assume !(1 == ~T6_E~0); 12379#L1077-1 assume !(1 == ~T7_E~0); 11966#L1082-1 assume !(1 == ~T8_E~0); 11967#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11758#L1092-1 assume !(1 == ~E_M~0); 11759#L1097-1 assume !(1 == ~E_1~0); 11787#L1102-1 assume !(1 == ~E_2~0); 12568#L1107-1 assume !(1 == ~E_3~0); 12503#L1112-1 assume !(1 == ~E_4~0); 12504#L1117-1 assume !(1 == ~E_5~0); 12544#L1122-1 assume !(1 == ~E_6~0); 12431#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12185#L1132-1 assume !(1 == ~E_8~0); 12186#L1137-1 assume !(1 == ~E_9~0); 12074#L1142-1 assume { :end_inline_reset_delta_events } true; 11934#L1428-2 [2021-12-15 17:20:36,326 INFO L793 eck$LassoCheckResult]: Loop: 11934#L1428-2 assume !false; 11935#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12009#L914 assume !false; 12499#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12500#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11771#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11772#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12731#L783 assume !(0 != eval_~tmp~0#1); 12171#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12172#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12567#L939-3 assume !(0 == ~M_E~0); 11990#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11991#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11756#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11757#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12393#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11836#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11837#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12043#L974-3 assume !(0 == ~T8_E~0); 12044#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12474#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12475#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12097#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12098#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12609#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11920#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11921#L1014-3 assume !(0 == ~E_6~0); 12460#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12461#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12442#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12394#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12395#L460-33 assume 1 == ~m_pc~0; 12432#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12433#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12189#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11764#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11765#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12125#L479-33 assume !(1 == ~t1_pc~0); 12126#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12093#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12094#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12678#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 12851#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12134#L498-33 assume 1 == ~t2_pc~0; 12135#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11880#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12014#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12015#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11992#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11993#L517-33 assume !(1 == ~t3_pc~0); 12899#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12782#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12783#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12595#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12596#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12221#L536-33 assume 1 == ~t4_pc~0; 12222#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12291#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12292#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12482#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12761#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11811#L555-33 assume !(1 == ~t5_pc~0); 11812#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12537#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12084#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12085#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12564#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11782#L574-33 assume 1 == ~t6_pc~0; 11783#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12773#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12099#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12100#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12353#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11858#L593-33 assume !(1 == ~t7_pc~0); 11859#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12314#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11964#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11965#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12624#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12751#L612-33 assume 1 == ~t8_pc~0; 12878#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12842#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12843#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12685#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11962#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11963#L631-33 assume 1 == ~t9_pc~0; 12803#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11904#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11905#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12159#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12016#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12017#L1047-3 assume !(1 == ~M_E~0); 12190#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12804#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12736#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12737#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11915#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11916#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12298#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12143#L1082-3 assume !(1 == ~T8_E~0); 12144#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12217#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12498#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12428#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12429#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12774#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12138#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L1122-3 assume !(1 == ~E_6~0); 12191#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12192#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12581#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12558#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12021#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11899#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12559#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12316#L1447 assume !(0 == start_simulation_~tmp~3#1); 12317#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12755#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12057#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12582#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 12167#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11924#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11925#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12380#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 11934#L1428-2 [2021-12-15 17:20:36,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,327 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2021-12-15 17:20:36,328 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533265507] [2021-12-15 17:20:36,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,351 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533265507] [2021-12-15 17:20:36,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533265507] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,351 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,352 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244950335] [2021-12-15 17:20:36,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,352 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,353 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 2 times [2021-12-15 17:20:36,353 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1365202461] [2021-12-15 17:20:36,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,354 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,384 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1365202461] [2021-12-15 17:20:36,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1365202461] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,384 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,384 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714352323] [2021-12-15 17:20:36,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,385 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,385 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:36,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:36,386 INFO L87 Difference]: Start difference. First operand 1170 states and 1738 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,404 INFO L93 Difference]: Finished difference Result 1170 states and 1737 transitions. [2021-12-15 17:20:36,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:36,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1737 transitions. [2021-12-15 17:20:36,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1737 transitions. [2021-12-15 17:20:36,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:36,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:36,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1737 transitions. [2021-12-15 17:20:36,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,419 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2021-12-15 17:20:36,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1737 transitions. [2021-12-15 17:20:36,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:36,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1737 transitions. [2021-12-15 17:20:36,436 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2021-12-15 17:20:36,436 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2021-12-15 17:20:36,437 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:36,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1737 transitions. [2021-12-15 17:20:36,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,443 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,443 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,443 INFO L791 eck$LassoCheckResult]: Stem: 14969#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14919#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14920#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15138#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 14805#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14806#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15115#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14614#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14615#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15041#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15042#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14113#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14114#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14317#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14705#L939 assume !(0 == ~M_E~0); 14949#L939-2 assume !(0 == ~T1_E~0); 14950#L944-1 assume !(0 == ~T2_E~0); 14734#L949-1 assume !(0 == ~T3_E~0); 14732#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14733#L959-1 assume !(0 == ~T5_E~0); 15152#L964-1 assume !(0 == ~T6_E~0); 14465#L969-1 assume !(0 == ~T7_E~0); 14466#L974-1 assume !(0 == ~T8_E~0); 15103#L979-1 assume !(0 == ~T9_E~0); 15104#L984-1 assume !(0 == ~E_M~0); 14626#L989-1 assume !(0 == ~E_1~0); 14627#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14515#L999-1 assume !(0 == ~E_3~0); 14516#L1004-1 assume !(0 == ~E_4~0); 14181#L1009-1 assume !(0 == ~E_5~0); 14182#L1014-1 assume !(0 == ~E_6~0); 14507#L1019-1 assume !(0 == ~E_7~0); 15048#L1024-1 assume !(0 == ~E_8~0); 14438#L1029-1 assume !(0 == ~E_9~0); 14439#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14529#L460 assume 1 == ~m_pc~0; 14097#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14098#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15014#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15253#L1167 assume !(0 != activate_threads_~tmp~1#1); 14722#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14723#L479 assume 1 == ~t1_pc~0; 14706#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14707#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15210#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14450#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 14451#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14299#L498 assume !(1 == ~t2_pc~0); 14300#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14703#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14704#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15081#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15004#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15005#L517 assume 1 == ~t3_pc~0; 15212#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15213#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14777#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14483#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 14484#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15057#L536 assume !(1 == ~t4_pc~0); 14767#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14766#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15143#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14759#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 14760#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14977#L555 assume 1 == ~t5_pc~0; 14978#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15049#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14212#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14213#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 14320#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14220#L574 assume !(1 == ~t6_pc~0); 14221#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14852#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14325#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14326#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 15075#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15237#L593 assume 1 == ~t7_pc~0; 15238#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14457#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15155#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15258#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 15218#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14621#L612 assume !(1 == ~t8_pc~0); 14622#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15031#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14889#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14890#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 14854#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14855#L631 assume 1 == ~t9_pc~0; 14873#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14211#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14179#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14180#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 14709#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15060#L1047 assume !(1 == ~M_E~0); 14149#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14150#L1052-1 assume !(1 == ~T2_E~0); 14132#L1057-1 assume !(1 == ~T3_E~0); 14133#L1062-1 assume !(1 == ~T4_E~0); 14422#L1067-1 assume !(1 == ~T5_E~0); 14725#L1072-1 assume !(1 == ~T6_E~0); 14726#L1077-1 assume !(1 == ~T7_E~0); 14313#L1082-1 assume !(1 == ~T8_E~0); 14314#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14105#L1092-1 assume !(1 == ~E_M~0); 14106#L1097-1 assume !(1 == ~E_1~0); 14134#L1102-1 assume !(1 == ~E_2~0); 14915#L1107-1 assume !(1 == ~E_3~0); 14850#L1112-1 assume !(1 == ~E_4~0); 14851#L1117-1 assume !(1 == ~E_5~0); 14891#L1122-1 assume !(1 == ~E_6~0); 14778#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14532#L1132-1 assume !(1 == ~E_8~0); 14533#L1137-1 assume !(1 == ~E_9~0); 14421#L1142-1 assume { :end_inline_reset_delta_events } true; 14281#L1428-2 [2021-12-15 17:20:36,444 INFO L793 eck$LassoCheckResult]: Loop: 14281#L1428-2 assume !false; 14282#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14356#L914 assume !false; 14846#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14847#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14118#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14119#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15078#L783 assume !(0 != eval_~tmp~0#1); 14518#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14519#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14914#L939-3 assume !(0 == ~M_E~0); 14337#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14338#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14103#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14104#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14740#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14183#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14184#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14390#L974-3 assume !(0 == ~T8_E~0); 14391#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14821#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14822#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14444#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14445#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14956#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14267#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14268#L1014-3 assume !(0 == ~E_6~0); 14807#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14808#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14789#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14741#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14742#L460-33 assume 1 == ~m_pc~0; 14779#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14780#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14536#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14111#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14112#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14472#L479-33 assume !(1 == ~t1_pc~0); 14473#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14440#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14441#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15025#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 15198#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14481#L498-33 assume 1 == ~t2_pc~0; 14482#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14227#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14361#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14362#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14339#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14340#L517-33 assume !(1 == ~t3_pc~0); 15246#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 15129#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15130#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14942#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14943#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14568#L536-33 assume 1 == ~t4_pc~0; 14569#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14638#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14639#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14829#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15108#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14158#L555-33 assume 1 == ~t5_pc~0; 14160#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14884#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14431#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14432#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14911#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14129#L574-33 assume 1 == ~t6_pc~0; 14130#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15120#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14446#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14447#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14700#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14205#L593-33 assume !(1 == ~t7_pc~0); 14206#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 14661#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14311#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14312#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14971#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15098#L612-33 assume 1 == ~t8_pc~0; 15225#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15189#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15190#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15032#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14309#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14310#L631-33 assume !(1 == ~t9_pc~0); 14918#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 14251#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14252#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14506#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14363#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14364#L1047-3 assume !(1 == ~M_E~0); 14537#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15151#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15083#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15084#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14262#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14263#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14645#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14490#L1082-3 assume !(1 == ~T8_E~0); 14491#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14564#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14845#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14775#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14776#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15121#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14485#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14486#L1122-3 assume !(1 == ~E_6~0); 14538#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14539#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14928#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14905#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14368#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14246#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14906#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14663#L1447 assume !(0 == start_simulation_~tmp~3#1); 14664#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15102#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14404#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14929#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 14514#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14271#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14272#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14727#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 14281#L1428-2 [2021-12-15 17:20:36,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2021-12-15 17:20:36,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277353606] [2021-12-15 17:20:36,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,445 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277353606] [2021-12-15 17:20:36,468 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277353606] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,468 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,468 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,468 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302098803] [2021-12-15 17:20:36,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,469 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,469 INFO L85 PathProgramCache]: Analyzing trace with hash -1283827122, now seen corresponding path program 1 times [2021-12-15 17:20:36,469 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647272782] [2021-12-15 17:20:36,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,470 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,529 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,529 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647272782] [2021-12-15 17:20:36,529 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647272782] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,529 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,530 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126511026] [2021-12-15 17:20:36,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,530 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,530 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:36,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:36,531 INFO L87 Difference]: Start difference. First operand 1170 states and 1737 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,548 INFO L93 Difference]: Finished difference Result 1170 states and 1736 transitions. [2021-12-15 17:20:36,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:36,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1736 transitions. [2021-12-15 17:20:36,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1736 transitions. [2021-12-15 17:20:36,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:36,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:36,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1736 transitions. [2021-12-15 17:20:36,566 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,566 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2021-12-15 17:20:36,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1736 transitions. [2021-12-15 17:20:36,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:36,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1736 transitions. [2021-12-15 17:20:36,586 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2021-12-15 17:20:36,586 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2021-12-15 17:20:36,586 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:36,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1736 transitions. [2021-12-15 17:20:36,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,594 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,595 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,595 INFO L791 eck$LassoCheckResult]: Stem: 17316#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17266#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17267#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17485#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 17152#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17153#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17462#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16961#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16962#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17390#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17391#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16460#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16461#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16664#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17052#L939 assume !(0 == ~M_E~0); 17296#L939-2 assume !(0 == ~T1_E~0); 17297#L944-1 assume !(0 == ~T2_E~0); 17081#L949-1 assume !(0 == ~T3_E~0); 17079#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17080#L959-1 assume !(0 == ~T5_E~0); 17499#L964-1 assume !(0 == ~T6_E~0); 16812#L969-1 assume !(0 == ~T7_E~0); 16813#L974-1 assume !(0 == ~T8_E~0); 17450#L979-1 assume !(0 == ~T9_E~0); 17451#L984-1 assume !(0 == ~E_M~0); 16973#L989-1 assume !(0 == ~E_1~0); 16974#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16862#L999-1 assume !(0 == ~E_3~0); 16863#L1004-1 assume !(0 == ~E_4~0); 16528#L1009-1 assume !(0 == ~E_5~0); 16529#L1014-1 assume !(0 == ~E_6~0); 16854#L1019-1 assume !(0 == ~E_7~0); 17395#L1024-1 assume !(0 == ~E_8~0); 16785#L1029-1 assume !(0 == ~E_9~0); 16786#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16876#L460 assume 1 == ~m_pc~0; 16444#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16445#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17361#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17600#L1167 assume !(0 != activate_threads_~tmp~1#1); 17069#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17070#L479 assume 1 == ~t1_pc~0; 17053#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17054#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17557#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16797#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 16798#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16646#L498 assume !(1 == ~t2_pc~0); 16647#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17050#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17051#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17428#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17352#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17353#L517 assume 1 == ~t3_pc~0; 17559#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17560#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17124#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16830#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 16831#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17404#L536 assume !(1 == ~t4_pc~0); 17114#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17113#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17490#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17106#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 17107#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17324#L555 assume 1 == ~t5_pc~0; 17325#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17396#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16559#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16560#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 16667#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16567#L574 assume !(1 == ~t6_pc~0); 16568#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17199#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16672#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16673#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 17422#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17584#L593 assume 1 == ~t7_pc~0; 17585#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16804#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17502#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17605#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 17565#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16968#L612 assume !(1 == ~t8_pc~0); 16969#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17378#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17236#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17237#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 17201#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17202#L631 assume 1 == ~t9_pc~0; 17220#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16558#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16526#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16527#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 17056#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17407#L1047 assume !(1 == ~M_E~0); 16496#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16497#L1052-1 assume !(1 == ~T2_E~0); 16479#L1057-1 assume !(1 == ~T3_E~0); 16480#L1062-1 assume !(1 == ~T4_E~0); 16769#L1067-1 assume !(1 == ~T5_E~0); 17072#L1072-1 assume !(1 == ~T6_E~0); 17073#L1077-1 assume !(1 == ~T7_E~0); 16660#L1082-1 assume !(1 == ~T8_E~0); 16661#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16452#L1092-1 assume !(1 == ~E_M~0); 16453#L1097-1 assume !(1 == ~E_1~0); 16481#L1102-1 assume !(1 == ~E_2~0); 17262#L1107-1 assume !(1 == ~E_3~0); 17197#L1112-1 assume !(1 == ~E_4~0); 17198#L1117-1 assume !(1 == ~E_5~0); 17238#L1122-1 assume !(1 == ~E_6~0); 17125#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16879#L1132-1 assume !(1 == ~E_8~0); 16880#L1137-1 assume !(1 == ~E_9~0); 16768#L1142-1 assume { :end_inline_reset_delta_events } true; 16628#L1428-2 [2021-12-15 17:20:36,598 INFO L793 eck$LassoCheckResult]: Loop: 16628#L1428-2 assume !false; 16629#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16703#L914 assume !false; 17193#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17194#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16465#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16466#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17425#L783 assume !(0 != eval_~tmp~0#1); 16865#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16866#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17261#L939-3 assume !(0 == ~M_E~0); 16684#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16685#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16450#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16451#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17087#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16530#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16531#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16737#L974-3 assume !(0 == ~T8_E~0); 16738#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17168#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17169#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16791#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16792#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17303#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16614#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16615#L1014-3 assume !(0 == ~E_6~0); 17154#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17155#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17136#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17088#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17089#L460-33 assume 1 == ~m_pc~0; 17126#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17127#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16883#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16458#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16459#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16820#L479-33 assume !(1 == ~t1_pc~0); 16821#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16787#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16788#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17372#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 17545#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16828#L498-33 assume 1 == ~t2_pc~0; 16829#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16574#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16708#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16709#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16686#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16687#L517-33 assume !(1 == ~t3_pc~0); 17593#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17476#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17477#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17289#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17290#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16915#L536-33 assume 1 == ~t4_pc~0; 16916#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16985#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16986#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17176#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17455#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16505#L555-33 assume !(1 == ~t5_pc~0); 16506#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 17231#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16778#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16779#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17258#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16476#L574-33 assume 1 == ~t6_pc~0; 16477#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17467#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16793#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16794#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17047#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16552#L593-33 assume !(1 == ~t7_pc~0); 16553#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 17009#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16658#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16659#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17318#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17445#L612-33 assume 1 == ~t8_pc~0; 17572#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17536#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17537#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17379#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16656#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16657#L631-33 assume !(1 == ~t9_pc~0); 17265#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 16598#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16599#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16853#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16710#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16711#L1047-3 assume !(1 == ~M_E~0); 16884#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17498#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17430#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17431#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16609#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16610#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16992#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16837#L1082-3 assume !(1 == ~T8_E~0); 16838#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16911#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17192#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17122#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17123#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17468#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16832#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16833#L1122-3 assume !(1 == ~E_6~0); 16885#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16886#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17275#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17252#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16715#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16593#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17253#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17010#L1447 assume !(0 == start_simulation_~tmp~3#1); 17011#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17449#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16751#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17276#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 16861#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16618#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16619#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17074#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 16628#L1428-2 [2021-12-15 17:20:36,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,599 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2021-12-15 17:20:36,599 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911206184] [2021-12-15 17:20:36,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,600 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,624 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911206184] [2021-12-15 17:20:36,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911206184] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,626 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,626 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,626 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429162609] [2021-12-15 17:20:36,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,627 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,627 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 2 times [2021-12-15 17:20:36,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473278254] [2021-12-15 17:20:36,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,631 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473278254] [2021-12-15 17:20:36,665 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473278254] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,665 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,665 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,666 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038427133] [2021-12-15 17:20:36,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,667 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,667 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:36,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:36,668 INFO L87 Difference]: Start difference. First operand 1170 states and 1736 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,685 INFO L93 Difference]: Finished difference Result 1170 states and 1735 transitions. [2021-12-15 17:20:36,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:36,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1735 transitions. [2021-12-15 17:20:36,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1735 transitions. [2021-12-15 17:20:36,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-15 17:20:36,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-15 17:20:36,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1735 transitions. [2021-12-15 17:20:36,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,703 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2021-12-15 17:20:36,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1735 transitions. [2021-12-15 17:20:36,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-15 17:20:36,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1735 transitions. [2021-12-15 17:20:36,721 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2021-12-15 17:20:36,721 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2021-12-15 17:20:36,721 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:36,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1735 transitions. [2021-12-15 17:20:36,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-15 17:20:36,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,729 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,729 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,729 INFO L791 eck$LassoCheckResult]: Stem: 19663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 19613#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19614#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19832#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 19499#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19500#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19809#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19308#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19309#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19737#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19738#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18807#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18808#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19011#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19399#L939 assume !(0 == ~M_E~0); 19643#L939-2 assume !(0 == ~T1_E~0); 19644#L944-1 assume !(0 == ~T2_E~0); 19428#L949-1 assume !(0 == ~T3_E~0); 19426#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19427#L959-1 assume !(0 == ~T5_E~0); 19846#L964-1 assume !(0 == ~T6_E~0); 19159#L969-1 assume !(0 == ~T7_E~0); 19160#L974-1 assume !(0 == ~T8_E~0); 19797#L979-1 assume !(0 == ~T9_E~0); 19798#L984-1 assume !(0 == ~E_M~0); 19320#L989-1 assume !(0 == ~E_1~0); 19321#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19209#L999-1 assume !(0 == ~E_3~0); 19210#L1004-1 assume !(0 == ~E_4~0); 18875#L1009-1 assume !(0 == ~E_5~0); 18876#L1014-1 assume !(0 == ~E_6~0); 19203#L1019-1 assume !(0 == ~E_7~0); 19742#L1024-1 assume !(0 == ~E_8~0); 19132#L1029-1 assume !(0 == ~E_9~0); 19133#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19223#L460 assume 1 == ~m_pc~0; 18791#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18792#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19708#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19947#L1167 assume !(0 != activate_threads_~tmp~1#1); 19416#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19417#L479 assume 1 == ~t1_pc~0; 19400#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19401#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19904#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19144#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 19145#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18993#L498 assume !(1 == ~t2_pc~0); 18994#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19397#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19398#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19775#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19699#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19700#L517 assume 1 == ~t3_pc~0; 19908#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19909#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19471#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19177#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 19178#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19753#L536 assume !(1 == ~t4_pc~0); 19461#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19460#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19837#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19453#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 19454#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19673#L555 assume 1 == ~t5_pc~0; 19674#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19743#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18906#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18907#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 19014#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18914#L574 assume !(1 == ~t6_pc~0); 18915#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19546#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19019#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19020#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 19771#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19931#L593 assume 1 == ~t7_pc~0; 19932#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19151#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19849#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19952#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 19912#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19315#L612 assume !(1 == ~t8_pc~0); 19316#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19725#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19583#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19584#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 19550#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19551#L631 assume 1 == ~t9_pc~0; 19567#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18905#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18873#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18874#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 19403#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19754#L1047 assume !(1 == ~M_E~0); 18843#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18844#L1052-1 assume !(1 == ~T2_E~0); 18826#L1057-1 assume !(1 == ~T3_E~0); 18827#L1062-1 assume !(1 == ~T4_E~0); 19116#L1067-1 assume !(1 == ~T5_E~0); 19419#L1072-1 assume !(1 == ~T6_E~0); 19420#L1077-1 assume !(1 == ~T7_E~0); 19007#L1082-1 assume !(1 == ~T8_E~0); 19008#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18801#L1092-1 assume !(1 == ~E_M~0); 18802#L1097-1 assume !(1 == ~E_1~0); 18828#L1102-1 assume !(1 == ~E_2~0); 19609#L1107-1 assume !(1 == ~E_3~0); 19544#L1112-1 assume !(1 == ~E_4~0); 19545#L1117-1 assume !(1 == ~E_5~0); 19585#L1122-1 assume !(1 == ~E_6~0); 19472#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19228#L1132-1 assume !(1 == ~E_8~0); 19229#L1137-1 assume !(1 == ~E_9~0); 19115#L1142-1 assume { :end_inline_reset_delta_events } true; 18975#L1428-2 [2021-12-15 17:20:36,730 INFO L793 eck$LassoCheckResult]: Loop: 18975#L1428-2 assume !false; 18976#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19050#L914 assume !false; 19540#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19541#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18812#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18813#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19772#L783 assume !(0 != eval_~tmp~0#1); 19212#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19213#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19608#L939-3 assume !(0 == ~M_E~0); 19031#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19032#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18797#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18798#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19434#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18877#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18878#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19084#L974-3 assume !(0 == ~T8_E~0); 19085#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19515#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19516#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19138#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19139#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19650#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18961#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18962#L1014-3 assume !(0 == ~E_6~0); 19501#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19502#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19483#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19435#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19436#L460-33 assume 1 == ~m_pc~0; 19473#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19474#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19230#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18805#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18806#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19167#L479-33 assume !(1 == ~t1_pc~0); 19168#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19134#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19135#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19719#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 19892#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19175#L498-33 assume 1 == ~t2_pc~0; 19176#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18921#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19057#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19058#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19033#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19034#L517-33 assume !(1 == ~t3_pc~0); 19940#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 19823#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19824#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19636#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19637#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19262#L536-33 assume !(1 == ~t4_pc~0); 19264#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 19332#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19333#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19523#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19802#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18852#L555-33 assume !(1 == ~t5_pc~0); 18853#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 19578#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19125#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19126#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19605#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18818#L574-33 assume 1 == ~t6_pc~0; 18819#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19814#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19140#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19141#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19394#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18894#L593-33 assume 1 == ~t7_pc~0; 18896#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19350#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19005#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19006#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19665#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19792#L612-33 assume !(1 == ~t8_pc~0); 19920#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 19883#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19884#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19726#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19001#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19002#L631-33 assume 1 == ~t9_pc~0; 19844#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18945#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18946#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19198#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19055#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19056#L1047-3 assume !(1 == ~M_E~0); 19231#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19845#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19777#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19778#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18956#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18957#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19339#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19184#L1082-3 assume !(1 == ~T8_E~0); 19185#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19258#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19539#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19469#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19470#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19815#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19179#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19180#L1122-3 assume !(1 == ~E_6~0); 19232#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19233#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19622#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19599#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19059#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18937#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19600#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19357#L1447 assume !(0 == start_simulation_~tmp~3#1); 19358#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19796#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19098#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19623#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 19208#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 18965#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18966#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19421#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 18975#L1428-2 [2021-12-15 17:20:36,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2021-12-15 17:20:36,731 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155043691] [2021-12-15 17:20:36,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,731 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,766 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,766 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155043691] [2021-12-15 17:20:36,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155043691] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,767 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048811327] [2021-12-15 17:20:36,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,768 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1679945009, now seen corresponding path program 1 times [2021-12-15 17:20:36,769 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890249895] [2021-12-15 17:20:36,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1890249895] [2021-12-15 17:20:36,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1890249895] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,799 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120780592] [2021-12-15 17:20:36,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,800 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,800 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:36,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:36,801 INFO L87 Difference]: Start difference. First operand 1170 states and 1735 transitions. cyclomatic complexity: 566 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:36,898 INFO L93 Difference]: Finished difference Result 2141 states and 3163 transitions. [2021-12-15 17:20:36,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:36,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2141 states and 3163 transitions. [2021-12-15 17:20:36,910 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2021-12-15 17:20:36,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2141 states to 2141 states and 3163 transitions. [2021-12-15 17:20:36,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2141 [2021-12-15 17:20:36,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2141 [2021-12-15 17:20:36,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2141 states and 3163 transitions. [2021-12-15 17:20:36,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:36,925 INFO L681 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2021-12-15 17:20:36,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states and 3163 transitions. [2021-12-15 17:20:36,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 2141. [2021-12-15 17:20:36,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2141 states to 2141 states and 3163 transitions. [2021-12-15 17:20:36,962 INFO L704 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2021-12-15 17:20:36,962 INFO L587 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2021-12-15 17:20:36,962 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:36,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2141 states and 3163 transitions. [2021-12-15 17:20:36,969 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2021-12-15 17:20:36,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,970 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,971 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,971 INFO L791 eck$LassoCheckResult]: Stem: 22999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 23000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22947#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22948#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23188#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 22828#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22829#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23164#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22634#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22635#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23082#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23083#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22128#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22129#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22332#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22725#L939 assume !(0 == ~M_E~0); 22977#L939-2 assume !(0 == ~T1_E~0); 22978#L944-1 assume !(0 == ~T2_E~0); 22754#L949-1 assume !(0 == ~T3_E~0); 22752#L954-1 assume !(0 == ~T4_E~0); 22753#L959-1 assume !(0 == ~T5_E~0); 23206#L964-1 assume !(0 == ~T6_E~0); 22481#L969-1 assume !(0 == ~T7_E~0); 22482#L974-1 assume !(0 == ~T8_E~0); 23152#L979-1 assume !(0 == ~T9_E~0); 23153#L984-1 assume !(0 == ~E_M~0); 22648#L989-1 assume !(0 == ~E_1~0); 22649#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22531#L999-1 assume !(0 == ~E_3~0); 22532#L1004-1 assume !(0 == ~E_4~0); 22196#L1009-1 assume !(0 == ~E_5~0); 22197#L1014-1 assume !(0 == ~E_6~0); 22527#L1019-1 assume !(0 == ~E_7~0); 23087#L1024-1 assume !(0 == ~E_8~0); 22454#L1029-1 assume !(0 == ~E_9~0); 22455#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22547#L460 assume 1 == ~m_pc~0; 22115#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22116#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23052#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23334#L1167 assume !(0 != activate_threads_~tmp~1#1); 22742#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22743#L479 assume 1 == ~t1_pc~0; 22726#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22727#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23276#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22467#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 22468#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22314#L498 assume !(1 == ~t2_pc~0); 22315#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22723#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22724#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23125#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23042#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23043#L517 assume 1 == ~t3_pc~0; 23281#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23282#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22798#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22499#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 22500#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23099#L536 assume !(1 == ~t4_pc~0); 22788#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22787#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23195#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22780#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 22781#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23011#L555 assume 1 == ~t5_pc~0; 23012#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23088#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22229#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22230#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 22335#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22235#L574 assume !(1 == ~t6_pc~0); 22236#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22878#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22340#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22341#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 23120#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23314#L593 assume 1 == ~t7_pc~0; 23315#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22473#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23210#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23343#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 23284#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22641#L612 assume !(1 == ~t8_pc~0); 22642#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23069#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22916#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22917#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 22882#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22883#L631 assume 1 == ~t9_pc~0; 22899#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22226#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22194#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22195#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 22729#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23100#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 22166#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22167#L1052-1 assume !(1 == ~T2_E~0); 23558#L1057-1 assume !(1 == ~T3_E~0); 23557#L1062-1 assume !(1 == ~T4_E~0); 22437#L1067-1 assume !(1 == ~T5_E~0); 22745#L1072-1 assume !(1 == ~T6_E~0); 22746#L1077-1 assume !(1 == ~T7_E~0); 22328#L1082-1 assume !(1 == ~T8_E~0); 22329#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22124#L1092-1 assume !(1 == ~E_M~0); 22125#L1097-1 assume !(1 == ~E_1~0); 22149#L1102-1 assume !(1 == ~E_2~0); 22943#L1107-1 assume !(1 == ~E_3~0); 22876#L1112-1 assume !(1 == ~E_4~0); 22877#L1117-1 assume !(1 == ~E_5~0); 22918#L1122-1 assume !(1 == ~E_6~0); 22799#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22550#L1132-1 assume !(1 == ~E_8~0); 22551#L1137-1 assume !(1 == ~E_9~0); 22436#L1142-1 assume { :end_inline_reset_delta_events } true; 22299#L1428-2 [2021-12-15 17:20:36,971 INFO L793 eck$LassoCheckResult]: Loop: 22299#L1428-2 assume !false; 22300#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23317#L914 assume !false; 23318#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23073#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22135#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22136#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23121#L783 assume !(0 != eval_~tmp~0#1); 23122#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22941#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22942#L939-3 assume !(0 == ~M_E~0); 22354#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22355#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22118#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22119#L954-3 assume !(0 == ~T4_E~0); 22760#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22200#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22201#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22405#L974-3 assume !(0 == ~T8_E~0); 22406#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22842#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22843#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22460#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22461#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22986#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22282#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22283#L1014-3 assume !(0 == ~E_6~0); 22826#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22827#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22808#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22761#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22762#L460-33 assume 1 == ~m_pc~0; 22800#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22801#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22552#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22126#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22127#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22485#L479-33 assume !(1 == ~t1_pc~0); 22486#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 23663#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23662#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23661#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 23660#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23659#L498-33 assume 1 == ~t2_pc~0; 23657#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23656#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23655#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23654#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23653#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23652#L517-33 assume 1 == ~t3_pc~0; 23650#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23649#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23648#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23647#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23646#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23645#L536-33 assume 1 == ~t4_pc~0; 23643#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23642#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23641#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23640#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23639#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23638#L555-33 assume !(1 == ~t5_pc~0); 23636#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 23635#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23634#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23633#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23632#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23631#L574-33 assume 1 == ~t6_pc~0; 23629#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23628#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23627#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23626#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23625#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23624#L593-33 assume !(1 == ~t7_pc~0); 23622#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 23621#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23620#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23619#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23618#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23617#L612-33 assume !(1 == ~t8_pc~0); 23616#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 23614#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23613#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23612#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23611#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23360#L631-33 assume !(1 == ~t9_pc~0); 22946#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 22266#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22267#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22520#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22378#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22379#L1047-3 assume !(1 == ~M_E~0); 22553#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23205#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23362#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23361#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22277#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22278#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22665#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22506#L1082-3 assume !(1 == ~T8_E~0); 22507#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22581#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22869#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22796#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22797#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23171#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22501#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22502#L1122-3 assume !(1 == ~E_6~0); 22554#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22555#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22956#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22932#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22383#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22258#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22933#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22683#L1447 assume !(0 == start_simulation_~tmp~3#1); 22684#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23489#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23480#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23479#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 23478#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 23477#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23476#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 22747#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 22299#L1428-2 [2021-12-15 17:20:36,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,972 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2021-12-15 17:20:36,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474219036] [2021-12-15 17:20:36,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474219036] [2021-12-15 17:20:37,000 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474219036] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,000 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,001 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441418716] [2021-12-15 17:20:37,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,002 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,002 INFO L85 PathProgramCache]: Analyzing trace with hash 442140877, now seen corresponding path program 1 times [2021-12-15 17:20:37,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652753384] [2021-12-15 17:20:37,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,007 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652753384] [2021-12-15 17:20:37,046 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652753384] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,046 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,046 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,047 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385298683] [2021-12-15 17:20:37,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,047 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:37,047 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:37,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:37,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:37,049 INFO L87 Difference]: Start difference. First operand 2141 states and 3163 transitions. cyclomatic complexity: 1024 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:37,189 INFO L93 Difference]: Finished difference Result 3925 states and 5786 transitions. [2021-12-15 17:20:37,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:37,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3925 states and 5786 transitions. [2021-12-15 17:20:37,228 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3752 [2021-12-15 17:20:37,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3925 states to 3925 states and 5786 transitions. [2021-12-15 17:20:37,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3925 [2021-12-15 17:20:37,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3925 [2021-12-15 17:20:37,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3925 states and 5786 transitions. [2021-12-15 17:20:37,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:37,255 INFO L681 BuchiCegarLoop]: Abstraction has 3925 states and 5786 transitions. [2021-12-15 17:20:37,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3925 states and 5786 transitions. [2021-12-15 17:20:37,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3925 to 3923. [2021-12-15 17:20:37,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3923 states, 3923 states have (on average 1.474381850624522) internal successors, (5784), 3922 states have internal predecessors, (5784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3923 states to 3923 states and 5784 transitions. [2021-12-15 17:20:37,325 INFO L704 BuchiCegarLoop]: Abstraction has 3923 states and 5784 transitions. [2021-12-15 17:20:37,325 INFO L587 BuchiCegarLoop]: Abstraction has 3923 states and 5784 transitions. [2021-12-15 17:20:37,325 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:37,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3923 states and 5784 transitions. [2021-12-15 17:20:37,339 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3752 [2021-12-15 17:20:37,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:37,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:37,341 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,341 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,342 INFO L791 eck$LassoCheckResult]: Stem: 29076#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 29077#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 29026#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29027#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29256#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 28905#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28906#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29231#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28713#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28714#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29153#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29154#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28204#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28205#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28409#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28803#L939 assume !(0 == ~M_E~0); 29056#L939-2 assume !(0 == ~T1_E~0); 29057#L944-1 assume !(0 == ~T2_E~0); 28832#L949-1 assume !(0 == ~T3_E~0); 28830#L954-1 assume !(0 == ~T4_E~0); 28831#L959-1 assume !(0 == ~T5_E~0); 29270#L964-1 assume !(0 == ~T6_E~0); 28559#L969-1 assume !(0 == ~T7_E~0); 28560#L974-1 assume !(0 == ~T8_E~0); 29221#L979-1 assume !(0 == ~T9_E~0); 29222#L984-1 assume !(0 == ~E_M~0); 28725#L989-1 assume !(0 == ~E_1~0); 28726#L994-1 assume !(0 == ~E_2~0); 28609#L999-1 assume !(0 == ~E_3~0); 28610#L1004-1 assume !(0 == ~E_4~0); 28272#L1009-1 assume !(0 == ~E_5~0); 28273#L1014-1 assume !(0 == ~E_6~0); 28605#L1019-1 assume !(0 == ~E_7~0); 29158#L1024-1 assume !(0 == ~E_8~0); 28532#L1029-1 assume !(0 == ~E_9~0); 28533#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28626#L460 assume 1 == ~m_pc~0; 28191#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28192#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29122#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29382#L1167 assume !(0 != activate_threads_~tmp~1#1); 28820#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28821#L479 assume 1 == ~t1_pc~0; 28804#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28805#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29332#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28545#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 28546#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28391#L498 assume !(1 == ~t2_pc~0); 28392#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28801#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28802#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29195#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29113#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29114#L517 assume 1 == ~t3_pc~0; 29337#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29338#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28875#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28577#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 28578#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29169#L536 assume !(1 == ~t4_pc~0); 28865#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28864#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29261#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28857#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 28858#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29088#L555 assume 1 == ~t5_pc~0; 29089#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29159#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28305#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28306#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 28414#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28311#L574 assume !(1 == ~t6_pc~0); 28312#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28955#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28417#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28418#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 29190#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29365#L593 assume 1 == ~t7_pc~0; 29366#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28551#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29275#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29391#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 29341#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28718#L612 assume !(1 == ~t8_pc~0); 28719#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29140#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28995#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28996#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 28960#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28961#L631 assume 1 == ~t9_pc~0; 28977#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28302#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28270#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28271#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 28807#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29170#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 29171#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28948#L1052-1 assume !(1 == ~T2_E~0); 28949#L1057-1 assume !(1 == ~T3_E~0); 28515#L1062-1 assume !(1 == ~T4_E~0); 28516#L1067-1 assume !(1 == ~T5_E~0); 28823#L1072-1 assume !(1 == ~T6_E~0); 28824#L1077-1 assume !(1 == ~T7_E~0); 29694#L1082-1 assume !(1 == ~T8_E~0); 29692#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29691#L1092-1 assume !(1 == ~E_M~0); 29482#L1097-1 assume !(1 == ~E_1~0); 29480#L1102-1 assume !(1 == ~E_2~0); 29476#L1107-1 assume !(1 == ~E_3~0); 29474#L1112-1 assume !(1 == ~E_4~0); 29472#L1117-1 assume !(1 == ~E_5~0); 29470#L1122-1 assume !(1 == ~E_6~0); 29468#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 29467#L1132-1 assume !(1 == ~E_8~0); 29453#L1137-1 assume !(1 == ~E_9~0); 29444#L1142-1 assume { :end_inline_reset_delta_events } true; 29436#L1428-2 [2021-12-15 17:20:37,342 INFO L793 eck$LassoCheckResult]: Loop: 29436#L1428-2 assume !false; 29430#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29426#L914 assume !false; 29425#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29423#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 29414#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29413#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29411#L783 assume !(0 != eval_~tmp~0#1); 29410#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29409#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29407#L939-3 assume !(0 == ~M_E~0); 29408#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30727#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30725#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30723#L954-3 assume !(0 == ~T4_E~0); 30721#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30719#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30718#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30715#L974-3 assume !(0 == ~T8_E~0); 30713#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30711#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30710#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30708#L994-3 assume !(0 == ~E_2~0); 30706#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30704#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30702#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30700#L1014-3 assume !(0 == ~E_6~0); 30448#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30446#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30444#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30442#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30439#L460-33 assume !(1 == ~m_pc~0); 30436#L460-35 is_master_triggered_~__retres1~0#1 := 0; 30434#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30432#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30430#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30428#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30425#L479-33 assume 1 == ~t1_pc~0; 30422#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30420#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30418#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30416#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 30414#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30411#L498-33 assume 1 == ~t2_pc~0; 30408#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30305#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30216#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30196#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30191#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30183#L517-33 assume 1 == ~t3_pc~0; 30155#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30153#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30151#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30149#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30147#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30109#L536-33 assume 1 == ~t4_pc~0; 30054#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30052#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30050#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30048#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30047#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30046#L555-33 assume !(1 == ~t5_pc~0); 29991#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 29989#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29986#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29984#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29982#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29980#L574-33 assume 1 == ~t6_pc~0; 29974#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29972#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29970#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29968#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29966#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29930#L593-33 assume !(1 == ~t7_pc~0); 29928#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 29927#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29926#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29924#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29922#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29920#L612-33 assume 1 == ~t8_pc~0; 29917#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29915#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29913#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29912#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29911#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29851#L631-33 assume !(1 == ~t9_pc~0); 29804#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 29775#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29755#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29753#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29751#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29749#L1047-3 assume !(1 == ~M_E~0); 28633#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29746#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29720#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29718#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29715#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29712#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29710#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29708#L1082-3 assume !(1 == ~T8_E~0); 29706#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29689#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29687#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29685#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29681#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29677#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29675#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29673#L1122-3 assume !(1 == ~E_6~0); 29672#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29671#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29670#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29669#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29667#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 29657#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29655#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 29653#L1447 assume !(0 == start_simulation_~tmp~3#1); 28917#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29647#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 29637#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29636#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 29635#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29466#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29452#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 29443#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 29436#L1428-2 [2021-12-15 17:20:37,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2021-12-15 17:20:37,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893232759] [2021-12-15 17:20:37,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,372 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893232759] [2021-12-15 17:20:37,372 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [893232759] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,372 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,372 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:37,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300177698] [2021-12-15 17:20:37,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,373 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,374 INFO L85 PathProgramCache]: Analyzing trace with hash 2051335050, now seen corresponding path program 1 times [2021-12-15 17:20:37,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630873902] [2021-12-15 17:20:37,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,375 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,402 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630873902] [2021-12-15 17:20:37,403 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [630873902] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,403 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,403 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,403 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980025794] [2021-12-15 17:20:37,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,404 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:37,404 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:37,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:37,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:37,405 INFO L87 Difference]: Start difference. First operand 3923 states and 5784 transitions. cyclomatic complexity: 1865 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:37,497 INFO L93 Difference]: Finished difference Result 7623 states and 11143 transitions. [2021-12-15 17:20:37,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:37,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7623 states and 11143 transitions. [2021-12-15 17:20:37,534 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7445 [2021-12-15 17:20:37,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7623 states to 7623 states and 11143 transitions. [2021-12-15 17:20:37,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7623 [2021-12-15 17:20:37,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7623 [2021-12-15 17:20:37,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7623 states and 11143 transitions. [2021-12-15 17:20:37,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:37,584 INFO L681 BuchiCegarLoop]: Abstraction has 7623 states and 11143 transitions. [2021-12-15 17:20:37,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7623 states and 11143 transitions. [2021-12-15 17:20:37,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7623 to 7347. [2021-12-15 17:20:37,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7347 states, 7347 states have (on average 1.463862801143324) internal successors, (10755), 7346 states have internal predecessors, (10755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7347 states to 7347 states and 10755 transitions. [2021-12-15 17:20:37,784 INFO L704 BuchiCegarLoop]: Abstraction has 7347 states and 10755 transitions. [2021-12-15 17:20:37,784 INFO L587 BuchiCegarLoop]: Abstraction has 7347 states and 10755 transitions. [2021-12-15 17:20:37,784 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:37,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7347 states and 10755 transitions. [2021-12-15 17:20:37,808 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7169 [2021-12-15 17:20:37,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:37,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:37,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,810 INFO L791 eck$LassoCheckResult]: Stem: 40645#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 40646#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 40591#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40592#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40837#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 40462#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40463#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40814#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40267#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40268#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40730#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40731#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39754#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39755#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39961#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40359#L939 assume !(0 == ~M_E~0); 40624#L939-2 assume !(0 == ~T1_E~0); 40625#L944-1 assume !(0 == ~T2_E~0); 40388#L949-1 assume !(0 == ~T3_E~0); 40386#L954-1 assume !(0 == ~T4_E~0); 40387#L959-1 assume !(0 == ~T5_E~0); 40852#L964-1 assume !(0 == ~T6_E~0); 40113#L969-1 assume !(0 == ~T7_E~0); 40114#L974-1 assume !(0 == ~T8_E~0); 40804#L979-1 assume !(0 == ~T9_E~0); 40805#L984-1 assume !(0 == ~E_M~0); 40280#L989-1 assume !(0 == ~E_1~0); 40281#L994-1 assume !(0 == ~E_2~0); 40162#L999-1 assume !(0 == ~E_3~0); 40163#L1004-1 assume !(0 == ~E_4~0); 39824#L1009-1 assume !(0 == ~E_5~0); 39825#L1014-1 assume !(0 == ~E_6~0); 40158#L1019-1 assume !(0 == ~E_7~0); 40736#L1024-1 assume !(0 == ~E_8~0); 40086#L1029-1 assume !(0 == ~E_9~0); 40087#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40179#L460 assume !(1 == ~m_pc~0); 40984#L460-2 is_master_triggered_~__retres1~0#1 := 0; 40697#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40698#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41014#L1167 assume !(0 != activate_threads_~tmp~1#1); 40376#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40377#L479 assume 1 == ~t1_pc~0; 40360#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40361#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40939#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40100#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 40101#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39943#L498 assume !(1 == ~t2_pc~0); 39944#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40357#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40358#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40774#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40688#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40689#L517 assume 1 == ~t3_pc~0; 40945#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40946#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40432#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40131#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 40132#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40747#L536 assume !(1 == ~t4_pc~0); 40421#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40420#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40843#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40413#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 40414#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40659#L555 assume 1 == ~t5_pc~0; 40660#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40737#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39857#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39858#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 39966#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39864#L574 assume !(1 == ~t6_pc~0); 39865#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40516#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39969#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39970#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 40769#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40991#L593 assume 1 == ~t7_pc~0; 40992#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40105#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40858#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41027#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 40950#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40273#L612 assume !(1 == ~t8_pc~0); 40274#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40716#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40557#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40558#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 40520#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40521#L631 assume 1 == ~t9_pc~0; 40538#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39854#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39822#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39823#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 40363#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40748#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 39793#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39794#L1052-1 assume !(1 == ~T2_E~0); 40509#L1057-1 assume !(1 == ~T3_E~0); 41867#L1062-1 assume !(1 == ~T4_E~0); 41853#L1067-1 assume !(1 == ~T5_E~0); 41849#L1072-1 assume !(1 == ~T6_E~0); 40718#L1077-1 assume !(1 == ~T7_E~0); 40719#L1082-1 assume !(1 == ~T8_E~0); 40488#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40489#L1092-1 assume !(1 == ~E_M~0); 39775#L1097-1 assume !(1 == ~E_1~0); 39776#L1102-1 assume !(1 == ~E_2~0); 41819#L1107-1 assume !(1 == ~E_3~0); 41806#L1112-1 assume !(1 == ~E_4~0); 41801#L1117-1 assume !(1 == ~E_5~0); 41421#L1122-1 assume !(1 == ~E_6~0); 41251#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41249#L1132-1 assume !(1 == ~E_8~0); 41211#L1137-1 assume !(1 == ~E_9~0); 41202#L1142-1 assume { :end_inline_reset_delta_events } true; 41194#L1428-2 [2021-12-15 17:20:37,811 INFO L793 eck$LassoCheckResult]: Loop: 41194#L1428-2 assume !false; 41188#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41184#L914 assume !false; 41183#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 41181#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 41172#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 41171#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41169#L783 assume !(0 != eval_~tmp~0#1); 41168#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41167#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41166#L939-3 assume !(0 == ~M_E~0); 41162#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41160#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41158#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41156#L954-3 assume !(0 == ~T4_E~0); 41155#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41152#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41150#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41148#L974-3 assume !(0 == ~T8_E~0); 41146#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41144#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41142#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41139#L994-3 assume !(0 == ~E_2~0); 41137#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41135#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41133#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41131#L1014-3 assume !(0 == ~E_6~0); 41129#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41127#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41128#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42065#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42059#L460-33 assume !(1 == ~m_pc~0); 42053#L460-35 is_master_triggered_~__retres1~0#1 := 0; 42046#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42041#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42037#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42033#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42029#L479-33 assume 1 == ~t1_pc~0; 42024#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42019#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42015#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42011#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 42006#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42002#L498-33 assume 1 == ~t2_pc~0; 41997#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41992#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41988#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41984#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41979#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41975#L517-33 assume 1 == ~t3_pc~0; 41970#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41965#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41960#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41956#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41951#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41947#L536-33 assume 1 == ~t4_pc~0; 41942#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41937#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41932#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41928#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41923#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41919#L555-33 assume !(1 == ~t5_pc~0); 41914#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 41909#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41904#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41900#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41896#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41893#L574-33 assume 1 == ~t6_pc~0; 41889#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41886#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41884#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41880#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41879#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41878#L593-33 assume !(1 == ~t7_pc~0); 41876#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 41875#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41874#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41873#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41871#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41870#L612-33 assume 1 == ~t8_pc~0; 41854#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41850#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41846#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41840#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41836#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41832#L631-33 assume !(1 == ~t9_pc~0); 41827#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 41823#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41820#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41816#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41813#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41810#L1047-3 assume !(1 == ~M_E~0); 41429#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41804#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41799#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41419#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41415#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41412#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41410#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41408#L1082-3 assume !(1 == ~T8_E~0); 41406#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41404#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41402#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41399#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41395#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41393#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41391#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41389#L1122-3 assume !(1 == ~E_6~0); 41387#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41384#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41382#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41380#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 41372#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 41362#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 41360#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 41358#L1447 assume !(0 == start_simulation_~tmp~3#1); 41356#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 41246#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 41236#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 41233#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 41231#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 41229#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41210#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 41201#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 41194#L1428-2 [2021-12-15 17:20:37,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,811 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2021-12-15 17:20:37,811 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752832991] [2021-12-15 17:20:37,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,812 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752832991] [2021-12-15 17:20:37,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752832991] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:37,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783061674] [2021-12-15 17:20:37,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,857 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,858 INFO L85 PathProgramCache]: Analyzing trace with hash 2051335050, now seen corresponding path program 2 times [2021-12-15 17:20:37,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541232877] [2021-12-15 17:20:37,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,886 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541232877] [2021-12-15 17:20:37,887 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541232877] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,887 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,887 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,887 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984421985] [2021-12-15 17:20:37,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,887 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:37,887 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:37,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:37,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:37,889 INFO L87 Difference]: Start difference. First operand 7347 states and 10755 transitions. cyclomatic complexity: 3416 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,047 INFO L93 Difference]: Finished difference Result 14143 states and 20561 transitions. [2021-12-15 17:20:38,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:38,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14143 states and 20561 transitions. [2021-12-15 17:20:38,113 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13950 [2021-12-15 17:20:38,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14143 states to 14143 states and 20561 transitions. [2021-12-15 17:20:38,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14143 [2021-12-15 17:20:38,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14143 [2021-12-15 17:20:38,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14143 states and 20561 transitions. [2021-12-15 17:20:38,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,194 INFO L681 BuchiCegarLoop]: Abstraction has 14143 states and 20561 transitions. [2021-12-15 17:20:38,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14143 states and 20561 transitions. [2021-12-15 17:20:38,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14143 to 14127. [2021-12-15 17:20:38,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14127 states, 14127 states have (on average 1.4543073547108374) internal successors, (20545), 14126 states have internal predecessors, (20545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14127 states to 14127 states and 20545 transitions. [2021-12-15 17:20:38,554 INFO L704 BuchiCegarLoop]: Abstraction has 14127 states and 20545 transitions. [2021-12-15 17:20:38,554 INFO L587 BuchiCegarLoop]: Abstraction has 14127 states and 20545 transitions. [2021-12-15 17:20:38,554 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:38,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14127 states and 20545 transitions. [2021-12-15 17:20:38,666 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13934 [2021-12-15 17:20:38,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,681 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,682 INFO L791 eck$LassoCheckResult]: Stem: 62148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 62149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 62090#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62091#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62343#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 61962#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61963#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62317#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61764#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61765#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62236#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62237#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61251#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 61252#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61455#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61862#L939 assume !(0 == ~M_E~0); 62124#L939-2 assume !(0 == ~T1_E~0); 62125#L944-1 assume !(0 == ~T2_E~0); 61890#L949-1 assume !(0 == ~T3_E~0); 61888#L954-1 assume !(0 == ~T4_E~0); 61889#L959-1 assume !(0 == ~T5_E~0); 62359#L964-1 assume !(0 == ~T6_E~0); 61604#L969-1 assume !(0 == ~T7_E~0); 61605#L974-1 assume !(0 == ~T8_E~0); 62304#L979-1 assume !(0 == ~T9_E~0); 62305#L984-1 assume !(0 == ~E_M~0); 61776#L989-1 assume !(0 == ~E_1~0); 61777#L994-1 assume !(0 == ~E_2~0); 61657#L999-1 assume !(0 == ~E_3~0); 61658#L1004-1 assume !(0 == ~E_4~0); 61319#L1009-1 assume !(0 == ~E_5~0); 61320#L1014-1 assume !(0 == ~E_6~0); 61649#L1019-1 assume !(0 == ~E_7~0); 62243#L1024-1 assume !(0 == ~E_8~0); 61577#L1029-1 assume !(0 == ~E_9~0); 61578#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61671#L460 assume !(1 == ~m_pc~0); 62481#L460-2 is_master_triggered_~__retres1~0#1 := 0; 62204#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62205#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62514#L1167 assume !(0 != activate_threads_~tmp~1#1); 61878#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61879#L479 assume !(1 == ~t1_pc~0); 62038#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62039#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62448#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61589#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 61590#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61437#L498 assume !(1 == ~t2_pc~0); 61438#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61860#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61861#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62278#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62192#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62193#L517 assume 1 == ~t3_pc~0; 62452#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62453#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61934#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61624#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 61625#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62252#L536 assume !(1 == ~t4_pc~0); 61923#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61922#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62349#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61915#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 61916#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62159#L555 assume 1 == ~t5_pc~0; 62160#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62244#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61350#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61351#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 61458#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61358#L574 assume !(1 == ~t6_pc~0); 61359#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 62015#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61463#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61464#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 62271#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62488#L593 assume 1 == ~t7_pc~0; 62489#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61596#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62364#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62531#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 62458#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61771#L612 assume !(1 == ~t8_pc~0); 61772#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62225#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62057#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62058#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 62017#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62018#L631 assume 1 == ~t9_pc~0; 62036#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61349#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61317#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61318#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 61863#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62255#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 62256#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62010#L1052-1 assume !(1 == ~T2_E~0); 61270#L1057-1 assume !(1 == ~T3_E~0); 61271#L1062-1 assume !(1 == ~T4_E~0); 61561#L1067-1 assume !(1 == ~T5_E~0); 64442#L1072-1 assume !(1 == ~T6_E~0); 62227#L1077-1 assume !(1 == ~T7_E~0); 61451#L1082-1 assume !(1 == ~T8_E~0); 61452#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61243#L1092-1 assume !(1 == ~E_M~0); 61244#L1097-1 assume !(1 == ~E_1~0); 61272#L1102-1 assume !(1 == ~E_2~0); 64126#L1107-1 assume !(1 == ~E_3~0); 64124#L1112-1 assume !(1 == ~E_4~0); 64122#L1117-1 assume !(1 == ~E_5~0); 64119#L1122-1 assume !(1 == ~E_6~0); 64117#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 64116#L1132-1 assume !(1 == ~E_8~0); 64112#L1137-1 assume !(1 == ~E_9~0); 64110#L1142-1 assume { :end_inline_reset_delta_events } true; 64100#L1428-2 [2021-12-15 17:20:38,682 INFO L793 eck$LassoCheckResult]: Loop: 64100#L1428-2 assume !false; 64067#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64045#L914 assume !false; 64042#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64024#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64013#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64006#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63999#L783 assume !(0 != eval_~tmp~0#1); 64000#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64831#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64829#L939-3 assume !(0 == ~M_E~0); 64827#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64825#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64823#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64821#L954-3 assume !(0 == ~T4_E~0); 64819#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64817#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64815#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64813#L974-3 assume !(0 == ~T8_E~0); 64811#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64809#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64807#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64805#L994-3 assume !(0 == ~E_2~0); 64803#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64801#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 64799#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64797#L1014-3 assume !(0 == ~E_6~0); 64795#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64793#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64791#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64789#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64787#L460-33 assume !(1 == ~m_pc~0); 64785#L460-35 is_master_triggered_~__retres1~0#1 := 0; 64783#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64781#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64779#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64777#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64774#L479-33 assume !(1 == ~t1_pc~0); 64772#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 64770#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64768#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 64766#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 64764#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64761#L498-33 assume 1 == ~t2_pc~0; 64758#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64756#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64754#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64752#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64750#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64747#L517-33 assume 1 == ~t3_pc~0; 64744#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64742#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64740#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64738#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64736#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64735#L536-33 assume 1 == ~t4_pc~0; 64731#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64729#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64727#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64725#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64723#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64721#L555-33 assume !(1 == ~t5_pc~0); 64716#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 64714#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64712#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64710#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64708#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64705#L574-33 assume 1 == ~t6_pc~0; 64702#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64700#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64698#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64696#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64694#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64693#L593-33 assume !(1 == ~t7_pc~0); 64691#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 64688#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64686#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64684#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64682#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64680#L612-33 assume 1 == ~t8_pc~0; 64677#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64676#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64674#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64672#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64670#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64668#L631-33 assume !(1 == ~t9_pc~0); 64665#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 64632#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64624#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64615#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64607#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64597#L1047-3 assume !(1 == ~M_E~0); 64585#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64593#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64591#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64572#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64568#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64566#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64563#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64561#L1082-3 assume !(1 == ~T8_E~0); 64559#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64557#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64555#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64540#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64533#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64523#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64494#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64492#L1122-3 assume !(1 == ~E_6~0); 64490#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64488#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64487#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64486#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64456#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64446#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64445#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 64444#L1447 assume !(0 == start_simulation_~tmp~3#1); 64436#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64198#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64187#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64185#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 64183#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 64181#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64179#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 64109#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 64100#L1428-2 [2021-12-15 17:20:38,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,683 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2021-12-15 17:20:38,683 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769038006] [2021-12-15 17:20:38,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,721 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769038006] [2021-12-15 17:20:38,721 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769038006] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,721 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,722 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:38,722 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535819157] [2021-12-15 17:20:38,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,723 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,723 INFO L85 PathProgramCache]: Analyzing trace with hash 566094859, now seen corresponding path program 1 times [2021-12-15 17:20:38,724 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075022660] [2021-12-15 17:20:38,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,724 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,751 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075022660] [2021-12-15 17:20:38,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075022660] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,751 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,752 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,752 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1218094491] [2021-12-15 17:20:38,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,753 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,753 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:38,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:38,754 INFO L87 Difference]: Start difference. First operand 14127 states and 20545 transitions. cyclomatic complexity: 6434 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:39,211 INFO L93 Difference]: Finished difference Result 38742 states and 56336 transitions. [2021-12-15 17:20:39,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:39,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38742 states and 56336 transitions. [2021-12-15 17:20:39,403 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38268 [2021-12-15 17:20:39,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38742 states to 38742 states and 56336 transitions. [2021-12-15 17:20:39,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38742 [2021-12-15 17:20:39,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38742 [2021-12-15 17:20:39,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38742 states and 56336 transitions. [2021-12-15 17:20:39,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:39,767 INFO L681 BuchiCegarLoop]: Abstraction has 38742 states and 56336 transitions. [2021-12-15 17:20:39,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38742 states and 56336 transitions. [2021-12-15 17:20:40,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38742 to 14610. [2021-12-15 17:20:40,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14610 states, 14610 states have (on average 1.4392881587953457) internal successors, (21028), 14609 states have internal predecessors, (21028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14610 states to 14610 states and 21028 transitions. [2021-12-15 17:20:40,173 INFO L704 BuchiCegarLoop]: Abstraction has 14610 states and 21028 transitions. [2021-12-15 17:20:40,173 INFO L587 BuchiCegarLoop]: Abstraction has 14610 states and 21028 transitions. [2021-12-15 17:20:40,173 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:40,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14610 states and 21028 transitions. [2021-12-15 17:20:40,222 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14414 [2021-12-15 17:20:40,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:40,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:40,224 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,224 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,225 INFO L791 eck$LassoCheckResult]: Stem: 115068#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 115069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 115008#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115009#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 115315#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 114861#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114862#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115281#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114655#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114656#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115182#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115183#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 114133#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 114134#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 114342#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114756#L939 assume !(0 == ~M_E~0); 115047#L939-2 assume !(0 == ~T1_E~0); 115048#L944-1 assume !(0 == ~T2_E~0); 114787#L949-1 assume !(0 == ~T3_E~0); 114785#L954-1 assume !(0 == ~T4_E~0); 114786#L959-1 assume !(0 == ~T5_E~0); 115337#L964-1 assume !(0 == ~T6_E~0); 114492#L969-1 assume !(0 == ~T7_E~0); 114493#L974-1 assume !(0 == ~T8_E~0); 115266#L979-1 assume !(0 == ~T9_E~0); 115267#L984-1 assume !(0 == ~E_M~0); 114667#L989-1 assume !(0 == ~E_1~0); 114668#L994-1 assume !(0 == ~E_2~0); 114544#L999-1 assume !(0 == ~E_3~0); 114545#L1004-1 assume !(0 == ~E_4~0); 114202#L1009-1 assume !(0 == ~E_5~0); 114203#L1014-1 assume !(0 == ~E_6~0); 114536#L1019-1 assume !(0 == ~E_7~0); 115191#L1024-1 assume !(0 == ~E_8~0); 114465#L1029-1 assume !(0 == ~E_9~0); 114466#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114559#L460 assume !(1 == ~m_pc~0); 115523#L460-2 is_master_triggered_~__retres1~0#1 := 0; 115139#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115140#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 115574#L1167 assume !(0 != activate_threads_~tmp~1#1); 114773#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114774#L479 assume !(1 == ~t1_pc~0); 114951#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114952#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115457#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 114477#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 114478#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114323#L498 assume !(1 == ~t2_pc~0); 114324#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 114754#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114755#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 115233#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 115126#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115127#L517 assume 1 == ~t3_pc~0; 115465#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 115466#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114834#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 114512#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 114513#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115200#L536 assume !(1 == ~t4_pc~0); 114823#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 114822#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115323#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 114814#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 114815#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115084#L555 assume 1 == ~t5_pc~0; 115085#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 115192#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114234#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114235#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 114345#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114243#L574 assume !(1 == ~t6_pc~0); 114244#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 114922#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114350#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114351#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 115225#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115533#L593 assume 1 == ~t7_pc~0; 115534#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 114484#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115342#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 115613#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 115473#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114662#L612 assume !(1 == ~t8_pc~0); 114663#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 115161#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114972#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114973#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 114925#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114926#L631 assume 1 == ~t9_pc~0; 114946#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 114233#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114200#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114201#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 114757#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115203#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 115204#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118476#L1052-1 assume !(1 == ~T2_E~0); 114152#L1057-1 assume !(1 == ~T3_E~0); 114153#L1062-1 assume !(1 == ~T4_E~0); 114449#L1067-1 assume !(1 == ~T5_E~0); 118474#L1072-1 assume !(1 == ~T6_E~0); 115163#L1077-1 assume !(1 == ~T7_E~0); 115164#L1082-1 assume !(1 == ~T8_E~0); 114890#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 114891#L1092-1 assume !(1 == ~E_M~0); 114154#L1097-1 assume !(1 == ~E_1~0); 114155#L1102-1 assume !(1 == ~E_2~0); 118327#L1107-1 assume !(1 == ~E_3~0); 118286#L1112-1 assume !(1 == ~E_4~0); 118259#L1117-1 assume !(1 == ~E_5~0); 118243#L1122-1 assume !(1 == ~E_6~0); 118241#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 118240#L1132-1 assume !(1 == ~E_8~0); 118226#L1137-1 assume !(1 == ~E_9~0); 118217#L1142-1 assume { :end_inline_reset_delta_events } true; 118209#L1428-2 [2021-12-15 17:20:40,225 INFO L793 eck$LassoCheckResult]: Loop: 118209#L1428-2 assume !false; 118203#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118199#L914 assume !false; 118198#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 118196#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 118187#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 118186#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 118184#L783 assume !(0 != eval_~tmp~0#1); 118183#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 118182#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 118180#L939-3 assume !(0 == ~M_E~0); 118181#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119131#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 119129#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 119127#L954-3 assume !(0 == ~T4_E~0); 119125#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119123#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 119121#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 119119#L974-3 assume !(0 == ~T8_E~0); 119117#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 119115#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 119113#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119111#L994-3 assume !(0 == ~E_2~0); 119109#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119107#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119105#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 119103#L1014-3 assume !(0 == ~E_6~0); 119101#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 119078#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 119076#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 119074#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119073#L460-33 assume !(1 == ~m_pc~0); 119072#L460-35 is_master_triggered_~__retres1~0#1 := 0; 119071#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119070#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119069#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119068#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119067#L479-33 assume !(1 == ~t1_pc~0); 119066#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 119065#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119064#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119063#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 119062#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119061#L498-33 assume 1 == ~t2_pc~0; 119059#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 119057#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119055#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119053#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119050#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119048#L517-33 assume 1 == ~t3_pc~0; 119045#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 119043#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119041#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119039#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 119036#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119034#L536-33 assume 1 == ~t4_pc~0; 119031#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 119029#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119027#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119004#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119000#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118997#L555-33 assume !(1 == ~t5_pc~0); 118971#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 118967#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118963#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 118960#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 118958#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118956#L574-33 assume !(1 == ~t6_pc~0); 118955#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 118926#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118923#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 118885#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 118877#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 118863#L593-33 assume 1 == ~t7_pc~0; 118839#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 118836#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118833#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118831#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 118829#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118827#L612-33 assume !(1 == ~t8_pc~0); 118793#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 118778#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 118770#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118769#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 118747#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 118746#L631-33 assume 1 == ~t9_pc~0; 118735#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 118704#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 118690#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118688#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 118656#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118654#L1047-3 assume !(1 == ~M_E~0); 116059#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118653#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 118590#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118588#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 118586#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 118585#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 118584#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 118583#L1082-3 assume !(1 == ~T8_E~0); 118506#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 118504#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 118501#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 118457#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 118453#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 118451#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118449#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118447#L1122-3 assume !(1 == ~E_6~0); 118445#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 118440#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 118436#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 118432#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 118398#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 118388#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 118386#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 118366#L1447 assume !(0 == start_simulation_~tmp~3#1); 114876#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 118321#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 118283#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 118258#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 118256#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 118239#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118225#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 118216#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 118209#L1428-2 [2021-12-15 17:20:40,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,226 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2021-12-15 17:20:40,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784132490] [2021-12-15 17:20:40,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,255 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784132490] [2021-12-15 17:20:40,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784132490] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,255 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:40,256 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290852036] [2021-12-15 17:20:40,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,256 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:40,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,257 INFO L85 PathProgramCache]: Analyzing trace with hash -1304313205, now seen corresponding path program 1 times [2021-12-15 17:20:40,257 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,257 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789711849] [2021-12-15 17:20:40,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,257 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,287 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789711849] [2021-12-15 17:20:40,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789711849] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,287 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,287 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:40,287 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784236953] [2021-12-15 17:20:40,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,288 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:40,288 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:40,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:40,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:40,289 INFO L87 Difference]: Start difference. First operand 14610 states and 21028 transitions. cyclomatic complexity: 6434 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:40,604 INFO L93 Difference]: Finished difference Result 34836 states and 49764 transitions. [2021-12-15 17:20:40,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:40,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34836 states and 49764 transitions. [2021-12-15 17:20:40,793 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 34553 [2021-12-15 17:20:40,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34836 states to 34836 states and 49764 transitions. [2021-12-15 17:20:40,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34836 [2021-12-15 17:20:40,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34836 [2021-12-15 17:20:40,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34836 states and 49764 transitions. [2021-12-15 17:20:41,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:41,151 INFO L681 BuchiCegarLoop]: Abstraction has 34836 states and 49764 transitions. [2021-12-15 17:20:41,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34836 states and 49764 transitions. [2021-12-15 17:20:41,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34836 to 27671. [2021-12-15 17:20:41,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27671 states, 27671 states have (on average 1.4327996819775215) internal successors, (39647), 27670 states have internal predecessors, (39647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27671 states to 27671 states and 39647 transitions. [2021-12-15 17:20:41,619 INFO L704 BuchiCegarLoop]: Abstraction has 27671 states and 39647 transitions. [2021-12-15 17:20:41,620 INFO L587 BuchiCegarLoop]: Abstraction has 27671 states and 39647 transitions. [2021-12-15 17:20:41,620 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:41,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27671 states and 39647 transitions. [2021-12-15 17:20:41,705 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27452 [2021-12-15 17:20:41,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:41,705 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:41,707 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,707 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,707 INFO L791 eck$LassoCheckResult]: Stem: 164489#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 164490#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 164429#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 164430#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164680#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 164298#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164299#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164654#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164101#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164102#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164572#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 164573#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 163591#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 163592#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 163796#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164192#L939 assume !(0 == ~M_E~0); 164466#L939-2 assume !(0 == ~T1_E~0); 164467#L944-1 assume !(0 == ~T2_E~0); 164221#L949-1 assume !(0 == ~T3_E~0); 164219#L954-1 assume !(0 == ~T4_E~0); 164220#L959-1 assume !(0 == ~T5_E~0); 164699#L964-1 assume !(0 == ~T6_E~0); 163950#L969-1 assume !(0 == ~T7_E~0); 163951#L974-1 assume !(0 == ~T8_E~0); 164642#L979-1 assume !(0 == ~T9_E~0); 164643#L984-1 assume !(0 == ~E_M~0); 164113#L989-1 assume !(0 == ~E_1~0); 164114#L994-1 assume !(0 == ~E_2~0); 163998#L999-1 assume !(0 == ~E_3~0); 163999#L1004-1 assume !(0 == ~E_4~0); 163659#L1009-1 assume !(0 == ~E_5~0); 163660#L1014-1 assume !(0 == ~E_6~0); 163994#L1019-1 assume !(0 == ~E_7~0); 164578#L1024-1 assume !(0 == ~E_8~0); 163921#L1029-1 assume !(0 == ~E_9~0); 163922#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164014#L460 assume !(1 == ~m_pc~0); 164818#L460-2 is_master_triggered_~__retres1~0#1 := 0; 164539#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 164540#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 164846#L1167 assume !(0 != activate_threads_~tmp~1#1); 164208#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164209#L479 assume !(1 == ~t1_pc~0); 164375#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 164376#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164776#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 163935#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 163936#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163778#L498 assume !(1 == ~t2_pc~0); 163779#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 164190#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164191#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 164615#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 164528#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164529#L517 assume !(1 == ~t3_pc~0); 164867#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 164868#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 164268#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163967#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 163968#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164589#L536 assume !(1 == ~t4_pc~0); 164257#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 164256#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164690#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 164249#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 164250#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164502#L555 assume 1 == ~t5_pc~0; 164503#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 164579#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163692#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163693#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 163803#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163698#L574 assume !(1 == ~t6_pc~0); 163699#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 164347#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163806#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163807#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 164610#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 164824#L593 assume 1 == ~t7_pc~0; 164825#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 163940#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 164705#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 164872#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 164783#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164106#L612 assume !(1 == ~t8_pc~0); 164107#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 164557#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164396#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164397#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 164352#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 164353#L631 assume 1 == ~t9_pc~0; 164370#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163689#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 163657#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 163658#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 164193#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164590#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 164591#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 164342#L1052-1 assume !(1 == ~T2_E~0); 164343#L1057-1 assume !(1 == ~T3_E~0); 163903#L1062-1 assume !(1 == ~T4_E~0); 163904#L1067-1 assume !(1 == ~T5_E~0); 164212#L1072-1 assume !(1 == ~T6_E~0); 164213#L1077-1 assume !(1 == ~T7_E~0); 163792#L1082-1 assume !(1 == ~T8_E~0); 163793#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 163587#L1092-1 assume !(1 == ~E_M~0); 163588#L1097-1 assume !(1 == ~E_1~0); 163612#L1102-1 assume !(1 == ~E_2~0); 164808#L1107-1 assume !(1 == ~E_3~0); 164345#L1112-1 assume !(1 == ~E_4~0); 164346#L1117-1 assume !(1 == ~E_5~0); 164891#L1122-1 assume !(1 == ~E_6~0); 164892#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 164017#L1132-1 assume !(1 == ~E_8~0); 164018#L1137-1 assume !(1 == ~E_9~0); 163901#L1142-1 assume { :end_inline_reset_delta_events } true; 163902#L1428-2 [2021-12-15 17:20:41,708 INFO L793 eck$LassoCheckResult]: Loop: 163902#L1428-2 assume !false; 188317#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188312#L914 assume !false; 188209#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 188110#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 188095#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 188092#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 188087#L783 assume !(0 != eval_~tmp~0#1); 188088#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 190732#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 190730#L939-3 assume !(0 == ~M_E~0); 190728#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 190726#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 190723#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 190721#L954-3 assume !(0 == ~T4_E~0); 190719#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 190717#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 190715#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 190713#L974-3 assume !(0 == ~T8_E~0); 190710#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 189720#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 189719#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 189718#L994-3 assume !(0 == ~E_2~0); 189717#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 189716#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 189715#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 189714#L1014-3 assume !(0 == ~E_6~0); 189712#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 189710#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 189709#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 189708#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189706#L460-33 assume !(1 == ~m_pc~0); 189705#L460-35 is_master_triggered_~__retres1~0#1 := 0; 189704#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189703#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189701#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 189699#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189697#L479-33 assume !(1 == ~t1_pc~0); 189695#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 189693#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189691#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189689#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 189687#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189685#L498-33 assume 1 == ~t2_pc~0; 189683#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 189684#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189707#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 189674#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 189671#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189669#L517-33 assume !(1 == ~t3_pc~0); 177335#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 189665#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189663#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 189661#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189660#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189658#L536-33 assume 1 == ~t4_pc~0; 189655#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 189653#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189651#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 189649#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 189648#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189647#L555-33 assume 1 == ~t5_pc~0; 189646#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 189644#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189643#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 189642#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 189641#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189640#L574-33 assume 1 == ~t6_pc~0; 189544#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 189542#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 189540#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 189538#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 189535#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 189533#L593-33 assume !(1 == ~t7_pc~0); 189530#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 189528#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 189526#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 189524#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 189521#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 189519#L612-33 assume 1 == ~t8_pc~0; 189516#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 189514#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 189512#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 189511#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 189510#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 189507#L631-33 assume !(1 == ~t9_pc~0); 189504#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 189501#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 189499#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 189497#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 189495#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189493#L1047-3 assume !(1 == ~M_E~0); 164021#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189489#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 189487#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 189485#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 164893#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189482#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189480#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 189477#L1082-3 assume !(1 == ~T8_E~0); 189475#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 189473#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 189471#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189469#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 183183#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 189465#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 189263#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189262#L1122-3 assume !(1 == ~E_6~0); 189261#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 189259#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 189257#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 189209#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 188752#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 188742#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 188739#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 188737#L1447 assume !(0 == start_simulation_~tmp~3#1); 188734#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 188726#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 188716#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 188712#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 188710#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 188665#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 188655#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 188646#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 163902#L1428-2 [2021-12-15 17:20:41,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,709 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2021-12-15 17:20:41,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316426062] [2021-12-15 17:20:41,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,709 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,736 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316426062] [2021-12-15 17:20:41,737 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316426062] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,737 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,737 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,737 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985648776] [2021-12-15 17:20:41,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,738 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:41,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,738 INFO L85 PathProgramCache]: Analyzing trace with hash 130265739, now seen corresponding path program 1 times [2021-12-15 17:20:41,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557718912] [2021-12-15 17:20:41,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,739 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557718912] [2021-12-15 17:20:41,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557718912] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530190536] [2021-12-15 17:20:41,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,763 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:41,763 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:41,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:41,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:41,764 INFO L87 Difference]: Start difference. First operand 27671 states and 39647 transitions. cyclomatic complexity: 11992 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:42,228 INFO L93 Difference]: Finished difference Result 65666 states and 93452 transitions. [2021-12-15 17:20:42,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:42,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65666 states and 93452 transitions. [2021-12-15 17:20:42,466 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 65272 [2021-12-15 17:20:42,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65666 states to 65666 states and 93452 transitions. [2021-12-15 17:20:42,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65666 [2021-12-15 17:20:42,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65666 [2021-12-15 17:20:42,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65666 states and 93452 transitions. [2021-12-15 17:20:42,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:42,851 INFO L681 BuchiCegarLoop]: Abstraction has 65666 states and 93452 transitions. [2021-12-15 17:20:42,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65666 states and 93452 transitions. [2021-12-15 17:20:43,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65666 to 52450. [2021-12-15 17:20:43,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52450 states, 52450 states have (on average 1.4271877979027645) internal successors, (74856), 52449 states have internal predecessors, (74856), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52450 states to 52450 states and 74856 transitions. [2021-12-15 17:20:43,605 INFO L704 BuchiCegarLoop]: Abstraction has 52450 states and 74856 transitions. [2021-12-15 17:20:43,605 INFO L587 BuchiCegarLoop]: Abstraction has 52450 states and 74856 transitions. [2021-12-15 17:20:43,605 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:43,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52450 states and 74856 transitions. [2021-12-15 17:20:43,928 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 52184 [2021-12-15 17:20:43,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,929 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,930 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,930 INFO L791 eck$LassoCheckResult]: Stem: 257832#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 257833#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 257777#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 257778#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 258027#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 257642#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 257643#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 258002#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 257450#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 257451#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 257914#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 257915#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 256938#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 256939#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 257142#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 257543#L939 assume !(0 == ~M_E~0); 257809#L939-2 assume !(0 == ~T1_E~0); 257810#L944-1 assume !(0 == ~T2_E~0); 257571#L949-1 assume !(0 == ~T3_E~0); 257569#L954-1 assume !(0 == ~T4_E~0); 257570#L959-1 assume !(0 == ~T5_E~0); 258051#L964-1 assume !(0 == ~T6_E~0); 257295#L969-1 assume !(0 == ~T7_E~0); 257296#L974-1 assume !(0 == ~T8_E~0); 257983#L979-1 assume !(0 == ~T9_E~0); 257984#L984-1 assume !(0 == ~E_M~0); 257462#L989-1 assume !(0 == ~E_1~0); 257463#L994-1 assume !(0 == ~E_2~0); 257346#L999-1 assume !(0 == ~E_3~0); 257347#L1004-1 assume !(0 == ~E_4~0); 257005#L1009-1 assume !(0 == ~E_5~0); 257006#L1014-1 assume !(0 == ~E_6~0); 257338#L1019-1 assume !(0 == ~E_7~0); 257922#L1024-1 assume !(0 == ~E_8~0); 257266#L1029-1 assume !(0 == ~E_9~0); 257267#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 257360#L460 assume !(1 == ~m_pc~0); 258179#L460-2 is_master_triggered_~__retres1~0#1 := 0; 257882#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 257883#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 258211#L1167 assume !(0 != activate_threads_~tmp~1#1); 257559#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 257560#L479 assume !(1 == ~t1_pc~0); 257721#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 257722#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 258138#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 257278#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 257279#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 257124#L498 assume !(1 == ~t2_pc~0); 257125#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 257541#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 257542#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 257961#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 257871#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 257872#L517 assume !(1 == ~t3_pc~0); 258232#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 258233#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 257615#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 257313#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 257314#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 257931#L536 assume !(1 == ~t4_pc~0); 257605#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 257604#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258041#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 257596#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 257597#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 257840#L555 assume !(1 == ~t5_pc~0); 257841#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 257923#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 257036#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 257037#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 257147#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 257045#L574 assume !(1 == ~t6_pc~0); 257046#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 257697#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 257152#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 257153#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 257954#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 258184#L593 assume 1 == ~t7_pc~0; 258185#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 257285#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 258056#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 258237#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 258147#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 257457#L612 assume !(1 == ~t8_pc~0); 257458#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 257900#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 257743#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 257744#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 257699#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 257700#L631 assume 1 == ~t9_pc~0; 257718#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 257035#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 257003#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 257004#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 257544#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 257934#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 257935#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 293634#L1052-1 assume !(1 == ~T2_E~0); 293632#L1057-1 assume !(1 == ~T3_E~0); 257249#L1062-1 assume !(1 == ~T4_E~0); 257250#L1067-1 assume !(1 == ~T5_E~0); 305210#L1072-1 assume !(1 == ~T6_E~0); 305209#L1077-1 assume !(1 == ~T7_E~0); 305208#L1082-1 assume !(1 == ~T8_E~0); 305207#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 305206#L1092-1 assume !(1 == ~E_M~0); 305205#L1097-1 assume !(1 == ~E_1~0); 305204#L1102-1 assume !(1 == ~E_2~0); 258170#L1107-1 assume !(1 == ~E_3~0); 305203#L1112-1 assume !(1 == ~E_4~0); 305202#L1117-1 assume !(1 == ~E_5~0); 305201#L1122-1 assume !(1 == ~E_6~0); 305200#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 305189#L1132-1 assume !(1 == ~E_8~0); 258171#L1137-1 assume !(1 == ~E_9~0); 258172#L1142-1 assume { :end_inline_reset_delta_events } true; 304753#L1428-2 [2021-12-15 17:20:43,930 INFO L793 eck$LassoCheckResult]: Loop: 304753#L1428-2 assume !false; 296876#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 296871#L914 assume !false; 296869#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 296861#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 296851#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 296849#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 296846#L783 assume !(0 != eval_~tmp~0#1); 296847#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 305082#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 305080#L939-3 assume !(0 == ~M_E~0); 305078#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 305076#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 305074#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 305072#L954-3 assume !(0 == ~T4_E~0); 305070#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 305068#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 305066#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 305064#L974-3 assume !(0 == ~T8_E~0); 305062#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 305060#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 305058#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 305056#L994-3 assume !(0 == ~E_2~0); 305054#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 305052#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 305050#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 305048#L1014-3 assume !(0 == ~E_6~0); 305046#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 305044#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 305042#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 305040#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 305038#L460-33 assume !(1 == ~m_pc~0); 305036#L460-35 is_master_triggered_~__retres1~0#1 := 0; 305034#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 305032#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 305030#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 305028#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 305026#L479-33 assume !(1 == ~t1_pc~0); 305024#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 305022#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 305020#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 305018#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 305016#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 305014#L498-33 assume 1 == ~t2_pc~0; 305012#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 305013#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 305083#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 305001#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 304998#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 304996#L517-33 assume !(1 == ~t3_pc~0); 294808#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 304994#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 304992#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304990#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 304988#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 304986#L536-33 assume 1 == ~t4_pc~0; 304983#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 304980#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 304978#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 304976#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 304974#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 304972#L555-33 assume !(1 == ~t5_pc~0); 266446#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 304970#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304968#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 304966#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 304964#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 304962#L574-33 assume !(1 == ~t6_pc~0); 304960#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 304956#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304954#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 304952#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 304950#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 304948#L593-33 assume !(1 == ~t7_pc~0); 304945#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 304942#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 304940#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 304938#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 304936#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 304934#L612-33 assume !(1 == ~t8_pc~0); 304932#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 304928#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 304926#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 304924#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 304922#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 304920#L631-33 assume !(1 == ~t9_pc~0); 304917#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 304914#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 304912#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 304910#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 304908#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304905#L1047-3 assume !(1 == ~M_E~0); 301051#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 304902#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 304900#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 304898#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 301961#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 304896#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 304894#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 304892#L1082-3 assume !(1 == ~T8_E~0); 304890#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 304888#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 304886#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 304885#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 304883#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 304882#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 304881#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 304880#L1122-3 assume !(1 == ~E_6~0); 304879#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 304878#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 304877#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 304876#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 304861#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 304852#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 304851#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 304848#L1447 assume !(0 == start_simulation_~tmp~3#1); 257659#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 304776#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 304766#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 304764#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 304762#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 304759#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 304757#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 304754#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 304753#L1428-2 [2021-12-15 17:20:43,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,931 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2021-12-15 17:20:43,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437151397] [2021-12-15 17:20:43,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,970 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437151397] [2021-12-15 17:20:43,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1437151397] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,971 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,971 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,971 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618566951] [2021-12-15 17:20:43,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,971 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:43,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,972 INFO L85 PathProgramCache]: Analyzing trace with hash 73984014, now seen corresponding path program 1 times [2021-12-15 17:20:43,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894641203] [2021-12-15 17:20:43,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,973 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894641203] [2021-12-15 17:20:44,002 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894641203] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,002 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,003 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:44,003 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1621240710] [2021-12-15 17:20:44,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,003 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,003 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:44,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:44,004 INFO L87 Difference]: Start difference. First operand 52450 states and 74856 transitions. cyclomatic complexity: 22422 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,641 INFO L93 Difference]: Finished difference Result 123573 states and 175273 transitions. [2021-12-15 17:20:44,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:44,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123573 states and 175273 transitions. [2021-12-15 17:20:45,359 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 122956 [2021-12-15 17:20:45,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123573 states to 123573 states and 175273 transitions. [2021-12-15 17:20:45,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123573 [2021-12-15 17:20:45,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123573 [2021-12-15 17:20:45,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123573 states and 175273 transitions. [2021-12-15 17:20:45,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:45,821 INFO L681 BuchiCegarLoop]: Abstraction has 123573 states and 175273 transitions. [2021-12-15 17:20:45,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123573 states and 175273 transitions. [2021-12-15 17:20:47,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123573 to 99353. [2021-12-15 17:20:47,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99353 states, 99353 states have (on average 1.4222922307328414) internal successors, (141309), 99352 states have internal predecessors, (141309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:47,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99353 states to 99353 states and 141309 transitions. [2021-12-15 17:20:47,553 INFO L704 BuchiCegarLoop]: Abstraction has 99353 states and 141309 transitions. [2021-12-15 17:20:47,553 INFO L587 BuchiCegarLoop]: Abstraction has 99353 states and 141309 transitions. [2021-12-15 17:20:47,553 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:47,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99353 states and 141309 transitions. [2021-12-15 17:20:47,824 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 98992 [2021-12-15 17:20:47,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:47,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:47,827 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,827 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,828 INFO L791 eck$LassoCheckResult]: Stem: 433870#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 433871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 433819#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 433820#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 434075#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 433689#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 433690#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 434046#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 433490#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 433491#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 433954#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 433955#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 432972#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 432973#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 433175#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 433585#L939 assume !(0 == ~M_E~0); 433849#L939-2 assume !(0 == ~T1_E~0); 433850#L944-1 assume !(0 == ~T2_E~0); 433613#L949-1 assume !(0 == ~T3_E~0); 433611#L954-1 assume !(0 == ~T4_E~0); 433612#L959-1 assume !(0 == ~T5_E~0); 434096#L964-1 assume !(0 == ~T6_E~0); 433332#L969-1 assume !(0 == ~T7_E~0); 433333#L974-1 assume !(0 == ~T8_E~0); 434028#L979-1 assume !(0 == ~T9_E~0); 434029#L984-1 assume !(0 == ~E_M~0); 433502#L989-1 assume !(0 == ~E_1~0); 433503#L994-1 assume !(0 == ~E_2~0); 433384#L999-1 assume !(0 == ~E_3~0); 433385#L1004-1 assume !(0 == ~E_4~0); 433040#L1009-1 assume !(0 == ~E_5~0); 433041#L1014-1 assume !(0 == ~E_6~0); 433376#L1019-1 assume !(0 == ~E_7~0); 433963#L1024-1 assume !(0 == ~E_8~0); 433301#L1029-1 assume !(0 == ~E_9~0); 433302#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 433399#L460 assume !(1 == ~m_pc~0); 434213#L460-2 is_master_triggered_~__retres1~0#1 := 0; 433920#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 433921#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 434238#L1167 assume !(0 != activate_threads_~tmp~1#1); 433601#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 433602#L479 assume !(1 == ~t1_pc~0); 433768#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 433769#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 434181#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 433313#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 433314#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 433157#L498 assume !(1 == ~t2_pc~0); 433158#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 433583#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 433584#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 434002#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 433910#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 433911#L517 assume !(1 == ~t3_pc~0); 434254#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 434255#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 433657#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 433350#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 433351#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 433974#L536 assume !(1 == ~t4_pc~0); 433647#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 433646#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434085#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 433638#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 433639#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 433880#L555 assume !(1 == ~t5_pc~0); 433881#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 433964#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 433070#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 433071#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 433180#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 433079#L574 assume !(1 == ~t6_pc~0); 433080#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 433742#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 433185#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 433186#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 433995#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 434219#L593 assume !(1 == ~t7_pc~0); 433320#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 433321#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 434101#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 434262#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 434187#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 433497#L612 assume !(1 == ~t8_pc~0); 433498#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 433941#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 433786#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 433787#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 433744#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 433745#L631 assume 1 == ~t9_pc~0; 433763#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 433069#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 433038#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 433039#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 433586#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 433977#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 433978#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 433737#L1052-1 assume !(1 == ~T2_E~0); 433738#L1057-1 assume !(1 == ~T3_E~0); 433284#L1062-1 assume !(1 == ~T4_E~0); 433285#L1067-1 assume !(1 == ~T5_E~0); 434097#L1072-1 assume !(1 == ~T6_E~0); 472595#L1077-1 assume !(1 == ~T7_E~0); 472592#L1082-1 assume !(1 == ~T8_E~0); 472588#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 472584#L1092-1 assume !(1 == ~E_M~0); 432993#L1097-1 assume !(1 == ~E_1~0); 432994#L1102-1 assume !(1 == ~E_2~0); 433815#L1107-1 assume !(1 == ~E_3~0); 433740#L1112-1 assume !(1 == ~E_4~0); 433741#L1117-1 assume !(1 == ~E_5~0); 433788#L1122-1 assume !(1 == ~E_6~0); 433658#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 433402#L1132-1 assume !(1 == ~E_8~0); 433403#L1137-1 assume !(1 == ~E_9~0); 434210#L1142-1 assume { :end_inline_reset_delta_events } true; 471508#L1428-2 [2021-12-15 17:20:47,828 INFO L793 eck$LassoCheckResult]: Loop: 471508#L1428-2 assume !false; 470007#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 470002#L914 assume !false; 470000#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 469783#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 469773#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 469770#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 469767#L783 assume !(0 != eval_~tmp~0#1); 469768#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 481234#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 481232#L939-3 assume !(0 == ~M_E~0); 481230#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 481228#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 481226#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 481224#L954-3 assume !(0 == ~T4_E~0); 481222#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 481220#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 481218#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 481215#L974-3 assume !(0 == ~T8_E~0); 481212#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 481209#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 481206#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 481204#L994-3 assume !(0 == ~E_2~0); 481202#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 481199#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 481197#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 481195#L1014-3 assume !(0 == ~E_6~0); 481193#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 481191#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 481189#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 481186#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 481184#L460-33 assume !(1 == ~m_pc~0); 481182#L460-35 is_master_triggered_~__retres1~0#1 := 0; 481180#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 481178#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 481176#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 481175#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 481173#L479-33 assume !(1 == ~t1_pc~0); 481171#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 481169#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 481167#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 481165#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 481162#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 481160#L498-33 assume !(1 == ~t2_pc~0); 481158#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 481155#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 481152#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 481149#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 481147#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 481145#L517-33 assume !(1 == ~t3_pc~0); 474747#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 481142#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 481140#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 481138#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 481135#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 481133#L536-33 assume !(1 == ~t4_pc~0); 481131#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 481128#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481126#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 481124#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 481122#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 473725#L555-33 assume !(1 == ~t5_pc~0); 473723#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 473721#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 473720#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 471663#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 471659#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 471654#L574-33 assume !(1 == ~t6_pc~0); 471650#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 471647#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 471645#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 471643#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 471641#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 471639#L593-33 assume !(1 == ~t7_pc~0); 445919#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 471636#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 471633#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 471631#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 471629#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 471627#L612-33 assume !(1 == ~t8_pc~0); 471625#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 471622#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 471621#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 471619#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 471617#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 471615#L631-33 assume 1 == ~t9_pc~0; 471613#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 471610#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 471607#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 471605#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 471603#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 471598#L1047-3 assume !(1 == ~M_E~0); 471596#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 471593#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 471591#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 471589#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 471585#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 471583#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 471581#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 471579#L1082-3 assume !(1 == ~T8_E~0); 471577#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 471575#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 471573#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 471571#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 471567#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 471565#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 471563#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 471561#L1122-3 assume !(1 == ~E_6~0); 471559#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 471557#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 471555#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 471553#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 471547#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 471537#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 471535#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 471534#L1447 assume !(0 == start_simulation_~tmp~3#1); 471532#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 471529#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 471519#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 471517#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 471515#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 471513#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 471511#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 471509#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 471508#L1428-2 [2021-12-15 17:20:47,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,829 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2021-12-15 17:20:47,835 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117003504] [2021-12-15 17:20:47,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,836 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:47,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:47,872 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:47,872 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117003504] [2021-12-15 17:20:47,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117003504] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:47,872 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:47,872 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:47,872 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378334236] [2021-12-15 17:20:47,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:47,873 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:47,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,873 INFO L85 PathProgramCache]: Analyzing trace with hash -639366511, now seen corresponding path program 1 times [2021-12-15 17:20:47,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298741030] [2021-12-15 17:20:47,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:47,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:47,906 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:47,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298741030] [2021-12-15 17:20:47,906 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298741030] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:47,906 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:47,907 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:47,907 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474535380] [2021-12-15 17:20:47,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:47,907 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:47,907 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:47,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:47,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:47,908 INFO L87 Difference]: Start difference. First operand 99353 states and 141309 transitions. cyclomatic complexity: 41972 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:49,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:49,021 INFO L93 Difference]: Finished difference Result 231960 states and 328042 transitions. [2021-12-15 17:20:49,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:49,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 231960 states and 328042 transitions. [2021-12-15 17:20:50,424 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 230896 [2021-12-15 17:20:50,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 231960 states to 231960 states and 328042 transitions. [2021-12-15 17:20:50,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231960 [2021-12-15 17:20:51,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231960 [2021-12-15 17:20:51,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 231960 states and 328042 transitions. [2021-12-15 17:20:51,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:51,540 INFO L681 BuchiCegarLoop]: Abstraction has 231960 states and 328042 transitions. [2021-12-15 17:20:51,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231960 states and 328042 transitions. [2021-12-15 17:20:53,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231960 to 187912. [2021-12-15 17:20:53,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 187912 states, 187912 states have (on average 1.4180786751245265) internal successors, (266474), 187911 states have internal predecessors, (266474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:54,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187912 states to 187912 states and 266474 transitions. [2021-12-15 17:20:54,059 INFO L704 BuchiCegarLoop]: Abstraction has 187912 states and 266474 transitions. [2021-12-15 17:20:54,059 INFO L587 BuchiCegarLoop]: Abstraction has 187912 states and 266474 transitions. [2021-12-15 17:20:54,059 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:20:54,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 187912 states and 266474 transitions. [2021-12-15 17:20:54,494 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 187360 [2021-12-15 17:20:54,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:54,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:54,497 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:54,497 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:54,498 INFO L791 eck$LassoCheckResult]: Stem: 765213#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 765214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 765153#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 765154#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 765450#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 765016#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 765017#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 765418#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 764812#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 764813#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 765309#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 765310#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 764297#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 764298#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 764500#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 764908#L939 assume !(0 == ~M_E~0); 765188#L939-2 assume !(0 == ~T1_E~0); 765189#L944-1 assume !(0 == ~T2_E~0); 764941#L949-1 assume !(0 == ~T3_E~0); 764937#L954-1 assume !(0 == ~T4_E~0); 764938#L959-1 assume !(0 == ~T5_E~0); 765476#L964-1 assume !(0 == ~T6_E~0); 764656#L969-1 assume !(0 == ~T7_E~0); 764657#L974-1 assume !(0 == ~T8_E~0); 765397#L979-1 assume !(0 == ~T9_E~0); 765398#L984-1 assume !(0 == ~E_M~0); 764825#L989-1 assume !(0 == ~E_1~0); 764826#L994-1 assume !(0 == ~E_2~0); 764707#L999-1 assume !(0 == ~E_3~0); 764708#L1004-1 assume !(0 == ~E_4~0); 764365#L1009-1 assume !(0 == ~E_5~0); 764366#L1014-1 assume !(0 == ~E_6~0); 764699#L1019-1 assume !(0 == ~E_7~0); 765318#L1024-1 assume !(0 == ~E_8~0); 764626#L1029-1 assume !(0 == ~E_9~0); 764627#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 764722#L460 assume !(1 == ~m_pc~0); 765612#L460-2 is_master_triggered_~__retres1~0#1 := 0; 765274#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 765275#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 765653#L1167 assume !(0 != activate_threads_~tmp~1#1); 764925#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 764926#L479 assume !(1 == ~t1_pc~0); 765095#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 765096#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 765575#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 764638#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 764639#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 764482#L498 assume !(1 == ~t2_pc~0); 764483#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 764906#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 764907#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 765365#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 765263#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 765264#L517 assume !(1 == ~t3_pc~0); 765682#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 765683#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 764987#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 764673#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 764674#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 765330#L536 assume !(1 == ~t4_pc~0); 764977#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 764976#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 765465#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 764969#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 764970#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 765226#L555 assume !(1 == ~t5_pc~0); 765227#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 765319#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 764395#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 764396#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 764503#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 764404#L574 assume !(1 == ~t6_pc~0); 764405#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 765071#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 764508#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 764509#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 765357#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 765620#L593 assume !(1 == ~t7_pc~0); 764645#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 764646#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 765482#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 765689#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 765584#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 764820#L612 assume !(1 == ~t8_pc~0); 764821#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 765293#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 765118#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 765119#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 765074#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 765075#L631 assume !(1 == ~t9_pc~0); 765152#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 764394#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 764363#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 764364#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 764909#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 765333#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 764334#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 764335#L1052-1 assume !(1 == ~T2_E~0); 764316#L1057-1 assume !(1 == ~T3_E~0); 764317#L1062-1 assume !(1 == ~T4_E~0); 764610#L1067-1 assume !(1 == ~T5_E~0); 764929#L1072-1 assume !(1 == ~T6_E~0); 764930#L1077-1 assume !(1 == ~T7_E~0); 764496#L1082-1 assume !(1 == ~T8_E~0); 764497#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 764289#L1092-1 assume !(1 == ~E_M~0); 764290#L1097-1 assume !(1 == ~E_1~0); 765608#L1102-1 assume !(1 == ~E_2~0); 765147#L1107-1 assume !(1 == ~E_3~0); 765069#L1112-1 assume !(1 == ~E_4~0); 765070#L1117-1 assume !(1 == ~E_5~0); 765120#L1122-1 assume !(1 == ~E_6~0); 764988#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 764725#L1132-1 assume !(1 == ~E_8~0); 764726#L1137-1 assume !(1 == ~E_9~0); 764608#L1142-1 assume { :end_inline_reset_delta_events } true; 764609#L1428-2 [2021-12-15 17:20:54,498 INFO L793 eck$LassoCheckResult]: Loop: 764609#L1428-2 assume !false; 919738#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 919733#L914 assume !false; 919729#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 919624#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 919606#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 919596#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 919586#L783 assume !(0 != eval_~tmp~0#1); 919587#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 943234#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 943232#L939-3 assume !(0 == ~M_E~0); 943230#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 943228#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 943226#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 943224#L954-3 assume !(0 == ~T4_E~0); 943222#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 943220#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 943218#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 943216#L974-3 assume !(0 == ~T8_E~0); 943214#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 943211#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 943209#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 943207#L994-3 assume !(0 == ~E_2~0); 943204#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 943202#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 943200#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 943199#L1014-3 assume !(0 == ~E_6~0); 943196#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 943194#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 943192#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 943190#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 943188#L460-33 assume !(1 == ~m_pc~0); 943186#L460-35 is_master_triggered_~__retres1~0#1 := 0; 943183#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 943181#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 943179#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 943177#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 943175#L479-33 assume !(1 == ~t1_pc~0); 943173#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 943172#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 943169#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 943167#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 943165#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 943163#L498-33 assume 1 == ~t2_pc~0; 943161#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 943162#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 943240#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 943151#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 943149#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 943147#L517-33 assume !(1 == ~t3_pc~0); 912642#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 943145#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 943144#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 943143#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 943142#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 943141#L536-33 assume !(1 == ~t4_pc~0); 943140#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 943137#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 943136#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 943135#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 943134#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 943133#L555-33 assume !(1 == ~t5_pc~0); 902540#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 943131#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 943128#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 943126#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 943124#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 943122#L574-33 assume 1 == ~t6_pc~0; 943119#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 943117#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 943115#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 943113#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 943111#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 943109#L593-33 assume !(1 == ~t7_pc~0); 915099#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 943104#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 943102#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 943100#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 943098#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 943095#L612-33 assume 1 == ~t8_pc~0; 943092#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 943090#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 943089#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 943087#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 943085#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 943083#L631-33 assume !(1 == ~t9_pc~0); 814627#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 943080#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 943077#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 943075#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 943073#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 943071#L1047-3 assume !(1 == ~M_E~0); 872762#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 943068#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 943067#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 943064#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 913436#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 943061#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 943059#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 943057#L1082-3 assume !(1 == ~T8_E~0); 943055#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 943052#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 943050#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 943048#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 872733#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 924442#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 924441#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 924440#L1122-3 assume !(1 == ~E_6~0); 924439#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 924438#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 924437#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 924436#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 924434#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 924425#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 924423#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 764863#L1447 assume !(0 == start_simulation_~tmp~3#1); 764864#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 919795#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 919785#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 919783#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 919781#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 919778#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 919777#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 919764#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 764609#L1428-2 [2021-12-15 17:20:54,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:54,499 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2021-12-15 17:20:54,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:54,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485409875] [2021-12-15 17:20:54,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:54,500 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:54,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:54,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:54,523 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:54,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485409875] [2021-12-15 17:20:54,524 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485409875] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:54,524 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:54,524 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:54,524 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114303584] [2021-12-15 17:20:54,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:54,524 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:54,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:54,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1844823245, now seen corresponding path program 1 times [2021-12-15 17:20:54,525 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:54,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944901580] [2021-12-15 17:20:54,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:54,526 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:54,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:54,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:54,549 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:54,549 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944901580] [2021-12-15 17:20:54,550 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944901580] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:54,550 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:54,550 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:54,550 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464735363] [2021-12-15 17:20:54,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:54,551 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:54,551 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:54,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:54,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:54,551 INFO L87 Difference]: Start difference. First operand 187912 states and 266474 transitions. cyclomatic complexity: 78578 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:55,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:55,583 INFO L93 Difference]: Finished difference Result 235804 states and 334609 transitions. [2021-12-15 17:20:55,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:55,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235804 states and 334609 transitions. [2021-12-15 17:20:56,634 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 235168 [2021-12-15 17:20:57,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235804 states to 235804 states and 334609 transitions. [2021-12-15 17:20:57,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235804 [2021-12-15 17:20:57,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235804 [2021-12-15 17:20:57,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235804 states and 334609 transitions. [2021-12-15 17:20:58,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:58,054 INFO L681 BuchiCegarLoop]: Abstraction has 235804 states and 334609 transitions. [2021-12-15 17:20:58,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235804 states and 334609 transitions. [2021-12-15 17:20:59,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235804 to 100540. [2021-12-15 17:20:59,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100540 states, 100540 states have (on average 1.424507658643326) internal successors, (143220), 100539 states have internal predecessors, (143220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:59,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100540 states to 100540 states and 143220 transitions. [2021-12-15 17:20:59,903 INFO L704 BuchiCegarLoop]: Abstraction has 100540 states and 143220 transitions. [2021-12-15 17:20:59,903 INFO L587 BuchiCegarLoop]: Abstraction has 100540 states and 143220 transitions. [2021-12-15 17:20:59,903 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:20:59,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100540 states and 143220 transitions. [2021-12-15 17:21:00,229 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 100224 [2021-12-15 17:21:00,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:00,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:00,236 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,236 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,237 INFO L791 eck$LassoCheckResult]: Stem: 1188929#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1188930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1188869#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1188870#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1189154#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1188739#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1188740#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1189128#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1188534#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1188535#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1189029#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1189030#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1188020#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1188021#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1188223#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1188631#L939 assume !(0 == ~M_E~0); 1188902#L939-2 assume !(0 == ~T1_E~0); 1188903#L944-1 assume !(0 == ~T2_E~0); 1188666#L949-1 assume !(0 == ~T3_E~0); 1188662#L954-1 assume !(0 == ~T4_E~0); 1188663#L959-1 assume !(0 == ~T5_E~0); 1189176#L964-1 assume !(0 == ~T6_E~0); 1188381#L969-1 assume !(0 == ~T7_E~0); 1188382#L974-1 assume !(0 == ~T8_E~0); 1189113#L979-1 assume !(0 == ~T9_E~0); 1189114#L984-1 assume !(0 == ~E_M~0); 1188546#L989-1 assume !(0 == ~E_1~0); 1188547#L994-1 assume !(0 == ~E_2~0); 1188430#L999-1 assume !(0 == ~E_3~0); 1188431#L1004-1 assume !(0 == ~E_4~0); 1188087#L1009-1 assume !(0 == ~E_5~0); 1188088#L1014-1 assume !(0 == ~E_6~0); 1188426#L1019-1 assume !(0 == ~E_7~0); 1189035#L1024-1 assume !(0 == ~E_8~0); 1188350#L1029-1 assume !(0 == ~E_9~0); 1188351#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1188446#L460 assume !(1 == ~m_pc~0); 1189329#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1188992#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1188993#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1189370#L1167 assume !(0 != activate_threads_~tmp~1#1); 1188651#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1188652#L479 assume !(1 == ~t1_pc~0); 1188815#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1188816#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1189286#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1188364#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1188365#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1188205#L498 assume !(1 == ~t2_pc~0); 1188206#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1188629#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1188630#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1189076#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1188980#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1188981#L517 assume !(1 == ~t3_pc~0); 1189393#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1189394#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1188710#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1188397#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1188398#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1189049#L536 assume !(1 == ~t4_pc~0); 1188700#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1188699#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1189165#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1188692#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1188693#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1188947#L555 assume !(1 == ~t5_pc~0); 1188948#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1189036#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1188119#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1188120#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1188230#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1188126#L574 assume !(1 == ~t6_pc~0); 1188127#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1188790#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1188233#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1188234#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1189071#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1189338#L593 assume !(1 == ~t7_pc~0); 1188369#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1188370#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1189182#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1189402#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1189293#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1188539#L612 assume !(1 == ~t8_pc~0); 1188540#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1189011#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1188836#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1188837#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1188794#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1188795#L631 assume !(1 == ~t9_pc~0); 1188868#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1188116#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1188085#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1188086#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1188632#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1189050#L1047 assume !(1 == ~M_E~0); 1188058#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1188059#L1052-1 assume !(1 == ~T2_E~0); 1188039#L1057-1 assume !(1 == ~T3_E~0); 1188040#L1062-1 assume !(1 == ~T4_E~0); 1188333#L1067-1 assume !(1 == ~T5_E~0); 1188654#L1072-1 assume !(1 == ~T6_E~0); 1188655#L1077-1 assume !(1 == ~T7_E~0); 1188219#L1082-1 assume !(1 == ~T8_E~0); 1188220#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1188016#L1092-1 assume !(1 == ~E_M~0); 1188017#L1097-1 assume !(1 == ~E_1~0); 1188041#L1102-1 assume !(1 == ~E_2~0); 1188863#L1107-1 assume !(1 == ~E_3~0); 1188788#L1112-1 assume !(1 == ~E_4~0); 1188789#L1117-1 assume !(1 == ~E_5~0); 1188838#L1122-1 assume !(1 == ~E_6~0); 1188711#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1188449#L1132-1 assume !(1 == ~E_8~0); 1188450#L1137-1 assume !(1 == ~E_9~0); 1188331#L1142-1 assume { :end_inline_reset_delta_events } true; 1188332#L1428-2 [2021-12-15 17:21:00,237 INFO L793 eck$LassoCheckResult]: Loop: 1188332#L1428-2 assume !false; 1277901#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1277590#L914 assume !false; 1277896#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1277817#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1277803#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1277798#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1277792#L783 assume !(0 != eval_~tmp~0#1); 1277793#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1288518#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1288517#L939-3 assume !(0 == ~M_E~0); 1188245#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1188246#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1188010#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1188011#L954-3 assume !(0 == ~T4_E~0); 1188672#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1188091#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1188092#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1188299#L974-3 assume !(0 == ~T8_E~0); 1188300#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1189388#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1288439#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1288438#L994-3 assume !(0 == ~E_2~0); 1288437#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1288359#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1188172#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1188173#L1014-3 assume !(0 == ~E_6~0); 1188737#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1188738#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1188719#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1188673#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1188674#L460-33 assume !(1 == ~m_pc~0); 1282378#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1282377#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1282376#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1282375#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1282374#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1282372#L479-33 assume !(1 == ~t1_pc~0); 1282371#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1282370#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1282369#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1282367#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1282365#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1282363#L498-33 assume !(1 == ~t2_pc~0); 1282362#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1282354#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1282355#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1282349#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1282346#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1282285#L517-33 assume !(1 == ~t3_pc~0); 1282283#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1282281#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1282278#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1282275#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1282276#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1286957#L536-33 assume !(1 == ~t4_pc~0); 1286954#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1286952#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1286951#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1286950#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1286949#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1280993#L555-33 assume !(1 == ~t5_pc~0); 1280991#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1280989#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1280986#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1280984#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1280982#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1280981#L574-33 assume !(1 == ~t6_pc~0); 1280979#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1280976#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1280974#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1280972#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1280970#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1250766#L593-33 assume !(1 == ~t7_pc~0); 1250764#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1250761#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1250759#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1250757#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1250755#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1250753#L612-33 assume !(1 == ~t8_pc~0); 1250750#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1250748#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1250745#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1250743#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1250741#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1242701#L631-33 assume !(1 == ~t9_pc~0); 1242697#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1242694#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1242690#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1242687#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1242683#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1242679#L1047-3 assume !(1 == ~M_E~0); 1229019#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1242673#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1242669#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1242665#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1242661#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1242657#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1242653#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1242649#L1082-3 assume !(1 == ~T8_E~0); 1242645#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1242641#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1242637#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1242633#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1242629#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1242624#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1242621#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1242620#L1122-3 assume !(1 == ~E_6~0); 1242607#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1242604#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1242601#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1242587#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1242529#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1242508#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1242176#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1229205#L1447 assume !(0 == start_simulation_~tmp~3#1); 1229206#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1277955#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1277941#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1277936#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1277930#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1277925#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1277919#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1277912#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1188332#L1428-2 [2021-12-15 17:21:00,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:00,238 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2021-12-15 17:21:00,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:00,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516913877] [2021-12-15 17:21:00,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:00,238 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:00,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:00,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:00,272 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:00,272 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516913877] [2021-12-15 17:21:00,272 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [516913877] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:00,272 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:00,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:00,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194409025] [2021-12-15 17:21:00,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:00,274 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:00,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:00,275 INFO L85 PathProgramCache]: Analyzing trace with hash -1596294894, now seen corresponding path program 1 times [2021-12-15 17:21:00,276 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:00,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590441415] [2021-12-15 17:21:00,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:00,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:00,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:00,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:00,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:00,308 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590441415] [2021-12-15 17:21:00,308 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1590441415] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:00,308 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:00,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:00,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81698008] [2021-12-15 17:21:00,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:00,309 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:00,310 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:00,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:00,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:00,310 INFO L87 Difference]: Start difference. First operand 100540 states and 143220 transitions. cyclomatic complexity: 42684 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:00,762 INFO L93 Difference]: Finished difference Result 158919 states and 225875 transitions. [2021-12-15 17:21:00,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:00,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158919 states and 225875 transitions. [2021-12-15 17:21:01,978 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 158400 [2021-12-15 17:21:02,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158919 states to 158919 states and 225875 transitions. [2021-12-15 17:21:02,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 158919 [2021-12-15 17:21:02,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 158919 [2021-12-15 17:21:02,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158919 states and 225875 transitions. [2021-12-15 17:21:02,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,449 INFO L681 BuchiCegarLoop]: Abstraction has 158919 states and 225875 transitions. [2021-12-15 17:21:02,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158919 states and 225875 transitions. [2021-12-15 17:21:04,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158919 to 112276. [2021-12-15 17:21:04,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112276 states, 112276 states have (on average 1.4254693790302468) internal successors, (160046), 112275 states have internal predecessors, (160046), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:04,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112276 states to 112276 states and 160046 transitions. [2021-12-15 17:21:04,296 INFO L704 BuchiCegarLoop]: Abstraction has 112276 states and 160046 transitions. [2021-12-15 17:21:04,296 INFO L587 BuchiCegarLoop]: Abstraction has 112276 states and 160046 transitions. [2021-12-15 17:21:04,296 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:21:04,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112276 states and 160046 transitions. [2021-12-15 17:21:04,684 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 111872 [2021-12-15 17:21:04,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:04,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:04,693 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,694 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,694 INFO L791 eck$LassoCheckResult]: Stem: 1448400#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1448401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1448342#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1448343#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1448641#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1448215#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1448216#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1448612#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1448009#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1448010#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1448504#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1448505#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1447491#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1447492#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1447693#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1448104#L939 assume !(0 == ~M_E~0); 1448376#L939-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1448377#L944-1 assume !(0 == ~T2_E~0); 1448635#L949-1 assume !(0 == ~T3_E~0); 1448133#L954-1 assume !(0 == ~T4_E~0); 1448134#L959-1 assume !(0 == ~T5_E~0); 1448666#L964-1 assume !(0 == ~T6_E~0); 1448667#L969-1 assume !(0 == ~T7_E~0); 1448980#L974-1 assume !(0 == ~T8_E~0); 1448599#L979-1 assume !(0 == ~T9_E~0); 1448600#L984-1 assume !(0 == ~E_M~0); 1448022#L989-1 assume !(0 == ~E_1~0); 1448023#L994-1 assume !(0 == ~E_2~0); 1448353#L999-1 assume !(0 == ~E_3~0); 1448560#L1004-1 assume !(0 == ~E_4~0); 1448561#L1009-1 assume !(0 == ~E_5~0); 1447895#L1014-1 assume !(0 == ~E_6~0); 1447896#L1019-1 assume !(0 == ~E_7~0); 1448978#L1024-1 assume !(0 == ~E_8~0); 1447818#L1029-1 assume !(0 == ~E_9~0); 1447819#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1448977#L460 assume !(1 == ~m_pc~0); 1448880#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1448881#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1448888#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1448865#L1167 assume !(0 != activate_threads_~tmp~1#1); 1448866#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1448975#L479 assume !(1 == ~t1_pc~0); 1448974#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1448879#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1448774#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1448775#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1448191#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1448192#L498 assume !(1 == ~t2_pc~0); 1448495#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1448524#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1448719#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1448720#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1448457#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1448458#L517 assume !(1 == ~t3_pc~0); 1448891#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1448892#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1448180#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1448181#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1448527#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1448528#L536 assume !(1 == ~t4_pc~0); 1448170#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1448169#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1448913#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1448914#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1448911#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1448912#L555 assume !(1 == ~t5_pc~0); 1448513#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1448514#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1447591#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1447592#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1447700#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1447598#L574 assume !(1 == ~t6_pc~0); 1447599#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1448921#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1448922#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1448553#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1448554#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1448971#L593 assume !(1 == ~t7_pc~0); 1447838#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1447839#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1448909#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1448910#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1448970#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1448015#L612 assume !(1 == ~t8_pc~0); 1448016#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1448488#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1448310#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1448311#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1448965#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1448964#L631 assume !(1 == ~t9_pc~0); 1448963#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1447587#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1447588#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1448105#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1448106#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1448529#L1047 assume !(1 == ~M_E~0); 1448530#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1447530#L1052-1 assume !(1 == ~T2_E~0); 1447510#L1057-1 assume !(1 == ~T3_E~0); 1447511#L1062-1 assume !(1 == ~T4_E~0); 1447802#L1067-1 assume !(1 == ~T5_E~0); 1448126#L1072-1 assume !(1 == ~T6_E~0); 1448127#L1077-1 assume !(1 == ~T7_E~0); 1447689#L1082-1 assume !(1 == ~T8_E~0); 1447690#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1447487#L1092-1 assume !(1 == ~E_M~0); 1447488#L1097-1 assume !(1 == ~E_1~0); 1447512#L1102-1 assume !(1 == ~E_2~0); 1448336#L1107-1 assume !(1 == ~E_3~0); 1448263#L1112-1 assume !(1 == ~E_4~0); 1448264#L1117-1 assume !(1 == ~E_5~0); 1448312#L1122-1 assume !(1 == ~E_6~0); 1448182#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1447920#L1132-1 assume !(1 == ~E_8~0); 1447921#L1137-1 assume !(1 == ~E_9~0); 1447801#L1142-1 assume { :end_inline_reset_delta_events } true; 1447661#L1428-2 [2021-12-15 17:21:04,695 INFO L793 eck$LassoCheckResult]: Loop: 1447661#L1428-2 assume !false; 1447662#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1447735#L914 assume !false; 1448259#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1448260#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1447498#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1447499#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1448555#L783 assume !(0 != eval_~tmp~0#1); 1448556#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1550331#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1550306#L939-3 assume !(0 == ~M_E~0); 1550295#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1550294#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1550293#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1550292#L954-3 assume !(0 == ~T4_E~0); 1550291#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1550290#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1550289#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1550288#L974-3 assume !(0 == ~T8_E~0); 1550287#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1550286#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1550285#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1550284#L994-3 assume !(0 == ~E_2~0); 1550283#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1550282#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1550281#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1550280#L1014-3 assume !(0 == ~E_6~0); 1550279#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1550278#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1550277#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1550276#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1550275#L460-33 assume !(1 == ~m_pc~0); 1550274#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1550273#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1550272#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1550271#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1550270#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1550269#L479-33 assume !(1 == ~t1_pc~0); 1550268#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1550267#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1550266#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1550265#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1550264#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1550263#L498-33 assume !(1 == ~t2_pc~0); 1550262#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1550260#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1550258#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1550256#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1550254#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1524634#L517-33 assume !(1 == ~t3_pc~0); 1524635#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1524627#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1524628#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1524621#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1524622#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1524614#L536-33 assume 1 == ~t4_pc~0; 1524615#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1524608#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1524609#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1524602#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1524603#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1524597#L555-33 assume !(1 == ~t5_pc~0); 1524596#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1524595#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1524594#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1524593#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1524592#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1524591#L574-33 assume !(1 == ~t6_pc~0); 1524590#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1524588#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1524587#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1524586#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1524585#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1524584#L593-33 assume !(1 == ~t7_pc~0); 1484135#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1524583#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1524582#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1524581#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1524580#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1524579#L612-33 assume !(1 == ~t8_pc~0); 1524578#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1524576#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1524575#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1524574#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1524573#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1524572#L631-33 assume !(1 == ~t9_pc~0); 1499543#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1524571#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1524570#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1524569#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1524568#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1524567#L1047-3 assume !(1 == ~M_E~0); 1507007#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1524564#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1524562#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1524560#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1524558#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1524556#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1524553#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1524552#L1082-3 assume !(1 == ~T8_E~0); 1524549#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1524547#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1524545#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1524543#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1524541#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1524540#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1524539#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1524538#L1122-3 assume !(1 == ~E_6~0); 1524438#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1524437#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1524436#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1524435#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1524348#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1524329#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1524273#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1498318#L1447 assume !(0 == start_simulation_~tmp~3#1); 1448228#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1448595#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1447784#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1448352#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1447899#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1447648#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1447649#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1448128#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1447661#L1428-2 [2021-12-15 17:21:04,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:04,696 INFO L85 PathProgramCache]: Analyzing trace with hash -532012407, now seen corresponding path program 1 times [2021-12-15 17:21:04,696 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:04,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137896846] [2021-12-15 17:21:04,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:04,696 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:04,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:04,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:04,721 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:04,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137896846] [2021-12-15 17:21:04,721 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2137896846] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:04,721 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:04,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:04,721 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052165135] [2021-12-15 17:21:04,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:04,722 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:04,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:04,723 INFO L85 PathProgramCache]: Analyzing trace with hash 1561043537, now seen corresponding path program 1 times [2021-12-15 17:21:04,723 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:04,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555680603] [2021-12-15 17:21:04,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:04,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:04,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:04,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:04,754 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:04,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555680603] [2021-12-15 17:21:04,755 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555680603] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:04,755 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:04,755 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:04,755 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144082084] [2021-12-15 17:21:04,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:04,756 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:04,756 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:04,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:04,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:04,757 INFO L87 Difference]: Start difference. First operand 112276 states and 160046 transitions. cyclomatic complexity: 47774 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:05,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:05,796 INFO L93 Difference]: Finished difference Result 147164 states and 208562 transitions. [2021-12-15 17:21:05,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:05,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147164 states and 208562 transitions. [2021-12-15 17:21:06,412 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 146752 [2021-12-15 17:21:06,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147164 states to 147164 states and 208562 transitions. [2021-12-15 17:21:06,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147164 [2021-12-15 17:21:06,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147164 [2021-12-15 17:21:06,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147164 states and 208562 transitions. [2021-12-15 17:21:06,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:06,983 INFO L681 BuchiCegarLoop]: Abstraction has 147164 states and 208562 transitions. [2021-12-15 17:21:07,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147164 states and 208562 transitions. [2021-12-15 17:21:08,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147164 to 100540. [2021-12-15 17:21:08,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100540 states, 100540 states have (on average 1.4206683906902726) internal successors, (142834), 100539 states have internal predecessors, (142834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:08,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100540 states to 100540 states and 142834 transitions. [2021-12-15 17:21:08,825 INFO L704 BuchiCegarLoop]: Abstraction has 100540 states and 142834 transitions. [2021-12-15 17:21:08,826 INFO L587 BuchiCegarLoop]: Abstraction has 100540 states and 142834 transitions. [2021-12-15 17:21:08,826 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:21:08,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100540 states and 142834 transitions. [2021-12-15 17:21:09,717 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 100224 [2021-12-15 17:21:09,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:09,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:09,723 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:09,723 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:09,723 INFO L791 eck$LassoCheckResult]: Stem: 1707841#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1707842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1707784#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1707785#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1708068#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1707656#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1707657#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1708036#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1707456#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1707457#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1707942#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1707943#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1706943#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1706944#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1707144#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1707549#L939 assume !(0 == ~M_E~0); 1707816#L939-2 assume !(0 == ~T1_E~0); 1707817#L944-1 assume !(0 == ~T2_E~0); 1707579#L949-1 assume !(0 == ~T3_E~0); 1707577#L954-1 assume !(0 == ~T4_E~0); 1707578#L959-1 assume !(0 == ~T5_E~0); 1708091#L964-1 assume !(0 == ~T6_E~0); 1707300#L969-1 assume !(0 == ~T7_E~0); 1707301#L974-1 assume !(0 == ~T8_E~0); 1708022#L979-1 assume !(0 == ~T9_E~0); 1708023#L984-1 assume !(0 == ~E_M~0); 1707468#L989-1 assume !(0 == ~E_1~0); 1707469#L994-1 assume !(0 == ~E_2~0); 1707349#L999-1 assume !(0 == ~E_3~0); 1707350#L1004-1 assume !(0 == ~E_4~0); 1707010#L1009-1 assume !(0 == ~E_5~0); 1707011#L1014-1 assume !(0 == ~E_6~0); 1707345#L1019-1 assume !(0 == ~E_7~0); 1707948#L1024-1 assume !(0 == ~E_8~0); 1707270#L1029-1 assume !(0 == ~E_9~0); 1707271#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1707366#L460 assume !(1 == ~m_pc~0); 1708244#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1707907#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1707908#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1708288#L1167 assume !(0 != activate_threads_~tmp~1#1); 1707566#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1707567#L479 assume !(1 == ~t1_pc~0); 1707732#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1707733#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1708200#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1707284#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1707285#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1707126#L498 assume !(1 == ~t2_pc~0); 1707127#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1707547#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1707548#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1707987#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1707895#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1707896#L517 assume !(1 == ~t3_pc~0); 1708316#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1708317#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1707625#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1707317#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1707318#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1707962#L536 assume !(1 == ~t4_pc~0); 1707615#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1707614#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1708081#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1707607#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1707608#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1707862#L555 assume !(1 == ~t5_pc~0); 1707863#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1707949#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1707042#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1707043#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1707151#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1707049#L574 assume !(1 == ~t6_pc~0); 1707050#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1707707#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1707154#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1707155#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1707982#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1708255#L593 assume !(1 == ~t7_pc~0); 1707288#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1707289#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1708097#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1708324#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1708213#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1707461#L612 assume !(1 == ~t8_pc~0); 1707462#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1707925#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1707751#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1707752#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1707711#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1707712#L631 assume !(1 == ~t9_pc~0); 1707783#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1707039#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1707008#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1707009#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1707550#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1707963#L1047 assume !(1 == ~M_E~0); 1706981#L1047-2 assume !(1 == ~T1_E~0); 1706982#L1052-1 assume !(1 == ~T2_E~0); 1706962#L1057-1 assume !(1 == ~T3_E~0); 1706963#L1062-1 assume !(1 == ~T4_E~0); 1707253#L1067-1 assume !(1 == ~T5_E~0); 1707570#L1072-1 assume !(1 == ~T6_E~0); 1707571#L1077-1 assume !(1 == ~T7_E~0); 1707140#L1082-1 assume !(1 == ~T8_E~0); 1707141#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1706939#L1092-1 assume !(1 == ~E_M~0); 1706940#L1097-1 assume !(1 == ~E_1~0); 1706964#L1102-1 assume !(1 == ~E_2~0); 1707779#L1107-1 assume !(1 == ~E_3~0); 1707705#L1112-1 assume !(1 == ~E_4~0); 1707706#L1117-1 assume !(1 == ~E_5~0); 1707753#L1122-1 assume !(1 == ~E_6~0); 1707626#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1707369#L1132-1 assume !(1 == ~E_8~0); 1707370#L1137-1 assume !(1 == ~E_9~0); 1707251#L1142-1 assume { :end_inline_reset_delta_events } true; 1707252#L1428-2 [2021-12-15 17:21:09,724 INFO L793 eck$LassoCheckResult]: Loop: 1707252#L1428-2 assume !false; 1748107#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1748102#L914 assume !false; 1748100#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1748093#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1748083#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1748080#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1748078#L783 assume !(0 != eval_~tmp~0#1); 1748075#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1748073#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1748071#L939-3 assume !(0 == ~M_E~0); 1748069#L939-5 assume !(0 == ~T1_E~0); 1748067#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1748065#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1748064#L954-3 assume !(0 == ~T4_E~0); 1748063#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1748061#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1748059#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1748058#L974-3 assume !(0 == ~T8_E~0); 1748057#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1748056#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1748054#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1748051#L994-3 assume !(0 == ~E_2~0); 1748049#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1748047#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1748045#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1748043#L1014-3 assume !(0 == ~E_6~0); 1748041#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1748039#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1748037#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1748035#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1748033#L460-33 assume !(1 == ~m_pc~0); 1748031#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1748029#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1748026#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1748024#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1748022#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1748019#L479-33 assume !(1 == ~t1_pc~0); 1748017#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1748015#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1748014#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1748012#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1748010#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1748008#L498-33 assume !(1 == ~t2_pc~0); 1748006#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1748267#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1748265#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1747912#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1747909#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1747907#L517-33 assume !(1 == ~t3_pc~0); 1743903#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1747903#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1747901#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1747899#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1747897#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1747895#L536-33 assume 1 == ~t4_pc~0; 1747807#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1747798#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1747790#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1747781#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1747773#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1747576#L555-33 assume !(1 == ~t5_pc~0); 1743652#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1747562#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1747553#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1747546#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1747538#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1747530#L574-33 assume 1 == ~t6_pc~0; 1747519#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1747513#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1747499#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1747449#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1747392#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1744796#L593-33 assume !(1 == ~t7_pc~0); 1744791#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1744787#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1744783#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1744778#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1744774#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1744769#L612-33 assume !(1 == ~t8_pc~0); 1744762#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1744756#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1744750#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1744743#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1744737#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1744728#L631-33 assume !(1 == ~t9_pc~0); 1744055#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1744559#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1744546#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1744535#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1744525#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1744517#L1047-3 assume !(1 == ~M_E~0); 1731833#L1047-5 assume !(1 == ~T1_E~0); 1744458#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1744443#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1744437#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1744432#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1744426#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1744421#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1744414#L1082-3 assume !(1 == ~T8_E~0); 1744409#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1744400#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1744394#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1744388#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1744382#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1744376#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1744370#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1744364#L1122-3 assume !(1 == ~E_6~0); 1744359#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1744354#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1744349#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1744343#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1744316#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1744302#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1744139#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1732093#L1447 assume !(0 == start_simulation_~tmp~3#1); 1732094#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1748131#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1748121#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1748119#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1748117#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1748115#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1748112#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1748110#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1707252#L1428-2 [2021-12-15 17:21:09,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:09,724 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2021-12-15 17:21:09,725 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:09,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186585759] [2021-12-15 17:21:09,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:09,725 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:09,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:09,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:09,787 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:09,787 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186585759] [2021-12-15 17:21:09,787 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186585759] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:09,787 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:09,787 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:09,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114492639] [2021-12-15 17:21:09,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:09,788 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:09,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:09,788 INFO L85 PathProgramCache]: Analyzing trace with hash -972286512, now seen corresponding path program 1 times [2021-12-15 17:21:09,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:09,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720581601] [2021-12-15 17:21:09,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:09,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:09,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:09,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:09,815 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:09,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720581601] [2021-12-15 17:21:09,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720581601] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:09,815 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:09,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:09,815 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232791439] [2021-12-15 17:21:09,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:09,816 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:09,816 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:09,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:09,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:09,817 INFO L87 Difference]: Start difference. First operand 100540 states and 142834 transitions. cyclomatic complexity: 42298 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:10,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:10,217 INFO L93 Difference]: Finished difference Result 158911 states and 225345 transitions. [2021-12-15 17:21:10,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:10,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158911 states and 225345 transitions. [2021-12-15 17:21:10,848 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 158400 [2021-12-15 17:21:11,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158911 states to 158911 states and 225345 transitions. [2021-12-15 17:21:11,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 158911 [2021-12-15 17:21:11,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 158911 [2021-12-15 17:21:11,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158911 states and 225345 transitions. [2021-12-15 17:21:12,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:12,041 INFO L681 BuchiCegarLoop]: Abstraction has 158911 states and 225345 transitions. [2021-12-15 17:21:12,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158911 states and 225345 transitions. [2021-12-15 17:21:13,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158911 to 112276. [2021-12-15 17:21:13,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112276 states, 112276 states have (on average 1.42203142256582) internal successors, (159660), 112275 states have internal predecessors, (159660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:14,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112276 states to 112276 states and 159660 transitions. [2021-12-15 17:21:14,014 INFO L704 BuchiCegarLoop]: Abstraction has 112276 states and 159660 transitions. [2021-12-15 17:21:14,014 INFO L587 BuchiCegarLoop]: Abstraction has 112276 states and 159660 transitions. [2021-12-15 17:21:14,014 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:21:14,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112276 states and 159660 transitions. [2021-12-15 17:21:14,298 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 111872 [2021-12-15 17:21:14,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:14,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:14,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:14,305 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:14,305 INFO L791 eck$LassoCheckResult]: Stem: 1967314#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1967315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1967255#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1967256#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1967554#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1967125#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1967126#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1967519#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1966918#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1966919#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1967412#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1967413#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1966404#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1966405#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1966605#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1967014#L939 assume !(0 == ~M_E~0); 1967289#L939-2 assume !(0 == ~T1_E~0); 1967290#L944-1 assume !(0 == ~T2_E~0); 1967044#L949-1 assume !(0 == ~T3_E~0); 1967042#L954-1 assume !(0 == ~T4_E~0); 1967043#L959-1 assume !(0 == ~T5_E~0); 1967577#L964-1 assume !(0 == ~T6_E~0); 1966762#L969-1 assume !(0 == ~T7_E~0); 1966763#L974-1 assume !(0 == ~T8_E~0); 1967505#L979-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1967506#L984-1 assume !(0 == ~E_M~0); 1967822#L989-1 assume !(0 == ~E_1~0); 1967885#L994-1 assume !(0 == ~E_2~0); 1967884#L999-1 assume !(0 == ~E_3~0); 1967465#L1004-1 assume !(0 == ~E_4~0); 1967466#L1009-1 assume !(0 == ~E_5~0); 1966808#L1014-1 assume !(0 == ~E_6~0); 1966809#L1019-1 assume !(0 == ~E_7~0); 1967883#L1024-1 assume !(0 == ~E_8~0); 1966730#L1029-1 assume !(0 == ~E_9~0); 1966731#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1966830#L460 assume !(1 == ~m_pc~0); 1967722#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1967375#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1967376#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1967880#L1167 assume !(0 != activate_threads_~tmp~1#1); 1967030#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1967031#L479 assume !(1 == ~t1_pc~0); 1967200#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1967201#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1967877#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1966746#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1966747#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1966587#L498 assume !(1 == ~t2_pc~0); 1966588#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1967431#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1967876#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1967467#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1967468#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1967831#L517 assume !(1 == ~t3_pc~0); 1967832#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1967796#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1967797#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1966779#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1966780#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1967615#L536 assume !(1 == ~t4_pc~0); 1967616#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1967567#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1967568#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1967070#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1967071#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1967330#L555 assume !(1 == ~t5_pc~0); 1967331#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1967500#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1966504#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1966505#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1967874#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1967873#L574 assume !(1 == ~t6_pc~0); 1967175#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1967176#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1967872#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1967458#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1967459#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1967871#L593 assume !(1 == ~t7_pc~0); 1966750#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1966751#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1967810#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1967811#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1967870#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1966924#L612 assume !(1 == ~t8_pc~0); 1966925#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1967395#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1967220#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1967221#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1967865#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1967864#L631 assume !(1 == ~t9_pc~0); 1967863#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1966500#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1966501#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1967015#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1967016#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1967436#L1047 assume !(1 == ~M_E~0); 1967437#L1047-2 assume !(1 == ~T1_E~0); 1967862#L1052-1 assume !(1 == ~T2_E~0); 1967861#L1057-1 assume !(1 == ~T3_E~0); 1966712#L1062-1 assume !(1 == ~T4_E~0); 1966713#L1067-1 assume !(1 == ~T5_E~0); 1967034#L1072-1 assume !(1 == ~T6_E~0); 1967035#L1077-1 assume !(1 == ~T7_E~0); 1967860#L1082-1 assume !(1 == ~T8_E~0); 1967859#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1966400#L1092-1 assume !(1 == ~E_M~0); 1966401#L1097-1 assume !(1 == ~E_1~0); 1966425#L1102-1 assume !(1 == ~E_2~0); 1967250#L1107-1 assume !(1 == ~E_3~0); 1967172#L1112-1 assume !(1 == ~E_4~0); 1967173#L1117-1 assume !(1 == ~E_5~0); 1967222#L1122-1 assume !(1 == ~E_6~0); 1967090#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1966833#L1132-1 assume !(1 == ~E_8~0); 1966834#L1137-1 assume !(1 == ~E_9~0); 1966710#L1142-1 assume { :end_inline_reset_delta_events } true; 1966711#L1428-2 [2021-12-15 17:21:14,306 INFO L793 eck$LassoCheckResult]: Loop: 1966711#L1428-2 assume !false; 2036490#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2036485#L914 assume !false; 2036483#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2036478#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2036468#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2036466#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2036462#L783 assume !(0 != eval_~tmp~0#1); 2036463#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2073930#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2073927#L939-3 assume !(0 == ~M_E~0); 2073924#L939-5 assume !(0 == ~T1_E~0); 2073920#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2073917#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2073914#L954-3 assume !(0 == ~T4_E~0); 2073911#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2073908#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2073858#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2073622#L974-3 assume !(0 == ~T8_E~0); 2073617#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2073615#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2073612#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2073609#L994-3 assume !(0 == ~E_2~0); 2073606#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2073603#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2073600#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2073597#L1014-3 assume !(0 == ~E_6~0); 2073594#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2073568#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2073559#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2073526#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2073523#L460-33 assume !(1 == ~m_pc~0); 2073521#L460-35 is_master_triggered_~__retres1~0#1 := 0; 2073519#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2073517#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2073515#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2073512#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2073509#L479-33 assume !(1 == ~t1_pc~0); 2073507#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2073505#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2073485#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2073481#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 2073476#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2073473#L498-33 assume !(1 == ~t2_pc~0); 2073469#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2073464#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2073458#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2073453#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 2073448#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2065469#L517-33 assume !(1 == ~t3_pc~0); 2065470#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2065463#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2065464#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2065457#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2065458#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2065449#L536-33 assume !(1 == ~t4_pc~0); 2065451#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2065442#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2065443#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2065436#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2065437#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2065430#L555-33 assume !(1 == ~t5_pc~0); 2063185#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2065425#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2065426#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2065419#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2065420#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2065411#L574-33 assume !(1 == ~t6_pc~0); 2065413#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2065404#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2065405#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2065398#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2065399#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2058092#L593-33 assume !(1 == ~t7_pc~0); 2058084#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2058075#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2058065#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2058056#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2058045#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2058033#L612-33 assume !(1 == ~t8_pc~0); 2058021#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2058009#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2057998#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2057991#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2057987#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2057818#L631-33 assume !(1 == ~t9_pc~0); 2057817#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2057814#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2057812#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2057810#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2057808#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2057806#L1047-3 assume !(1 == ~M_E~0); 2015643#L1047-5 assume !(1 == ~T1_E~0); 2057799#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2057795#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2057789#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2057784#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2057778#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2057772#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2057765#L1082-3 assume !(1 == ~T8_E~0); 2057758#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2057404#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2057400#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2057396#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2057391#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2057353#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2057253#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2057185#L1122-3 assume !(1 == ~E_6~0); 2057045#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2057028#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2057025#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2057021#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2057010#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2056996#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2056990#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2014648#L1447 assume !(0 == start_simulation_~tmp~3#1); 2014649#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2036514#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2036504#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2036502#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2036500#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2036498#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2036495#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2036493#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1966711#L1428-2 [2021-12-15 17:21:14,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:14,306 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2021-12-15 17:21:14,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:14,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452706319] [2021-12-15 17:21:14,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:14,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:14,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:14,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:14,331 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:14,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452706319] [2021-12-15 17:21:14,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452706319] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:14,332 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:14,332 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:14,332 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951126648] [2021-12-15 17:21:14,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:14,332 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:14,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:14,333 INFO L85 PathProgramCache]: Analyzing trace with hash 405609682, now seen corresponding path program 1 times [2021-12-15 17:21:14,333 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:14,333 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97732331] [2021-12-15 17:21:14,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:14,333 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:14,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:14,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:14,360 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:14,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97732331] [2021-12-15 17:21:14,360 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97732331] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:14,361 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:14,361 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:14,361 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099377277] [2021-12-15 17:21:14,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:14,361 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:14,361 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:14,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:14,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:14,362 INFO L87 Difference]: Start difference. First operand 112276 states and 159660 transitions. cyclomatic complexity: 47388 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:14,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:14,783 INFO L93 Difference]: Finished difference Result 147164 states and 208048 transitions. [2021-12-15 17:21:14,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:14,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147164 states and 208048 transitions. [2021-12-15 17:21:15,362 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 146752 [2021-12-15 17:21:16,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147164 states to 147164 states and 208048 transitions. [2021-12-15 17:21:16,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147164 [2021-12-15 17:21:16,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147164 [2021-12-15 17:21:16,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147164 states and 208048 transitions. [2021-12-15 17:21:16,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:16,475 INFO L681 BuchiCegarLoop]: Abstraction has 147164 states and 208048 transitions. [2021-12-15 17:21:16,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147164 states and 208048 transitions. [2021-12-15 17:21:17,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147164 to 100540. [2021-12-15 17:21:17,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100540 states, 100540 states have (on average 1.416829122737219) internal successors, (142448), 100539 states have internal predecessors, (142448), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:17,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100540 states to 100540 states and 142448 transitions. [2021-12-15 17:21:17,645 INFO L704 BuchiCegarLoop]: Abstraction has 100540 states and 142448 transitions. [2021-12-15 17:21:17,645 INFO L587 BuchiCegarLoop]: Abstraction has 100540 states and 142448 transitions. [2021-12-15 17:21:17,645 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-15 17:21:17,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100540 states and 142448 transitions.