./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:32,741 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:32,743 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:32,781 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:32,781 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:32,782 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:32,783 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:32,785 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:32,786 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:32,787 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:32,788 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:32,789 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:32,789 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:32,790 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:32,791 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:32,792 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:32,793 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:32,794 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:32,796 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:32,797 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:32,799 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:32,800 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:32,801 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:32,802 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:32,804 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:32,805 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:32,805 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:32,806 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:32,806 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:32,807 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:32,807 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:32,808 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:32,808 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:32,809 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:32,810 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:32,810 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:32,811 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:32,811 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:32,811 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:32,812 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:32,812 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:32,813 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:32,831 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:32,832 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:32,832 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:32,832 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:32,833 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:32,834 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:32,834 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:32,834 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:32,834 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:32,835 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:32,835 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:32,835 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:32,835 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:32,835 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:32,836 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:32,836 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:32,836 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:32,836 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:32,837 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:32,837 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:32,837 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:32,837 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:32,838 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:32,838 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:32,838 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:32,838 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:32,838 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:32,839 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:32,839 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:32,839 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:32,839 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:32,840 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:32,841 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:32,841 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2021-12-15 17:20:33,024 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:33,048 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:33,052 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:33,053 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:33,054 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:33,055 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2021-12-15 17:20:33,120 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c970de65d/0273e56b844744669b613e6d06b103df/FLAGf61baca2d [2021-12-15 17:20:33,594 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:33,595 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2021-12-15 17:20:33,613 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c970de65d/0273e56b844744669b613e6d06b103df/FLAGf61baca2d [2021-12-15 17:20:33,930 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c970de65d/0273e56b844744669b613e6d06b103df [2021-12-15 17:20:33,932 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:33,933 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:33,935 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:33,935 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:33,939 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:33,940 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,941 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@15494d35 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:33, skipping insertion in model container [2021-12-15 17:20:33,941 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:33" (1/1) ... [2021-12-15 17:20:33,947 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:33,987 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:34,132 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2021-12-15 17:20:34,226 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:34,236 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:34,247 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2021-12-15 17:20:34,318 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:34,337 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:34,338 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34 WrapperNode [2021-12-15 17:20:34,338 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:34,339 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:34,340 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:34,340 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:34,349 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,358 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,454 INFO L137 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3198 [2021-12-15 17:20:34,454 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:34,455 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:34,456 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:34,456 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:34,463 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,464 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,482 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,484 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,534 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,581 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,590 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,606 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:34,607 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:34,608 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:34,608 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:34,609 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (1/1) ... [2021-12-15 17:20:34,616 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:34,628 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:34,649 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:34,659 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:34,693 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:34,694 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:34,694 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:34,694 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:34,783 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:34,785 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:36,295 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:36,315 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:36,315 INFO L301 CfgBuilder]: Removed 13 assume(true) statements. [2021-12-15 17:20:36,318 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:36 BoogieIcfgContainer [2021-12-15 17:20:36,319 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:36,320 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:36,320 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:36,323 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:36,324 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:36,324 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:33" (1/3) ... [2021-12-15 17:20:36,326 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@375c7c87 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:36, skipping insertion in model container [2021-12-15 17:20:36,326 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:36,326 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:34" (2/3) ... [2021-12-15 17:20:36,326 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@375c7c87 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:36, skipping insertion in model container [2021-12-15 17:20:36,326 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:36,327 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:36" (3/3) ... [2021-12-15 17:20:36,328 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2021-12-15 17:20:36,375 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:36,375 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:36,375 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:36,375 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:36,375 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:36,376 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:36,376 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:36,376 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:36,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2021-12-15 17:20:36,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,539 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,540 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,540 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:36,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:36,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2021-12-15 17:20:36,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:36,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:36,567 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,568 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:36,581 INFO L791 eck$LassoCheckResult]: Stem: 667#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1260#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 970#L1528true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24#L724true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1154#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1022#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 933#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 999#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1316#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 174#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 232#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 833#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 339#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 175#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58#L1036true assume !(0 == ~M_E~0); 1028#L1036-2true assume !(0 == ~T1_E~0); 609#L1041-1true assume !(0 == ~T2_E~0); 971#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 197#L1051-1true assume !(0 == ~T4_E~0); 748#L1056-1true assume !(0 == ~T5_E~0); 797#L1061-1true assume !(0 == ~T6_E~0); 143#L1066-1true assume !(0 == ~T7_E~0); 1149#L1071-1true assume !(0 == ~T8_E~0); 729#L1076-1true assume !(0 == ~T9_E~0); 91#L1081-1true assume !(0 == ~T10_E~0); 309#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1169#L1091-1true assume !(0 == ~E_1~0); 1030#L1096-1true assume !(0 == ~E_2~0); 1265#L1101-1true assume !(0 == ~E_3~0); 350#L1106-1true assume !(0 == ~E_4~0); 548#L1111-1true assume !(0 == ~E_5~0); 459#L1116-1true assume !(0 == ~E_6~0); 1087#L1121-1true assume !(0 == ~E_7~0); 345#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 530#L1131-1true assume !(0 == ~E_9~0); 619#L1136-1true assume !(0 == ~E_10~0); 899#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 785#L514true assume 1 == ~m_pc~0; 738#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 356#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 302#L526true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1101#L1285true assume !(0 != activate_threads_~tmp~1#1); 1187#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151#L533true assume !(1 == ~t1_pc~0); 1042#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 499#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 380#L545true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 911#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 643#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902#L552true assume 1 == ~t2_pc~0; 276#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 934#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 714#L564true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 976#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 365#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 511#L571true assume 1 == ~t3_pc~0; 496#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 684#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111#L583true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 653#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 462#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50#L590true assume !(1 == ~t4_pc~0); 510#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1286#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 709#L602true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1112#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 668#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 460#L609true assume 1 == ~t5_pc~0; 1276#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1098#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69#L621true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1376#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 455#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1275#L628true assume !(1 == ~t6_pc~0); 531#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1254#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1061#L640true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1178#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 707#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 842#L647true assume 1 == ~t7_pc~0; 351#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 888#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 556#L659true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 352#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1248#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1218#L666true assume !(1 == ~t8_pc~0); 783#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 364#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 815#L678true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 477#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 307#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1131#L685true assume 1 == ~t9_pc~0; 1296#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 913#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 893#L697true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 323#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1008#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 587#L704true assume !(1 == ~t10_pc~0); 1083#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1036#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 746#L716true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 202#L1365-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 696#L1154true assume !(1 == ~M_E~0); 1175#L1154-2true assume !(1 == ~T1_E~0); 186#L1159-1true assume !(1 == ~T2_E~0); 1306#L1164-1true assume !(1 == ~T3_E~0); 475#L1169-1true assume !(1 == ~T4_E~0); 383#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 257#L1179-1true assume !(1 == ~T6_E~0); 179#L1184-1true assume !(1 == ~T7_E~0); 221#L1189-1true assume !(1 == ~T8_E~0); 299#L1194-1true assume !(1 == ~T9_E~0); 1356#L1199-1true assume !(1 == ~T10_E~0); 268#L1204-1true assume !(1 == ~E_M~0); 1212#L1209-1true assume !(1 == ~E_1~0); 663#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1304#L1219-1true assume !(1 == ~E_3~0); 1183#L1224-1true assume !(1 == ~E_4~0); 493#L1229-1true assume !(1 == ~E_5~0); 122#L1234-1true assume !(1 == ~E_6~0); 773#L1239-1true assume !(1 == ~E_7~0); 149#L1244-1true assume !(1 == ~E_8~0); 820#L1249-1true assume !(1 == ~E_9~0); 735#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 74#L1259-1true assume { :end_inline_reset_delta_events } true; 1164#L1565-2true [2021-12-15 17:20:36,591 INFO L793 eck$LassoCheckResult]: Loop: 1164#L1565-2true assume !false; 672#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279#L1011true assume false; 1307#L1026true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 581#L724-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 743#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1062#L1036-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1302#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 827#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1184#L1051-3true assume !(0 == ~T4_E~0); 744#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 195#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 196#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1321#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1065#L1076-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 71#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1238#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 96#L1091-3true assume !(0 == ~E_1~0); 1141#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1002#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1060#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1118#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 986#L1116-3true assume 0 == ~E_6~0;~E_6~0 := 1; 595#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 936#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 853#L1131-3true assume !(0 == ~E_9~0); 1297#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1272#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 599#L514-36true assume !(1 == ~m_pc~0); 394#L514-38true is_master_triggered_~__retres1~0#1 := 0; 291#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1012#L526-12true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 641#L1285-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 226#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L533-36true assume 1 == ~t1_pc~0; 466#L534-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 958#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 737#L545-12true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 683#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 509#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1366#L552-36true assume 1 == ~t2_pc~0; 223#L553-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 547#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131#L564-12true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1173#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 208#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 830#L571-36true assume 1 == ~t3_pc~0; 452#L572-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 258#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 334#L583-12true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 826#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 873#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242#L590-36true assume !(1 == ~t4_pc~0); 879#L590-38true is_transmit4_triggered_~__retres1~4#1 := 0; 1015#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 355#L602-12true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1311#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 791#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1053#L609-36true assume !(1 == ~t5_pc~0); 1327#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 513#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 377#L621-12true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 859#L1325-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 570#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432#L628-36true assume 1 == ~t6_pc~0; 336#L629-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1132#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 673#L640-12true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 749#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 601#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1093#L647-36true assume 1 == ~t7_pc~0; 543#L648-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104#L659-12true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93#L1341-36true assume !(0 != activate_threads_~tmp___6~0#1); 698#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 768#L666-36true assume 1 == ~t8_pc~0; 185#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1193#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 994#L678-12true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1210#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 275#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 583#L685-36true assume !(1 == ~t9_pc~0); 136#L685-38true is_transmit9_triggered_~__retres1~9#1 := 0; 874#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 443#L697-12true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1264#L1357-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 362#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 369#L704-36true assume !(1 == ~t10_pc~0); 271#L704-38true is_transmit10_triggered_~__retres1~10#1 := 0; 1146#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 644#L716-12true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 724#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 145#L1365-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1349#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 969#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 758#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1323#L1164-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1090#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 317#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1180#L1179-3true assume !(1 == ~T6_E~0); 916#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 85#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 921#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 282#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1360#L1204-3true assume 1 == ~E_M~0;~E_M~0 := 2; 489#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 20#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1013#L1219-3true assume !(1 == ~E_3~0); 652#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1370#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 671#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 150#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 526#L1244-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1069#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 987#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 655#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 752#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1282#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 503#L852-1true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 607#L1584true assume !(0 == start_simulation_~tmp~3#1); 636#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 156#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 935#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 234#L852-2true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 348#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 977#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 326#L1547true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1158#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1164#L1565-2true [2021-12-15 17:20:36,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,597 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2021-12-15 17:20:36,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245253118] [2021-12-15 17:20:36,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,607 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,791 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,792 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245253118] [2021-12-15 17:20:36,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245253118] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,793 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,793 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:36,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410876238] [2021-12-15 17:20:36,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,799 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:36,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:36,800 INFO L85 PathProgramCache]: Analyzing trace with hash 1515191513, now seen corresponding path program 1 times [2021-12-15 17:20:36,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:36,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065301907] [2021-12-15 17:20:36,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:36,801 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:36,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:36,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:36,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:36,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065301907] [2021-12-15 17:20:36,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065301907] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:36,870 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:36,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:36,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809561410] [2021-12-15 17:20:36,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:36,873 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:36,874 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:36,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:36,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:36,909 INFO L87 Difference]: Start difference. First operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:37,011 INFO L93 Difference]: Finished difference Result 1372 states and 2038 transitions. [2021-12-15 17:20:37,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:37,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2038 transitions. [2021-12-15 17:20:37,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:37,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1366 states and 2032 transitions. [2021-12-15 17:20:37,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:37,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:37,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2032 transitions. [2021-12-15 17:20:37,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:37,066 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2021-12-15 17:20:37,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2032 transitions. [2021-12-15 17:20:37,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:37,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2032 transitions. [2021-12-15 17:20:37,150 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2021-12-15 17:20:37,151 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2021-12-15 17:20:37,151 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:37,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2032 transitions. [2021-12-15 17:20:37,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:37,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:37,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:37,177 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,178 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,178 INFO L791 eck$LassoCheckResult]: Stem: 3813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4021#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2806#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2807#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4046#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4004#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4005#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4035#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3115#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3116#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3219#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3464#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3395#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3117#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2777#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2778#L1036 assume !(0 == ~M_E~0); 2876#L1036-2 assume !(0 == ~T1_E~0); 3752#L1041-1 assume !(0 == ~T2_E~0); 3753#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3151#L1051-1 assume !(0 == ~T4_E~0); 3152#L1056-1 assume !(0 == ~T5_E~0); 3890#L1061-1 assume !(0 == ~T6_E~0); 3049#L1066-1 assume !(0 == ~T7_E~0); 3050#L1071-1 assume !(0 == ~T8_E~0); 3873#L1076-1 assume !(0 == ~T9_E~0); 2944#L1081-1 assume !(0 == ~T10_E~0); 2945#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3348#L1091-1 assume !(0 == ~E_1~0); 4050#L1096-1 assume !(0 == ~E_2~0); 4051#L1101-1 assume !(0 == ~E_3~0); 3409#L1106-1 assume !(0 == ~E_4~0); 3410#L1111-1 assume !(0 == ~E_5~0); 3566#L1116-1 assume !(0 == ~E_6~0); 3567#L1121-1 assume !(0 == ~E_7~0); 3402#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3403#L1131-1 assume !(0 == ~E_9~0); 3653#L1136-1 assume !(0 == ~E_10~0); 3760#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3917#L514 assume 1 == ~m_pc~0; 3880#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3423#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3342#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3343#L1285 assume !(0 != activate_threads_~tmp~1#1); 4086#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3068#L533 assume !(1 == ~t1_pc~0); 3069#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3582#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3455#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3456#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3782#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3783#L552 assume 1 == ~t2_pc~0; 3294#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3295#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3861#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3862#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3437#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3438#L571 assume 1 == ~t3_pc~0; 3614#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3615#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2984#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2985#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3572#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2860#L590 assume !(1 == ~t4_pc~0); 2861#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3625#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3858#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3859#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3815#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3568#L609 assume 1 == ~t5_pc~0; 3569#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4083#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2895#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2896#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3563#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3564#L628 assume !(1 == ~t6_pc~0); 3497#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3496#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4068#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4069#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3853#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3854#L647 assume 1 == ~t7_pc~0; 3411#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3412#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3690#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3418#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3419#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4115#L666 assume !(1 == ~t8_pc~0); 3198#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3199#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3433#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3590#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3345#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3346#L685 assume 1 == ~t9_pc~0; 4092#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3989#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3981#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3371#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3372#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3724#L704 assume !(1 == ~t10_pc~0); 3363#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3362#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3888#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2916#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2917#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3162#L1154 assume !(1 == ~M_E~0); 3841#L1154-2 assume !(1 == ~T1_E~0); 3134#L1159-1 assume !(1 == ~T2_E~0); 3135#L1164-1 assume !(1 == ~T3_E~0); 3587#L1169-1 assume !(1 == ~T4_E~0); 3459#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3266#L1179-1 assume !(1 == ~T6_E~0); 3120#L1184-1 assume !(1 == ~T7_E~0); 3121#L1189-1 assume !(1 == ~T8_E~0); 3196#L1194-1 assume !(1 == ~T9_E~0); 3335#L1199-1 assume !(1 == ~T10_E~0); 3281#L1204-1 assume !(1 == ~E_M~0); 3282#L1209-1 assume !(1 == ~E_1~0); 3808#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3809#L1219-1 assume !(1 == ~E_3~0); 4108#L1224-1 assume !(1 == ~E_4~0); 3607#L1229-1 assume !(1 == ~E_5~0); 3005#L1234-1 assume !(1 == ~E_6~0); 3006#L1239-1 assume !(1 == ~E_7~0); 3064#L1244-1 assume !(1 == ~E_8~0); 3065#L1249-1 assume !(1 == ~E_9~0); 3878#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2907#L1259-1 assume { :end_inline_reset_delta_events } true; 2908#L1565-2 [2021-12-15 17:20:37,178 INFO L793 eck$LassoCheckResult]: Loop: 2908#L1565-2 assume !false; 3816#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3300#L1011 assume !false; 3301#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3350#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3104#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3969#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3131#L866 assume !(0 != eval_~tmp~0#1); 3133#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3719#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3720#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3884#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4070#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3943#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3944#L1051-3 assume !(0 == ~T4_E~0); 3885#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3148#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3149#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3150#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4071#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2899#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2900#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2958#L1091-3 assume !(0 == ~E_1~0); 2959#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4037#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4038#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4067#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4028#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3735#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3736#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3959#L1131-3 assume !(0 == ~E_9~0); 3960#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4119#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3738#L514-36 assume !(1 == ~m_pc~0); 3475#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3325#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3326#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3781#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3207#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3208#L533-36 assume 1 == ~t1_pc~0; 3483#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3579#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3879#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3827#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3630#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3631#L552-36 assume 1 == ~t2_pc~0; 3200#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3202#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3021#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3022#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3174#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3175#L571-36 assume 1 == ~t3_pc~0; 3559#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3264#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3265#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3386#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3942#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3232#L590-36 assume !(1 == ~t4_pc~0); 3233#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3842#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3420#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3421#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3921#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3922#L609-36 assume 1 == ~t5_pc~0; 3797#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3632#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3450#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3451#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3704#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3530#L628-36 assume 1 == ~t6_pc~0; 3387#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3388#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3817#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3818#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3742#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3743#L647-36 assume 1 == ~t7_pc~0; 3671#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2928#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2929#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2948#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 2949#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3843#L666-36 assume 1 == ~t8_pc~0; 3128#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3129#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4032#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4033#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3291#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3292#L685-36 assume 1 == ~t9_pc~0; 3718#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3033#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3548#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3549#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3430#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3431#L704-36 assume !(1 == ~t10_pc~0); 3025#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3024#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3784#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3785#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3053#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3054#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4020#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3898#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3899#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4079#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3359#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3360#L1179-3 assume !(1 == ~T6_E~0); 3991#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2930#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2931#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3304#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3305#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3603#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2793#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2794#L1219-3 assume !(1 == ~E_3~0); 3792#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3793#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3812#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3066#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3067#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3646#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4029#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3795#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3796#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2874#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3619#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3620#L1584 assume !(0 == start_simulation_~tmp~3#1); 3750#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3080#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2775#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3222#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3223#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3406#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3374#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3375#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2908#L1565-2 [2021-12-15 17:20:37,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,181 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2021-12-15 17:20:37,181 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294055367] [2021-12-15 17:20:37,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,182 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,270 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,272 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294055367] [2021-12-15 17:20:37,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294055367] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,273 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,274 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,274 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455162606] [2021-12-15 17:20:37,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,277 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,282 INFO L85 PathProgramCache]: Analyzing trace with hash 2100759252, now seen corresponding path program 1 times [2021-12-15 17:20:37,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806224877] [2021-12-15 17:20:37,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,284 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,464 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,465 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806224877] [2021-12-15 17:20:37,465 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806224877] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,465 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157264521] [2021-12-15 17:20:37,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,467 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:37,468 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:37,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:37,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:37,471 INFO L87 Difference]: Start difference. First operand 1366 states and 2032 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:37,507 INFO L93 Difference]: Finished difference Result 1366 states and 2031 transitions. [2021-12-15 17:20:37,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:37,509 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2031 transitions. [2021-12-15 17:20:37,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:37,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2031 transitions. [2021-12-15 17:20:37,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:37,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:37,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2031 transitions. [2021-12-15 17:20:37,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:37,535 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2021-12-15 17:20:37,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2031 transitions. [2021-12-15 17:20:37,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:37,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2031 transitions. [2021-12-15 17:20:37,563 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2021-12-15 17:20:37,563 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2021-12-15 17:20:37,563 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:37,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2031 transitions. [2021-12-15 17:20:37,570 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:37,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:37,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:37,576 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,576 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,578 INFO L791 eck$LassoCheckResult]: Stem: 6551#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6760#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5543#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5544#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6784#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6743#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6744#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6774#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5852#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5853#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5958#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6203#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6134#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5854#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5516#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5517#L1036 assume !(0 == ~M_E~0); 5615#L1036-2 assume !(0 == ~T1_E~0); 6491#L1041-1 assume !(0 == ~T2_E~0); 6492#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5890#L1051-1 assume !(0 == ~T4_E~0); 5891#L1056-1 assume !(0 == ~T5_E~0); 6629#L1061-1 assume !(0 == ~T6_E~0); 5788#L1066-1 assume !(0 == ~T7_E~0); 5789#L1071-1 assume !(0 == ~T8_E~0); 6612#L1076-1 assume !(0 == ~T9_E~0); 5683#L1081-1 assume !(0 == ~T10_E~0); 5684#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6087#L1091-1 assume !(0 == ~E_1~0); 6788#L1096-1 assume !(0 == ~E_2~0); 6789#L1101-1 assume !(0 == ~E_3~0); 6148#L1106-1 assume !(0 == ~E_4~0); 6149#L1111-1 assume !(0 == ~E_5~0); 6305#L1116-1 assume !(0 == ~E_6~0); 6306#L1121-1 assume !(0 == ~E_7~0); 6141#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6142#L1131-1 assume !(0 == ~E_9~0); 6392#L1136-1 assume !(0 == ~E_10~0); 6499#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6656#L514 assume 1 == ~m_pc~0; 6619#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6161#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6078#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6079#L1285 assume !(0 != activate_threads_~tmp~1#1); 6824#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5807#L533 assume !(1 == ~t1_pc~0); 5808#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6321#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6194#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6195#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6521#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6522#L552 assume 1 == ~t2_pc~0; 6032#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6033#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6600#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6601#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6173#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6174#L571 assume 1 == ~t3_pc~0; 6351#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6352#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5721#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5722#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6311#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5597#L590 assume !(1 == ~t4_pc~0); 5598#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6364#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6596#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6597#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6553#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6307#L609 assume 1 == ~t5_pc~0; 6308#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6822#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5634#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5635#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6302#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6303#L628 assume !(1 == ~t6_pc~0); 6236#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6235#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6807#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6808#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6592#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6593#L647 assume 1 == ~t7_pc~0; 6150#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6151#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6427#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6153#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6154#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6854#L666 assume !(1 == ~t8_pc~0); 5937#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5938#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6172#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6328#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6084#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6085#L685 assume 1 == ~t9_pc~0; 6831#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6728#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6720#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6110#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6111#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6463#L704 assume !(1 == ~t10_pc~0); 6102#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6101#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6627#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5653#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5654#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5901#L1154 assume !(1 == ~M_E~0); 6580#L1154-2 assume !(1 == ~T1_E~0); 5873#L1159-1 assume !(1 == ~T2_E~0); 5874#L1164-1 assume !(1 == ~T3_E~0); 6326#L1169-1 assume !(1 == ~T4_E~0); 6198#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6003#L1179-1 assume !(1 == ~T6_E~0); 5859#L1184-1 assume !(1 == ~T7_E~0); 5860#L1189-1 assume !(1 == ~T8_E~0); 5935#L1194-1 assume !(1 == ~T9_E~0); 6074#L1199-1 assume !(1 == ~T10_E~0); 6018#L1204-1 assume !(1 == ~E_M~0); 6019#L1209-1 assume !(1 == ~E_1~0); 6545#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6546#L1219-1 assume !(1 == ~E_3~0); 6847#L1224-1 assume !(1 == ~E_4~0); 6346#L1229-1 assume !(1 == ~E_5~0); 5744#L1234-1 assume !(1 == ~E_6~0); 5745#L1239-1 assume !(1 == ~E_7~0); 5803#L1244-1 assume !(1 == ~E_8~0); 5804#L1249-1 assume !(1 == ~E_9~0); 6617#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5646#L1259-1 assume { :end_inline_reset_delta_events } true; 5647#L1565-2 [2021-12-15 17:20:37,578 INFO L793 eck$LassoCheckResult]: Loop: 5647#L1565-2 assume !false; 6555#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6039#L1011 assume !false; 6040#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6089#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5843#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6708#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5867#L866 assume !(0 != eval_~tmp~0#1); 5869#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6456#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6457#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6623#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6809#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6682#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6683#L1051-3 assume !(0 == ~T4_E~0); 6624#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5887#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5888#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5889#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6810#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5638#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5639#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5693#L1091-3 assume !(0 == ~E_1~0); 5694#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6776#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6777#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6806#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6767#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6473#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6474#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6698#L1131-3 assume !(0 == ~E_9~0); 6699#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6858#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6477#L514-36 assume !(1 == ~m_pc~0); 6214#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6062#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6063#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6520#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5946#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5947#L533-36 assume 1 == ~t1_pc~0; 6222#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6315#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6618#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6566#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6369#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6370#L552-36 assume 1 == ~t2_pc~0; 5939#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5941#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5760#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5761#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5913#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5914#L571-36 assume 1 == ~t3_pc~0; 6298#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6004#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6005#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6125#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6681#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5974#L590-36 assume !(1 == ~t4_pc~0); 5975#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 6581#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6159#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6160#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6660#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6661#L609-36 assume 1 == ~t5_pc~0; 6536#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6371#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6189#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6190#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6443#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6269#L628-36 assume 1 == ~t6_pc~0; 6128#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6129#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6556#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6557#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6481#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6482#L647-36 assume 1 == ~t7_pc~0; 6410#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5667#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5668#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5687#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 5688#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6582#L666-36 assume !(1 == ~t8_pc~0); 5872#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5871#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6771#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6772#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6030#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6031#L685-36 assume !(1 == ~t9_pc~0); 5771#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5772#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6287#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6288#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6169#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6170#L704-36 assume 1 == ~t10_pc~0; 5762#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5763#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6523#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6524#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5792#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5793#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6759#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6637#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6638#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6818#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6098#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6099#L1179-3 assume !(1 == ~T6_E~0); 6730#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5669#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5670#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6045#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6046#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6342#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5532#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5533#L1219-3 assume !(1 == ~E_3~0); 6531#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6532#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6554#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5805#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5806#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6389#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6768#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6534#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6535#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5613#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6360#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6361#L1584 assume !(0 == start_simulation_~tmp~3#1); 6489#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5819#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5514#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5961#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5962#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6146#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6113#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6114#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5647#L1565-2 [2021-12-15 17:20:37,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2021-12-15 17:20:37,582 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,582 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195334556] [2021-12-15 17:20:37,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,582 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,661 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195334556] [2021-12-15 17:20:37,662 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195334556] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,662 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,662 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,662 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995563940] [2021-12-15 17:20:37,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,663 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,664 INFO L85 PathProgramCache]: Analyzing trace with hash 418713301, now seen corresponding path program 1 times [2021-12-15 17:20:37,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706523407] [2021-12-15 17:20:37,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,781 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706523407] [2021-12-15 17:20:37,782 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706523407] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,782 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,783 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,783 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593870293] [2021-12-15 17:20:37,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,783 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:37,784 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:37,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:37,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:37,785 INFO L87 Difference]: Start difference. First operand 1366 states and 2031 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:37,807 INFO L93 Difference]: Finished difference Result 1366 states and 2030 transitions. [2021-12-15 17:20:37,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:37,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2030 transitions. [2021-12-15 17:20:37,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:37,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2030 transitions. [2021-12-15 17:20:37,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:37,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:37,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2030 transitions. [2021-12-15 17:20:37,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:37,830 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2021-12-15 17:20:37,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2030 transitions. [2021-12-15 17:20:37,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:37,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:37,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2030 transitions. [2021-12-15 17:20:37,854 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2021-12-15 17:20:37,854 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2021-12-15 17:20:37,855 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:37,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2030 transitions. [2021-12-15 17:20:37,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:37,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:37,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:37,864 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,864 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:37,864 INFO L791 eck$LassoCheckResult]: Stem: 9290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 9291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9499#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8282#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8283#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9523#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9482#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9483#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9513#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8591#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8592#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8697#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8942#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8873#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8593#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8255#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8256#L1036 assume !(0 == ~M_E~0); 8354#L1036-2 assume !(0 == ~T1_E~0); 9230#L1041-1 assume !(0 == ~T2_E~0); 9231#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8629#L1051-1 assume !(0 == ~T4_E~0); 8630#L1056-1 assume !(0 == ~T5_E~0); 9368#L1061-1 assume !(0 == ~T6_E~0); 8527#L1066-1 assume !(0 == ~T7_E~0); 8528#L1071-1 assume !(0 == ~T8_E~0); 9351#L1076-1 assume !(0 == ~T9_E~0); 8422#L1081-1 assume !(0 == ~T10_E~0); 8423#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8826#L1091-1 assume !(0 == ~E_1~0); 9527#L1096-1 assume !(0 == ~E_2~0); 9528#L1101-1 assume !(0 == ~E_3~0); 8887#L1106-1 assume !(0 == ~E_4~0); 8888#L1111-1 assume !(0 == ~E_5~0); 9044#L1116-1 assume !(0 == ~E_6~0); 9045#L1121-1 assume !(0 == ~E_7~0); 8880#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8881#L1131-1 assume !(0 == ~E_9~0); 9131#L1136-1 assume !(0 == ~E_10~0); 9238#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9395#L514 assume 1 == ~m_pc~0; 9358#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8900#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8817#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8818#L1285 assume !(0 != activate_threads_~tmp~1#1); 9563#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8546#L533 assume !(1 == ~t1_pc~0); 8547#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9060#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8933#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8934#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9260#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9261#L552 assume 1 == ~t2_pc~0; 8771#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8772#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9339#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9340#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8912#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8913#L571 assume 1 == ~t3_pc~0; 9090#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9091#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8460#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8461#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9050#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8336#L590 assume !(1 == ~t4_pc~0); 8337#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9103#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9335#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9336#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9292#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9046#L609 assume 1 == ~t5_pc~0; 9047#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9561#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8373#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8374#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9041#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9042#L628 assume !(1 == ~t6_pc~0); 8975#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8974#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9546#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9547#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9331#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9332#L647 assume 1 == ~t7_pc~0; 8889#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8890#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9166#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8892#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8893#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9593#L666 assume !(1 == ~t8_pc~0); 8676#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8677#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8911#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9067#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8823#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8824#L685 assume 1 == ~t9_pc~0; 9570#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9467#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9459#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8849#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8850#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9202#L704 assume !(1 == ~t10_pc~0); 8841#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8840#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9366#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8392#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8393#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8640#L1154 assume !(1 == ~M_E~0); 9319#L1154-2 assume !(1 == ~T1_E~0); 8612#L1159-1 assume !(1 == ~T2_E~0); 8613#L1164-1 assume !(1 == ~T3_E~0); 9065#L1169-1 assume !(1 == ~T4_E~0); 8937#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8742#L1179-1 assume !(1 == ~T6_E~0); 8598#L1184-1 assume !(1 == ~T7_E~0); 8599#L1189-1 assume !(1 == ~T8_E~0); 8674#L1194-1 assume !(1 == ~T9_E~0); 8813#L1199-1 assume !(1 == ~T10_E~0); 8757#L1204-1 assume !(1 == ~E_M~0); 8758#L1209-1 assume !(1 == ~E_1~0); 9284#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9285#L1219-1 assume !(1 == ~E_3~0); 9586#L1224-1 assume !(1 == ~E_4~0); 9085#L1229-1 assume !(1 == ~E_5~0); 8483#L1234-1 assume !(1 == ~E_6~0); 8484#L1239-1 assume !(1 == ~E_7~0); 8542#L1244-1 assume !(1 == ~E_8~0); 8543#L1249-1 assume !(1 == ~E_9~0); 9356#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8385#L1259-1 assume { :end_inline_reset_delta_events } true; 8386#L1565-2 [2021-12-15 17:20:37,865 INFO L793 eck$LassoCheckResult]: Loop: 8386#L1565-2 assume !false; 9294#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8778#L1011 assume !false; 8779#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8828#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8582#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9447#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8606#L866 assume !(0 != eval_~tmp~0#1); 8608#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9195#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9196#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9362#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9548#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9421#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9422#L1051-3 assume !(0 == ~T4_E~0); 9363#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8626#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8627#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8628#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9549#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8377#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8378#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8432#L1091-3 assume !(0 == ~E_1~0); 8433#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9515#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9516#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9545#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9506#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9212#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9213#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9437#L1131-3 assume !(0 == ~E_9~0); 9438#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9597#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9216#L514-36 assume 1 == ~m_pc~0; 9217#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8801#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8802#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9259#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8685#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8686#L533-36 assume 1 == ~t1_pc~0; 8961#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9054#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9357#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9305#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9108#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9109#L552-36 assume 1 == ~t2_pc~0; 8678#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8680#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8499#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8500#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8652#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8653#L571-36 assume 1 == ~t3_pc~0; 9037#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8743#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8744#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8864#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9420#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8713#L590-36 assume !(1 == ~t4_pc~0); 8714#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 9320#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8898#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8899#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9399#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9400#L609-36 assume 1 == ~t5_pc~0; 9275#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9110#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8928#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8929#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9182#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9008#L628-36 assume 1 == ~t6_pc~0; 8867#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8868#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9295#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9296#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9220#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9221#L647-36 assume 1 == ~t7_pc~0; 9149#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8406#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8407#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8426#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 8427#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9321#L666-36 assume 1 == ~t8_pc~0; 8609#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8610#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9510#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9511#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8769#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8770#L685-36 assume !(1 == ~t9_pc~0); 8510#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 8511#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9026#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9027#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8908#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8909#L704-36 assume 1 == ~t10_pc~0; 8501#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8502#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9262#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9263#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8531#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8532#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9498#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9376#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9377#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9557#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8837#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8838#L1179-3 assume !(1 == ~T6_E~0); 9469#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8408#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8409#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8784#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8785#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9081#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8271#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8272#L1219-3 assume !(1 == ~E_3~0); 9270#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9271#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9293#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8544#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8545#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9128#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9507#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9273#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9274#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8352#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9099#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9100#L1584 assume !(0 == start_simulation_~tmp~3#1); 9228#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8558#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8253#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8700#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8701#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8885#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8852#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 8853#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8386#L1565-2 [2021-12-15 17:20:37,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,866 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2021-12-15 17:20:37,867 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,867 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162256834] [2021-12-15 17:20:37,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,868 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,926 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162256834] [2021-12-15 17:20:37,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162256834] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,928 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576217221] [2021-12-15 17:20:37,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:37,932 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:37,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:37,933 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 1 times [2021-12-15 17:20:37,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:37,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793981437] [2021-12-15 17:20:37,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:37,936 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:37,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:37,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:37,998 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:37,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793981437] [2021-12-15 17:20:37,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793981437] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:37,999 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:37,999 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:37,999 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76308402] [2021-12-15 17:20:37,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,000 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,000 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:38,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:38,002 INFO L87 Difference]: Start difference. First operand 1366 states and 2030 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,024 INFO L93 Difference]: Finished difference Result 1366 states and 2029 transitions. [2021-12-15 17:20:38,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:38,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2029 transitions. [2021-12-15 17:20:38,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2029 transitions. [2021-12-15 17:20:38,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:38,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:38,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2029 transitions. [2021-12-15 17:20:38,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,045 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2021-12-15 17:20:38,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2029 transitions. [2021-12-15 17:20:38,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:38,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2029 transitions. [2021-12-15 17:20:38,100 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2021-12-15 17:20:38,100 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2021-12-15 17:20:38,100 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:38,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2029 transitions. [2021-12-15 17:20:38,105 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,107 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,107 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,108 INFO L791 eck$LassoCheckResult]: Stem: 12030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 12031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12238#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11023#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11024#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 12263#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12221#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12222#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12252#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11332#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11333#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11436#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11681#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11612#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11334#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10994#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10995#L1036 assume !(0 == ~M_E~0); 11093#L1036-2 assume !(0 == ~T1_E~0); 11969#L1041-1 assume !(0 == ~T2_E~0); 11970#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11368#L1051-1 assume !(0 == ~T4_E~0); 11369#L1056-1 assume !(0 == ~T5_E~0); 12107#L1061-1 assume !(0 == ~T6_E~0); 11266#L1066-1 assume !(0 == ~T7_E~0); 11267#L1071-1 assume !(0 == ~T8_E~0); 12090#L1076-1 assume !(0 == ~T9_E~0); 11161#L1081-1 assume !(0 == ~T10_E~0); 11162#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 11565#L1091-1 assume !(0 == ~E_1~0); 12267#L1096-1 assume !(0 == ~E_2~0); 12268#L1101-1 assume !(0 == ~E_3~0); 11626#L1106-1 assume !(0 == ~E_4~0); 11627#L1111-1 assume !(0 == ~E_5~0); 11783#L1116-1 assume !(0 == ~E_6~0); 11784#L1121-1 assume !(0 == ~E_7~0); 11619#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11620#L1131-1 assume !(0 == ~E_9~0); 11870#L1136-1 assume !(0 == ~E_10~0); 11977#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12134#L514 assume 1 == ~m_pc~0; 12097#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11640#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11559#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11560#L1285 assume !(0 != activate_threads_~tmp~1#1); 12303#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11285#L533 assume !(1 == ~t1_pc~0); 11286#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11799#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11672#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11673#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 11999#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12000#L552 assume 1 == ~t2_pc~0; 11511#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11512#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12078#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12079#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11654#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11655#L571 assume 1 == ~t3_pc~0; 11831#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11832#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11201#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11202#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11789#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11077#L590 assume !(1 == ~t4_pc~0); 11078#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11842#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12075#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12076#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12032#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11785#L609 assume 1 == ~t5_pc~0; 11786#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12300#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11112#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11113#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11780#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11781#L628 assume !(1 == ~t6_pc~0); 11714#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11713#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12285#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12286#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 12070#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12071#L647 assume 1 == ~t7_pc~0; 11628#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11629#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11907#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11635#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11636#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12332#L666 assume !(1 == ~t8_pc~0); 11415#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11416#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11650#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11807#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11563#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11564#L685 assume 1 == ~t9_pc~0; 12309#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12206#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12198#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11588#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11589#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11941#L704 assume !(1 == ~t10_pc~0); 11580#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11579#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12105#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11133#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11134#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11379#L1154 assume !(1 == ~M_E~0); 12058#L1154-2 assume !(1 == ~T1_E~0); 11351#L1159-1 assume !(1 == ~T2_E~0); 11352#L1164-1 assume !(1 == ~T3_E~0); 11804#L1169-1 assume !(1 == ~T4_E~0); 11676#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11483#L1179-1 assume !(1 == ~T6_E~0); 11337#L1184-1 assume !(1 == ~T7_E~0); 11338#L1189-1 assume !(1 == ~T8_E~0); 11413#L1194-1 assume !(1 == ~T9_E~0); 11552#L1199-1 assume !(1 == ~T10_E~0); 11498#L1204-1 assume !(1 == ~E_M~0); 11499#L1209-1 assume !(1 == ~E_1~0); 12025#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12026#L1219-1 assume !(1 == ~E_3~0); 12325#L1224-1 assume !(1 == ~E_4~0); 11824#L1229-1 assume !(1 == ~E_5~0); 11222#L1234-1 assume !(1 == ~E_6~0); 11223#L1239-1 assume !(1 == ~E_7~0); 11281#L1244-1 assume !(1 == ~E_8~0); 11282#L1249-1 assume !(1 == ~E_9~0); 12095#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11124#L1259-1 assume { :end_inline_reset_delta_events } true; 11125#L1565-2 [2021-12-15 17:20:38,108 INFO L793 eck$LassoCheckResult]: Loop: 11125#L1565-2 assume !false; 12033#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11517#L1011 assume !false; 11518#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11567#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11321#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12186#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11348#L866 assume !(0 != eval_~tmp~0#1); 11350#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11936#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11937#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12101#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12287#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12160#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12161#L1051-3 assume !(0 == ~T4_E~0); 12102#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11365#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11366#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11367#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12288#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11116#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11117#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11175#L1091-3 assume !(0 == ~E_1~0); 11176#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12254#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12255#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12284#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12245#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11952#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11953#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12176#L1131-3 assume !(0 == ~E_9~0); 12177#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12336#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11955#L514-36 assume 1 == ~m_pc~0; 11956#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11542#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11543#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11998#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11424#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11425#L533-36 assume 1 == ~t1_pc~0; 11700#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11796#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12096#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12044#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11847#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11848#L552-36 assume 1 == ~t2_pc~0; 11417#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11419#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11238#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11239#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11391#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11392#L571-36 assume 1 == ~t3_pc~0; 11776#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11481#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11482#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11603#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12159#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11449#L590-36 assume !(1 == ~t4_pc~0); 11450#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 12059#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11637#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11638#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12138#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12139#L609-36 assume 1 == ~t5_pc~0; 12014#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11849#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11667#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11668#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11921#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11747#L628-36 assume 1 == ~t6_pc~0; 11604#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11605#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12034#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12035#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11959#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11960#L647-36 assume 1 == ~t7_pc~0; 11888#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11145#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11146#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11165#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 11166#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12060#L666-36 assume 1 == ~t8_pc~0; 11345#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11346#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12249#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12250#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11508#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11509#L685-36 assume !(1 == ~t9_pc~0); 11249#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 11250#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11765#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11766#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11647#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11648#L704-36 assume 1 == ~t10_pc~0; 11240#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11241#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12001#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12002#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11270#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11271#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12237#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12115#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12116#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12296#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11576#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11577#L1179-3 assume !(1 == ~T6_E~0); 12208#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11147#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11148#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11521#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11522#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11820#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11010#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11011#L1219-3 assume !(1 == ~E_3~0); 12009#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12010#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12029#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11283#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11284#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11863#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12246#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12012#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12013#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11091#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11836#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11837#L1584 assume !(0 == start_simulation_~tmp~3#1); 11967#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11297#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10992#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11439#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11440#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11623#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11591#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11592#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11125#L1565-2 [2021-12-15 17:20:38,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2021-12-15 17:20:38,109 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776613388] [2021-12-15 17:20:38,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,139 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776613388] [2021-12-15 17:20:38,139 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776613388] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,139 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410812103] [2021-12-15 17:20:38,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,140 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,140 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 2 times [2021-12-15 17:20:38,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760395891] [2021-12-15 17:20:38,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,141 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,186 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,186 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760395891] [2021-12-15 17:20:38,187 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760395891] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,187 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,187 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,187 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017884895] [2021-12-15 17:20:38,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,188 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,189 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,189 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:38,189 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:38,189 INFO L87 Difference]: Start difference. First operand 1366 states and 2029 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,210 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2021-12-15 17:20:38,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:38,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2021-12-15 17:20:38,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2028 transitions. [2021-12-15 17:20:38,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:38,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:38,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2028 transitions. [2021-12-15 17:20:38,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,231 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2021-12-15 17:20:38,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2028 transitions. [2021-12-15 17:20:38,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:38,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2028 transitions. [2021-12-15 17:20:38,253 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2021-12-15 17:20:38,253 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2021-12-15 17:20:38,254 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:38,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2028 transitions. [2021-12-15 17:20:38,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,261 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,262 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,262 INFO L791 eck$LassoCheckResult]: Stem: 14768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14977#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13760#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13761#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 15001#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14960#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14961#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14991#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14069#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14070#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14175#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14420#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14351#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14071#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13733#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13734#L1036 assume !(0 == ~M_E~0); 13832#L1036-2 assume !(0 == ~T1_E~0); 14708#L1041-1 assume !(0 == ~T2_E~0); 14709#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14107#L1051-1 assume !(0 == ~T4_E~0); 14108#L1056-1 assume !(0 == ~T5_E~0); 14846#L1061-1 assume !(0 == ~T6_E~0); 14005#L1066-1 assume !(0 == ~T7_E~0); 14006#L1071-1 assume !(0 == ~T8_E~0); 14829#L1076-1 assume !(0 == ~T9_E~0); 13900#L1081-1 assume !(0 == ~T10_E~0); 13901#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14304#L1091-1 assume !(0 == ~E_1~0); 15005#L1096-1 assume !(0 == ~E_2~0); 15006#L1101-1 assume !(0 == ~E_3~0); 14365#L1106-1 assume !(0 == ~E_4~0); 14366#L1111-1 assume !(0 == ~E_5~0); 14522#L1116-1 assume !(0 == ~E_6~0); 14523#L1121-1 assume !(0 == ~E_7~0); 14358#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14359#L1131-1 assume !(0 == ~E_9~0); 14609#L1136-1 assume !(0 == ~E_10~0); 14716#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14873#L514 assume 1 == ~m_pc~0; 14836#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14378#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14295#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14296#L1285 assume !(0 != activate_threads_~tmp~1#1); 15041#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14024#L533 assume !(1 == ~t1_pc~0); 14025#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14538#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14411#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14412#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14738#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14739#L552 assume 1 == ~t2_pc~0; 14249#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14250#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14817#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14818#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14390#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14391#L571 assume 1 == ~t3_pc~0; 14568#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14569#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13938#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13939#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14528#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13814#L590 assume !(1 == ~t4_pc~0); 13815#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14581#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14813#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14814#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14770#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14524#L609 assume 1 == ~t5_pc~0; 14525#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15039#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13851#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13852#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14519#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14520#L628 assume !(1 == ~t6_pc~0); 14453#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14452#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15024#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15025#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14809#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14810#L647 assume 1 == ~t7_pc~0; 14367#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14368#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14644#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14370#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14371#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15071#L666 assume !(1 == ~t8_pc~0); 14154#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14155#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14389#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14545#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14301#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14302#L685 assume 1 == ~t9_pc~0; 15048#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14945#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14937#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14327#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14328#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14680#L704 assume !(1 == ~t10_pc~0); 14319#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14318#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14844#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13870#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13871#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14118#L1154 assume !(1 == ~M_E~0); 14797#L1154-2 assume !(1 == ~T1_E~0); 14090#L1159-1 assume !(1 == ~T2_E~0); 14091#L1164-1 assume !(1 == ~T3_E~0); 14543#L1169-1 assume !(1 == ~T4_E~0); 14415#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14220#L1179-1 assume !(1 == ~T6_E~0); 14076#L1184-1 assume !(1 == ~T7_E~0); 14077#L1189-1 assume !(1 == ~T8_E~0); 14152#L1194-1 assume !(1 == ~T9_E~0); 14291#L1199-1 assume !(1 == ~T10_E~0); 14235#L1204-1 assume !(1 == ~E_M~0); 14236#L1209-1 assume !(1 == ~E_1~0); 14762#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14763#L1219-1 assume !(1 == ~E_3~0); 15064#L1224-1 assume !(1 == ~E_4~0); 14563#L1229-1 assume !(1 == ~E_5~0); 13961#L1234-1 assume !(1 == ~E_6~0); 13962#L1239-1 assume !(1 == ~E_7~0); 14020#L1244-1 assume !(1 == ~E_8~0); 14021#L1249-1 assume !(1 == ~E_9~0); 14834#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13863#L1259-1 assume { :end_inline_reset_delta_events } true; 13864#L1565-2 [2021-12-15 17:20:38,262 INFO L793 eck$LassoCheckResult]: Loop: 13864#L1565-2 assume !false; 14772#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14256#L1011 assume !false; 14257#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14306#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14060#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14925#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14084#L866 assume !(0 != eval_~tmp~0#1); 14086#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14673#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14674#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14840#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15026#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14899#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14900#L1051-3 assume !(0 == ~T4_E~0); 14841#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14104#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14105#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14106#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15027#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13855#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13856#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13910#L1091-3 assume !(0 == ~E_1~0); 13911#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14993#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14994#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15023#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14984#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14690#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14691#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14915#L1131-3 assume !(0 == ~E_9~0); 14916#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15075#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14694#L514-36 assume 1 == ~m_pc~0; 14695#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14279#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14280#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14737#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14163#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14164#L533-36 assume 1 == ~t1_pc~0; 14439#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14532#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14835#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14783#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14586#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14587#L552-36 assume 1 == ~t2_pc~0; 14156#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14158#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13977#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13978#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14130#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14131#L571-36 assume 1 == ~t3_pc~0; 14515#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14221#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14222#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14342#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14898#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14191#L590-36 assume !(1 == ~t4_pc~0); 14192#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 14798#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14376#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14377#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14877#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14878#L609-36 assume 1 == ~t5_pc~0; 14753#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14588#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14406#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14407#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14660#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14486#L628-36 assume 1 == ~t6_pc~0; 14345#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14346#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14773#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14774#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14698#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14699#L647-36 assume 1 == ~t7_pc~0; 14627#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13884#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13885#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13904#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 13905#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14799#L666-36 assume 1 == ~t8_pc~0; 14087#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14088#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14988#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14989#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14247#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14248#L685-36 assume !(1 == ~t9_pc~0); 13988#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 13989#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14504#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14505#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14386#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14387#L704-36 assume 1 == ~t10_pc~0; 13979#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13980#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14740#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14741#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14009#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14010#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14976#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14854#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14855#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15035#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14315#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14316#L1179-3 assume !(1 == ~T6_E~0); 14947#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13886#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13887#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14262#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14263#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14559#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13749#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13750#L1219-3 assume !(1 == ~E_3~0); 14748#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14749#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14771#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14022#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14023#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14606#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14985#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14751#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14752#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13830#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14577#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14578#L1584 assume !(0 == start_simulation_~tmp~3#1); 14706#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14036#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13731#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14178#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14179#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14363#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14330#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14331#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13864#L1565-2 [2021-12-15 17:20:38,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,267 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2021-12-15 17:20:38,267 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101716014] [2021-12-15 17:20:38,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,268 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,295 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101716014] [2021-12-15 17:20:38,295 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1101716014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,295 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,295 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,296 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701097090] [2021-12-15 17:20:38,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,296 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 3 times [2021-12-15 17:20:38,297 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841311021] [2021-12-15 17:20:38,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,368 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841311021] [2021-12-15 17:20:38,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841311021] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,369 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,369 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,369 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023531948] [2021-12-15 17:20:38,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,370 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,370 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,371 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:38,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:38,371 INFO L87 Difference]: Start difference. First operand 1366 states and 2028 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,408 INFO L93 Difference]: Finished difference Result 1366 states and 2027 transitions. [2021-12-15 17:20:38,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:38,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2027 transitions. [2021-12-15 17:20:38,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2027 transitions. [2021-12-15 17:20:38,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:38,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:38,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2027 transitions. [2021-12-15 17:20:38,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,430 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2021-12-15 17:20:38,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2027 transitions. [2021-12-15 17:20:38,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:38,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2027 transitions. [2021-12-15 17:20:38,457 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2021-12-15 17:20:38,458 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2021-12-15 17:20:38,458 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:38,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2027 transitions. [2021-12-15 17:20:38,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,468 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,468 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,468 INFO L791 eck$LassoCheckResult]: Stem: 17507#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17716#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16499#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16500#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17740#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17699#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17700#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17730#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16808#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16809#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16914#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17159#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17090#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16810#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16472#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16473#L1036 assume !(0 == ~M_E~0); 16571#L1036-2 assume !(0 == ~T1_E~0); 17447#L1041-1 assume !(0 == ~T2_E~0); 17448#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16846#L1051-1 assume !(0 == ~T4_E~0); 16847#L1056-1 assume !(0 == ~T5_E~0); 17585#L1061-1 assume !(0 == ~T6_E~0); 16744#L1066-1 assume !(0 == ~T7_E~0); 16745#L1071-1 assume !(0 == ~T8_E~0); 17568#L1076-1 assume !(0 == ~T9_E~0); 16639#L1081-1 assume !(0 == ~T10_E~0); 16640#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17043#L1091-1 assume !(0 == ~E_1~0); 17744#L1096-1 assume !(0 == ~E_2~0); 17745#L1101-1 assume !(0 == ~E_3~0); 17104#L1106-1 assume !(0 == ~E_4~0); 17105#L1111-1 assume !(0 == ~E_5~0); 17261#L1116-1 assume !(0 == ~E_6~0); 17262#L1121-1 assume !(0 == ~E_7~0); 17097#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17098#L1131-1 assume !(0 == ~E_9~0); 17348#L1136-1 assume !(0 == ~E_10~0); 17455#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17612#L514 assume 1 == ~m_pc~0; 17575#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17117#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17034#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17035#L1285 assume !(0 != activate_threads_~tmp~1#1); 17780#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16763#L533 assume !(1 == ~t1_pc~0); 16764#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17277#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17150#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17151#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 17477#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17478#L552 assume 1 == ~t2_pc~0; 16988#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16989#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17556#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17557#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 17129#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17130#L571 assume 1 == ~t3_pc~0; 17307#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17308#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16677#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16678#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 17267#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16553#L590 assume !(1 == ~t4_pc~0); 16554#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17320#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17552#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17553#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17509#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17263#L609 assume 1 == ~t5_pc~0; 17264#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17778#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16590#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16591#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 17258#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17259#L628 assume !(1 == ~t6_pc~0); 17192#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17191#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17763#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17764#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 17548#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17549#L647 assume 1 == ~t7_pc~0; 17106#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17107#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17383#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17109#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 17110#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17810#L666 assume !(1 == ~t8_pc~0); 16893#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16894#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17128#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17284#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 17040#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17041#L685 assume 1 == ~t9_pc~0; 17787#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17684#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17676#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17066#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 17067#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17419#L704 assume !(1 == ~t10_pc~0); 17058#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17057#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17583#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16609#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 16610#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16857#L1154 assume !(1 == ~M_E~0); 17536#L1154-2 assume !(1 == ~T1_E~0); 16829#L1159-1 assume !(1 == ~T2_E~0); 16830#L1164-1 assume !(1 == ~T3_E~0); 17282#L1169-1 assume !(1 == ~T4_E~0); 17154#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16959#L1179-1 assume !(1 == ~T6_E~0); 16815#L1184-1 assume !(1 == ~T7_E~0); 16816#L1189-1 assume !(1 == ~T8_E~0); 16891#L1194-1 assume !(1 == ~T9_E~0); 17030#L1199-1 assume !(1 == ~T10_E~0); 16974#L1204-1 assume !(1 == ~E_M~0); 16975#L1209-1 assume !(1 == ~E_1~0); 17501#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17502#L1219-1 assume !(1 == ~E_3~0); 17803#L1224-1 assume !(1 == ~E_4~0); 17302#L1229-1 assume !(1 == ~E_5~0); 16700#L1234-1 assume !(1 == ~E_6~0); 16701#L1239-1 assume !(1 == ~E_7~0); 16759#L1244-1 assume !(1 == ~E_8~0); 16760#L1249-1 assume !(1 == ~E_9~0); 17573#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16602#L1259-1 assume { :end_inline_reset_delta_events } true; 16603#L1565-2 [2021-12-15 17:20:38,469 INFO L793 eck$LassoCheckResult]: Loop: 16603#L1565-2 assume !false; 17511#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16995#L1011 assume !false; 16996#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17045#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16799#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17664#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16823#L866 assume !(0 != eval_~tmp~0#1); 16825#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17412#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17413#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17579#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17765#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17638#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17639#L1051-3 assume !(0 == ~T4_E~0); 17580#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16843#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16844#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16845#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17766#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16594#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16595#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16649#L1091-3 assume !(0 == ~E_1~0); 16650#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17732#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17733#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17762#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17723#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17429#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17430#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17654#L1131-3 assume !(0 == ~E_9~0); 17655#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17814#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17433#L514-36 assume !(1 == ~m_pc~0); 17170#L514-38 is_master_triggered_~__retres1~0#1 := 0; 17018#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17019#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17476#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16902#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16903#L533-36 assume 1 == ~t1_pc~0; 17178#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17271#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17574#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17522#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17325#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17326#L552-36 assume !(1 == ~t2_pc~0); 16896#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 16897#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16716#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16717#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16869#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16870#L571-36 assume 1 == ~t3_pc~0; 17254#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16960#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16961#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17081#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17637#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16930#L590-36 assume !(1 == ~t4_pc~0); 16931#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 17537#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17115#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17116#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17616#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17617#L609-36 assume 1 == ~t5_pc~0; 17492#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17327#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17145#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17146#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17399#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17225#L628-36 assume 1 == ~t6_pc~0; 17084#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17085#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17512#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17513#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17437#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17438#L647-36 assume 1 == ~t7_pc~0; 17366#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16623#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16624#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16643#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 16644#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17538#L666-36 assume 1 == ~t8_pc~0; 16826#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16827#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17727#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17728#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16986#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16987#L685-36 assume !(1 == ~t9_pc~0); 16727#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 16728#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17243#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17244#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17125#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17126#L704-36 assume !(1 == ~t10_pc~0); 16720#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 16719#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17479#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17480#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16748#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16749#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17715#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17593#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17594#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17774#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17054#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17055#L1179-3 assume !(1 == ~T6_E~0); 17686#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16625#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16626#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17001#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17002#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17298#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16491#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16492#L1219-3 assume !(1 == ~E_3~0); 17487#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17488#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17510#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16761#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16762#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17345#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17724#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17490#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17491#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16569#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17316#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17317#L1584 assume !(0 == start_simulation_~tmp~3#1); 17445#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16775#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16470#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16917#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 16918#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17102#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17069#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17070#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 16603#L1565-2 [2021-12-15 17:20:38,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,470 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2021-12-15 17:20:38,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468697231] [2021-12-15 17:20:38,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,470 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,504 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1468697231] [2021-12-15 17:20:38,504 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1468697231] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,504 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942132979] [2021-12-15 17:20:38,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,505 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,506 INFO L85 PathProgramCache]: Analyzing trace with hash -1179364202, now seen corresponding path program 1 times [2021-12-15 17:20:38,506 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197465050] [2021-12-15 17:20:38,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,507 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,543 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197465050] [2021-12-15 17:20:38,543 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197465050] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,544 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,544 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,544 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013582642] [2021-12-15 17:20:38,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,544 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,545 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,545 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:38,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:38,545 INFO L87 Difference]: Start difference. First operand 1366 states and 2027 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,569 INFO L93 Difference]: Finished difference Result 1366 states and 2026 transitions. [2021-12-15 17:20:38,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:38,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2026 transitions. [2021-12-15 17:20:38,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2026 transitions. [2021-12-15 17:20:38,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:38,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:38,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2026 transitions. [2021-12-15 17:20:38,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,589 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2021-12-15 17:20:38,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2026 transitions. [2021-12-15 17:20:38,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:38,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2026 transitions. [2021-12-15 17:20:38,616 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2021-12-15 17:20:38,616 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2021-12-15 17:20:38,616 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:38,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2026 transitions. [2021-12-15 17:20:38,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,626 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,626 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,626 INFO L791 eck$LassoCheckResult]: Stem: 20247#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 20248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20455#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19240#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19241#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20480#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20438#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20439#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20469#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19549#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19550#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19653#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19898#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19829#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19551#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19211#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19212#L1036 assume !(0 == ~M_E~0); 19310#L1036-2 assume !(0 == ~T1_E~0); 20186#L1041-1 assume !(0 == ~T2_E~0); 20187#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19585#L1051-1 assume !(0 == ~T4_E~0); 19586#L1056-1 assume !(0 == ~T5_E~0); 20324#L1061-1 assume !(0 == ~T6_E~0); 19483#L1066-1 assume !(0 == ~T7_E~0); 19484#L1071-1 assume !(0 == ~T8_E~0); 20307#L1076-1 assume !(0 == ~T9_E~0); 19378#L1081-1 assume !(0 == ~T10_E~0); 19379#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19782#L1091-1 assume !(0 == ~E_1~0); 20484#L1096-1 assume !(0 == ~E_2~0); 20485#L1101-1 assume !(0 == ~E_3~0); 19843#L1106-1 assume !(0 == ~E_4~0); 19844#L1111-1 assume !(0 == ~E_5~0); 20000#L1116-1 assume !(0 == ~E_6~0); 20001#L1121-1 assume !(0 == ~E_7~0); 19836#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19837#L1131-1 assume !(0 == ~E_9~0); 20087#L1136-1 assume !(0 == ~E_10~0); 20194#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20351#L514 assume 1 == ~m_pc~0; 20314#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19857#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19776#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19777#L1285 assume !(0 != activate_threads_~tmp~1#1); 20520#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19502#L533 assume !(1 == ~t1_pc~0); 19503#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20016#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19889#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19890#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20216#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20217#L552 assume 1 == ~t2_pc~0; 19728#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19729#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20295#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20296#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 19871#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19872#L571 assume 1 == ~t3_pc~0; 20048#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20049#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19418#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19419#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 20006#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19294#L590 assume !(1 == ~t4_pc~0); 19295#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20059#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20292#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20293#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20249#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20002#L609 assume 1 == ~t5_pc~0; 20003#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20517#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19329#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19330#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 19997#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19998#L628 assume !(1 == ~t6_pc~0); 19931#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19930#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20502#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20503#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20287#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20288#L647 assume 1 == ~t7_pc~0; 19845#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19846#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20124#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19852#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 19853#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20549#L666 assume !(1 == ~t8_pc~0); 19632#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19633#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19867#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20024#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19780#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19781#L685 assume 1 == ~t9_pc~0; 20526#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20423#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20415#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19805#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19806#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20158#L704 assume !(1 == ~t10_pc~0); 19797#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19796#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20322#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19350#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19351#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19596#L1154 assume !(1 == ~M_E~0); 20275#L1154-2 assume !(1 == ~T1_E~0); 19568#L1159-1 assume !(1 == ~T2_E~0); 19569#L1164-1 assume !(1 == ~T3_E~0); 20021#L1169-1 assume !(1 == ~T4_E~0); 19893#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19700#L1179-1 assume !(1 == ~T6_E~0); 19554#L1184-1 assume !(1 == ~T7_E~0); 19555#L1189-1 assume !(1 == ~T8_E~0); 19630#L1194-1 assume !(1 == ~T9_E~0); 19769#L1199-1 assume !(1 == ~T10_E~0); 19715#L1204-1 assume !(1 == ~E_M~0); 19716#L1209-1 assume !(1 == ~E_1~0); 20242#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20243#L1219-1 assume !(1 == ~E_3~0); 20542#L1224-1 assume !(1 == ~E_4~0); 20041#L1229-1 assume !(1 == ~E_5~0); 19439#L1234-1 assume !(1 == ~E_6~0); 19440#L1239-1 assume !(1 == ~E_7~0); 19498#L1244-1 assume !(1 == ~E_8~0); 19499#L1249-1 assume !(1 == ~E_9~0); 20312#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19341#L1259-1 assume { :end_inline_reset_delta_events } true; 19342#L1565-2 [2021-12-15 17:20:38,627 INFO L793 eck$LassoCheckResult]: Loop: 19342#L1565-2 assume !false; 20250#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19734#L1011 assume !false; 19735#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19784#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19538#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20403#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19565#L866 assume !(0 != eval_~tmp~0#1); 19567#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20153#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20154#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20318#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20504#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20377#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20378#L1051-3 assume !(0 == ~T4_E~0); 20319#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19582#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19583#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19584#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20505#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19333#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19334#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19392#L1091-3 assume !(0 == ~E_1~0); 19393#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20471#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20472#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20501#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20462#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20169#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20170#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20393#L1131-3 assume !(0 == ~E_9~0); 20394#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20553#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20172#L514-36 assume !(1 == ~m_pc~0); 19909#L514-38 is_master_triggered_~__retres1~0#1 := 0; 19759#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19760#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20215#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19641#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19642#L533-36 assume 1 == ~t1_pc~0; 19917#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20013#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20313#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20261#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20064#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20065#L552-36 assume 1 == ~t2_pc~0; 19634#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19636#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19455#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19456#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19608#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19609#L571-36 assume 1 == ~t3_pc~0; 19993#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19698#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19699#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19820#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20376#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19666#L590-36 assume !(1 == ~t4_pc~0); 19667#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20276#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19854#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19855#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20355#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20356#L609-36 assume 1 == ~t5_pc~0; 20231#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20066#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19884#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19885#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20138#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19964#L628-36 assume 1 == ~t6_pc~0; 19821#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19822#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20251#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20252#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20176#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20177#L647-36 assume 1 == ~t7_pc~0; 20105#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19362#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19363#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19382#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 19383#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20277#L666-36 assume 1 == ~t8_pc~0; 19562#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19563#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20466#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20467#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19725#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19726#L685-36 assume 1 == ~t9_pc~0; 20152#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19467#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19982#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19983#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19864#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19865#L704-36 assume 1 == ~t10_pc~0; 19457#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19458#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20218#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20219#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19487#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19488#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20454#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20332#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20333#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20513#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19793#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19794#L1179-3 assume !(1 == ~T6_E~0); 20425#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19364#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19365#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19738#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19739#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20037#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19227#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19228#L1219-3 assume !(1 == ~E_3~0); 20226#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20227#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20246#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19500#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19501#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20080#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20463#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20229#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20230#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19308#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20053#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20054#L1584 assume !(0 == start_simulation_~tmp~3#1); 20184#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19514#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19209#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19656#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19657#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19841#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19808#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19809#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19342#L1565-2 [2021-12-15 17:20:38,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2021-12-15 17:20:38,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92037156] [2021-12-15 17:20:38,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,655 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92037156] [2021-12-15 17:20:38,655 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92037156] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,656 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,656 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,657 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958558468] [2021-12-15 17:20:38,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,657 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,658 INFO L85 PathProgramCache]: Analyzing trace with hash -1709033325, now seen corresponding path program 1 times [2021-12-15 17:20:38,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263557881] [2021-12-15 17:20:38,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,695 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263557881] [2021-12-15 17:20:38,698 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263557881] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,698 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,698 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,698 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673393756] [2021-12-15 17:20:38,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,699 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,699 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:38,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:38,700 INFO L87 Difference]: Start difference. First operand 1366 states and 2026 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,720 INFO L93 Difference]: Finished difference Result 1366 states and 2025 transitions. [2021-12-15 17:20:38,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:38,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2025 transitions. [2021-12-15 17:20:38,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2025 transitions. [2021-12-15 17:20:38,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:38,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:38,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2025 transitions. [2021-12-15 17:20:38,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,741 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2021-12-15 17:20:38,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2025 transitions. [2021-12-15 17:20:38,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:38,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2025 transitions. [2021-12-15 17:20:38,763 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2021-12-15 17:20:38,763 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2021-12-15 17:20:38,763 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:38,763 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2025 transitions. [2021-12-15 17:20:38,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,770 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,770 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,770 INFO L791 eck$LassoCheckResult]: Stem: 22985#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23194#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21977#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21978#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23218#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23177#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23178#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23208#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22286#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22287#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22392#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22637#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22568#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22288#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21950#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21951#L1036 assume !(0 == ~M_E~0); 22049#L1036-2 assume !(0 == ~T1_E~0); 22925#L1041-1 assume !(0 == ~T2_E~0); 22926#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22324#L1051-1 assume !(0 == ~T4_E~0); 22325#L1056-1 assume !(0 == ~T5_E~0); 23063#L1061-1 assume !(0 == ~T6_E~0); 22222#L1066-1 assume !(0 == ~T7_E~0); 22223#L1071-1 assume !(0 == ~T8_E~0); 23046#L1076-1 assume !(0 == ~T9_E~0); 22117#L1081-1 assume !(0 == ~T10_E~0); 22118#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 22521#L1091-1 assume !(0 == ~E_1~0); 23222#L1096-1 assume !(0 == ~E_2~0); 23223#L1101-1 assume !(0 == ~E_3~0); 22582#L1106-1 assume !(0 == ~E_4~0); 22583#L1111-1 assume !(0 == ~E_5~0); 22739#L1116-1 assume !(0 == ~E_6~0); 22740#L1121-1 assume !(0 == ~E_7~0); 22575#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22576#L1131-1 assume !(0 == ~E_9~0); 22826#L1136-1 assume !(0 == ~E_10~0); 22933#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23090#L514 assume 1 == ~m_pc~0; 23053#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22595#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22512#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22513#L1285 assume !(0 != activate_threads_~tmp~1#1); 23258#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22241#L533 assume !(1 == ~t1_pc~0); 22242#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22755#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22628#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22629#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 22955#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22956#L552 assume 1 == ~t2_pc~0; 22466#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22467#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23034#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23035#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 22607#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22608#L571 assume 1 == ~t3_pc~0; 22785#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22786#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22155#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22156#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 22745#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22031#L590 assume !(1 == ~t4_pc~0); 22032#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22798#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23030#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23031#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22987#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22741#L609 assume 1 == ~t5_pc~0; 22742#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23256#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22068#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22069#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 22736#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22737#L628 assume !(1 == ~t6_pc~0); 22670#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22669#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23241#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23242#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 23026#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23027#L647 assume 1 == ~t7_pc~0; 22584#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22585#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22861#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22587#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 22588#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23288#L666 assume !(1 == ~t8_pc~0); 22371#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22372#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22606#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22762#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 22518#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22519#L685 assume 1 == ~t9_pc~0; 23265#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23162#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23154#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22544#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 22545#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22897#L704 assume !(1 == ~t10_pc~0); 22536#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22535#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23061#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22087#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 22088#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22335#L1154 assume !(1 == ~M_E~0); 23014#L1154-2 assume !(1 == ~T1_E~0); 22307#L1159-1 assume !(1 == ~T2_E~0); 22308#L1164-1 assume !(1 == ~T3_E~0); 22760#L1169-1 assume !(1 == ~T4_E~0); 22632#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22437#L1179-1 assume !(1 == ~T6_E~0); 22293#L1184-1 assume !(1 == ~T7_E~0); 22294#L1189-1 assume !(1 == ~T8_E~0); 22369#L1194-1 assume !(1 == ~T9_E~0); 22508#L1199-1 assume !(1 == ~T10_E~0); 22452#L1204-1 assume !(1 == ~E_M~0); 22453#L1209-1 assume !(1 == ~E_1~0); 22979#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22980#L1219-1 assume !(1 == ~E_3~0); 23281#L1224-1 assume !(1 == ~E_4~0); 22780#L1229-1 assume !(1 == ~E_5~0); 22178#L1234-1 assume !(1 == ~E_6~0); 22179#L1239-1 assume !(1 == ~E_7~0); 22237#L1244-1 assume !(1 == ~E_8~0); 22238#L1249-1 assume !(1 == ~E_9~0); 23051#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22080#L1259-1 assume { :end_inline_reset_delta_events } true; 22081#L1565-2 [2021-12-15 17:20:38,771 INFO L793 eck$LassoCheckResult]: Loop: 22081#L1565-2 assume !false; 22989#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22473#L1011 assume !false; 22474#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22523#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22277#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23142#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22301#L866 assume !(0 != eval_~tmp~0#1); 22303#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22890#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22891#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23057#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23243#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23116#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23117#L1051-3 assume !(0 == ~T4_E~0); 23058#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22321#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22322#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22323#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23244#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22072#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22073#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22127#L1091-3 assume !(0 == ~E_1~0); 22128#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23210#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23211#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23240#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23201#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22907#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22908#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23132#L1131-3 assume !(0 == ~E_9~0); 23133#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23292#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22911#L514-36 assume 1 == ~m_pc~0; 22912#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22496#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22497#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22954#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22380#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22381#L533-36 assume 1 == ~t1_pc~0; 22656#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22749#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23052#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23000#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22803#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22804#L552-36 assume 1 == ~t2_pc~0; 22373#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22375#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22194#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22195#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22347#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22348#L571-36 assume 1 == ~t3_pc~0; 22732#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22438#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22439#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22559#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23115#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22408#L590-36 assume !(1 == ~t4_pc~0); 22409#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 23015#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22593#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22594#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23094#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23095#L609-36 assume 1 == ~t5_pc~0; 22970#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22805#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22623#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22624#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22877#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22703#L628-36 assume 1 == ~t6_pc~0; 22562#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22563#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22990#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22991#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22915#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22916#L647-36 assume 1 == ~t7_pc~0; 22844#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22101#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22102#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22121#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 22122#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23016#L666-36 assume 1 == ~t8_pc~0; 22304#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22305#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23205#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23206#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22464#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22465#L685-36 assume !(1 == ~t9_pc~0); 22205#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22206#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22721#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22722#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22603#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22604#L704-36 assume 1 == ~t10_pc~0; 22196#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22197#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22957#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22958#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22226#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22227#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23193#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23071#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23072#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23252#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22532#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22533#L1179-3 assume !(1 == ~T6_E~0); 23164#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22103#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22104#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22479#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22480#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22776#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21966#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21967#L1219-3 assume !(1 == ~E_3~0); 22965#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22966#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22988#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22239#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22240#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22823#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23202#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22968#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22969#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22047#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22794#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22795#L1584 assume !(0 == start_simulation_~tmp~3#1); 22923#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22253#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21948#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22395#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 22396#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22580#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22547#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22548#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 22081#L1565-2 [2021-12-15 17:20:38,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2021-12-15 17:20:38,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517446764] [2021-12-15 17:20:38,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,813 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,813 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517446764] [2021-12-15 17:20:38,814 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [517446764] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,814 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,814 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,814 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279487706] [2021-12-15 17:20:38,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,815 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,815 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 4 times [2021-12-15 17:20:38,815 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114331679] [2021-12-15 17:20:38,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,816 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,858 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114331679] [2021-12-15 17:20:38,858 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114331679] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,858 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,858 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,859 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441039867] [2021-12-15 17:20:38,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,859 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:38,859 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:38,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:38,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:38,860 INFO L87 Difference]: Start difference. First operand 1366 states and 2025 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:38,883 INFO L93 Difference]: Finished difference Result 1366 states and 2024 transitions. [2021-12-15 17:20:38,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:38,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2024 transitions. [2021-12-15 17:20:38,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2024 transitions. [2021-12-15 17:20:38,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-15 17:20:38,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-15 17:20:38,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2024 transitions. [2021-12-15 17:20:38,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:38,903 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2021-12-15 17:20:38,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2024 transitions. [2021-12-15 17:20:38,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-15 17:20:38,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:38,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2024 transitions. [2021-12-15 17:20:38,930 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2021-12-15 17:20:38,930 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2021-12-15 17:20:38,930 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:38,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2024 transitions. [2021-12-15 17:20:38,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-15 17:20:38,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:38,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:38,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:38,939 INFO L791 eck$LassoCheckResult]: Stem: 25724#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 25933#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24716#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24717#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 25957#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25916#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25917#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25947#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25025#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25026#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25131#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25376#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25307#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25027#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 24689#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24690#L1036 assume !(0 == ~M_E~0); 24788#L1036-2 assume !(0 == ~T1_E~0); 25664#L1041-1 assume !(0 == ~T2_E~0); 25665#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25063#L1051-1 assume !(0 == ~T4_E~0); 25064#L1056-1 assume !(0 == ~T5_E~0); 25802#L1061-1 assume !(0 == ~T6_E~0); 24961#L1066-1 assume !(0 == ~T7_E~0); 24962#L1071-1 assume !(0 == ~T8_E~0); 25785#L1076-1 assume !(0 == ~T9_E~0); 24856#L1081-1 assume !(0 == ~T10_E~0); 24857#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25260#L1091-1 assume !(0 == ~E_1~0); 25961#L1096-1 assume !(0 == ~E_2~0); 25962#L1101-1 assume !(0 == ~E_3~0); 25321#L1106-1 assume !(0 == ~E_4~0); 25322#L1111-1 assume !(0 == ~E_5~0); 25478#L1116-1 assume !(0 == ~E_6~0); 25479#L1121-1 assume !(0 == ~E_7~0); 25314#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25315#L1131-1 assume !(0 == ~E_9~0); 25565#L1136-1 assume !(0 == ~E_10~0); 25672#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25829#L514 assume 1 == ~m_pc~0; 25792#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25334#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25251#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25252#L1285 assume !(0 != activate_threads_~tmp~1#1); 25997#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24980#L533 assume !(1 == ~t1_pc~0); 24981#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25494#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25367#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25368#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25694#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25695#L552 assume 1 == ~t2_pc~0; 25205#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25206#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25773#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25774#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25346#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25347#L571 assume 1 == ~t3_pc~0; 25524#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25525#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24894#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24895#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25484#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24770#L590 assume !(1 == ~t4_pc~0); 24771#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25537#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25769#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25770#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25726#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25480#L609 assume 1 == ~t5_pc~0; 25481#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25995#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24807#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24808#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25475#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25476#L628 assume !(1 == ~t6_pc~0); 25409#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25408#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25980#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25981#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25765#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25766#L647 assume 1 == ~t7_pc~0; 25323#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25324#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25600#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25328#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25329#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26027#L666 assume !(1 == ~t8_pc~0); 25110#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25111#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25345#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25501#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25257#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25258#L685 assume 1 == ~t9_pc~0; 26004#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25901#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25893#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25283#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25284#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25636#L704 assume !(1 == ~t10_pc~0); 25275#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25274#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25800#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24826#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 24827#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25074#L1154 assume !(1 == ~M_E~0); 25753#L1154-2 assume !(1 == ~T1_E~0); 25046#L1159-1 assume !(1 == ~T2_E~0); 25047#L1164-1 assume !(1 == ~T3_E~0); 25499#L1169-1 assume !(1 == ~T4_E~0); 25371#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25176#L1179-1 assume !(1 == ~T6_E~0); 25032#L1184-1 assume !(1 == ~T7_E~0); 25033#L1189-1 assume !(1 == ~T8_E~0); 25108#L1194-1 assume !(1 == ~T9_E~0); 25247#L1199-1 assume !(1 == ~T10_E~0); 25191#L1204-1 assume !(1 == ~E_M~0); 25192#L1209-1 assume !(1 == ~E_1~0); 25718#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25719#L1219-1 assume !(1 == ~E_3~0); 26020#L1224-1 assume !(1 == ~E_4~0); 25519#L1229-1 assume !(1 == ~E_5~0); 24917#L1234-1 assume !(1 == ~E_6~0); 24918#L1239-1 assume !(1 == ~E_7~0); 24976#L1244-1 assume !(1 == ~E_8~0); 24977#L1249-1 assume !(1 == ~E_9~0); 25790#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 24819#L1259-1 assume { :end_inline_reset_delta_events } true; 24820#L1565-2 [2021-12-15 17:20:38,939 INFO L793 eck$LassoCheckResult]: Loop: 24820#L1565-2 assume !false; 25728#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25212#L1011 assume !false; 25213#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25262#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25016#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25881#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25040#L866 assume !(0 != eval_~tmp~0#1); 25042#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25629#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25630#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25796#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25982#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25855#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25856#L1051-3 assume !(0 == ~T4_E~0); 25797#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25060#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25061#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25062#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25983#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24811#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24812#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24866#L1091-3 assume !(0 == ~E_1~0); 24867#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25949#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25950#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25979#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25940#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25646#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25647#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25871#L1131-3 assume !(0 == ~E_9~0); 25872#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26031#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25650#L514-36 assume 1 == ~m_pc~0; 25651#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25235#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25236#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25693#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25119#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25120#L533-36 assume 1 == ~t1_pc~0; 25395#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25488#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25791#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25739#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25542#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25543#L552-36 assume 1 == ~t2_pc~0; 25112#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25114#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24933#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24934#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25086#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25087#L571-36 assume !(1 == ~t3_pc~0); 25472#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 25177#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25178#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25298#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25854#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25147#L590-36 assume !(1 == ~t4_pc~0); 25148#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25754#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25332#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25333#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25833#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25834#L609-36 assume 1 == ~t5_pc~0; 25709#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25544#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25362#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25363#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25616#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25442#L628-36 assume 1 == ~t6_pc~0; 25301#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25302#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25729#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25730#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25654#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25655#L647-36 assume !(1 == ~t7_pc~0); 25584#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 24840#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24841#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24860#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 24861#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25755#L666-36 assume 1 == ~t8_pc~0; 25043#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25044#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25944#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25945#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25203#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25204#L685-36 assume !(1 == ~t9_pc~0); 24944#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24945#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25460#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25461#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25342#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25343#L704-36 assume 1 == ~t10_pc~0; 24935#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24936#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25696#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25697#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24965#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24966#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25932#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25810#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25811#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25991#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25271#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25272#L1179-3 assume !(1 == ~T6_E~0); 25903#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24842#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24843#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25218#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25219#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25515#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24708#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24709#L1219-3 assume !(1 == ~E_3~0); 25704#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25705#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25727#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24978#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24979#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25562#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25941#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25707#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25708#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24786#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25533#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25534#L1584 assume !(0 == start_simulation_~tmp~3#1); 25662#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24992#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24687#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25134#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 25135#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25319#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25286#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25287#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 24820#L1565-2 [2021-12-15 17:20:38,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,940 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2021-12-15 17:20:38,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317230821] [2021-12-15 17:20:38,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:38,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:38,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:38,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317230821] [2021-12-15 17:20:38,976 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317230821] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:38,976 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:38,976 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:38,976 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485337385] [2021-12-15 17:20:38,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:38,977 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:38,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:38,978 INFO L85 PathProgramCache]: Analyzing trace with hash -708994987, now seen corresponding path program 1 times [2021-12-15 17:20:38,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:38,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910666238] [2021-12-15 17:20:38,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:38,978 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:38,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,009 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,010 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910666238] [2021-12-15 17:20:39,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910666238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,010 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,010 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891426650] [2021-12-15 17:20:39,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,011 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:39,011 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:39,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:39,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:39,012 INFO L87 Difference]: Start difference. First operand 1366 states and 2024 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:39,103 INFO L93 Difference]: Finished difference Result 2514 states and 3712 transitions. [2021-12-15 17:20:39,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:39,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2514 states and 3712 transitions. [2021-12-15 17:20:39,117 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2021-12-15 17:20:39,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2514 states to 2514 states and 3712 transitions. [2021-12-15 17:20:39,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2514 [2021-12-15 17:20:39,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2514 [2021-12-15 17:20:39,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2514 states and 3712 transitions. [2021-12-15 17:20:39,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:39,136 INFO L681 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2021-12-15 17:20:39,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2514 states and 3712 transitions. [2021-12-15 17:20:39,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2514 to 2514. [2021-12-15 17:20:39,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2514 states to 2514 states and 3712 transitions. [2021-12-15 17:20:39,182 INFO L704 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2021-12-15 17:20:39,182 INFO L587 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2021-12-15 17:20:39,182 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:39,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2514 states and 3712 transitions. [2021-12-15 17:20:39,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2021-12-15 17:20:39,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:39,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:39,194 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,194 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,194 INFO L791 eck$LassoCheckResult]: Stem: 29618#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29831#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28606#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28607#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 29857#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29814#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29815#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29846#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28915#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28916#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29021#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29266#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29197#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28917#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 28579#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28580#L1036 assume !(0 == ~M_E~0); 28678#L1036-2 assume !(0 == ~T1_E~0); 29558#L1041-1 assume !(0 == ~T2_E~0); 29559#L1046-1 assume !(0 == ~T3_E~0); 28953#L1051-1 assume !(0 == ~T4_E~0); 28954#L1056-1 assume !(0 == ~T5_E~0); 29697#L1061-1 assume !(0 == ~T6_E~0); 28851#L1066-1 assume !(0 == ~T7_E~0); 28852#L1071-1 assume !(0 == ~T8_E~0); 29680#L1076-1 assume !(0 == ~T9_E~0); 28746#L1081-1 assume !(0 == ~T10_E~0); 28747#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29150#L1091-1 assume !(0 == ~E_1~0); 29861#L1096-1 assume !(0 == ~E_2~0); 29862#L1101-1 assume !(0 == ~E_3~0); 29211#L1106-1 assume !(0 == ~E_4~0); 29212#L1111-1 assume !(0 == ~E_5~0); 29368#L1116-1 assume !(0 == ~E_6~0); 29369#L1121-1 assume !(0 == ~E_7~0); 29204#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29205#L1131-1 assume !(0 == ~E_9~0); 29458#L1136-1 assume !(0 == ~E_10~0); 29566#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29726#L514 assume 1 == ~m_pc~0; 29687#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29224#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29141#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29142#L1285 assume !(0 != activate_threads_~tmp~1#1); 29904#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28870#L533 assume !(1 == ~t1_pc~0); 28871#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29384#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29257#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29258#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 29588#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29589#L552 assume 1 == ~t2_pc~0; 29095#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29096#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29668#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29669#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 29236#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29237#L571 assume 1 == ~t3_pc~0; 29416#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29417#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28784#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28785#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 29374#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28660#L590 assume !(1 == ~t4_pc~0); 28661#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29429#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29664#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29665#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29620#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29370#L609 assume 1 == ~t5_pc~0; 29371#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29902#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28697#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28698#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 29365#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29366#L628 assume !(1 == ~t6_pc~0); 29299#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29298#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29882#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29883#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 29660#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29661#L647 assume 1 == ~t7_pc~0; 29213#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29214#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29493#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29216#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 29217#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29939#L666 assume !(1 == ~t8_pc~0); 29000#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29001#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29235#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29392#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 29147#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29148#L685 assume 1 == ~t9_pc~0; 29915#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29798#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29790#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29173#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 29174#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29530#L704 assume !(1 == ~t10_pc~0); 29165#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29164#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29695#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28716#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 28717#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28964#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29647#L1154-2 assume !(1 == ~T1_E~0); 30126#L1159-1 assume !(1 == ~T2_E~0); 30124#L1164-1 assume !(1 == ~T3_E~0); 29945#L1169-1 assume !(1 == ~T4_E~0); 30121#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30119#L1179-1 assume !(1 == ~T6_E~0); 30116#L1184-1 assume !(1 == ~T7_E~0); 30114#L1189-1 assume !(1 == ~T8_E~0); 30112#L1194-1 assume !(1 == ~T9_E~0); 30110#L1199-1 assume !(1 == ~T10_E~0); 30108#L1204-1 assume !(1 == ~E_M~0); 30106#L1209-1 assume !(1 == ~E_1~0); 30103#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30101#L1219-1 assume !(1 == ~E_3~0); 30099#L1224-1 assume !(1 == ~E_4~0); 30097#L1229-1 assume !(1 == ~E_5~0); 30095#L1234-1 assume !(1 == ~E_6~0); 30094#L1239-1 assume !(1 == ~E_7~0); 30093#L1244-1 assume !(1 == ~E_8~0); 29998#L1249-1 assume !(1 == ~E_9~0); 29996#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29986#L1259-1 assume { :end_inline_reset_delta_events } true; 29979#L1565-2 [2021-12-15 17:20:39,195 INFO L793 eck$LassoCheckResult]: Loop: 29979#L1565-2 assume !false; 29973#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29968#L1011 assume !false; 29967#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29966#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 29955#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29954#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29953#L866 assume !(0 != eval_~tmp~0#1); 29952#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29951#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29950#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29884#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29885#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29752#L1046-3 assume !(0 == ~T3_E~0); 29753#L1051-3 assume !(0 == ~T4_E~0); 29692#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28950#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28951#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28952#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29886#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28701#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28702#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28756#L1091-3 assume !(0 == ~E_1~0); 28757#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29848#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29849#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29881#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29838#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29540#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29541#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29768#L1131-3 assume !(0 == ~E_9~0); 29769#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29943#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29544#L514-36 assume 1 == ~m_pc~0; 29545#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29125#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29126#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29587#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29009#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29010#L533-36 assume 1 == ~t1_pc~0; 29285#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29378#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29686#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29633#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29434#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29435#L552-36 assume 1 == ~t2_pc~0; 29002#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29004#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28823#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28824#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28976#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28977#L571-36 assume 1 == ~t3_pc~0; 29361#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29067#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29068#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29188#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29751#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29037#L590-36 assume !(1 == ~t4_pc~0); 29038#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 29649#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29222#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29223#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29730#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29731#L609-36 assume 1 == ~t5_pc~0; 29603#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29436#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29252#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29253#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29509#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29332#L628-36 assume 1 == ~t6_pc~0; 29191#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29192#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29623#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29624#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29548#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29549#L647-36 assume 1 == ~t7_pc~0; 29476#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28730#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28731#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28750#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 28751#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29650#L666-36 assume 1 == ~t8_pc~0; 28933#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28934#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29842#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29843#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29093#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29094#L685-36 assume !(1 == ~t9_pc~0); 28834#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 28835#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29350#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29351#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29232#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29233#L704-36 assume 1 == ~t10_pc~0; 28825#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28826#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29590#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29591#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28855#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28856#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29830#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29705#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29706#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29898#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29161#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29162#L1179-3 assume !(1 == ~T6_E~0); 29800#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28732#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28733#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29108#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29109#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29407#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28595#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28596#L1219-3 assume !(1 == ~E_3~0); 29598#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29599#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29621#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28868#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28869#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29455#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29839#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29601#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29602#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28676#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29425#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 29426#L1584 assume !(0 == start_simulation_~tmp~3#1); 29556#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28882#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28577#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29024#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29025#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29209#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29176#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 29177#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 29979#L1565-2 [2021-12-15 17:20:39,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2021-12-15 17:20:39,196 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,196 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743419261] [2021-12-15 17:20:39,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,196 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,225 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743419261] [2021-12-15 17:20:39,226 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743419261] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,226 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,226 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,226 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177527182] [2021-12-15 17:20:39,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,227 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:39,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,227 INFO L85 PathProgramCache]: Analyzing trace with hash -2084436651, now seen corresponding path program 1 times [2021-12-15 17:20:39,227 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241679223] [2021-12-15 17:20:39,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,228 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,282 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241679223] [2021-12-15 17:20:39,282 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241679223] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,282 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,282 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,283 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030008369] [2021-12-15 17:20:39,283 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,283 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:39,283 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:39,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:39,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:39,284 INFO L87 Difference]: Start difference. First operand 2514 states and 3712 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:39,434 INFO L93 Difference]: Finished difference Result 4640 states and 6839 transitions. [2021-12-15 17:20:39,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:39,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4640 states and 6839 transitions. [2021-12-15 17:20:39,459 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2021-12-15 17:20:39,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4640 states to 4640 states and 6839 transitions. [2021-12-15 17:20:39,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4640 [2021-12-15 17:20:39,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4640 [2021-12-15 17:20:39,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4640 states and 6839 transitions. [2021-12-15 17:20:39,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:39,501 INFO L681 BuchiCegarLoop]: Abstraction has 4640 states and 6839 transitions. [2021-12-15 17:20:39,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4640 states and 6839 transitions. [2021-12-15 17:20:39,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4640 to 4638. [2021-12-15 17:20:39,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4638 states to 4638 states and 6837 transitions. [2021-12-15 17:20:39,579 INFO L704 BuchiCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2021-12-15 17:20:39,579 INFO L587 BuchiCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2021-12-15 17:20:39,580 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:39,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4638 states and 6837 transitions. [2021-12-15 17:20:39,595 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2021-12-15 17:20:39,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:39,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:39,597 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,598 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:39,598 INFO L791 eck$LassoCheckResult]: Stem: 36799#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36800#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37024#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35772#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35773#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 37053#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37003#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37004#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37041#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36081#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36082#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36185#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36438#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36366#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36083#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35743#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35744#L1036 assume !(0 == ~M_E~0); 35842#L1036-2 assume !(0 == ~T1_E~0); 36734#L1041-1 assume !(0 == ~T2_E~0); 36735#L1046-1 assume !(0 == ~T3_E~0); 36117#L1051-1 assume !(0 == ~T4_E~0); 36118#L1056-1 assume !(0 == ~T5_E~0); 36879#L1061-1 assume !(0 == ~T6_E~0); 36015#L1066-1 assume !(0 == ~T7_E~0); 36016#L1071-1 assume !(0 == ~T8_E~0); 36862#L1076-1 assume !(0 == ~T9_E~0); 35910#L1081-1 assume !(0 == ~T10_E~0); 35911#L1086-1 assume !(0 == ~E_M~0); 36318#L1091-1 assume !(0 == ~E_1~0); 37057#L1096-1 assume !(0 == ~E_2~0); 37058#L1101-1 assume !(0 == ~E_3~0); 36381#L1106-1 assume !(0 == ~E_4~0); 36382#L1111-1 assume !(0 == ~E_5~0); 36543#L1116-1 assume !(0 == ~E_6~0); 36544#L1121-1 assume !(0 == ~E_7~0); 36374#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36375#L1131-1 assume !(0 == ~E_9~0); 36632#L1136-1 assume !(0 == ~E_10~0); 36742#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36906#L514 assume 1 == ~m_pc~0; 36869#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36395#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36312#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36313#L1285 assume !(0 != activate_threads_~tmp~1#1); 37095#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36034#L533 assume !(1 == ~t1_pc~0); 36035#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36559#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36427#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36428#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 36764#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36765#L552 assume 1 == ~t2_pc~0; 36264#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36265#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36850#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36851#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36409#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36410#L571 assume 1 == ~t3_pc~0; 36592#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36593#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35950#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35951#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36549#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35826#L590 assume !(1 == ~t4_pc~0); 35827#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36603#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36847#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36848#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36801#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36545#L609 assume 1 == ~t5_pc~0; 36546#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37092#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35861#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35862#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36540#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36541#L628 assume !(1 == ~t6_pc~0); 36471#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36470#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37075#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37076#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 36842#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36843#L647 assume 1 == ~t7_pc~0; 36383#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36384#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36670#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36390#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36391#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37128#L666 assume !(1 == ~t8_pc~0); 36164#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36165#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36405#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36568#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36316#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36317#L685 assume 1 == ~t9_pc~0; 37101#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36985#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36977#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36342#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36343#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36705#L704 assume !(1 == ~t10_pc~0); 36334#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36333#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36877#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35882#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 35883#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36128#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 36828#L1154-2 assume !(1 == ~T1_E~0); 36100#L1159-1 assume !(1 == ~T2_E~0); 36101#L1164-1 assume !(1 == ~T3_E~0); 37137#L1169-1 assume !(1 == ~T4_E~0); 37902#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37901#L1179-1 assume !(1 == ~T6_E~0); 37900#L1184-1 assume !(1 == ~T7_E~0); 37899#L1189-1 assume !(1 == ~T8_E~0); 37898#L1194-1 assume !(1 == ~T9_E~0); 37897#L1199-1 assume !(1 == ~T10_E~0); 37894#L1204-1 assume !(1 == ~E_M~0); 37890#L1209-1 assume !(1 == ~E_1~0); 37888#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37886#L1219-1 assume !(1 == ~E_3~0); 37884#L1224-1 assume !(1 == ~E_4~0); 37882#L1229-1 assume !(1 == ~E_5~0); 37881#L1234-1 assume !(1 == ~E_6~0); 37241#L1239-1 assume !(1 == ~E_7~0); 37240#L1244-1 assume !(1 == ~E_8~0); 37239#L1249-1 assume !(1 == ~E_9~0); 37189#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37180#L1259-1 assume { :end_inline_reset_delta_events } true; 37173#L1565-2 [2021-12-15 17:20:39,598 INFO L793 eck$LassoCheckResult]: Loop: 37173#L1565-2 assume !false; 37167#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37162#L1011 assume !false; 37161#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37160#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37149#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37148#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37146#L866 assume !(0 != eval_~tmp~0#1); 37145#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37144#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37142#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37143#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37591#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37588#L1046-3 assume !(0 == ~T3_E~0); 37586#L1051-3 assume !(0 == ~T4_E~0); 37584#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37582#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37580#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37578#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37575#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37573#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37571#L1086-3 assume !(0 == ~E_M~0); 37569#L1091-3 assume !(0 == ~E_1~0); 37567#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37565#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37562#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37560#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37558#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37556#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37554#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37552#L1131-3 assume !(0 == ~E_9~0); 37549#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37547#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37545#L514-36 assume 1 == ~m_pc~0; 37542#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37540#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37538#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37535#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37533#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37531#L533-36 assume 1 == ~t1_pc~0; 37528#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37526#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37524#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37522#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37520#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37519#L552-36 assume !(1 == ~t2_pc~0); 37517#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 37516#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37515#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37514#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37513#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37512#L571-36 assume 1 == ~t3_pc~0; 37510#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37509#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37508#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37507#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37506#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37505#L590-36 assume !(1 == ~t4_pc~0); 37502#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 37500#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37498#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37496#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37494#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37491#L609-36 assume 1 == ~t5_pc~0; 37488#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37486#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37484#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37482#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37480#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37479#L628-36 assume !(1 == ~t6_pc~0); 37475#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 37473#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37471#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37469#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37467#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37465#L647-36 assume 1 == ~t7_pc~0; 37461#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37459#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37457#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37455#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 37453#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37451#L666-36 assume 1 == ~t8_pc~0; 37447#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37445#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37443#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37441#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37439#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37437#L685-36 assume !(1 == ~t9_pc~0); 37433#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 37431#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37429#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37427#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37425#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37423#L704-36 assume 1 == ~t10_pc~0; 37419#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37417#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37415#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37413#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37411#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37409#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37140#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37406#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37404#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37402#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37400#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37398#L1179-3 assume !(1 == ~T6_E~0); 37396#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37394#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37392#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37390#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37389#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37387#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37386#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37384#L1219-3 assume !(1 == ~E_3~0); 37381#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37379#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37377#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37375#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37373#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37371#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37368#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37366#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37343#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37339#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37337#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37335#L1584 assume !(0 == start_simulation_~tmp~3#1); 37133#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37207#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37196#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37194#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 37193#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37192#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37190#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 37181#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 37173#L1565-2 [2021-12-15 17:20:39,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,599 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2021-12-15 17:20:39,599 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754377959] [2021-12-15 17:20:39,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,600 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,629 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754377959] [2021-12-15 17:20:39,630 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754377959] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,631 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,631 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,632 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512904177] [2021-12-15 17:20:39,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,633 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:39,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:39,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1366330151, now seen corresponding path program 1 times [2021-12-15 17:20:39,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:39,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922469903] [2021-12-15 17:20:39,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:39,634 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:39,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:39,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:39,663 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:39,663 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922469903] [2021-12-15 17:20:39,663 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [922469903] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:39,664 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:39,664 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:39,664 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665283595] [2021-12-15 17:20:39,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:39,664 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:39,665 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:39,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:39,665 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:39,665 INFO L87 Difference]: Start difference. First operand 4638 states and 6837 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:39,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:39,864 INFO L93 Difference]: Finished difference Result 8692 states and 12784 transitions. [2021-12-15 17:20:39,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:39,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8692 states and 12784 transitions. [2021-12-15 17:20:39,911 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2021-12-15 17:20:39,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8692 states to 8692 states and 12784 transitions. [2021-12-15 17:20:39,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8692 [2021-12-15 17:20:39,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8692 [2021-12-15 17:20:39,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8692 states and 12784 transitions. [2021-12-15 17:20:39,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:39,981 INFO L681 BuchiCegarLoop]: Abstraction has 8692 states and 12784 transitions. [2021-12-15 17:20:39,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8692 states and 12784 transitions. [2021-12-15 17:20:40,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8692 to 8688. [2021-12-15 17:20:40,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8688 states to 8688 states and 12780 transitions. [2021-12-15 17:20:40,178 INFO L704 BuchiCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2021-12-15 17:20:40,178 INFO L587 BuchiCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2021-12-15 17:20:40,178 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:40,178 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8688 states and 12780 transitions. [2021-12-15 17:20:40,214 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2021-12-15 17:20:40,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:40,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:40,241 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,241 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:40,242 INFO L791 eck$LassoCheckResult]: Stem: 50132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 50133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50357#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49110#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49111#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 50381#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50337#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50338#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50371#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49420#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49421#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49526#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49774#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49704#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49422#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49083#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49084#L1036 assume !(0 == ~M_E~0); 49182#L1036-2 assume !(0 == ~T1_E~0); 50066#L1041-1 assume !(0 == ~T2_E~0); 50067#L1046-1 assume !(0 == ~T3_E~0); 49458#L1051-1 assume !(0 == ~T4_E~0); 49459#L1056-1 assume !(0 == ~T5_E~0); 50214#L1061-1 assume !(0 == ~T6_E~0); 49355#L1066-1 assume !(0 == ~T7_E~0); 49356#L1071-1 assume !(0 == ~T8_E~0); 50197#L1076-1 assume !(0 == ~T9_E~0); 49250#L1081-1 assume !(0 == ~T10_E~0); 49251#L1086-1 assume !(0 == ~E_M~0); 49657#L1091-1 assume !(0 == ~E_1~0); 50385#L1096-1 assume !(0 == ~E_2~0); 50386#L1101-1 assume !(0 == ~E_3~0); 49718#L1106-1 assume !(0 == ~E_4~0); 49719#L1111-1 assume !(0 == ~E_5~0); 49877#L1116-1 assume !(0 == ~E_6~0); 49878#L1121-1 assume !(0 == ~E_7~0); 49711#L1126-1 assume !(0 == ~E_8~0); 49712#L1131-1 assume !(0 == ~E_9~0); 49966#L1136-1 assume !(0 == ~E_10~0); 50075#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50242#L514 assume 1 == ~m_pc~0; 50204#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49731#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49648#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49649#L1285 assume !(0 != activate_threads_~tmp~1#1); 50424#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49375#L533 assume !(1 == ~t1_pc~0); 49376#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49893#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49764#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49765#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 50097#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50098#L552 assume 1 == ~t2_pc~0; 49602#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49603#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50185#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50186#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 49743#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49744#L571 assume 1 == ~t3_pc~0; 49924#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49925#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49288#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49289#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 49883#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49164#L590 assume !(1 == ~t4_pc~0); 49165#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49937#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50181#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50182#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50134#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49879#L609 assume 1 == ~t5_pc~0; 49880#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50422#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49201#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49202#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 49874#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49875#L628 assume !(1 == ~t6_pc~0); 49807#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49806#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50405#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50406#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 50177#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50178#L647 assume 1 == ~t7_pc~0; 49720#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49721#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50001#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49723#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 49724#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50460#L666 assume !(1 == ~t8_pc~0); 49505#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49506#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49742#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49901#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 49654#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49655#L685 assume 1 == ~t9_pc~0; 50432#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50320#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50312#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49680#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 49681#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50038#L704 assume !(1 == ~t10_pc~0); 49672#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49671#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50212#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49220#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 49221#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49469#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 50161#L1154-2 assume !(1 == ~T1_E~0); 49441#L1159-1 assume !(1 == ~T2_E~0); 49442#L1164-1 assume !(1 == ~T3_E~0); 50721#L1169-1 assume !(1 == ~T4_E~0); 50719#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50717#L1179-1 assume !(1 == ~T6_E~0); 50715#L1184-1 assume !(1 == ~T7_E~0); 50714#L1189-1 assume !(1 == ~T8_E~0); 50702#L1194-1 assume !(1 == ~T9_E~0); 50482#L1199-1 assume !(1 == ~T10_E~0); 50483#L1204-1 assume !(1 == ~E_M~0); 50672#L1209-1 assume !(1 == ~E_1~0); 50668#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50664#L1219-1 assume !(1 == ~E_3~0); 50660#L1224-1 assume !(1 == ~E_4~0); 50656#L1229-1 assume !(1 == ~E_5~0); 50650#L1234-1 assume !(1 == ~E_6~0); 50646#L1239-1 assume !(1 == ~E_7~0); 50642#L1244-1 assume !(1 == ~E_8~0); 50549#L1249-1 assume !(1 == ~E_9~0); 50534#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50524#L1259-1 assume { :end_inline_reset_delta_events } true; 50517#L1565-2 [2021-12-15 17:20:40,242 INFO L793 eck$LassoCheckResult]: Loop: 50517#L1565-2 assume !false; 50511#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50506#L1011 assume !false; 50505#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50504#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50493#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50492#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50490#L866 assume !(0 != eval_~tmp~0#1); 50489#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50488#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50486#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50487#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52471#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52469#L1046-3 assume !(0 == ~T3_E~0); 52467#L1051-3 assume !(0 == ~T4_E~0); 52231#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52229#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52228#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52226#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52224#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52010#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52008#L1086-3 assume !(0 == ~E_M~0); 52006#L1091-3 assume !(0 == ~E_1~0); 52004#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52002#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52000#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51843#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51841#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51839#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51837#L1126-3 assume !(0 == ~E_8~0); 51835#L1131-3 assume !(0 == ~E_9~0); 51833#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51830#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51828#L514-36 assume 1 == ~m_pc~0; 51825#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51823#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51822#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51820#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51818#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51816#L533-36 assume 1 == ~t1_pc~0; 51813#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51810#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51808#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51806#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51804#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51802#L552-36 assume !(1 == ~t2_pc~0); 51799#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 51796#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51794#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51792#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49481#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49482#L571-36 assume 1 == ~t3_pc~0; 50274#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49573#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49574#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49695#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51291#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51290#L590-36 assume !(1 == ~t4_pc~0); 51287#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 51285#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51283#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51281#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51279#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51276#L609-36 assume 1 == ~t5_pc~0; 51273#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51271#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51269#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51267#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51265#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51264#L628-36 assume !(1 == ~t6_pc~0); 51262#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 51260#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51257#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51255#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51253#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51251#L647-36 assume 1 == ~t7_pc~0; 51248#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51246#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51243#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51242#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 51240#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51237#L666-36 assume 1 == ~t8_pc~0; 51234#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51232#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51230#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51228#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51226#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51223#L685-36 assume !(1 == ~t9_pc~0); 51220#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 51218#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51216#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51214#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51041#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51039#L704-36 assume 1 == ~t10_pc~0; 51002#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51000#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50998#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50965#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50963#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50961#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50481#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50924#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50921#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50917#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50885#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50883#L1179-3 assume !(1 == ~T6_E~0); 50853#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50851#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50849#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50821#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50758#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50752#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50750#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50748#L1219-3 assume !(1 == ~E_3~0); 50746#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50744#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50742#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50740#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50738#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50735#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50734#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50733#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50724#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50720#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50718#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50716#L1584 assume !(0 == start_simulation_~tmp~3#1); 50471#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50712#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50701#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50683#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 50675#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50550#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50535#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 50525#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 50517#L1565-2 [2021-12-15 17:20:40,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,242 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2021-12-15 17:20:40,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014797844] [2021-12-15 17:20:40,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,276 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,276 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014797844] [2021-12-15 17:20:40,276 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014797844] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,277 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,277 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:40,277 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128516416] [2021-12-15 17:20:40,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,278 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:40,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:40,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1247888677, now seen corresponding path program 1 times [2021-12-15 17:20:40,279 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:40,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228930652] [2021-12-15 17:20:40,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:40,280 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:40,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:40,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:40,323 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:40,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228930652] [2021-12-15 17:20:40,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228930652] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:40,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:40,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:40,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009542917] [2021-12-15 17:20:40,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:40,325 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:40,325 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:40,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:40,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:40,326 INFO L87 Difference]: Start difference. First operand 8688 states and 12780 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:40,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:40,477 INFO L93 Difference]: Finished difference Result 17019 states and 24843 transitions. [2021-12-15 17:20:40,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:40,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17019 states and 24843 transitions. [2021-12-15 17:20:40,567 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16793 [2021-12-15 17:20:40,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17019 states to 17019 states and 24843 transitions. [2021-12-15 17:20:40,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17019 [2021-12-15 17:20:40,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17019 [2021-12-15 17:20:40,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17019 states and 24843 transitions. [2021-12-15 17:20:40,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:40,672 INFO L681 BuchiCegarLoop]: Abstraction has 17019 states and 24843 transitions. [2021-12-15 17:20:40,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17019 states and 24843 transitions. [2021-12-15 17:20:41,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17019 to 16411. [2021-12-15 17:20:41,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16411 states, 16411 states have (on average 1.4616415818658217) internal successors, (23987), 16410 states have internal predecessors, (23987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16411 states to 16411 states and 23987 transitions. [2021-12-15 17:20:41,080 INFO L704 BuchiCegarLoop]: Abstraction has 16411 states and 23987 transitions. [2021-12-15 17:20:41,080 INFO L587 BuchiCegarLoop]: Abstraction has 16411 states and 23987 transitions. [2021-12-15 17:20:41,080 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:41,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16411 states and 23987 transitions. [2021-12-15 17:20:41,144 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16185 [2021-12-15 17:20:41,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:41,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:41,146 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:41,146 INFO L791 eck$LassoCheckResult]: Stem: 75913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76208#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74826#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74827#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 76240#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76178#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76179#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76225#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75140#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75141#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75257#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75512#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75440#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75142#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74797#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74798#L1036 assume !(0 == ~M_E~0); 74896#L1036-2 assume !(0 == ~T1_E~0); 75836#L1041-1 assume !(0 == ~T2_E~0); 75837#L1046-1 assume !(0 == ~T3_E~0); 75183#L1051-1 assume !(0 == ~T4_E~0); 75184#L1056-1 assume !(0 == ~T5_E~0); 76005#L1061-1 assume !(0 == ~T6_E~0); 75070#L1066-1 assume !(0 == ~T7_E~0); 75071#L1071-1 assume !(0 == ~T8_E~0); 75987#L1076-1 assume !(0 == ~T9_E~0); 74963#L1081-1 assume !(0 == ~T10_E~0); 74964#L1086-1 assume !(0 == ~E_M~0); 75394#L1091-1 assume !(0 == ~E_1~0); 76244#L1096-1 assume !(0 == ~E_2~0); 76245#L1101-1 assume !(0 == ~E_3~0); 75454#L1106-1 assume !(0 == ~E_4~0); 75455#L1111-1 assume !(0 == ~E_5~0); 75620#L1116-1 assume !(0 == ~E_6~0); 75621#L1121-1 assume !(0 == ~E_7~0); 75447#L1126-1 assume !(0 == ~E_8~0); 75448#L1131-1 assume !(0 == ~E_9~0); 75716#L1136-1 assume !(0 == ~E_10~0); 75849#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76044#L514 assume !(1 == ~m_pc~0); 76045#L514-2 is_master_triggered_~__retres1~0#1 := 0; 75468#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75387#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75388#L1285 assume !(0 != activate_threads_~tmp~1#1); 76308#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75093#L533 assume !(1 == ~t1_pc~0); 75094#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75636#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75503#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75504#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 75875#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75876#L552 assume 1 == ~t2_pc~0; 75337#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75338#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75972#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75973#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 75484#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75485#L571 assume 1 == ~t3_pc~0; 75673#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75674#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75004#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75005#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 75626#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74880#L590 assume !(1 == ~t4_pc~0); 74881#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75684#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75969#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75970#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75915#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75622#L609 assume 1 == ~t5_pc~0; 75623#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76302#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74915#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74916#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 75616#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75617#L628 assume !(1 == ~t6_pc~0); 75547#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75546#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76275#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76276#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 75964#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75965#L647 assume 1 == ~t7_pc~0; 75456#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75457#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75761#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75463#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 75464#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76378#L666 assume !(1 == ~t8_pc~0); 75236#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75237#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75479#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75645#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 75391#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75392#L685 assume 1 == ~t9_pc~0; 76318#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76156#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76148#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75416#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 75417#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75804#L704 assume !(1 == ~t10_pc~0); 75409#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75408#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76003#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74935#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 74936#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75193#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 75946#L1154-2 assume !(1 == ~T1_E~0); 79646#L1159-1 assume !(1 == ~T2_E~0); 76432#L1164-1 assume !(1 == ~T3_E~0); 75642#L1169-1 assume !(1 == ~T4_E~0); 75507#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75306#L1179-1 assume !(1 == ~T6_E~0); 75146#L1184-1 assume !(1 == ~T7_E~0); 75147#L1189-1 assume !(1 == ~T8_E~0); 79542#L1194-1 assume !(1 == ~T9_E~0); 79540#L1199-1 assume !(1 == ~T10_E~0); 79538#L1204-1 assume !(1 == ~E_M~0); 79535#L1209-1 assume !(1 == ~E_1~0); 79217#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 78884#L1219-1 assume !(1 == ~E_3~0); 78693#L1224-1 assume !(1 == ~E_4~0); 78691#L1229-1 assume !(1 == ~E_5~0); 78689#L1234-1 assume !(1 == ~E_6~0); 78687#L1239-1 assume !(1 == ~E_7~0); 77570#L1244-1 assume !(1 == ~E_8~0); 77567#L1249-1 assume !(1 == ~E_9~0); 77546#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77530#L1259-1 assume { :end_inline_reset_delta_events } true; 77518#L1565-2 [2021-12-15 17:20:41,147 INFO L793 eck$LassoCheckResult]: Loop: 77518#L1565-2 assume !false; 77511#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77505#L1011 assume !false; 77504#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77492#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77480#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77478#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77473#L866 assume !(0 != eval_~tmp~0#1); 77475#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78700#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77468#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77469#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86994#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86992#L1046-3 assume !(0 == ~T3_E~0); 84955#L1051-3 assume !(0 == ~T4_E~0); 84952#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 84950#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 84948#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 84946#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 84944#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 84942#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 84939#L1086-3 assume !(0 == ~E_M~0); 84937#L1091-3 assume !(0 == ~E_1~0); 84935#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 84933#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84931#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 84929#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83345#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83343#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 83341#L1126-3 assume !(0 == ~E_8~0); 83004#L1131-3 assume !(0 == ~E_9~0); 83002#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 83000#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82998#L514-36 assume !(1 == ~m_pc~0); 82996#L514-38 is_master_triggered_~__retres1~0#1 := 0; 82993#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82991#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82989#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 82986#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82442#L533-36 assume 1 == ~t1_pc~0; 82439#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 82437#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82435#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82433#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82432#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82431#L552-36 assume !(1 == ~t2_pc~0); 82429#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 82428#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82427#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82425#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82422#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82420#L571-36 assume 1 == ~t3_pc~0; 82007#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 82005#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82002#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82000#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81998#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81848#L590-36 assume !(1 == ~t4_pc~0); 81845#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 81843#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81841#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81839#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81838#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81679#L609-36 assume !(1 == ~t5_pc~0); 81677#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 81522#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81520#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81519#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81514#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81513#L628-36 assume !(1 == ~t6_pc~0); 81385#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 81383#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81381#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81376#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 81375#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81374#L647-36 assume 1 == ~t7_pc~0; 81369#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81367#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81365#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81364#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 81363#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81198#L666-36 assume !(1 == ~t8_pc~0); 81195#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 81192#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81190#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81188#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81186#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81184#L685-36 assume !(1 == ~t9_pc~0); 81179#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 81177#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81175#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81173#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 81171#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81168#L704-36 assume 1 == ~t10_pc~0; 81165#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 81163#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81161#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81159#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81157#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81155#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76446#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81153#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81150#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81146#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81144#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81142#L1179-3 assume !(1 == ~T6_E~0); 81140#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81138#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 81136#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81134#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81133#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81127#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81125#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81123#L1219-3 assume !(1 == ~E_3~0); 81122#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80898#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80897#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80896#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 79549#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 79546#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 79545#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 79544#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 79234#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 79228#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 79226#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 79224#L1584 assume !(0 == start_simulation_~tmp~3#1); 76417#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 78898#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 78887#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 78886#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 78694#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77572#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77550#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77531#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 77518#L1565-2 [2021-12-15 17:20:41,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,148 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2021-12-15 17:20:41,148 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897132553] [2021-12-15 17:20:41,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,148 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,177 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897132553] [2021-12-15 17:20:41,177 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897132553] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,177 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,178 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,178 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443819882] [2021-12-15 17:20:41,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,178 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:41,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:41,179 INFO L85 PathProgramCache]: Analyzing trace with hash -212012834, now seen corresponding path program 1 times [2021-12-15 17:20:41,179 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:41,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815752164] [2021-12-15 17:20:41,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:41,179 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:41,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:41,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:41,208 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:41,208 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815752164] [2021-12-15 17:20:41,208 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815752164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:41,209 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:41,209 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:41,209 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291132238] [2021-12-15 17:20:41,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:41,210 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:41,210 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:41,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:41,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:41,211 INFO L87 Difference]: Start difference. First operand 16411 states and 23987 transitions. cyclomatic complexity: 7592 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:41,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:41,612 INFO L93 Difference]: Finished difference Result 45557 states and 65961 transitions. [2021-12-15 17:20:41,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:41,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45557 states and 65961 transitions. [2021-12-15 17:20:42,006 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45173 [2021-12-15 17:20:42,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45557 states to 45557 states and 65961 transitions. [2021-12-15 17:20:42,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45557 [2021-12-15 17:20:42,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45557 [2021-12-15 17:20:42,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45557 states and 65961 transitions. [2021-12-15 17:20:42,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:42,475 INFO L681 BuchiCegarLoop]: Abstraction has 45557 states and 65961 transitions. [2021-12-15 17:20:42,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45557 states and 65961 transitions. [2021-12-15 17:20:43,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45557 to 44437. [2021-12-15 17:20:43,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44437 states, 44437 states have (on average 1.4498053423948511) internal successors, (64425), 44436 states have internal predecessors, (64425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44437 states to 44437 states and 64425 transitions. [2021-12-15 17:20:43,331 INFO L704 BuchiCegarLoop]: Abstraction has 44437 states and 64425 transitions. [2021-12-15 17:20:43,332 INFO L587 BuchiCegarLoop]: Abstraction has 44437 states and 64425 transitions. [2021-12-15 17:20:43,332 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:43,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44437 states and 64425 transitions. [2021-12-15 17:20:43,466 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44149 [2021-12-15 17:20:43,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,468 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,468 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,468 INFO L791 eck$LassoCheckResult]: Stem: 137870#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 137871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 138136#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 136802#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 136803#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 138171#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 138107#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 138108#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 138156#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 137106#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 137107#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 137213#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 137467#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 137395#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 137108#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 136775#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 136776#L1036 assume !(0 == ~M_E~0); 136873#L1036-2 assume !(0 == ~T1_E~0); 137793#L1041-1 assume !(0 == ~T2_E~0); 137794#L1046-1 assume !(0 == ~T3_E~0); 137145#L1051-1 assume !(0 == ~T4_E~0); 137146#L1056-1 assume !(0 == ~T5_E~0); 137960#L1061-1 assume !(0 == ~T6_E~0); 137045#L1066-1 assume !(0 == ~T7_E~0); 137046#L1071-1 assume !(0 == ~T8_E~0); 137941#L1076-1 assume !(0 == ~T9_E~0); 136940#L1081-1 assume !(0 == ~T10_E~0); 136941#L1086-1 assume !(0 == ~E_M~0); 137348#L1091-1 assume !(0 == ~E_1~0); 138178#L1096-1 assume !(0 == ~E_2~0); 138179#L1101-1 assume !(0 == ~E_3~0); 137410#L1106-1 assume !(0 == ~E_4~0); 137411#L1111-1 assume !(0 == ~E_5~0); 137582#L1116-1 assume !(0 == ~E_6~0); 137583#L1121-1 assume !(0 == ~E_7~0); 137403#L1126-1 assume !(0 == ~E_8~0); 137404#L1131-1 assume !(0 == ~E_9~0); 137682#L1136-1 assume !(0 == ~E_10~0); 137806#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137992#L514 assume !(1 == ~m_pc~0); 137993#L514-2 is_master_triggered_~__retres1~0#1 := 0; 137424#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137338#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 137339#L1285 assume !(0 != activate_threads_~tmp~1#1); 138227#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137063#L533 assume !(1 == ~t1_pc~0); 137064#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 137638#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137456#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 137457#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 137834#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137835#L552 assume !(1 == ~t2_pc~0); 137539#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 137540#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137926#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137927#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 137438#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137439#L571 assume 1 == ~t3_pc~0; 137632#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 137633#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136980#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136981#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 137588#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136855#L590 assume !(1 == ~t4_pc~0); 136856#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 137647#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137923#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 137924#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 137872#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137584#L609 assume 1 == ~t5_pc~0; 137585#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 138225#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136892#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 136893#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 137577#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137578#L628 assume !(1 == ~t6_pc~0); 137502#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 137501#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138204#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138205#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 137918#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137919#L647 assume 1 == ~t7_pc~0; 137412#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 137413#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137719#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137417#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 137418#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138286#L666 assume !(1 == ~t8_pc~0); 137193#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 137194#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137434#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 137608#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 137345#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 137346#L685 assume 1 == ~t9_pc~0; 138237#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 138091#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 138080#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 137370#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 137371#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 137758#L704 assume !(1 == ~t10_pc~0); 137363#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 137362#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 137958#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 136910#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 136911#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137156#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 137902#L1154-2 assume !(1 == ~T1_E~0); 137127#L1159-1 assume !(1 == ~T2_E~0); 137128#L1164-1 assume !(1 == ~T3_E~0); 137605#L1169-1 assume !(1 == ~T4_E~0); 137462#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137260#L1179-1 assume !(1 == ~T6_E~0); 137113#L1184-1 assume !(1 == ~T7_E~0); 137114#L1189-1 assume !(1 == ~T8_E~0); 137191#L1194-1 assume !(1 == ~T9_E~0); 137334#L1199-1 assume !(1 == ~T10_E~0); 137277#L1204-1 assume !(1 == ~E_M~0); 137278#L1209-1 assume !(1 == ~E_1~0); 157593#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 157592#L1219-1 assume !(1 == ~E_3~0); 157591#L1224-1 assume !(1 == ~E_4~0); 137627#L1229-1 assume !(1 == ~E_5~0); 137000#L1234-1 assume !(1 == ~E_6~0); 137001#L1239-1 assume !(1 == ~E_7~0); 137059#L1244-1 assume !(1 == ~E_8~0); 137060#L1249-1 assume !(1 == ~E_9~0); 137946#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 136903#L1259-1 assume { :end_inline_reset_delta_events } true; 136904#L1565-2 [2021-12-15 17:20:43,469 INFO L793 eck$LassoCheckResult]: Loop: 136904#L1565-2 assume !false; 137873#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 137296#L1011 assume !false; 137297#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 137350#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 137097#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 138061#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 137124#L866 assume !(0 != eval_~tmp~0#1); 137126#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 179198#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 179197#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 179196#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 179195#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 179193#L1046-3 assume !(0 == ~T3_E~0); 179191#L1051-3 assume !(0 == ~T4_E~0); 179189#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 178623#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 178622#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 178621#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 178620#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 178619#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 178618#L1086-3 assume !(0 == ~E_M~0); 178617#L1091-3 assume !(0 == ~E_1~0); 178616#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 178615#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 178614#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 178613#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 178611#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 178609#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 178608#L1126-3 assume !(0 == ~E_8~0); 178606#L1131-3 assume !(0 == ~E_9~0); 178605#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 178604#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178603#L514-36 assume !(1 == ~m_pc~0); 178602#L514-38 is_master_triggered_~__retres1~0#1 := 0; 178601#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178600#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 178599#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 178598#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178597#L533-36 assume !(1 == ~t1_pc~0); 178596#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 178595#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178594#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 178593#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 178591#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178589#L552-36 assume !(1 == ~t2_pc~0); 178587#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 178585#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178583#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 178581#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 178579#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178577#L571-36 assume 1 == ~t3_pc~0; 178574#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 178571#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 178569#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 178567#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 178565#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178563#L590-36 assume !(1 == ~t4_pc~0); 178560#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 178557#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178555#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 178553#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 178551#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 178549#L609-36 assume 1 == ~t5_pc~0; 178546#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 178543#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178541#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 178539#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 178537#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 178535#L628-36 assume !(1 == ~t6_pc~0); 178532#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 178529#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 178527#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 178525#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 178523#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 178521#L647-36 assume 1 == ~t7_pc~0; 178518#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 178515#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 178513#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 178511#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 178509#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 178507#L666-36 assume 1 == ~t8_pc~0; 178504#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 178501#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 178499#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 178497#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 178495#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 178493#L685-36 assume !(1 == ~t9_pc~0); 178490#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 178487#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 178485#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 178483#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 178481#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 178479#L704-36 assume 1 == ~t10_pc~0; 178476#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 178473#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 178472#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 178471#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 137047#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137048#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 138135#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 137969#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 137970#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138218#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137359#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137360#L1179-3 assume !(1 == ~T6_E~0); 138093#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 136926#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 136927#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 137300#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 137301#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 137622#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 136794#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 136795#L1219-3 assume !(1 == ~E_3~0); 137847#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 137848#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 137869#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 137061#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 137062#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 137673#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 138146#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 137852#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 137853#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 136871#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 137640#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 137641#L1584 assume !(0 == start_simulation_~tmp~3#1); 137789#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 178664#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 178653#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 178651#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 178649#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 178647#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 178646#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 178645#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 136904#L1565-2 [2021-12-15 17:20:43,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,469 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2021-12-15 17:20:43,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294854509] [2021-12-15 17:20:43,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,470 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,504 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294854509] [2021-12-15 17:20:43,505 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294854509] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,505 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532553508] [2021-12-15 17:20:43,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,506 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:43,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,506 INFO L85 PathProgramCache]: Analyzing trace with hash 1890010397, now seen corresponding path program 1 times [2021-12-15 17:20:43,506 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349658182] [2021-12-15 17:20:43,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,507 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,541 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349658182] [2021-12-15 17:20:43,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349658182] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,542 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,542 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689571096] [2021-12-15 17:20:43,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,543 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:43,543 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:43,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:43,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:43,544 INFO L87 Difference]: Start difference. First operand 44437 states and 64425 transitions. cyclomatic complexity: 20020 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,400 INFO L93 Difference]: Finished difference Result 124414 states and 179052 transitions. [2021-12-15 17:20:44,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:44,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124414 states and 179052 transitions. [2021-12-15 17:20:45,622 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123647 [2021-12-15 17:20:46,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124414 states to 124414 states and 179052 transitions. [2021-12-15 17:20:46,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124414 [2021-12-15 17:20:46,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124414 [2021-12-15 17:20:46,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124414 states and 179052 transitions. [2021-12-15 17:20:46,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:46,323 INFO L681 BuchiCegarLoop]: Abstraction has 124414 states and 179052 transitions. [2021-12-15 17:20:46,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124414 states and 179052 transitions. [2021-12-15 17:20:47,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124414 to 121358. [2021-12-15 17:20:47,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121358 states, 121358 states have (on average 1.4408609238781127) internal successors, (174860), 121357 states have internal predecessors, (174860), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:48,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121358 states to 121358 states and 174860 transitions. [2021-12-15 17:20:48,402 INFO L704 BuchiCegarLoop]: Abstraction has 121358 states and 174860 transitions. [2021-12-15 17:20:48,402 INFO L587 BuchiCegarLoop]: Abstraction has 121358 states and 174860 transitions. [2021-12-15 17:20:48,402 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:48,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121358 states and 174860 transitions. [2021-12-15 17:20:48,919 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 120911 [2021-12-15 17:20:48,919 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:48,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:48,921 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:48,921 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:48,921 INFO L791 eck$LassoCheckResult]: Stem: 306705#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 306706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 306956#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 305665#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 305666#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 306987#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 306937#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 306938#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 306971#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 305971#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 305972#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 306079#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 306324#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 306252#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 305973#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 305636#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 305637#L1036 assume !(0 == ~M_E~0); 305734#L1036-2 assume !(0 == ~T1_E~0); 306633#L1041-1 assume !(0 == ~T2_E~0); 306634#L1046-1 assume !(0 == ~T3_E~0); 306012#L1051-1 assume !(0 == ~T4_E~0); 306013#L1056-1 assume !(0 == ~T5_E~0); 306792#L1061-1 assume !(0 == ~T6_E~0); 305906#L1066-1 assume !(0 == ~T7_E~0); 305907#L1071-1 assume !(0 == ~T8_E~0); 306773#L1076-1 assume !(0 == ~T9_E~0); 305803#L1081-1 assume !(0 == ~T10_E~0); 305804#L1086-1 assume !(0 == ~E_M~0); 306206#L1091-1 assume !(0 == ~E_1~0); 306997#L1096-1 assume !(0 == ~E_2~0); 306998#L1101-1 assume !(0 == ~E_3~0); 306266#L1106-1 assume !(0 == ~E_4~0); 306267#L1111-1 assume !(0 == ~E_5~0); 306433#L1116-1 assume !(0 == ~E_6~0); 306434#L1121-1 assume !(0 == ~E_7~0); 306259#L1126-1 assume !(0 == ~E_8~0); 306260#L1131-1 assume !(0 == ~E_9~0); 306529#L1136-1 assume !(0 == ~E_10~0); 306644#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 306820#L514 assume !(1 == ~m_pc~0); 306821#L514-2 is_master_triggered_~__retres1~0#1 := 0; 306280#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 306197#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 306198#L1285 assume !(0 != activate_threads_~tmp~1#1); 307047#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 305926#L533 assume !(1 == ~t1_pc~0); 305927#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 306489#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 306315#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 306316#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 306668#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 306669#L552 assume !(1 == ~t2_pc~0); 306393#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 306394#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 306759#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 306760#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 306297#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 306298#L571 assume !(1 == ~t3_pc~0); 306503#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 306575#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 305842#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 305843#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 306440#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 305718#L590 assume !(1 == ~t4_pc~0); 305719#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 306496#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 306753#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 306754#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 306707#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 306435#L609 assume 1 == ~t5_pc~0; 306436#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 307042#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 305753#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 305754#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 306428#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 306429#L628 assume !(1 == ~t6_pc~0); 306359#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 306358#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 307025#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 307026#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 306748#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 306749#L647 assume 1 == ~t7_pc~0; 306268#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 306269#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 306567#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 306273#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 306274#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 307095#L666 assume !(1 == ~t8_pc~0); 306058#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 306059#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306290#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 306462#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 306204#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 306205#L685 assume 1 == ~t9_pc~0; 307054#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 306920#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 306908#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 306228#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 306229#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 306603#L704 assume !(1 == ~t10_pc~0); 306221#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 306220#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 306790#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 305775#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 305776#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306021#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 306734#L1154-2 assume !(1 == ~T1_E~0); 307078#L1159-1 assume !(1 == ~T2_E~0); 307123#L1164-1 assume !(1 == ~T3_E~0); 306458#L1169-1 assume !(1 == ~T4_E~0); 306319#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 306124#L1179-1 assume !(1 == ~T6_E~0); 305978#L1184-1 assume !(1 == ~T7_E~0); 305979#L1189-1 assume !(1 == ~T8_E~0); 306056#L1194-1 assume !(1 == ~T9_E~0); 306193#L1199-1 assume !(1 == ~T10_E~0); 306139#L1204-1 assume !(1 == ~E_M~0); 306140#L1209-1 assume !(1 == ~E_1~0); 306699#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 306700#L1219-1 assume !(1 == ~E_3~0); 307079#L1224-1 assume !(1 == ~E_4~0); 306480#L1229-1 assume !(1 == ~E_5~0); 305862#L1234-1 assume !(1 == ~E_6~0); 305863#L1239-1 assume !(1 == ~E_7~0); 305920#L1244-1 assume !(1 == ~E_8~0); 305921#L1249-1 assume !(1 == ~E_9~0); 306780#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 305767#L1259-1 assume { :end_inline_reset_delta_events } true; 305768#L1565-2 [2021-12-15 17:20:48,922 INFO L793 eck$LassoCheckResult]: Loop: 305768#L1565-2 assume !false; 406708#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 421589#L1011 assume !false; 421588#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 421587#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 421576#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 406664#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 406660#L866 assume !(0 != eval_~tmp~0#1); 406661#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 423083#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 423082#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 423081#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 423080#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 423079#L1046-3 assume !(0 == ~T3_E~0); 423078#L1051-3 assume !(0 == ~T4_E~0); 423077#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 423076#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 423075#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 423074#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 423073#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 423072#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 423071#L1086-3 assume !(0 == ~E_M~0); 423070#L1091-3 assume !(0 == ~E_1~0); 423069#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 423068#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 423067#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 423066#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 423065#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 423064#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 423063#L1126-3 assume !(0 == ~E_8~0); 423062#L1131-3 assume !(0 == ~E_9~0); 423061#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 423060#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 423059#L514-36 assume !(1 == ~m_pc~0); 423058#L514-38 is_master_triggered_~__retres1~0#1 := 0; 423057#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 423056#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 423055#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 423054#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 423053#L533-36 assume !(1 == ~t1_pc~0); 423052#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 423051#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 423050#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 423049#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 423048#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 423047#L552-36 assume !(1 == ~t2_pc~0); 423046#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 423045#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423044#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 423043#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 423042#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 423041#L571-36 assume !(1 == ~t3_pc~0); 423040#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 423039#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 423038#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 423037#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 423036#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 423035#L590-36 assume 1 == ~t4_pc~0; 423034#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 423032#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 423031#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 423030#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 423029#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423028#L609-36 assume 1 == ~t5_pc~0; 423026#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 423025#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 423024#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 423023#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 423022#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 423021#L628-36 assume 1 == ~t6_pc~0; 423020#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 423018#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 423017#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 423016#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 423015#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 423014#L647-36 assume 1 == ~t7_pc~0; 423012#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 423011#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 423010#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 423009#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 423008#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 423007#L666-36 assume !(1 == ~t8_pc~0); 423006#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 423004#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 423003#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 423002#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 423001#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 423000#L685-36 assume !(1 == ~t9_pc~0); 422998#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 422997#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 422996#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 422995#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 422994#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 422993#L704-36 assume !(1 == ~t10_pc~0); 422992#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 422990#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 422989#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 422988#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 422987#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422986#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 369814#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 422985#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 422984#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 403537#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 422983#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 422982#L1179-3 assume !(1 == ~T6_E~0); 422981#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 422980#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 422979#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 422978#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 422977#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 406140#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 422976#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 422975#L1219-3 assume !(1 == ~E_3~0); 422974#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 422973#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 422972#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 422971#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 422970#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 385443#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 422969#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 407101#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 407102#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 407062#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 407063#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 407041#L1584 assume !(0 == start_simulation_~tmp~3#1); 407040#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 406752#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 406741#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 406739#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 406737#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 406736#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 406732#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 406719#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 305768#L1565-2 [2021-12-15 17:20:48,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:48,922 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2021-12-15 17:20:48,923 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:48,923 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675347029] [2021-12-15 17:20:48,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:48,923 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:48,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:48,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:48,960 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:48,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675347029] [2021-12-15 17:20:48,961 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675347029] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:48,961 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:48,961 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:48,961 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958778442] [2021-12-15 17:20:48,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:48,962 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:48,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:48,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1195580446, now seen corresponding path program 1 times [2021-12-15 17:20:48,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:48,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375139917] [2021-12-15 17:20:48,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:48,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:48,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:48,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:48,994 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:48,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375139917] [2021-12-15 17:20:48,995 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1375139917] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:48,995 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:48,995 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:48,995 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291463423] [2021-12-15 17:20:48,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:48,996 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:48,996 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:48,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:48,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:48,997 INFO L87 Difference]: Start difference. First operand 121358 states and 174860 transitions. cyclomatic complexity: 53566 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:50,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:50,685 INFO L93 Difference]: Finished difference Result 320148 states and 463610 transitions. [2021-12-15 17:20:50,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:50,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 320148 states and 463610 transitions. [2021-12-15 17:20:52,221 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 318942 [2021-12-15 17:20:53,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 320148 states to 320148 states and 463610 transitions. [2021-12-15 17:20:53,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 320148 [2021-12-15 17:20:53,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 320148 [2021-12-15 17:20:53,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 320148 states and 463610 transitions. [2021-12-15 17:20:53,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:53,628 INFO L681 BuchiCegarLoop]: Abstraction has 320148 states and 463610 transitions. [2021-12-15 17:20:53,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320148 states and 463610 transitions. [2021-12-15 17:20:55,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320148 to 125135. [2021-12-15 17:20:55,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125135 states, 125135 states have (on average 1.4275542414192672) internal successors, (178637), 125134 states have internal predecessors, (178637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125135 states to 125135 states and 178637 transitions. [2021-12-15 17:20:56,089 INFO L704 BuchiCegarLoop]: Abstraction has 125135 states and 178637 transitions. [2021-12-15 17:20:56,089 INFO L587 BuchiCegarLoop]: Abstraction has 125135 states and 178637 transitions. [2021-12-15 17:20:56,090 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:56,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125135 states and 178637 transitions. [2021-12-15 17:20:56,442 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124685 [2021-12-15 17:20:56,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:56,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:56,445 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,445 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,445 INFO L791 eck$LassoCheckResult]: Stem: 748256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 748257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 748541#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 747184#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 747185#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 748579#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 748513#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 748514#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 748565#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 747491#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 747492#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 747603#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 747860#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 747788#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 747493#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 747155#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 747156#L1036 assume !(0 == ~M_E~0); 747253#L1036-2 assume !(0 == ~T1_E~0); 748179#L1041-1 assume !(0 == ~T2_E~0); 748180#L1046-1 assume !(0 == ~T3_E~0); 747532#L1051-1 assume !(0 == ~T4_E~0); 747533#L1056-1 assume !(0 == ~T5_E~0); 748344#L1061-1 assume !(0 == ~T6_E~0); 747424#L1066-1 assume !(0 == ~T7_E~0); 747425#L1071-1 assume !(0 == ~T8_E~0); 748324#L1076-1 assume !(0 == ~T9_E~0); 747321#L1081-1 assume !(0 == ~T10_E~0); 747322#L1086-1 assume !(0 == ~E_M~0); 747742#L1091-1 assume !(0 == ~E_1~0); 748588#L1096-1 assume !(0 == ~E_2~0); 748589#L1101-1 assume !(0 == ~E_3~0); 747802#L1106-1 assume !(0 == ~E_4~0); 747803#L1111-1 assume !(0 == ~E_5~0); 747976#L1116-1 assume !(0 == ~E_6~0); 747977#L1121-1 assume !(0 == ~E_7~0); 747795#L1126-1 assume !(0 == ~E_8~0); 747796#L1131-1 assume !(0 == ~E_9~0); 748070#L1136-1 assume !(0 == ~E_10~0); 748189#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 748375#L514 assume !(1 == ~m_pc~0); 748376#L514-2 is_master_triggered_~__retres1~0#1 := 0; 747816#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 747732#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 747733#L1285 assume !(0 != activate_threads_~tmp~1#1); 748641#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 747445#L533 assume !(1 == ~t1_pc~0); 747446#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 748029#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 747850#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 747851#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 748219#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 748220#L552 assume !(1 == ~t2_pc~0); 747934#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 747935#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 748310#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 748311#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 747832#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 747833#L571 assume !(1 == ~t3_pc~0); 748045#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 748122#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 747360#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 747361#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 747982#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 747237#L590 assume !(1 == ~t4_pc~0); 747238#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 748043#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 748730#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 748643#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 748258#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 747978#L609 assume 1 == ~t5_pc~0; 747979#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 748636#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 747272#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 747273#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 747973#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 747974#L628 assume !(1 == ~t6_pc~0); 747898#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 747897#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 748611#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 748612#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 748299#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 748300#L647 assume 1 == ~t7_pc~0; 747804#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 747805#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 748110#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 747811#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 747812#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 748703#L666 assume !(1 == ~t8_pc~0); 747582#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 747583#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 747826#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 748001#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 747738#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 747739#L685 assume 1 == ~t9_pc~0; 748650#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 748495#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 748482#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 747763#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 747764#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 748150#L704 assume !(1 == ~t10_pc~0); 747756#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 747755#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 748341#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 747293#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 747294#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 747542#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 748285#L1154-2 assume !(1 == ~T1_E~0); 748675#L1159-1 assume !(1 == ~T2_E~0); 748739#L1164-1 assume !(1 == ~T3_E~0); 747998#L1169-1 assume !(1 == ~T4_E~0); 747855#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 747652#L1179-1 assume !(1 == ~T6_E~0); 747498#L1184-1 assume !(1 == ~T7_E~0); 747499#L1189-1 assume !(1 == ~T8_E~0); 747580#L1194-1 assume !(1 == ~T9_E~0); 747724#L1199-1 assume !(1 == ~T10_E~0); 747667#L1204-1 assume !(1 == ~E_M~0); 747668#L1209-1 assume !(1 == ~E_1~0); 748700#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 748737#L1219-1 assume !(1 == ~E_3~0); 748738#L1224-1 assume !(1 == ~E_4~0); 748021#L1229-1 assume !(1 == ~E_5~0); 747380#L1234-1 assume !(1 == ~E_6~0); 747381#L1239-1 assume !(1 == ~E_7~0); 801321#L1244-1 assume !(1 == ~E_8~0); 747439#L1249-1 assume !(1 == ~E_9~0); 801265#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 747286#L1259-1 assume { :end_inline_reset_delta_events } true; 747287#L1565-2 [2021-12-15 17:20:56,445 INFO L793 eck$LassoCheckResult]: Loop: 747287#L1565-2 assume !false; 804060#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 804053#L1011 assume !false; 804051#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 804049#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 804026#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 804023#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 804018#L866 assume !(0 != eval_~tmp~0#1); 804019#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 804383#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 804381#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 804379#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 804377#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 804374#L1046-3 assume !(0 == ~T3_E~0); 804372#L1051-3 assume !(0 == ~T4_E~0); 804370#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 804368#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 804366#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 804364#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 804361#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 804359#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 804357#L1086-3 assume !(0 == ~E_M~0); 804355#L1091-3 assume !(0 == ~E_1~0); 804353#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 804351#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 804348#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 804347#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 804346#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 804345#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 804344#L1126-3 assume !(0 == ~E_8~0); 804343#L1131-3 assume !(0 == ~E_9~0); 804342#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 804341#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 804340#L514-36 assume !(1 == ~m_pc~0); 804339#L514-38 is_master_triggered_~__retres1~0#1 := 0; 804338#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804337#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 804336#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 804335#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 804334#L533-36 assume !(1 == ~t1_pc~0); 804333#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 804332#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804331#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 804330#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 804329#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 804328#L552-36 assume !(1 == ~t2_pc~0); 804327#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 804326#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 804325#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 804324#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 804323#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 804322#L571-36 assume !(1 == ~t3_pc~0); 804321#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 804320#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 804319#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 804318#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 804317#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 804316#L590-36 assume 1 == ~t4_pc~0; 804314#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 804312#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 804310#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 804308#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 804306#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 804304#L609-36 assume 1 == ~t5_pc~0; 804301#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 804299#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 804297#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 804294#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 804292#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 804290#L628-36 assume !(1 == ~t6_pc~0); 804287#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 804285#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 804283#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 804280#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 804278#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 804276#L647-36 assume 1 == ~t7_pc~0; 804273#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 804271#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 804270#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 804269#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 804265#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 804263#L666-36 assume 1 == ~t8_pc~0; 804260#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 804259#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 804258#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 804257#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 804256#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 804255#L685-36 assume 1 == ~t9_pc~0; 804252#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 804249#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 804247#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 804245#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 804243#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 804241#L704-36 assume 1 == ~t10_pc~0; 804237#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 804235#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 804233#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 804231#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 804229#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 804227#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 772656#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 804223#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 804221#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 800753#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 804218#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 804216#L1179-3 assume !(1 == ~T6_E~0); 804214#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 804212#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 804210#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 804208#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 804206#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 793081#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 804203#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 804201#L1219-3 assume !(1 == ~E_3~0); 804199#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 804197#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 804195#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 804193#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 804191#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 801688#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 804188#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 804186#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 804117#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 804113#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 804111#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 804109#L1584 assume !(0 == start_simulation_~tmp~3#1); 804095#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 804080#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 804069#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 804067#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 804065#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 804063#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 804062#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 804061#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 747287#L1565-2 [2021-12-15 17:20:56,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,446 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2021-12-15 17:20:56,446 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1695153979] [2021-12-15 17:20:56,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,478 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1695153979] [2021-12-15 17:20:56,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1695153979] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,479 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,479 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,479 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532233337] [2021-12-15 17:20:56,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,479 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:56,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,480 INFO L85 PathProgramCache]: Analyzing trace with hash -69348644, now seen corresponding path program 1 times [2021-12-15 17:20:56,480 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781037405] [2021-12-15 17:20:56,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,510 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781037405] [2021-12-15 17:20:56,510 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1781037405] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,510 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,510 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924090680] [2021-12-15 17:20:56,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,511 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:56,511 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:56,512 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:56,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:56,512 INFO L87 Difference]: Start difference. First operand 125135 states and 178637 transitions. cyclomatic complexity: 53566 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:58,145 INFO L93 Difference]: Finished difference Result 349804 states and 496644 transitions. [2021-12-15 17:20:58,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:58,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349804 states and 496644 transitions. [2021-12-15 17:20:59,961 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 348043 [2021-12-15 17:21:01,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349804 states to 349804 states and 496644 transitions. [2021-12-15 17:21:01,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 349804 [2021-12-15 17:21:01,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 349804 [2021-12-15 17:21:01,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 349804 states and 496644 transitions. [2021-12-15 17:21:01,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:01,666 INFO L681 BuchiCegarLoop]: Abstraction has 349804 states and 496644 transitions. [2021-12-15 17:21:01,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349804 states and 496644 transitions. [2021-12-15 17:21:05,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349804 to 342716. [2021-12-15 17:21:05,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 342716 states, 342716 states have (on average 1.4210366600917377) internal successors, (487012), 342715 states have internal predecessors, (487012), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:06,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342716 states to 342716 states and 487012 transitions. [2021-12-15 17:21:06,631 INFO L704 BuchiCegarLoop]: Abstraction has 342716 states and 487012 transitions. [2021-12-15 17:21:06,631 INFO L587 BuchiCegarLoop]: Abstraction has 342716 states and 487012 transitions. [2021-12-15 17:21:06,631 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:21:06,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342716 states and 487012 transitions. [2021-12-15 17:21:08,211 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 341851 [2021-12-15 17:21:08,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:08,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:08,214 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:08,214 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:08,215 INFO L791 eck$LassoCheckResult]: Stem: 1223195#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1223196#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1223485#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1222133#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1222134#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1223519#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1223458#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1223459#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1223504#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1222440#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1222441#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1222547#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1222802#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1222729#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1222442#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1222104#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1222105#L1036 assume !(0 == ~M_E~0); 1222200#L1036-2 assume !(0 == ~T1_E~0); 1223118#L1041-1 assume !(0 == ~T2_E~0); 1223119#L1046-1 assume !(0 == ~T3_E~0); 1222480#L1051-1 assume !(0 == ~T4_E~0); 1222481#L1056-1 assume !(0 == ~T5_E~0); 1223297#L1061-1 assume !(0 == ~T6_E~0); 1222375#L1066-1 assume !(0 == ~T7_E~0); 1222376#L1071-1 assume !(0 == ~T8_E~0); 1223277#L1076-1 assume !(0 == ~T9_E~0); 1222269#L1081-1 assume !(0 == ~T10_E~0); 1222270#L1086-1 assume !(0 == ~E_M~0); 1222679#L1091-1 assume !(0 == ~E_1~0); 1223527#L1096-1 assume !(0 == ~E_2~0); 1223528#L1101-1 assume !(0 == ~E_3~0); 1222744#L1106-1 assume !(0 == ~E_4~0); 1222745#L1111-1 assume !(0 == ~E_5~0); 1222918#L1116-1 assume !(0 == ~E_6~0); 1222919#L1121-1 assume !(0 == ~E_7~0); 1222736#L1126-1 assume !(0 == ~E_8~0); 1222737#L1131-1 assume !(0 == ~E_9~0); 1223013#L1136-1 assume !(0 == ~E_10~0); 1223131#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1223335#L514 assume !(1 == ~m_pc~0); 1223336#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1222758#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1222669#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1222670#L1285 assume !(0 != activate_threads_~tmp~1#1); 1223579#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1222395#L533 assume !(1 == ~t1_pc~0); 1222396#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1222972#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1222792#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1222793#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1223160#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1223161#L552 assume !(1 == ~t2_pc~0); 1222875#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1222876#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1223259#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1223260#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1222774#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1222775#L571 assume !(1 == ~t3_pc~0); 1222989#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1223066#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1222309#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1222310#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1222923#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1222184#L590 assume !(1 == ~t4_pc~0); 1222185#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1222986#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1223710#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1223581#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1223197#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1222920#L609 assume !(1 == ~t5_pc~0); 1222921#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1223574#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1222219#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1222220#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1222915#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1222916#L628 assume !(1 == ~t6_pc~0); 1222838#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1222837#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1223553#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1223554#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1223249#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1223250#L647 assume 1 == ~t7_pc~0; 1222746#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1222747#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1223053#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1222751#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1222752#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1223630#L666 assume !(1 == ~t8_pc~0); 1222527#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1222528#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1222768#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1222943#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1222676#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1222677#L685 assume 1 == ~t9_pc~0; 1223587#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1223439#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1223429#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1222702#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1222703#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1223091#L704 assume !(1 == ~t10_pc~0); 1222695#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1222694#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1223295#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1222241#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1222242#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1222489#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1223232#L1154-2 assume !(1 == ~T1_E~0); 1223608#L1159-1 assume !(1 == ~T2_E~0); 1223671#L1164-1 assume !(1 == ~T3_E~0); 1223672#L1169-1 assume !(1 == ~T4_E~0); 1222796#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1222797#L1179-1 assume !(1 == ~T6_E~0); 1222445#L1184-1 assume !(1 == ~T7_E~0); 1222446#L1189-1 assume !(1 == ~T8_E~0); 1222663#L1194-1 assume !(1 == ~T9_E~0); 1222664#L1199-1 assume !(1 == ~T10_E~0); 1222609#L1204-1 assume !(1 == ~E_M~0); 1222610#L1209-1 assume !(1 == ~E_1~0); 1223190#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1223191#L1219-1 assume !(1 == ~E_3~0); 1223611#L1224-1 assume !(1 == ~E_4~0); 1223612#L1229-1 assume !(1 == ~E_5~0); 1222330#L1234-1 assume !(1 == ~E_6~0); 1222331#L1239-1 assume !(1 == ~E_7~0); 1222389#L1244-1 assume !(1 == ~E_8~0); 1222390#L1249-1 assume !(1 == ~E_9~0); 1223282#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1223283#L1259-1 assume { :end_inline_reset_delta_events } true; 1271241#L1565-2 [2021-12-15 17:21:08,215 INFO L793 eck$LassoCheckResult]: Loop: 1271241#L1565-2 assume !false; 1415564#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1415365#L1011 assume !false; 1415187#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1271180#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1271165#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1271159#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1271152#L866 assume !(0 != eval_~tmp~0#1); 1271153#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1453250#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1453246#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1453242#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1453238#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1453234#L1046-3 assume !(0 == ~T3_E~0); 1453230#L1051-3 assume !(0 == ~T4_E~0); 1453227#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1453223#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1453218#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1453213#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1453208#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1453203#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1453199#L1086-3 assume !(0 == ~E_M~0); 1453195#L1091-3 assume !(0 == ~E_1~0); 1453191#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1453187#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1453183#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1453179#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1453174#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1453169#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1453163#L1126-3 assume !(0 == ~E_8~0); 1453158#L1131-3 assume !(0 == ~E_9~0); 1453154#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1453149#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1453145#L514-36 assume !(1 == ~m_pc~0); 1453140#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1453134#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1453130#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1453126#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1453122#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1453117#L533-36 assume !(1 == ~t1_pc~0); 1453113#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1453108#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1453104#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1453101#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1453097#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1453093#L552-36 assume !(1 == ~t2_pc~0); 1453089#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1453085#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1453081#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1453077#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1453070#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1453065#L571-36 assume !(1 == ~t3_pc~0); 1453061#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1453057#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1453054#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1453050#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1453047#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1453042#L590-36 assume 1 == ~t4_pc~0; 1453036#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1453031#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1453026#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1453020#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1453017#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1453013#L609-36 assume !(1 == ~t5_pc~0); 1453011#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1453009#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1446991#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1446989#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1446987#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1446984#L628-36 assume 1 == ~t6_pc~0; 1446982#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1446979#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1446977#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1446973#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1446969#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1446964#L647-36 assume !(1 == ~t7_pc~0); 1446960#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1446955#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1446949#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1446945#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 1446941#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1446935#L666-36 assume 1 == ~t8_pc~0; 1446932#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1446928#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1446924#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1446920#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1446916#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1446912#L685-36 assume !(1 == ~t9_pc~0); 1446906#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1446901#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1446895#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1446890#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1446885#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1446879#L704-36 assume 1 == ~t10_pc~0; 1446872#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1446867#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1446862#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1446857#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1446851#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1417261#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1416812#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1417254#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1416802#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1416800#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1416798#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1416796#L1179-3 assume !(1 == ~T6_E~0); 1416794#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1416792#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1416791#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1416790#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1416788#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1416784#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1416782#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1416779#L1219-3 assume !(1 == ~E_3~0); 1416777#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1416775#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1416774#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1416773#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1416772#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1416769#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1416768#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1416767#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1416414#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1416410#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1416408#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1416407#L1584 assume !(0 == start_simulation_~tmp~3#1); 1416404#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1416073#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1416061#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1416059#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1416057#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1415725#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1415723#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1415721#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1271241#L1565-2 [2021-12-15 17:21:08,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:08,216 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2021-12-15 17:21:08,216 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:08,217 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203615416] [2021-12-15 17:21:08,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:08,217 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:08,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:08,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:08,250 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:08,250 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203615416] [2021-12-15 17:21:08,250 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203615416] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:08,250 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:08,250 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:08,251 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966790699] [2021-12-15 17:21:08,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:08,251 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:08,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:08,252 INFO L85 PathProgramCache]: Analyzing trace with hash -1032118370, now seen corresponding path program 1 times [2021-12-15 17:21:08,252 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:08,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395212926] [2021-12-15 17:21:08,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:08,252 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:08,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:08,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:08,280 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:08,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395212926] [2021-12-15 17:21:08,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395212926] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:08,280 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:08,281 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:08,281 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781907702] [2021-12-15 17:21:08,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:08,281 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:08,281 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:08,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:08,282 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:08,282 INFO L87 Difference]: Start difference. First operand 342716 states and 487012 transitions. cyclomatic complexity: 144424 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:12,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:12,657 INFO L93 Difference]: Finished difference Result 980597 states and 1384671 transitions. [2021-12-15 17:21:12,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:12,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 980597 states and 1384671 transitions. [2021-12-15 17:21:18,079 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 976181 [2021-12-15 17:21:21,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 980597 states to 980597 states and 1384671 transitions. [2021-12-15 17:21:21,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 980597