./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:39,431 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:39,432 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:39,465 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:39,466 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:39,467 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:39,468 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:39,469 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:39,470 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:39,470 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:39,471 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:39,472 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:39,472 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:39,473 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:39,473 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:39,474 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:39,475 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:39,476 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:39,477 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:39,478 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:39,479 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:39,480 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:39,481 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:39,482 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:39,484 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:39,484 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:39,484 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:39,485 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:39,485 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:39,486 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:39,486 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:39,487 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:39,488 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:39,488 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:39,489 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:39,489 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:39,490 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:39,490 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:39,490 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:39,491 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:39,491 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:39,492 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:39,508 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:39,508 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:39,508 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:39,508 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:39,509 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:39,509 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:39,510 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:39,510 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:39,510 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:39,510 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:39,510 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:39,511 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:39,511 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:39,511 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:39,511 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:39,511 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:39,512 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:39,512 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:39,512 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:39,512 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:39,512 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:39,512 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:39,513 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:39,513 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:39,513 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:39,513 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:39,513 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:39,514 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:39,514 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:39,514 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:39,514 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:39,514 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:39,515 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:39,515 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2021-12-15 17:20:39,713 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:39,747 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:39,749 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:39,750 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:39,750 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:39,751 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2021-12-15 17:20:39,805 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1ddf1122e/9143232555e847ba8c499692c8af9950/FLAG3540d8fb1 [2021-12-15 17:20:40,274 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:40,277 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2021-12-15 17:20:40,290 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1ddf1122e/9143232555e847ba8c499692c8af9950/FLAG3540d8fb1 [2021-12-15 17:20:40,611 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1ddf1122e/9143232555e847ba8c499692c8af9950 [2021-12-15 17:20:40,613 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:40,615 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:40,625 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:40,626 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:40,628 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:40,629 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:40,630 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2f63b95c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40, skipping insertion in model container [2021-12-15 17:20:40,630 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:40,634 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:40,671 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:40,780 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2021-12-15 17:20:40,872 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:40,896 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:40,904 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2021-12-15 17:20:40,958 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:40,977 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:40,977 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40 WrapperNode [2021-12-15 17:20:40,977 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:40,978 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:40,978 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:40,978 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:40,983 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:40,992 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,083 INFO L137 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 209, statements flattened = 3186 [2021-12-15 17:20:41,084 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:41,084 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:41,084 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:41,085 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:41,090 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,090 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,101 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,102 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,136 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,158 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,168 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,181 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:41,181 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:41,182 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:41,182 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:41,188 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (1/1) ... [2021-12-15 17:20:41,193 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:41,203 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:41,213 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:41,217 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:41,248 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:41,248 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:41,249 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:41,249 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:41,350 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:41,351 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:42,550 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:42,561 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:42,561 INFO L301 CfgBuilder]: Removed 13 assume(true) statements. [2021-12-15 17:20:42,564 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:42 BoogieIcfgContainer [2021-12-15 17:20:42,564 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:42,564 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:42,565 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:42,567 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:42,567 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:42,567 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:40" (1/3) ... [2021-12-15 17:20:42,568 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7343425b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:42, skipping insertion in model container [2021-12-15 17:20:42,569 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:42,569 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:40" (2/3) ... [2021-12-15 17:20:42,569 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7343425b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:42, skipping insertion in model container [2021-12-15 17:20:42,569 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:42,569 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:42" (3/3) ... [2021-12-15 17:20:42,570 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2021-12-15 17:20:42,597 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:42,598 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:42,598 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:42,598 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:42,598 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:42,598 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:42,598 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:42,598 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:42,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2021-12-15 17:20:42,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:42,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:42,680 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,681 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:42,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:42,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2021-12-15 17:20:42,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:42,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:42,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,695 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:42,701 INFO L791 eck$LassoCheckResult]: Stem: 630#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1246#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23#L1516true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 562#L712true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 570#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 347#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 543#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 706#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1236#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 460#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 827#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 379#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 663#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 846#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 619#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 550#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 834#L1024true assume !(0 == ~M_E~0); 936#L1024-2true assume !(0 == ~T1_E~0); 186#L1029-1true assume !(0 == ~T2_E~0); 246#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1313#L1039-1true assume !(0 == ~T4_E~0); 1007#L1044-1true assume !(0 == ~T5_E~0); 394#L1049-1true assume !(0 == ~T6_E~0); 1325#L1054-1true assume !(0 == ~T7_E~0); 569#L1059-1true assume !(0 == ~T8_E~0); 213#L1064-1true assume !(0 == ~T9_E~0); 793#L1069-1true assume !(0 == ~T10_E~0); 1229#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 875#L1079-1true assume !(0 == ~E_1~0); 837#L1084-1true assume !(0 == ~E_2~0); 1034#L1089-1true assume !(0 == ~E_3~0); 907#L1094-1true assume !(0 == ~E_4~0); 453#L1099-1true assume !(0 == ~E_5~0); 1049#L1104-1true assume !(0 == ~E_6~0); 682#L1109-1true assume !(0 == ~E_7~0); 318#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1275#L1119-1true assume !(0 == ~E_9~0); 353#L1124-1true assume !(0 == ~E_10~0); 40#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 698#L502true assume 1 == ~m_pc~0; 567#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 742#L514true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 616#L1273true assume !(0 != activate_threads_~tmp~1#1); 1367#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1123#L521true assume !(1 == ~t1_pc~0); 1044#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 68#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136#L533true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 633#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 59#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 853#L540true assume 1 == ~t2_pc~0; 1104#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 857#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 873#L552true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1230#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 945#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200#L559true assume 1 == ~t3_pc~0; 1015#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 366#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472#L571true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 644#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1253#L578true assume !(1 == ~t4_pc~0); 800#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 833#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56#L590true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1090#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 599#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162#L597true assume 1 == ~t5_pc~0; 1331#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 427#L609true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1351#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 551#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 613#L616true assume !(1 == ~t6_pc~0); 1175#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1064#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1256#L628true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 493#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 446#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 677#L635true assume 1 == ~t7_pc~0; 602#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 258#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 807#L647true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 903#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 546#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 787#L654true assume !(1 == ~t8_pc~0); 411#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 946#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1210#L666true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 789#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 993#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185#L673true assume 1 == ~t9_pc~0; 1009#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1203#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1112#L685true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 745#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 693#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 865#L692true assume !(1 == ~t10_pc~0); 680#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 999#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 553#L704true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 456#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 768#L1353-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1310#L1142true assume !(1 == ~M_E~0); 139#L1142-2true assume !(1 == ~T1_E~0); 746#L1147-1true assume !(1 == ~T2_E~0); 1309#L1152-1true assume !(1 == ~T3_E~0); 371#L1157-1true assume !(1 == ~T4_E~0); 845#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 475#L1167-1true assume !(1 == ~T6_E~0); 929#L1172-1true assume !(1 == ~T7_E~0); 962#L1177-1true assume !(1 == ~T8_E~0); 584#L1182-1true assume !(1 == ~T9_E~0); 687#L1187-1true assume !(1 == ~T10_E~0); 735#L1192-1true assume !(1 == ~E_M~0); 288#L1197-1true assume !(1 == ~E_1~0); 750#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 535#L1207-1true assume !(1 == ~E_3~0); 521#L1212-1true assume !(1 == ~E_4~0); 71#L1217-1true assume !(1 == ~E_5~0); 1369#L1222-1true assume !(1 == ~E_6~0); 517#L1227-1true assume !(1 == ~E_7~0); 580#L1232-1true assume !(1 == ~E_8~0); 9#L1237-1true assume !(1 == ~E_9~0); 1056#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 568#L1247-1true assume { :end_inline_reset_delta_events } true; 90#L1553-2true [2021-12-15 17:20:42,703 INFO L793 eck$LassoCheckResult]: Loop: 90#L1553-2true assume !false; 732#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1336#L999true assume false; 808#L1014true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 234#L712-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1289#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 997#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 444#L1029-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 420#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 711#L1039-3true assume !(0 == ~T4_E~0); 765#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 182#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 643#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 69#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1335#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 401#L1069-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 689#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 975#L1079-3true assume !(0 == ~E_1~0); 576#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 486#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 641#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 434#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 709#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1062#L1109-3true assume 0 == ~E_7~0;~E_7~0 := 1; 696#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1190#L1119-3true assume !(0 == ~E_9~0); 1328#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1227#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1096#L502-36true assume 1 == ~m_pc~0; 712#L503-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1221#L514-12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 214#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 683#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 381#L521-36true assume 1 == ~t1_pc~0; 390#L522-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 511#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 541#L533-12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1196#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 799#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1107#L540-36true assume 1 == ~t2_pc~0; 1258#L541-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 259#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1248#L552-12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1337#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 471#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8#L559-36true assume !(1 == ~t3_pc~0); 237#L559-38true is_transmit3_triggered_~__retres1~3#1 := 0; 734#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153#L571-12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 586#L1297-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 871#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1240#L578-36true assume 1 == ~t4_pc~0; 560#L579-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1245#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 914#L590-12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1308#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 404#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 575#L597-36true assume !(1 == ~t5_pc~0); 1120#L597-38true is_transmit5_triggered_~__retres1~5#1 := 0; 1054#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510#L609-12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 536#L1313-36true assume !(0 != activate_threads_~tmp___4~0#1); 289#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1109#L616-36true assume 1 == ~t6_pc~0; 1334#L617-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 369#L628-12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 440#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 730#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1348#L635-36true assume 1 == ~t7_pc~0; 1003#L636-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 814#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 476#L647-12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1268#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 432#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1282#L654-36true assume !(1 == ~t8_pc~0); 1005#L654-38true is_transmit8_triggered_~__retres1~8#1 := 0; 1330#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1280#L666-12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1174#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1125#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 230#L673-36true assume !(1 == ~t9_pc~0); 717#L673-38true is_transmit9_triggered_~__retres1~9#1 := 0; 461#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 822#L685-12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1023#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1186#L692-36true assume !(1 == ~t10_pc~0); 112#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 439#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 887#L704-12true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 210#L1353-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 438#L1353-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1170#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1006#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1068#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 497#L1157-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 809#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1066#L1167-3true assume !(1 == ~T6_E~0); 985#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 430#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 364#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 844#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 373#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 265#L1197-3true assume 1 == ~E_1~0;~E_1~0 := 2; 418#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 503#L1207-3true assume !(1 == ~E_3~0); 1105#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 707#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 205#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 50#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 876#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 848#L1237-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1293#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1251#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 919#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 120#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1228#L840-1true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 561#L1572true assume !(0 == start_simulation_~tmp~3#1); 383#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1218#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1081#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1085#L840-2true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1285#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 819#L1535true start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1358#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 90#L1553-2true [2021-12-15 17:20:42,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,707 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2021-12-15 17:20:42,712 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765441128] [2021-12-15 17:20:42,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,714 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:42,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:42,858 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:42,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765441128] [2021-12-15 17:20:42,858 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765441128] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:42,858 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:42,859 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:42,860 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278106043] [2021-12-15 17:20:42,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:42,863 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:42,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:42,864 INFO L85 PathProgramCache]: Analyzing trace with hash -724132039, now seen corresponding path program 1 times [2021-12-15 17:20:42,864 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:42,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466952040] [2021-12-15 17:20:42,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:42,864 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:42,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:42,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:42,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:42,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466952040] [2021-12-15 17:20:42,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466952040] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:42,895 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:42,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:42,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397047968] [2021-12-15 17:20:42,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:42,896 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:42,897 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:42,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:42,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:42,931 INFO L87 Difference]: Start difference. First operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:43,022 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2021-12-15 17:20:43,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:43,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2021-12-15 17:20:43,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1361 states and 2023 transitions. [2021-12-15 17:20:43,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:43,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:43,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2023 transitions. [2021-12-15 17:20:43,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,094 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2021-12-15 17:20:43,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2023 transitions. [2021-12-15 17:20:43,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:43,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2023 transitions. [2021-12-15 17:20:43,160 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2021-12-15 17:20:43,161 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2021-12-15 17:20:43,161 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:43,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2023 transitions. [2021-12-15 17:20:43,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,168 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,168 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,168 INFO L791 eck$LassoCheckResult]: Stem: 3750#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3751#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2791#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2792#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3680#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3384#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3385#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3662#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3818#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3550#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3551#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3440#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3441#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3778#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3740#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3668#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3669#L1024 assume !(0 == ~M_E~0); 3914#L1024-2 assume !(0 == ~T1_E~0); 3118#L1029-1 assume !(0 == ~T2_E~0); 3119#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3225#L1039-1 assume !(0 == ~T4_E~0); 4031#L1044-1 assume !(0 == ~T5_E~0); 3462#L1049-1 assume !(0 == ~T6_E~0); 3463#L1054-1 assume !(0 == ~T7_E~0); 3688#L1059-1 assume !(0 == ~T8_E~0); 3165#L1064-1 assume !(0 == ~T9_E~0); 3166#L1069-1 assume !(0 == ~T10_E~0); 3882#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3948#L1079-1 assume !(0 == ~E_1~0); 3916#L1084-1 assume !(0 == ~E_2~0); 3917#L1089-1 assume !(0 == ~E_3~0); 3967#L1094-1 assume !(0 == ~E_4~0); 3538#L1099-1 assume !(0 == ~E_5~0); 3539#L1104-1 assume !(0 == ~E_6~0); 3796#L1109-1 assume !(0 == ~E_7~0); 3339#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3340#L1119-1 assume !(0 == ~E_9~0); 3396#L1124-1 assume !(0 == ~E_10~0); 2824#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2825#L502 assume 1 == ~m_pc~0; 3686#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2953#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2954#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3736#L1273 assume !(0 != activate_threads_~tmp~1#1); 3737#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4066#L521 assume !(1 == ~t1_pc~0); 3999#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2884#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2885#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3028#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2868#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2869#L540 assume 1 == ~t2_pc~0; 3930#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3651#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3933#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3946#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3993#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3140#L559 assume 1 == ~t3_pc~0; 3141#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3421#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3563#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2971#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2972#L578 assume !(1 == ~t4_pc~0); 3092#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3091#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2860#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2861#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3720#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3721#L597 assume 1 == ~t5_pc~0; 4083#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2905#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2906#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3511#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3670#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3671#L616 assume !(1 == ~t6_pc~0); 3685#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3684#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4048#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3593#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3530#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3531#L635 assume 1 == ~t7_pc~0; 3725#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2874#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3245#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3891#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3663#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3664#L654 assume !(1 == ~t8_pc~0); 3486#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3487#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3994#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3879#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3880#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3116#L673 assume 1 == ~t9_pc~0; 3117#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2815#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4063#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3849#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3805#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3806#L692 assume !(1 == ~t10_pc~0); 3754#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3753#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3672#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3542#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3543#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3860#L1142 assume !(1 == ~M_E~0); 3031#L1142-2 assume !(1 == ~T1_E~0); 3032#L1147-1 assume !(1 == ~T2_E~0); 3850#L1152-1 assume !(1 == ~T3_E~0); 3426#L1157-1 assume !(1 == ~T4_E~0); 3427#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3567#L1167-1 assume !(1 == ~T6_E~0); 3568#L1172-1 assume !(1 == ~T7_E~0); 3987#L1177-1 assume !(1 == ~T8_E~0); 3705#L1182-1 assume !(1 == ~T9_E~0); 3706#L1187-1 assume !(1 == ~T10_E~0); 3799#L1192-1 assume !(1 == ~E_M~0); 3292#L1197-1 assume !(1 == ~E_1~0); 3293#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3654#L1207-1 assume !(1 == ~E_3~0); 3633#L1212-1 assume !(1 == ~E_4~0); 2890#L1217-1 assume !(1 == ~E_5~0); 2891#L1222-1 assume !(1 == ~E_6~0); 3629#L1227-1 assume !(1 == ~E_7~0); 3630#L1232-1 assume !(1 == ~E_8~0); 2756#L1237-1 assume !(1 == ~E_9~0); 2757#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3687#L1247-1 assume { :end_inline_reset_delta_events } true; 2930#L1553-2 [2021-12-15 17:20:43,169 INFO L793 eck$LassoCheckResult]: Loop: 2930#L1553-2 assume !false; 2931#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3840#L999 assume !false; 3888#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3015#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2908#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3403#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3757#L854 assume !(0 != eval_~tmp~0#1); 3758#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3202#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3203#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4020#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3499#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3500#L1039-3 assume !(0 == ~T4_E~0); 3823#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3110#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3111#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2886#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2887#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3471#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3472#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3801#L1079-3 assume !(0 == ~E_1~0); 3699#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3586#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3587#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3516#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3517#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3821#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3809#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3810#L1119-3 assume !(0 == ~E_9~0); 4090#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4097#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4057#L502-36 assume 1 == ~m_pc~0; 3824#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2742#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2743#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3167#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3168#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3445#L521-36 assume 1 == ~t1_pc~0; 3446#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3455#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3622#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3659#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3884#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3885#L540-36 assume !(1 == ~t2_pc~0); 2833#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2834#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3246#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4098#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3561#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2750#L559-36 assume !(1 == ~t3_pc~0); 2752#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3204#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3060#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3061#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3707#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3943#L578-36 assume !(1 == ~t4_pc~0); 3636#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3637#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3973#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3974#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3475#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3476#L597-36 assume !(1 == ~t5_pc~0); 3696#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4046#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3620#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3621#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3290#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3291#L616-36 assume !(1 == ~t6_pc~0); 4018#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2820#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2821#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3423#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3524#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3839#L635-36 assume 1 == ~t7_pc~0; 4023#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3896#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3569#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3570#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3512#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3513#L654-36 assume !(1 == ~t8_pc~0); 4027#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4028#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4100#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4085#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4067#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3195#L673-36 assume !(1 == ~t9_pc~0); 3196#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3548#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3549#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3903#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2763#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2764#L692-36 assume 1 == ~t10_pc~0; 3698#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2980#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3523#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3158#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3159#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3522#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3667#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4029#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4030#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3600#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3601#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3892#L1167-3 assume !(1 == ~T6_E~0); 4014#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3510#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3415#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3416#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3429#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3254#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3255#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3496#L1207-3 assume !(1 == ~E_3~0); 3611#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3819#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3149#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2847#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2848#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3923#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3924#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4099#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3977#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2999#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3000#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3679#L1572 assume !(0 == start_simulation_~tmp~3#1); 3295#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3448#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2777#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4051#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4052#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2746#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2747#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3901#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2930#L1553-2 [2021-12-15 17:20:43,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,170 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2021-12-15 17:20:43,170 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506840206] [2021-12-15 17:20:43,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,170 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,232 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,232 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506840206] [2021-12-15 17:20:43,232 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506840206] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,232 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,232 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,233 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539044984] [2021-12-15 17:20:43,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,233 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:43,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,234 INFO L85 PathProgramCache]: Analyzing trace with hash -2058537928, now seen corresponding path program 1 times [2021-12-15 17:20:43,234 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283610747] [2021-12-15 17:20:43,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283610747] [2021-12-15 17:20:43,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283610747] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,305 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,305 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,306 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843191813] [2021-12-15 17:20:43,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,306 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:43,306 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:43,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:43,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:43,307 INFO L87 Difference]: Start difference. First operand 1361 states and 2023 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:43,360 INFO L93 Difference]: Finished difference Result 1361 states and 2022 transitions. [2021-12-15 17:20:43,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:43,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2022 transitions. [2021-12-15 17:20:43,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2022 transitions. [2021-12-15 17:20:43,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:43,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:43,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2022 transitions. [2021-12-15 17:20:43,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,436 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2021-12-15 17:20:43,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2022 transitions. [2021-12-15 17:20:43,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:43,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2022 transitions. [2021-12-15 17:20:43,470 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2021-12-15 17:20:43,470 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2021-12-15 17:20:43,470 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:43,470 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2022 transitions. [2021-12-15 17:20:43,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,486 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,486 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,488 INFO L791 eck$LassoCheckResult]: Stem: 6479#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5520#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5521#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6409#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6112#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6113#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6391#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6547#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6277#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6278#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6167#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6168#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6507#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6469#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6396#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6397#L1024 assume !(0 == ~M_E~0); 6643#L1024-2 assume !(0 == ~T1_E~0); 5847#L1029-1 assume !(0 == ~T2_E~0); 5848#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5954#L1039-1 assume !(0 == ~T4_E~0); 6760#L1044-1 assume !(0 == ~T5_E~0); 6189#L1049-1 assume !(0 == ~T6_E~0); 6190#L1054-1 assume !(0 == ~T7_E~0); 6417#L1059-1 assume !(0 == ~T8_E~0); 5894#L1064-1 assume !(0 == ~T9_E~0); 5895#L1069-1 assume !(0 == ~T10_E~0); 6611#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6677#L1079-1 assume !(0 == ~E_1~0); 6645#L1084-1 assume !(0 == ~E_2~0); 6646#L1089-1 assume !(0 == ~E_3~0); 6696#L1094-1 assume !(0 == ~E_4~0); 6267#L1099-1 assume !(0 == ~E_5~0); 6268#L1104-1 assume !(0 == ~E_6~0); 6525#L1109-1 assume !(0 == ~E_7~0); 6068#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6069#L1119-1 assume !(0 == ~E_9~0); 6123#L1124-1 assume !(0 == ~E_10~0); 5553#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5554#L502 assume 1 == ~m_pc~0; 6415#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5682#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5683#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6464#L1273 assume !(0 != activate_threads_~tmp~1#1); 6465#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6795#L521 assume !(1 == ~t1_pc~0); 6728#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5613#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5614#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5756#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5595#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5596#L540 assume 1 == ~t2_pc~0; 6659#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6380#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6662#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6675#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6722#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5869#L559 assume 1 == ~t3_pc~0; 5870#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6148#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6149#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6292#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5700#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5701#L578 assume !(1 == ~t4_pc~0); 5819#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5818#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5589#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5590#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6447#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6448#L597 assume 1 == ~t5_pc~0; 6810#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5634#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5635#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6235#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6398#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6399#L616 assume !(1 == ~t6_pc~0); 6413#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6412#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6777#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6322#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6259#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6260#L635 assume 1 == ~t7_pc~0; 6452#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5603#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5974#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6620#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6392#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6393#L654 assume !(1 == ~t8_pc~0); 6215#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6216#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6723#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6608#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6609#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5845#L673 assume 1 == ~t9_pc~0; 5846#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5544#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6792#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6578#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6534#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6535#L692 assume !(1 == ~t10_pc~0); 6483#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6482#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6401#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6271#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6272#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6589#L1142 assume !(1 == ~M_E~0); 5760#L1142-2 assume !(1 == ~T1_E~0); 5761#L1147-1 assume !(1 == ~T2_E~0); 6579#L1152-1 assume !(1 == ~T3_E~0); 6155#L1157-1 assume !(1 == ~T4_E~0); 6156#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6296#L1167-1 assume !(1 == ~T6_E~0); 6297#L1172-1 assume !(1 == ~T7_E~0); 6716#L1177-1 assume !(1 == ~T8_E~0); 6434#L1182-1 assume !(1 == ~T9_E~0); 6435#L1187-1 assume !(1 == ~T10_E~0); 6528#L1192-1 assume !(1 == ~E_M~0); 6019#L1197-1 assume !(1 == ~E_1~0); 6020#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6383#L1207-1 assume !(1 == ~E_3~0); 6362#L1212-1 assume !(1 == ~E_4~0); 5619#L1217-1 assume !(1 == ~E_5~0); 5620#L1222-1 assume !(1 == ~E_6~0); 6358#L1227-1 assume !(1 == ~E_7~0); 6359#L1232-1 assume !(1 == ~E_8~0); 5485#L1237-1 assume !(1 == ~E_9~0); 5486#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6416#L1247-1 assume { :end_inline_reset_delta_events } true; 5659#L1553-2 [2021-12-15 17:20:43,490 INFO L793 eck$LassoCheckResult]: Loop: 5659#L1553-2 assume !false; 5660#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6569#L999 assume !false; 6615#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5744#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5637#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6132#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6486#L854 assume !(0 != eval_~tmp~0#1); 6487#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5931#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5932#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6749#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6258#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6228#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6229#L1039-3 assume !(0 == ~T4_E~0); 6552#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5839#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5840#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5615#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5616#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6200#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6201#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6530#L1079-3 assume !(0 == ~E_1~0); 6427#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6315#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6316#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6245#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6246#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6550#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6538#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6539#L1119-3 assume !(0 == ~E_9~0); 6819#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6826#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6786#L502-36 assume !(1 == ~m_pc~0); 5986#L502-38 is_master_triggered_~__retres1~0#1 := 0; 5471#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5472#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5896#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5897#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6172#L521-36 assume 1 == ~t1_pc~0; 6173#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6184#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6351#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6388#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6613#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6614#L540-36 assume 1 == ~t2_pc~0; 6788#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5561#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5975#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6827#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6291#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5482#L559-36 assume 1 == ~t3_pc~0; 5483#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5939#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5789#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5790#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6436#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6672#L578-36 assume !(1 == ~t4_pc~0); 6368#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 6369#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6702#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6703#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6206#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6207#L597-36 assume !(1 == ~t5_pc~0); 6425#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6775#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6349#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6350#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 6021#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6022#L616-36 assume 1 == ~t6_pc~0; 6789#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5549#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5550#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6152#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6253#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6568#L635-36 assume 1 == ~t7_pc~0; 6752#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6625#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6298#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6299#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6241#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6242#L654-36 assume !(1 == ~t8_pc~0); 6756#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6757#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6829#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6814#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6796#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5924#L673-36 assume !(1 == ~t9_pc~0); 5925#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 6279#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6280#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6632#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5492#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5493#L692-36 assume 1 == ~t10_pc~0; 6428#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5709#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6252#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5887#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5888#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6251#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6400#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6758#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6759#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6329#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6330#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6621#L1167-3 assume !(1 == ~T6_E~0); 6743#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6240#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6144#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6145#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6158#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5983#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5984#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6225#L1207-3 assume !(1 == ~E_3~0); 6340#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6548#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5879#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5576#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5577#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6653#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6654#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6828#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6706#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5728#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5729#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6408#L1572 assume !(0 == start_simulation_~tmp~3#1); 6026#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6177#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5506#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6780#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 6781#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5475#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5476#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6630#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5659#L1553-2 [2021-12-15 17:20:43,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2021-12-15 17:20:43,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39366642] [2021-12-15 17:20:43,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,497 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39366642] [2021-12-15 17:20:43,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39366642] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,547 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,548 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391169097] [2021-12-15 17:20:43,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,548 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:43,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,549 INFO L85 PathProgramCache]: Analyzing trace with hash -679343498, now seen corresponding path program 1 times [2021-12-15 17:20:43,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583558644] [2021-12-15 17:20:43,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,640 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583558644] [2021-12-15 17:20:43,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1583558644] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,641 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775264786] [2021-12-15 17:20:43,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,642 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:43,642 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:43,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:43,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:43,644 INFO L87 Difference]: Start difference. First operand 1361 states and 2022 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:43,680 INFO L93 Difference]: Finished difference Result 1361 states and 2021 transitions. [2021-12-15 17:20:43,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:43,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2021 transitions. [2021-12-15 17:20:43,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2021 transitions. [2021-12-15 17:20:43,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:43,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:43,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2021 transitions. [2021-12-15 17:20:43,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,702 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2021-12-15 17:20:43,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2021 transitions. [2021-12-15 17:20:43,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:43,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2021 transitions. [2021-12-15 17:20:43,726 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2021-12-15 17:20:43,727 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2021-12-15 17:20:43,727 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:43,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2021 transitions. [2021-12-15 17:20:43,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,738 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,738 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,739 INFO L791 eck$LassoCheckResult]: Stem: 9208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 9209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8249#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8250#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9138#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8841#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8842#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9120#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9276#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9006#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9007#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8896#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8897#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9236#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9198#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9125#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9126#L1024 assume !(0 == ~M_E~0); 9372#L1024-2 assume !(0 == ~T1_E~0); 8576#L1029-1 assume !(0 == ~T2_E~0); 8577#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8683#L1039-1 assume !(0 == ~T4_E~0); 9489#L1044-1 assume !(0 == ~T5_E~0); 8918#L1049-1 assume !(0 == ~T6_E~0); 8919#L1054-1 assume !(0 == ~T7_E~0); 9146#L1059-1 assume !(0 == ~T8_E~0); 8623#L1064-1 assume !(0 == ~T9_E~0); 8624#L1069-1 assume !(0 == ~T10_E~0); 9340#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9406#L1079-1 assume !(0 == ~E_1~0); 9374#L1084-1 assume !(0 == ~E_2~0); 9375#L1089-1 assume !(0 == ~E_3~0); 9425#L1094-1 assume !(0 == ~E_4~0); 8996#L1099-1 assume !(0 == ~E_5~0); 8997#L1104-1 assume !(0 == ~E_6~0); 9254#L1109-1 assume !(0 == ~E_7~0); 8797#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8798#L1119-1 assume !(0 == ~E_9~0); 8852#L1124-1 assume !(0 == ~E_10~0); 8282#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8283#L502 assume 1 == ~m_pc~0; 9144#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8411#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8412#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9193#L1273 assume !(0 != activate_threads_~tmp~1#1); 9194#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9524#L521 assume !(1 == ~t1_pc~0); 9457#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8342#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8343#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8485#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8324#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8325#L540 assume 1 == ~t2_pc~0; 9388#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9109#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9391#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9404#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9451#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8598#L559 assume 1 == ~t3_pc~0; 8599#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8877#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8878#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9021#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8429#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8430#L578 assume !(1 == ~t4_pc~0); 8550#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8549#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8318#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8319#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9178#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9179#L597 assume 1 == ~t5_pc~0; 9539#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8363#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8364#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8964#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9127#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9128#L616 assume !(1 == ~t6_pc~0); 9142#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9141#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9506#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9051#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 8988#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8989#L635 assume 1 == ~t7_pc~0; 9181#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8332#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8703#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9349#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9121#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9122#L654 assume !(1 == ~t8_pc~0); 8944#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8945#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9452#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9337#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9338#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8574#L673 assume 1 == ~t9_pc~0; 8575#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8273#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9521#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9307#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9263#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9264#L692 assume !(1 == ~t10_pc~0); 9212#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9211#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9130#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9000#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 9001#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9318#L1142 assume !(1 == ~M_E~0); 8489#L1142-2 assume !(1 == ~T1_E~0); 8490#L1147-1 assume !(1 == ~T2_E~0); 9308#L1152-1 assume !(1 == ~T3_E~0); 8884#L1157-1 assume !(1 == ~T4_E~0); 8885#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9025#L1167-1 assume !(1 == ~T6_E~0); 9026#L1172-1 assume !(1 == ~T7_E~0); 9445#L1177-1 assume !(1 == ~T8_E~0); 9163#L1182-1 assume !(1 == ~T9_E~0); 9164#L1187-1 assume !(1 == ~T10_E~0); 9257#L1192-1 assume !(1 == ~E_M~0); 8748#L1197-1 assume !(1 == ~E_1~0); 8749#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9112#L1207-1 assume !(1 == ~E_3~0); 9091#L1212-1 assume !(1 == ~E_4~0); 8348#L1217-1 assume !(1 == ~E_5~0); 8349#L1222-1 assume !(1 == ~E_6~0); 9087#L1227-1 assume !(1 == ~E_7~0); 9088#L1232-1 assume !(1 == ~E_8~0); 8214#L1237-1 assume !(1 == ~E_9~0); 8215#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9145#L1247-1 assume { :end_inline_reset_delta_events } true; 8388#L1553-2 [2021-12-15 17:20:43,739 INFO L793 eck$LassoCheckResult]: Loop: 8388#L1553-2 assume !false; 8389#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9298#L999 assume !false; 9344#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8473#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8366#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8861#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9215#L854 assume !(0 != eval_~tmp~0#1); 9216#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8660#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8661#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9478#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8987#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8957#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8958#L1039-3 assume !(0 == ~T4_E~0); 9281#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8568#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8569#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8344#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8345#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8929#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8930#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9259#L1079-3 assume !(0 == ~E_1~0); 9156#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9044#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9045#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8974#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8975#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9279#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9267#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9268#L1119-3 assume !(0 == ~E_9~0); 9548#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9555#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9515#L502-36 assume 1 == ~m_pc~0; 9282#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8200#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8201#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8625#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8626#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8901#L521-36 assume 1 == ~t1_pc~0; 8902#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8913#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9080#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9117#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9342#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9343#L540-36 assume !(1 == ~t2_pc~0); 8289#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 8290#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8704#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9556#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9020#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8211#L559-36 assume 1 == ~t3_pc~0; 8212#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8668#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8518#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8519#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9165#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9401#L578-36 assume 1 == ~t4_pc~0; 9136#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9098#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9431#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9432#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8935#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8936#L597-36 assume !(1 == ~t5_pc~0); 9154#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9504#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9078#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9079#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 8750#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8751#L616-36 assume !(1 == ~t6_pc~0); 9476#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 8278#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8279#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8881#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8982#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9297#L635-36 assume 1 == ~t7_pc~0; 9481#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9354#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9027#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9028#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8970#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8971#L654-36 assume !(1 == ~t8_pc~0); 9485#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9486#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9558#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9543#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9525#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8653#L673-36 assume !(1 == ~t9_pc~0); 8654#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 9008#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9009#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9361#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8221#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8222#L692-36 assume 1 == ~t10_pc~0; 9157#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8438#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8981#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8616#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8617#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8980#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9129#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9487#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9488#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9058#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9059#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9350#L1167-3 assume !(1 == ~T6_E~0); 9472#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8969#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8873#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8874#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8887#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8712#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8713#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8954#L1207-3 assume !(1 == ~E_3~0); 9069#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9277#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8608#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8305#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8306#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9382#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9383#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9557#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9435#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8457#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8458#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 9137#L1572 assume !(0 == start_simulation_~tmp~3#1); 8753#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8906#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8235#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9509#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 9510#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8204#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8205#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9359#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8388#L1553-2 [2021-12-15 17:20:43,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,741 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2021-12-15 17:20:43,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925809590] [2021-12-15 17:20:43,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,743 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,821 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925809590] [2021-12-15 17:20:43,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925809590] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,822 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,822 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,823 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134579963] [2021-12-15 17:20:43,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,823 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:43,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1183923574, now seen corresponding path program 1 times [2021-12-15 17:20:43,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823756821] [2021-12-15 17:20:43,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:43,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:43,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:43,910 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:43,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823756821] [2021-12-15 17:20:43,910 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [823756821] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:43,911 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:43,911 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:43,911 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375578009] [2021-12-15 17:20:43,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:43,912 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:43,912 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:43,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:43,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:43,914 INFO L87 Difference]: Start difference. First operand 1361 states and 2021 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:43,930 INFO L93 Difference]: Finished difference Result 1361 states and 2020 transitions. [2021-12-15 17:20:43,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:43,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2020 transitions. [2021-12-15 17:20:43,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2020 transitions. [2021-12-15 17:20:43,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:43,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:43,947 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2020 transitions. [2021-12-15 17:20:43,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:43,948 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2021-12-15 17:20:43,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2020 transitions. [2021-12-15 17:20:43,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:43,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:43,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2020 transitions. [2021-12-15 17:20:43,964 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2021-12-15 17:20:43,964 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2021-12-15 17:20:43,964 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:43,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2020 transitions. [2021-12-15 17:20:43,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:43,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:43,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:43,970 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,970 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:43,970 INFO L791 eck$LassoCheckResult]: Stem: 11937#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 10978#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10979#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11867#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 11571#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11572#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11849#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12005#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11737#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11738#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11627#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11628#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11965#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11927#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11855#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11856#L1024 assume !(0 == ~M_E~0); 12101#L1024-2 assume !(0 == ~T1_E~0); 11305#L1029-1 assume !(0 == ~T2_E~0); 11306#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11412#L1039-1 assume !(0 == ~T4_E~0); 12218#L1044-1 assume !(0 == ~T5_E~0); 11649#L1049-1 assume !(0 == ~T6_E~0); 11650#L1054-1 assume !(0 == ~T7_E~0); 11875#L1059-1 assume !(0 == ~T8_E~0); 11352#L1064-1 assume !(0 == ~T9_E~0); 11353#L1069-1 assume !(0 == ~T10_E~0); 12069#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12135#L1079-1 assume !(0 == ~E_1~0); 12103#L1084-1 assume !(0 == ~E_2~0); 12104#L1089-1 assume !(0 == ~E_3~0); 12154#L1094-1 assume !(0 == ~E_4~0); 11725#L1099-1 assume !(0 == ~E_5~0); 11726#L1104-1 assume !(0 == ~E_6~0); 11983#L1109-1 assume !(0 == ~E_7~0); 11526#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11527#L1119-1 assume !(0 == ~E_9~0); 11583#L1124-1 assume !(0 == ~E_10~0); 11011#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11012#L502 assume 1 == ~m_pc~0; 11873#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11140#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11141#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11923#L1273 assume !(0 != activate_threads_~tmp~1#1); 11924#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12253#L521 assume !(1 == ~t1_pc~0); 12186#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11071#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11072#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11215#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 11055#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11056#L540 assume 1 == ~t2_pc~0; 12117#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11838#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12120#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12133#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 12180#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11327#L559 assume 1 == ~t3_pc~0; 11328#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11607#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11608#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11750#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 11158#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11159#L578 assume !(1 == ~t4_pc~0); 11279#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11278#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11047#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11048#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11907#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11908#L597 assume 1 == ~t5_pc~0; 12270#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11092#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11093#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11698#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 11857#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11858#L616 assume !(1 == ~t6_pc~0); 11872#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11871#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12235#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11780#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 11717#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11718#L635 assume 1 == ~t7_pc~0; 11912#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11061#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11432#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12078#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 11850#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11851#L654 assume !(1 == ~t8_pc~0); 11673#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11674#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12181#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12066#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 12067#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11303#L673 assume 1 == ~t9_pc~0; 11304#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11002#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12250#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12036#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 11992#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11993#L692 assume !(1 == ~t10_pc~0); 11941#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11940#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11859#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11729#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 11730#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12047#L1142 assume !(1 == ~M_E~0); 11218#L1142-2 assume !(1 == ~T1_E~0); 11219#L1147-1 assume !(1 == ~T2_E~0); 12037#L1152-1 assume !(1 == ~T3_E~0); 11613#L1157-1 assume !(1 == ~T4_E~0); 11614#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11754#L1167-1 assume !(1 == ~T6_E~0); 11755#L1172-1 assume !(1 == ~T7_E~0); 12174#L1177-1 assume !(1 == ~T8_E~0); 11892#L1182-1 assume !(1 == ~T9_E~0); 11893#L1187-1 assume !(1 == ~T10_E~0); 11986#L1192-1 assume !(1 == ~E_M~0); 11479#L1197-1 assume !(1 == ~E_1~0); 11480#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11841#L1207-1 assume !(1 == ~E_3~0); 11820#L1212-1 assume !(1 == ~E_4~0); 11077#L1217-1 assume !(1 == ~E_5~0); 11078#L1222-1 assume !(1 == ~E_6~0); 11816#L1227-1 assume !(1 == ~E_7~0); 11817#L1232-1 assume !(1 == ~E_8~0); 10943#L1237-1 assume !(1 == ~E_9~0); 10944#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11874#L1247-1 assume { :end_inline_reset_delta_events } true; 11117#L1553-2 [2021-12-15 17:20:43,970 INFO L793 eck$LassoCheckResult]: Loop: 11117#L1553-2 assume !false; 11118#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12027#L999 assume !false; 12075#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11202#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11095#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11590#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11944#L854 assume !(0 != eval_~tmp~0#1); 11945#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11389#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11390#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12207#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11716#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11686#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11687#L1039-3 assume !(0 == ~T4_E~0); 12010#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11297#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11298#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11073#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11074#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11658#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11659#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11988#L1079-3 assume !(0 == ~E_1~0); 11886#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11773#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11774#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11703#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11704#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12008#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11996#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11997#L1119-3 assume !(0 == ~E_9~0); 12277#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12284#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12244#L502-36 assume !(1 == ~m_pc~0); 11444#L502-38 is_master_triggered_~__retres1~0#1 := 0; 10929#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10930#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11354#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11355#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11632#L521-36 assume 1 == ~t1_pc~0; 11633#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11642#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11809#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11846#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12071#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12072#L540-36 assume 1 == ~t2_pc~0; 12246#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11021#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11433#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12285#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11748#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10937#L559-36 assume 1 == ~t3_pc~0; 10938#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11391#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11247#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11248#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11894#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12130#L578-36 assume 1 == ~t4_pc~0; 11865#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11824#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12160#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12161#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11662#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11663#L597-36 assume !(1 == ~t5_pc~0); 11883#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 12233#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11807#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11808#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 11477#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11478#L616-36 assume 1 == ~t6_pc~0; 12247#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11007#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11008#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11610#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11711#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12026#L635-36 assume 1 == ~t7_pc~0; 12210#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12083#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11756#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11757#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11699#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11700#L654-36 assume !(1 == ~t8_pc~0); 12214#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12215#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12287#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12272#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12254#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11382#L673-36 assume !(1 == ~t9_pc~0); 11383#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 11735#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11736#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12090#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10950#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10951#L692-36 assume 1 == ~t10_pc~0; 11885#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11167#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11710#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11345#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11346#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11709#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11854#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12216#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12217#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11787#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11788#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12079#L1167-3 assume !(1 == ~T6_E~0); 12201#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11697#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11602#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11603#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11616#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11441#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11442#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11683#L1207-3 assume !(1 == ~E_3~0); 11798#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12006#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11336#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11034#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11035#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12110#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12111#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12286#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12164#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11186#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11187#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11866#L1572 assume !(0 == start_simulation_~tmp~3#1); 11482#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11635#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10964#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12238#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 12239#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10933#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10934#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12088#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 11117#L1553-2 [2021-12-15 17:20:43,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:43,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2021-12-15 17:20:43,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:43,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709980624] [2021-12-15 17:20:43,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:43,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,024 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,024 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709980624] [2021-12-15 17:20:44,025 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709980624] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,025 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,025 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,025 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1128938477] [2021-12-15 17:20:44,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,026 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,026 INFO L85 PathProgramCache]: Analyzing trace with hash 1162970293, now seen corresponding path program 1 times [2021-12-15 17:20:44,026 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32997896] [2021-12-15 17:20:44,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,027 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,068 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,068 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32997896] [2021-12-15 17:20:44,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32997896] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,068 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,068 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,068 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209315691] [2021-12-15 17:20:44,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,069 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,069 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:44,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:44,070 INFO L87 Difference]: Start difference. First operand 1361 states and 2020 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,087 INFO L93 Difference]: Finished difference Result 1361 states and 2019 transitions. [2021-12-15 17:20:44,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:44,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2019 transitions. [2021-12-15 17:20:44,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2019 transitions. [2021-12-15 17:20:44,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:44,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:44,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2019 transitions. [2021-12-15 17:20:44,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,104 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2021-12-15 17:20:44,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2019 transitions. [2021-12-15 17:20:44,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:44,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2019 transitions. [2021-12-15 17:20:44,121 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2021-12-15 17:20:44,121 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2021-12-15 17:20:44,121 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:44,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2019 transitions. [2021-12-15 17:20:44,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,127 INFO L791 eck$LassoCheckResult]: Stem: 14666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14667#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 13707#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13708#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14596#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14299#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14300#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14578#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14734#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14464#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14465#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14354#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14355#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14694#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14656#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14583#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14584#L1024 assume !(0 == ~M_E~0); 14830#L1024-2 assume !(0 == ~T1_E~0); 14034#L1029-1 assume !(0 == ~T2_E~0); 14035#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14141#L1039-1 assume !(0 == ~T4_E~0); 14947#L1044-1 assume !(0 == ~T5_E~0); 14376#L1049-1 assume !(0 == ~T6_E~0); 14377#L1054-1 assume !(0 == ~T7_E~0); 14604#L1059-1 assume !(0 == ~T8_E~0); 14081#L1064-1 assume !(0 == ~T9_E~0); 14082#L1069-1 assume !(0 == ~T10_E~0); 14798#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14864#L1079-1 assume !(0 == ~E_1~0); 14832#L1084-1 assume !(0 == ~E_2~0); 14833#L1089-1 assume !(0 == ~E_3~0); 14883#L1094-1 assume !(0 == ~E_4~0); 14454#L1099-1 assume !(0 == ~E_5~0); 14455#L1104-1 assume !(0 == ~E_6~0); 14712#L1109-1 assume !(0 == ~E_7~0); 14255#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14256#L1119-1 assume !(0 == ~E_9~0); 14310#L1124-1 assume !(0 == ~E_10~0); 13740#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13741#L502 assume 1 == ~m_pc~0; 14602#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13869#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13870#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14651#L1273 assume !(0 != activate_threads_~tmp~1#1); 14652#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14982#L521 assume !(1 == ~t1_pc~0); 14915#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13800#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13801#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13943#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13782#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13783#L540 assume 1 == ~t2_pc~0; 14846#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14567#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14849#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14862#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 14909#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14056#L559 assume 1 == ~t3_pc~0; 14057#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14335#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14336#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14479#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13887#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13888#L578 assume !(1 == ~t4_pc~0); 14006#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14005#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13776#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13777#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14634#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14635#L597 assume 1 == ~t5_pc~0; 14997#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13821#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13822#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14422#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14585#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14586#L616 assume !(1 == ~t6_pc~0); 14600#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14599#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14964#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14509#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14446#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14447#L635 assume 1 == ~t7_pc~0; 14639#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13790#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14161#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14807#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14579#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14580#L654 assume !(1 == ~t8_pc~0); 14402#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14403#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14910#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14795#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14796#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14032#L673 assume 1 == ~t9_pc~0; 14033#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13731#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14979#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14765#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14721#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14722#L692 assume !(1 == ~t10_pc~0); 14670#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14669#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14588#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14458#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14459#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14776#L1142 assume !(1 == ~M_E~0); 13947#L1142-2 assume !(1 == ~T1_E~0); 13948#L1147-1 assume !(1 == ~T2_E~0); 14766#L1152-1 assume !(1 == ~T3_E~0); 14342#L1157-1 assume !(1 == ~T4_E~0); 14343#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14483#L1167-1 assume !(1 == ~T6_E~0); 14484#L1172-1 assume !(1 == ~T7_E~0); 14903#L1177-1 assume !(1 == ~T8_E~0); 14621#L1182-1 assume !(1 == ~T9_E~0); 14622#L1187-1 assume !(1 == ~T10_E~0); 14715#L1192-1 assume !(1 == ~E_M~0); 14206#L1197-1 assume !(1 == ~E_1~0); 14207#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14570#L1207-1 assume !(1 == ~E_3~0); 14549#L1212-1 assume !(1 == ~E_4~0); 13806#L1217-1 assume !(1 == ~E_5~0); 13807#L1222-1 assume !(1 == ~E_6~0); 14545#L1227-1 assume !(1 == ~E_7~0); 14546#L1232-1 assume !(1 == ~E_8~0); 13672#L1237-1 assume !(1 == ~E_9~0); 13673#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14603#L1247-1 assume { :end_inline_reset_delta_events } true; 13846#L1553-2 [2021-12-15 17:20:44,127 INFO L793 eck$LassoCheckResult]: Loop: 13846#L1553-2 assume !false; 13847#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14756#L999 assume !false; 14802#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13931#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13824#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14319#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14673#L854 assume !(0 != eval_~tmp~0#1); 14674#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14118#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14119#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14936#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14445#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14415#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14416#L1039-3 assume !(0 == ~T4_E~0); 14739#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14026#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14027#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13802#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13803#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14387#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14388#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14717#L1079-3 assume !(0 == ~E_1~0); 14614#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14502#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14503#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14432#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14433#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14737#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14725#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14726#L1119-3 assume !(0 == ~E_9~0); 15006#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15013#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14973#L502-36 assume 1 == ~m_pc~0; 14740#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13658#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13659#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14083#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14084#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14359#L521-36 assume 1 == ~t1_pc~0; 14360#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14371#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14538#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14575#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14800#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14801#L540-36 assume !(1 == ~t2_pc~0); 13747#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 13748#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14162#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15014#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14478#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13669#L559-36 assume 1 == ~t3_pc~0; 13670#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14126#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13976#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13977#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14623#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14859#L578-36 assume 1 == ~t4_pc~0; 14594#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14556#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14889#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14890#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14393#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14394#L597-36 assume !(1 == ~t5_pc~0); 14612#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 14962#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14536#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14537#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 14208#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14209#L616-36 assume 1 == ~t6_pc~0; 14976#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13736#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13737#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14339#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14440#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14755#L635-36 assume 1 == ~t7_pc~0; 14939#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14812#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14485#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14486#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14428#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14429#L654-36 assume 1 == ~t8_pc~0; 15009#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14944#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15016#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15001#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14983#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14111#L673-36 assume !(1 == ~t9_pc~0); 14112#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14466#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14467#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14819#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13679#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13680#L692-36 assume 1 == ~t10_pc~0; 14615#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13896#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14439#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14074#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14075#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14438#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14587#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14945#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14946#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14516#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14517#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14808#L1167-3 assume !(1 == ~T6_E~0); 14930#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14427#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14331#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14332#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14345#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14170#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14171#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14412#L1207-3 assume !(1 == ~E_3~0); 14527#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14735#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14066#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13763#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13764#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14840#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14841#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15015#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14893#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13915#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13916#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14595#L1572 assume !(0 == start_simulation_~tmp~3#1); 14213#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14364#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13693#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14967#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 14968#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13662#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13663#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14817#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13846#L1553-2 [2021-12-15 17:20:44,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,128 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2021-12-15 17:20:44,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715510049] [2021-12-15 17:20:44,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,157 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715510049] [2021-12-15 17:20:44,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715510049] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,157 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518470075] [2021-12-15 17:20:44,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,158 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,161 INFO L85 PathProgramCache]: Analyzing trace with hash 1080059252, now seen corresponding path program 1 times [2021-12-15 17:20:44,161 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719139350] [2021-12-15 17:20:44,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,164 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,188 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [719139350] [2021-12-15 17:20:44,193 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [719139350] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,193 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,193 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,194 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430243247] [2021-12-15 17:20:44,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,194 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,194 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:44,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:44,195 INFO L87 Difference]: Start difference. First operand 1361 states and 2019 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,210 INFO L93 Difference]: Finished difference Result 1361 states and 2018 transitions. [2021-12-15 17:20:44,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:44,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2018 transitions. [2021-12-15 17:20:44,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2018 transitions. [2021-12-15 17:20:44,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:44,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:44,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2018 transitions. [2021-12-15 17:20:44,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,223 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2021-12-15 17:20:44,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2018 transitions. [2021-12-15 17:20:44,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:44,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2018 transitions. [2021-12-15 17:20:44,239 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2021-12-15 17:20:44,239 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2021-12-15 17:20:44,239 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:44,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2018 transitions. [2021-12-15 17:20:44,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,245 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,245 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,246 INFO L791 eck$LassoCheckResult]: Stem: 17395#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17396#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16436#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16437#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17325#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 17028#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17029#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17307#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17463#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17193#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17194#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17083#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17084#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17423#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17385#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17312#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17313#L1024 assume !(0 == ~M_E~0); 17559#L1024-2 assume !(0 == ~T1_E~0); 16763#L1029-1 assume !(0 == ~T2_E~0); 16764#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16870#L1039-1 assume !(0 == ~T4_E~0); 17676#L1044-1 assume !(0 == ~T5_E~0); 17105#L1049-1 assume !(0 == ~T6_E~0); 17106#L1054-1 assume !(0 == ~T7_E~0); 17333#L1059-1 assume !(0 == ~T8_E~0); 16810#L1064-1 assume !(0 == ~T9_E~0); 16811#L1069-1 assume !(0 == ~T10_E~0); 17527#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17593#L1079-1 assume !(0 == ~E_1~0); 17561#L1084-1 assume !(0 == ~E_2~0); 17562#L1089-1 assume !(0 == ~E_3~0); 17612#L1094-1 assume !(0 == ~E_4~0); 17183#L1099-1 assume !(0 == ~E_5~0); 17184#L1104-1 assume !(0 == ~E_6~0); 17441#L1109-1 assume !(0 == ~E_7~0); 16984#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 16985#L1119-1 assume !(0 == ~E_9~0); 17039#L1124-1 assume !(0 == ~E_10~0); 16469#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16470#L502 assume 1 == ~m_pc~0; 17331#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16598#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16599#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17380#L1273 assume !(0 != activate_threads_~tmp~1#1); 17381#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17711#L521 assume !(1 == ~t1_pc~0); 17644#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16529#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16530#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16672#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 16511#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16512#L540 assume 1 == ~t2_pc~0; 17575#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17296#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17578#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17591#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 17638#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16785#L559 assume 1 == ~t3_pc~0; 16786#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17064#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17065#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17208#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 16616#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16617#L578 assume !(1 == ~t4_pc~0); 16735#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16734#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16505#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16506#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17363#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17364#L597 assume 1 == ~t5_pc~0; 17726#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16550#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16551#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17151#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 17314#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17315#L616 assume !(1 == ~t6_pc~0); 17329#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17328#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17693#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17238#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 17175#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17176#L635 assume 1 == ~t7_pc~0; 17368#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16519#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16890#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17536#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 17308#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17309#L654 assume !(1 == ~t8_pc~0); 17131#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17132#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17639#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17524#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 17525#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16761#L673 assume 1 == ~t9_pc~0; 16762#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16460#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17708#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17494#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 17450#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17451#L692 assume !(1 == ~t10_pc~0); 17399#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17398#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17317#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17187#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 17188#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17505#L1142 assume !(1 == ~M_E~0); 16676#L1142-2 assume !(1 == ~T1_E~0); 16677#L1147-1 assume !(1 == ~T2_E~0); 17495#L1152-1 assume !(1 == ~T3_E~0); 17071#L1157-1 assume !(1 == ~T4_E~0); 17072#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17212#L1167-1 assume !(1 == ~T6_E~0); 17213#L1172-1 assume !(1 == ~T7_E~0); 17632#L1177-1 assume !(1 == ~T8_E~0); 17350#L1182-1 assume !(1 == ~T9_E~0); 17351#L1187-1 assume !(1 == ~T10_E~0); 17444#L1192-1 assume !(1 == ~E_M~0); 16935#L1197-1 assume !(1 == ~E_1~0); 16936#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17299#L1207-1 assume !(1 == ~E_3~0); 17278#L1212-1 assume !(1 == ~E_4~0); 16535#L1217-1 assume !(1 == ~E_5~0); 16536#L1222-1 assume !(1 == ~E_6~0); 17274#L1227-1 assume !(1 == ~E_7~0); 17275#L1232-1 assume !(1 == ~E_8~0); 16401#L1237-1 assume !(1 == ~E_9~0); 16402#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17332#L1247-1 assume { :end_inline_reset_delta_events } true; 16575#L1553-2 [2021-12-15 17:20:44,246 INFO L793 eck$LassoCheckResult]: Loop: 16575#L1553-2 assume !false; 16576#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17485#L999 assume !false; 17531#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16660#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16553#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17048#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17402#L854 assume !(0 != eval_~tmp~0#1); 17403#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16847#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16848#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17665#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17174#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17144#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17145#L1039-3 assume !(0 == ~T4_E~0); 17468#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16755#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16756#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16531#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16532#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17116#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17117#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17446#L1079-3 assume !(0 == ~E_1~0); 17343#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17231#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17232#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17161#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17162#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17466#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17454#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17455#L1119-3 assume !(0 == ~E_9~0); 17735#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17742#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17702#L502-36 assume !(1 == ~m_pc~0); 16902#L502-38 is_master_triggered_~__retres1~0#1 := 0; 16387#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16388#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16812#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16813#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17088#L521-36 assume 1 == ~t1_pc~0; 17089#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17100#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17267#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17304#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17529#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17530#L540-36 assume 1 == ~t2_pc~0; 17704#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16477#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16891#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17743#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17207#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16398#L559-36 assume !(1 == ~t3_pc~0); 16400#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 16855#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16705#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16706#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17352#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17588#L578-36 assume !(1 == ~t4_pc~0); 17284#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 17285#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17618#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17619#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17122#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17123#L597-36 assume !(1 == ~t5_pc~0); 17341#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 17691#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17265#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17266#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 16937#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16938#L616-36 assume 1 == ~t6_pc~0; 17705#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16465#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16466#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17068#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17169#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17484#L635-36 assume 1 == ~t7_pc~0; 17668#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17541#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17214#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17215#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17157#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17158#L654-36 assume !(1 == ~t8_pc~0); 17672#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 17673#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17745#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17730#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17712#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16840#L673-36 assume !(1 == ~t9_pc~0); 16841#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 17195#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17196#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17548#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16408#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16409#L692-36 assume 1 == ~t10_pc~0; 17344#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16625#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17168#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16803#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16804#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17167#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17316#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17674#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17675#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17245#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17246#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17537#L1167-3 assume !(1 == ~T6_E~0); 17659#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17156#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17060#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17061#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17074#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16899#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16900#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17141#L1207-3 assume !(1 == ~E_3~0); 17256#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17464#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16795#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16492#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16493#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17569#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17570#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17744#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17622#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16644#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16645#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17324#L1572 assume !(0 == start_simulation_~tmp~3#1); 16940#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17093#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16422#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17696#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 17697#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16391#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16392#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17546#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 16575#L1553-2 [2021-12-15 17:20:44,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,247 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2021-12-15 17:20:44,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262315835] [2021-12-15 17:20:44,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1262315835] [2021-12-15 17:20:44,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1262315835] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,267 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109363282] [2021-12-15 17:20:44,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,268 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,268 INFO L85 PathProgramCache]: Analyzing trace with hash -2079491209, now seen corresponding path program 1 times [2021-12-15 17:20:44,268 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830360974] [2021-12-15 17:20:44,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,269 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,295 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830360974] [2021-12-15 17:20:44,295 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830360974] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,295 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,295 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,296 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34285947] [2021-12-15 17:20:44,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,296 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,296 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:44,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:44,297 INFO L87 Difference]: Start difference. First operand 1361 states and 2018 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,311 INFO L93 Difference]: Finished difference Result 1361 states and 2017 transitions. [2021-12-15 17:20:44,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:44,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2017 transitions. [2021-12-15 17:20:44,316 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2017 transitions. [2021-12-15 17:20:44,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:44,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:44,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2017 transitions. [2021-12-15 17:20:44,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,322 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2021-12-15 17:20:44,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2017 transitions. [2021-12-15 17:20:44,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:44,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2017 transitions. [2021-12-15 17:20:44,357 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2021-12-15 17:20:44,357 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2021-12-15 17:20:44,357 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:44,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2017 transitions. [2021-12-15 17:20:44,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,361 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,361 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,362 INFO L791 eck$LassoCheckResult]: Stem: 20124#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 20125#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19165#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19166#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20054#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19758#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19759#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20036#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20192#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19924#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19925#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19814#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19815#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20152#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20114#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20042#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20043#L1024 assume !(0 == ~M_E~0); 20288#L1024-2 assume !(0 == ~T1_E~0); 19492#L1029-1 assume !(0 == ~T2_E~0); 19493#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19599#L1039-1 assume !(0 == ~T4_E~0); 20405#L1044-1 assume !(0 == ~T5_E~0); 19836#L1049-1 assume !(0 == ~T6_E~0); 19837#L1054-1 assume !(0 == ~T7_E~0); 20062#L1059-1 assume !(0 == ~T8_E~0); 19539#L1064-1 assume !(0 == ~T9_E~0); 19540#L1069-1 assume !(0 == ~T10_E~0); 20256#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20322#L1079-1 assume !(0 == ~E_1~0); 20290#L1084-1 assume !(0 == ~E_2~0); 20291#L1089-1 assume !(0 == ~E_3~0); 20341#L1094-1 assume !(0 == ~E_4~0); 19912#L1099-1 assume !(0 == ~E_5~0); 19913#L1104-1 assume !(0 == ~E_6~0); 20170#L1109-1 assume !(0 == ~E_7~0); 19713#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19714#L1119-1 assume !(0 == ~E_9~0); 19770#L1124-1 assume !(0 == ~E_10~0); 19198#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19199#L502 assume 1 == ~m_pc~0; 20060#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19327#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19328#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20110#L1273 assume !(0 != activate_threads_~tmp~1#1); 20111#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20440#L521 assume !(1 == ~t1_pc~0); 20373#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19258#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19259#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19402#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19242#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19243#L540 assume 1 == ~t2_pc~0; 20304#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20025#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20307#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20320#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20367#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19514#L559 assume 1 == ~t3_pc~0; 19515#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19794#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19795#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19937#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19345#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19346#L578 assume !(1 == ~t4_pc~0); 19466#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19465#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19234#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19235#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20094#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20095#L597 assume 1 == ~t5_pc~0; 20457#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19279#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19280#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19885#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20044#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20045#L616 assume !(1 == ~t6_pc~0); 20059#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20058#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20422#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19967#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 19904#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19905#L635 assume 1 == ~t7_pc~0; 20099#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19248#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19619#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20265#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20037#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20038#L654 assume !(1 == ~t8_pc~0); 19860#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19861#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20368#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20253#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20254#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19490#L673 assume 1 == ~t9_pc~0; 19491#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19189#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20437#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20223#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20179#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20180#L692 assume !(1 == ~t10_pc~0); 20128#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20127#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20046#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19916#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 19917#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20234#L1142 assume !(1 == ~M_E~0); 19405#L1142-2 assume !(1 == ~T1_E~0); 19406#L1147-1 assume !(1 == ~T2_E~0); 20224#L1152-1 assume !(1 == ~T3_E~0); 19800#L1157-1 assume !(1 == ~T4_E~0); 19801#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19941#L1167-1 assume !(1 == ~T6_E~0); 19942#L1172-1 assume !(1 == ~T7_E~0); 20361#L1177-1 assume !(1 == ~T8_E~0); 20079#L1182-1 assume !(1 == ~T9_E~0); 20080#L1187-1 assume !(1 == ~T10_E~0); 20173#L1192-1 assume !(1 == ~E_M~0); 19666#L1197-1 assume !(1 == ~E_1~0); 19667#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20028#L1207-1 assume !(1 == ~E_3~0); 20007#L1212-1 assume !(1 == ~E_4~0); 19264#L1217-1 assume !(1 == ~E_5~0); 19265#L1222-1 assume !(1 == ~E_6~0); 20003#L1227-1 assume !(1 == ~E_7~0); 20004#L1232-1 assume !(1 == ~E_8~0); 19130#L1237-1 assume !(1 == ~E_9~0); 19131#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20061#L1247-1 assume { :end_inline_reset_delta_events } true; 19304#L1553-2 [2021-12-15 17:20:44,362 INFO L793 eck$LassoCheckResult]: Loop: 19304#L1553-2 assume !false; 19305#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20214#L999 assume !false; 20262#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19389#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19282#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19777#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20131#L854 assume !(0 != eval_~tmp~0#1); 20132#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19576#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19577#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20394#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19903#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19873#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19874#L1039-3 assume !(0 == ~T4_E~0); 20197#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19484#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19485#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19260#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19261#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19845#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19846#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20175#L1079-3 assume !(0 == ~E_1~0); 20073#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19960#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19961#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19890#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19891#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20195#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20183#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20184#L1119-3 assume !(0 == ~E_9~0); 20464#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20471#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20431#L502-36 assume 1 == ~m_pc~0; 20198#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19116#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19117#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19541#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19542#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19819#L521-36 assume 1 == ~t1_pc~0; 19820#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19829#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19996#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20033#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20258#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20259#L540-36 assume 1 == ~t2_pc~0; 20433#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19208#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19620#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20472#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19935#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19124#L559-36 assume 1 == ~t3_pc~0; 19125#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19578#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19434#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19435#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20081#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20317#L578-36 assume 1 == ~t4_pc~0; 20052#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20011#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20347#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20348#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19849#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19850#L597-36 assume !(1 == ~t5_pc~0); 20067#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20420#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19994#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19995#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 19664#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19665#L616-36 assume 1 == ~t6_pc~0; 20434#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19194#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19195#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19797#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19898#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20213#L635-36 assume 1 == ~t7_pc~0; 20397#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20270#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19943#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19944#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19886#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19887#L654-36 assume !(1 == ~t8_pc~0); 20401#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 20402#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20474#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20459#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20441#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19569#L673-36 assume !(1 == ~t9_pc~0); 19570#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19922#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19923#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20277#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19137#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19138#L692-36 assume 1 == ~t10_pc~0; 20072#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19354#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19897#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19532#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19533#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19896#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20041#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20403#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20404#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19974#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19975#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20266#L1167-3 assume !(1 == ~T6_E~0); 20388#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19884#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19789#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19790#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19803#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19628#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19629#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19870#L1207-3 assume !(1 == ~E_3~0); 19985#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20193#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19523#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19221#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19222#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20297#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20298#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20473#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20351#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19373#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19374#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 20053#L1572 assume !(0 == start_simulation_~tmp~3#1); 19669#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19822#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19151#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20425#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 20426#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19120#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19121#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20275#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19304#L1553-2 [2021-12-15 17:20:44,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,362 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2021-12-15 17:20:44,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023435795] [2021-12-15 17:20:44,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,363 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,380 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,380 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023435795] [2021-12-15 17:20:44,381 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1023435795] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,381 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,381 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,381 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [208741490] [2021-12-15 17:20:44,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,381 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,382 INFO L85 PathProgramCache]: Analyzing trace with hash -2102005260, now seen corresponding path program 1 times [2021-12-15 17:20:44,382 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795548930] [2021-12-15 17:20:44,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,382 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,404 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,404 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795548930] [2021-12-15 17:20:44,405 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [795548930] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,405 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,405 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,405 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673416402] [2021-12-15 17:20:44,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,405 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,405 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:44,406 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:44,406 INFO L87 Difference]: Start difference. First operand 1361 states and 2017 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,420 INFO L93 Difference]: Finished difference Result 1361 states and 2016 transitions. [2021-12-15 17:20:44,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:44,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2016 transitions. [2021-12-15 17:20:44,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2016 transitions. [2021-12-15 17:20:44,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:44,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:44,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2016 transitions. [2021-12-15 17:20:44,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,431 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2021-12-15 17:20:44,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2016 transitions. [2021-12-15 17:20:44,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:44,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2016 transitions. [2021-12-15 17:20:44,446 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2021-12-15 17:20:44,446 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2021-12-15 17:20:44,446 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:44,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2016 transitions. [2021-12-15 17:20:44,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,450 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,451 INFO L791 eck$LassoCheckResult]: Stem: 22853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21894#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21895#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22783#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 22486#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22487#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22765#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22921#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22651#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22652#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22541#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22542#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22881#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22843#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22770#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22771#L1024 assume !(0 == ~M_E~0); 23017#L1024-2 assume !(0 == ~T1_E~0); 22221#L1029-1 assume !(0 == ~T2_E~0); 22222#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22328#L1039-1 assume !(0 == ~T4_E~0); 23134#L1044-1 assume !(0 == ~T5_E~0); 22563#L1049-1 assume !(0 == ~T6_E~0); 22564#L1054-1 assume !(0 == ~T7_E~0); 22791#L1059-1 assume !(0 == ~T8_E~0); 22268#L1064-1 assume !(0 == ~T9_E~0); 22269#L1069-1 assume !(0 == ~T10_E~0); 22985#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 23051#L1079-1 assume !(0 == ~E_1~0); 23019#L1084-1 assume !(0 == ~E_2~0); 23020#L1089-1 assume !(0 == ~E_3~0); 23070#L1094-1 assume !(0 == ~E_4~0); 22641#L1099-1 assume !(0 == ~E_5~0); 22642#L1104-1 assume !(0 == ~E_6~0); 22899#L1109-1 assume !(0 == ~E_7~0); 22442#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22443#L1119-1 assume !(0 == ~E_9~0); 22497#L1124-1 assume !(0 == ~E_10~0); 21927#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21928#L502 assume 1 == ~m_pc~0; 22789#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22056#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22057#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22838#L1273 assume !(0 != activate_threads_~tmp~1#1); 22839#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23169#L521 assume !(1 == ~t1_pc~0); 23102#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21987#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21988#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22130#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 21969#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21970#L540 assume 1 == ~t2_pc~0; 23033#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22754#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23036#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23049#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 23096#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22243#L559 assume 1 == ~t3_pc~0; 22244#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22522#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22523#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22666#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 22074#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22075#L578 assume !(1 == ~t4_pc~0); 22193#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22192#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21963#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21964#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22821#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22822#L597 assume 1 == ~t5_pc~0; 23184#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22008#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22009#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22609#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 22772#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22773#L616 assume !(1 == ~t6_pc~0); 22787#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22786#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23151#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22696#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 22633#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22634#L635 assume 1 == ~t7_pc~0; 22826#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21977#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22348#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22994#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 22766#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22767#L654 assume !(1 == ~t8_pc~0); 22589#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22590#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23097#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22982#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 22983#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22219#L673 assume 1 == ~t9_pc~0; 22220#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21918#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23166#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22952#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 22908#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22909#L692 assume !(1 == ~t10_pc~0); 22857#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22856#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22775#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22645#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 22646#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22963#L1142 assume !(1 == ~M_E~0); 22134#L1142-2 assume !(1 == ~T1_E~0); 22135#L1147-1 assume !(1 == ~T2_E~0); 22953#L1152-1 assume !(1 == ~T3_E~0); 22529#L1157-1 assume !(1 == ~T4_E~0); 22530#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22670#L1167-1 assume !(1 == ~T6_E~0); 22671#L1172-1 assume !(1 == ~T7_E~0); 23090#L1177-1 assume !(1 == ~T8_E~0); 22808#L1182-1 assume !(1 == ~T9_E~0); 22809#L1187-1 assume !(1 == ~T10_E~0); 22902#L1192-1 assume !(1 == ~E_M~0); 22393#L1197-1 assume !(1 == ~E_1~0); 22394#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22757#L1207-1 assume !(1 == ~E_3~0); 22736#L1212-1 assume !(1 == ~E_4~0); 21993#L1217-1 assume !(1 == ~E_5~0); 21994#L1222-1 assume !(1 == ~E_6~0); 22732#L1227-1 assume !(1 == ~E_7~0); 22733#L1232-1 assume !(1 == ~E_8~0); 21859#L1237-1 assume !(1 == ~E_9~0); 21860#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22790#L1247-1 assume { :end_inline_reset_delta_events } true; 22033#L1553-2 [2021-12-15 17:20:44,451 INFO L793 eck$LassoCheckResult]: Loop: 22033#L1553-2 assume !false; 22034#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22943#L999 assume !false; 22989#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22118#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22011#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22506#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22860#L854 assume !(0 != eval_~tmp~0#1); 22861#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22305#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22306#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23123#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22632#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22602#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22603#L1039-3 assume !(0 == ~T4_E~0); 22926#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22213#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22214#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21989#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21990#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22574#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22575#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22904#L1079-3 assume !(0 == ~E_1~0); 22801#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22689#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22690#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22619#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22620#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22924#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22912#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22913#L1119-3 assume !(0 == ~E_9~0); 23193#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23200#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23160#L502-36 assume !(1 == ~m_pc~0); 22360#L502-38 is_master_triggered_~__retres1~0#1 := 0; 21845#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21846#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22270#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22271#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22546#L521-36 assume 1 == ~t1_pc~0; 22547#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22558#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22725#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22762#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22987#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22988#L540-36 assume 1 == ~t2_pc~0; 23162#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21935#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22349#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23201#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22665#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21856#L559-36 assume 1 == ~t3_pc~0; 21857#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22313#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22163#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22164#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22810#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23046#L578-36 assume !(1 == ~t4_pc~0); 22742#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 22743#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23076#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23077#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22580#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22581#L597-36 assume 1 == ~t5_pc~0; 22800#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23149#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22723#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22724#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 22395#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22396#L616-36 assume !(1 == ~t6_pc~0); 23121#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 21923#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21924#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22526#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22627#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22942#L635-36 assume 1 == ~t7_pc~0; 23126#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22999#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22672#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22673#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22615#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22616#L654-36 assume !(1 == ~t8_pc~0); 23130#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 23131#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23203#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23188#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23170#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22298#L673-36 assume !(1 == ~t9_pc~0); 22299#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22653#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22654#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23006#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21866#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21867#L692-36 assume 1 == ~t10_pc~0; 22802#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22083#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22626#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22261#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22262#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22625#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22774#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23132#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23133#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22703#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22704#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22995#L1167-3 assume !(1 == ~T6_E~0); 23117#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22614#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22518#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22519#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22532#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22357#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22358#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22599#L1207-3 assume !(1 == ~E_3~0); 22714#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22922#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22253#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21950#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21951#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23027#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23028#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23202#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23080#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22102#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22103#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 22782#L1572 assume !(0 == start_simulation_~tmp~3#1); 22400#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22551#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21880#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23154#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 23155#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21849#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21850#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 23004#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 22033#L1553-2 [2021-12-15 17:20:44,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,452 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2021-12-15 17:20:44,452 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715604998] [2021-12-15 17:20:44,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,452 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,469 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715604998] [2021-12-15 17:20:44,469 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715604998] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,469 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236362682] [2021-12-15 17:20:44,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,470 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1653620534, now seen corresponding path program 1 times [2021-12-15 17:20:44,471 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381343381] [2021-12-15 17:20:44,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,471 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,496 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381343381] [2021-12-15 17:20:44,496 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381343381] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,496 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,496 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,496 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491924437] [2021-12-15 17:20:44,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,497 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,497 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:44,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:44,497 INFO L87 Difference]: Start difference. First operand 1361 states and 2016 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,511 INFO L93 Difference]: Finished difference Result 1361 states and 2015 transitions. [2021-12-15 17:20:44,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:44,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2015 transitions. [2021-12-15 17:20:44,515 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2015 transitions. [2021-12-15 17:20:44,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2021-12-15 17:20:44,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2021-12-15 17:20:44,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2015 transitions. [2021-12-15 17:20:44,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,521 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2021-12-15 17:20:44,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2015 transitions. [2021-12-15 17:20:44,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2021-12-15 17:20:44,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2015 transitions. [2021-12-15 17:20:44,536 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2021-12-15 17:20:44,536 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2021-12-15 17:20:44,536 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:44,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2015 transitions. [2021-12-15 17:20:44,539 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2021-12-15 17:20:44,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,540 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,540 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,540 INFO L791 eck$LassoCheckResult]: Stem: 25582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24623#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24624#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25512#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25215#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25216#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25494#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25650#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25380#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25381#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25270#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25271#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25610#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25572#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 25499#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25500#L1024 assume !(0 == ~M_E~0); 25746#L1024-2 assume !(0 == ~T1_E~0); 24950#L1029-1 assume !(0 == ~T2_E~0); 24951#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25057#L1039-1 assume !(0 == ~T4_E~0); 25863#L1044-1 assume !(0 == ~T5_E~0); 25292#L1049-1 assume !(0 == ~T6_E~0); 25293#L1054-1 assume !(0 == ~T7_E~0); 25520#L1059-1 assume !(0 == ~T8_E~0); 24997#L1064-1 assume !(0 == ~T9_E~0); 24998#L1069-1 assume !(0 == ~T10_E~0); 25714#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25780#L1079-1 assume !(0 == ~E_1~0); 25748#L1084-1 assume !(0 == ~E_2~0); 25749#L1089-1 assume !(0 == ~E_3~0); 25799#L1094-1 assume !(0 == ~E_4~0); 25370#L1099-1 assume !(0 == ~E_5~0); 25371#L1104-1 assume !(0 == ~E_6~0); 25628#L1109-1 assume !(0 == ~E_7~0); 25171#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25172#L1119-1 assume !(0 == ~E_9~0); 25226#L1124-1 assume !(0 == ~E_10~0); 24656#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24657#L502 assume 1 == ~m_pc~0; 25518#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24785#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24786#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25567#L1273 assume !(0 != activate_threads_~tmp~1#1); 25568#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25898#L521 assume !(1 == ~t1_pc~0); 25831#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24716#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24717#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24859#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24698#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24699#L540 assume 1 == ~t2_pc~0; 25762#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25483#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25765#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25778#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 25825#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24972#L559 assume 1 == ~t3_pc~0; 24973#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25251#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25252#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25395#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24803#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24804#L578 assume !(1 == ~t4_pc~0); 24922#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24921#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24692#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24693#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25550#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25551#L597 assume 1 == ~t5_pc~0; 25913#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24737#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24738#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25338#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25501#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25502#L616 assume !(1 == ~t6_pc~0); 25516#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25515#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25880#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25425#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25362#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25363#L635 assume 1 == ~t7_pc~0; 25555#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24706#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25077#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25723#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25495#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25496#L654 assume !(1 == ~t8_pc~0); 25318#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25319#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25826#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25711#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25712#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24948#L673 assume 1 == ~t9_pc~0; 24949#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24647#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25895#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25681#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25637#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25638#L692 assume !(1 == ~t10_pc~0); 25586#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25585#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25504#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25374#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25375#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25692#L1142 assume !(1 == ~M_E~0); 24863#L1142-2 assume !(1 == ~T1_E~0); 24864#L1147-1 assume !(1 == ~T2_E~0); 25682#L1152-1 assume !(1 == ~T3_E~0); 25258#L1157-1 assume !(1 == ~T4_E~0); 25259#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25399#L1167-1 assume !(1 == ~T6_E~0); 25400#L1172-1 assume !(1 == ~T7_E~0); 25819#L1177-1 assume !(1 == ~T8_E~0); 25537#L1182-1 assume !(1 == ~T9_E~0); 25538#L1187-1 assume !(1 == ~T10_E~0); 25631#L1192-1 assume !(1 == ~E_M~0); 25122#L1197-1 assume !(1 == ~E_1~0); 25123#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25486#L1207-1 assume !(1 == ~E_3~0); 25465#L1212-1 assume !(1 == ~E_4~0); 24722#L1217-1 assume !(1 == ~E_5~0); 24723#L1222-1 assume !(1 == ~E_6~0); 25461#L1227-1 assume !(1 == ~E_7~0); 25462#L1232-1 assume !(1 == ~E_8~0); 24588#L1237-1 assume !(1 == ~E_9~0); 24589#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25519#L1247-1 assume { :end_inline_reset_delta_events } true; 24762#L1553-2 [2021-12-15 17:20:44,540 INFO L793 eck$LassoCheckResult]: Loop: 24762#L1553-2 assume !false; 24763#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25672#L999 assume !false; 25718#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24847#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24740#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25235#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25589#L854 assume !(0 != eval_~tmp~0#1); 25590#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25034#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25035#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25852#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25361#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25331#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25332#L1039-3 assume !(0 == ~T4_E~0); 25655#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24942#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24943#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24718#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24719#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25303#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25304#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25633#L1079-3 assume !(0 == ~E_1~0); 25530#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25418#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25419#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25348#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25349#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25653#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25641#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25642#L1119-3 assume !(0 == ~E_9~0); 25922#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25929#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25889#L502-36 assume !(1 == ~m_pc~0); 25089#L502-38 is_master_triggered_~__retres1~0#1 := 0; 24574#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24575#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24999#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25000#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25275#L521-36 assume 1 == ~t1_pc~0; 25276#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25287#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25454#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25491#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25716#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25717#L540-36 assume 1 == ~t2_pc~0; 25891#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24664#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25078#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25930#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25394#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24585#L559-36 assume 1 == ~t3_pc~0; 24586#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25042#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24892#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24893#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25539#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25775#L578-36 assume 1 == ~t4_pc~0; 25510#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25472#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25805#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25806#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25309#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25310#L597-36 assume !(1 == ~t5_pc~0); 25528#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 25878#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25452#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25453#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 25124#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25125#L616-36 assume 1 == ~t6_pc~0; 25892#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24652#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24653#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25255#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25356#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25671#L635-36 assume !(1 == ~t7_pc~0); 25856#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 25728#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25401#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25402#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25344#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25345#L654-36 assume !(1 == ~t8_pc~0); 25859#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 25860#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25932#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25917#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25899#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25027#L673-36 assume !(1 == ~t9_pc~0); 25028#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25382#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25383#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25735#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24595#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24596#L692-36 assume 1 == ~t10_pc~0; 25531#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24812#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25355#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24990#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24991#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25354#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25503#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25861#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25862#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25432#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25433#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25724#L1167-3 assume !(1 == ~T6_E~0); 25846#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25343#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25247#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25248#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25261#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25086#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25087#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25328#L1207-3 assume !(1 == ~E_3~0); 25443#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25651#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24982#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24679#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24680#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25756#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25757#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25931#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25809#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24831#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24832#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25511#L1572 assume !(0 == start_simulation_~tmp~3#1); 25129#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25280#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24609#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25883#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 25884#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24578#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24579#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25733#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24762#L1553-2 [2021-12-15 17:20:44,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,541 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2021-12-15 17:20:44,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333072100] [2021-12-15 17:20:44,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,571 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333072100] [2021-12-15 17:20:44,571 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333072100] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,571 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,572 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333326023] [2021-12-15 17:20:44,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,572 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,572 INFO L85 PathProgramCache]: Analyzing trace with hash 131639478, now seen corresponding path program 1 times [2021-12-15 17:20:44,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086085705] [2021-12-15 17:20:44,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,598 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086085705] [2021-12-15 17:20:44,598 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086085705] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,598 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,599 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,599 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919775837] [2021-12-15 17:20:44,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,599 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,599 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,600 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:44,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:44,600 INFO L87 Difference]: Start difference. First operand 1361 states and 2015 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,682 INFO L93 Difference]: Finished difference Result 2504 states and 3694 transitions. [2021-12-15 17:20:44,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:44,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2504 states and 3694 transitions. [2021-12-15 17:20:44,690 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2021-12-15 17:20:44,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2504 states to 2504 states and 3694 transitions. [2021-12-15 17:20:44,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2504 [2021-12-15 17:20:44,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2504 [2021-12-15 17:20:44,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2504 states and 3694 transitions. [2021-12-15 17:20:44,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,701 INFO L681 BuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2021-12-15 17:20:44,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2504 states and 3694 transitions. [2021-12-15 17:20:44,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2504 to 2504. [2021-12-15 17:20:44,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2504 states to 2504 states and 3694 transitions. [2021-12-15 17:20:44,730 INFO L704 BuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2021-12-15 17:20:44,730 INFO L587 BuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2021-12-15 17:20:44,730 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:44,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2504 states and 3694 transitions. [2021-12-15 17:20:44,735 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2021-12-15 17:20:44,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:44,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:44,736 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,737 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:44,737 INFO L791 eck$LassoCheckResult]: Stem: 29462#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28498#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28499#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29392#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 29092#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29093#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29373#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29530#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29259#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29260#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29147#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29148#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29490#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29452#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 29378#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29379#L1024 assume !(0 == ~M_E~0); 29631#L1024-2 assume !(0 == ~T1_E~0); 28827#L1029-1 assume !(0 == ~T2_E~0); 28828#L1034-1 assume !(0 == ~T3_E~0); 28934#L1039-1 assume !(0 == ~T4_E~0); 29752#L1044-1 assume !(0 == ~T5_E~0); 29170#L1049-1 assume !(0 == ~T6_E~0); 29171#L1054-1 assume !(0 == ~T7_E~0); 29400#L1059-1 assume !(0 == ~T8_E~0); 28874#L1064-1 assume !(0 == ~T9_E~0); 28875#L1069-1 assume !(0 == ~T10_E~0); 29597#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29666#L1079-1 assume !(0 == ~E_1~0); 29633#L1084-1 assume !(0 == ~E_2~0); 29634#L1089-1 assume !(0 == ~E_3~0); 29685#L1094-1 assume !(0 == ~E_4~0); 29249#L1099-1 assume !(0 == ~E_5~0); 29250#L1104-1 assume !(0 == ~E_6~0); 29508#L1109-1 assume !(0 == ~E_7~0); 29048#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29049#L1119-1 assume !(0 == ~E_9~0); 29103#L1124-1 assume !(0 == ~E_10~0); 28531#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28532#L502 assume 1 == ~m_pc~0; 29398#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28660#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28661#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29447#L1273 assume !(0 != activate_threads_~tmp~1#1); 29448#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29798#L521 assume !(1 == ~t1_pc~0); 29718#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28591#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28592#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28734#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 28573#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28574#L540 assume 1 == ~t2_pc~0; 29648#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29362#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29651#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29664#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 29712#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28849#L559 assume 1 == ~t3_pc~0; 28850#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29128#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29129#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29274#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 28678#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28679#L578 assume !(1 == ~t4_pc~0); 28799#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28798#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28567#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28568#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29430#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29431#L597 assume 1 == ~t5_pc~0; 29822#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28612#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28613#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29216#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 29380#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29381#L616 assume !(1 == ~t6_pc~0); 29396#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29395#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29774#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29304#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 29241#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29242#L635 assume 1 == ~t7_pc~0; 29435#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28581#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28954#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29606#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 29374#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29375#L654 assume !(1 == ~t8_pc~0); 29196#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29197#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29713#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29594#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 29595#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28825#L673 assume 1 == ~t9_pc~0; 28826#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28522#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29794#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29562#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 29517#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29518#L692 assume !(1 == ~t10_pc~0); 29466#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29465#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29384#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29253#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 29254#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29574#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 28738#L1142-2 assume !(1 == ~T1_E~0); 28739#L1147-1 assume !(1 == ~T2_E~0); 29563#L1152-1 assume !(1 == ~T3_E~0); 29135#L1157-1 assume !(1 == ~T4_E~0); 29136#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29978#L1167-1 assume !(1 == ~T6_E~0); 29967#L1172-1 assume !(1 == ~T7_E~0); 29965#L1177-1 assume !(1 == ~T8_E~0); 29963#L1182-1 assume !(1 == ~T9_E~0); 29961#L1187-1 assume !(1 == ~T10_E~0); 29927#L1192-1 assume !(1 == ~E_M~0); 29926#L1197-1 assume !(1 == ~E_1~0); 29925#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29365#L1207-1 assume !(1 == ~E_3~0); 29344#L1212-1 assume !(1 == ~E_4~0); 28597#L1217-1 assume !(1 == ~E_5~0); 28598#L1222-1 assume !(1 == ~E_6~0); 29340#L1227-1 assume !(1 == ~E_7~0); 29341#L1232-1 assume !(1 == ~E_8~0); 28463#L1237-1 assume !(1 == ~E_9~0); 28464#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29399#L1247-1 assume { :end_inline_reset_delta_events } true; 28637#L1553-2 [2021-12-15 17:20:44,737 INFO L793 eck$LassoCheckResult]: Loop: 28637#L1553-2 assume !false; 28638#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29552#L999 assume !false; 29601#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28722#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28615#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29112#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29856#L854 assume !(0 != eval_~tmp~0#1); 29855#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29854#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29853#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29741#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29240#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29209#L1034-3 assume !(0 == ~T3_E~0); 29210#L1039-3 assume !(0 == ~T4_E~0); 29535#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28819#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28820#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28593#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28594#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29181#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29182#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29513#L1079-3 assume !(0 == ~E_1~0); 29410#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29297#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29298#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29226#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29227#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29533#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29521#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29522#L1119-3 assume !(0 == ~E_9~0); 29833#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29843#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29787#L502-36 assume 1 == ~m_pc~0; 29536#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28449#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28450#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28876#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28877#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29152#L521-36 assume 1 == ~t1_pc~0; 29153#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29165#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29333#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29370#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29599#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29600#L540-36 assume !(1 == ~t2_pc~0); 28538#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 28539#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28955#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29844#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29273#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28460#L559-36 assume 1 == ~t3_pc~0; 28461#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28919#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28767#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28768#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29419#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29661#L578-36 assume !(1 == ~t4_pc~0); 29350#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 29351#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29691#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29692#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29187#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29188#L597-36 assume !(1 == ~t5_pc~0); 29408#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 29772#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29331#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29332#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 29001#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29002#L616-36 assume !(1 == ~t6_pc~0); 29739#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 28527#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28528#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29132#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29235#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29551#L635-36 assume 1 == ~t7_pc~0; 29744#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29612#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29280#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29281#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29222#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29223#L654-36 assume !(1 == ~t8_pc~0); 29748#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 29749#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29847#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29826#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29800#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28904#L673-36 assume !(1 == ~t9_pc~0); 28905#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 29261#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29262#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30844#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30843#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30842#L692-36 assume 1 == ~t10_pc~0; 30840#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30839#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30838#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30837#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30836#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30835#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29382#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30834#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30833#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29776#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30832#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30831#L1167-3 assume !(1 == ~T6_E~0); 30830#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30829#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30828#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30827#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30826#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30825#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30824#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30823#L1207-3 assume !(1 == ~E_3~0); 30822#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30821#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30820#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30819#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30818#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30817#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30816#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30815#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30804#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30604#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30603#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 30602#L1572 assume !(0 == start_simulation_~tmp~3#1); 29006#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29842#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28484#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29780#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 29782#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28453#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28454#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 29617#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 28637#L1553-2 [2021-12-15 17:20:44,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2021-12-15 17:20:44,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,738 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772185904] [2021-12-15 17:20:44,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,738 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,761 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,761 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [772185904] [2021-12-15 17:20:44,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [772185904] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282205603] [2021-12-15 17:20:44,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,762 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:44,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:44,763 INFO L85 PathProgramCache]: Analyzing trace with hash -170343111, now seen corresponding path program 1 times [2021-12-15 17:20:44,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:44,763 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4425638] [2021-12-15 17:20:44,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:44,763 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:44,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:44,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:44,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:44,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4425638] [2021-12-15 17:20:44,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [4425638] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:44,788 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:44,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:44,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587024463] [2021-12-15 17:20:44,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:44,789 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:44,789 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:44,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:44,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:44,789 INFO L87 Difference]: Start difference. First operand 2504 states and 3694 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:44,901 INFO L93 Difference]: Finished difference Result 4620 states and 6803 transitions. [2021-12-15 17:20:44,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:44,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4620 states and 6803 transitions. [2021-12-15 17:20:44,917 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2021-12-15 17:20:44,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4620 states to 4620 states and 6803 transitions. [2021-12-15 17:20:44,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4620 [2021-12-15 17:20:44,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4620 [2021-12-15 17:20:44,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4620 states and 6803 transitions. [2021-12-15 17:20:44,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:44,941 INFO L681 BuchiCegarLoop]: Abstraction has 4620 states and 6803 transitions. [2021-12-15 17:20:44,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4620 states and 6803 transitions. [2021-12-15 17:20:44,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4620 to 4618. [2021-12-15 17:20:44,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:44,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4618 states to 4618 states and 6801 transitions. [2021-12-15 17:20:44,997 INFO L704 BuchiCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2021-12-15 17:20:44,997 INFO L587 BuchiCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2021-12-15 17:20:44,997 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:44,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4618 states and 6801 transitions. [2021-12-15 17:20:45,009 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2021-12-15 17:20:45,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:45,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:45,011 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,011 INFO L791 eck$LassoCheckResult]: Stem: 36620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35632#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35633#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36545#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36232#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36233#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36523#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36695#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36405#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36406#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36293#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36294#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36648#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36609#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36533#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36534#L1024 assume !(0 == ~M_E~0); 36810#L1024-2 assume !(0 == ~T1_E~0); 35961#L1029-1 assume !(0 == ~T2_E~0); 35962#L1034-1 assume !(0 == ~T3_E~0); 36070#L1039-1 assume !(0 == ~T4_E~0); 36945#L1044-1 assume !(0 == ~T5_E~0); 36314#L1049-1 assume !(0 == ~T6_E~0); 36315#L1054-1 assume !(0 == ~T7_E~0); 36555#L1059-1 assume !(0 == ~T8_E~0); 36008#L1064-1 assume !(0 == ~T9_E~0); 36009#L1069-1 assume !(0 == ~T10_E~0); 36775#L1074-1 assume !(0 == ~E_M~0); 36851#L1079-1 assume !(0 == ~E_1~0); 36812#L1084-1 assume !(0 == ~E_2~0); 36813#L1089-1 assume !(0 == ~E_3~0); 36872#L1094-1 assume !(0 == ~E_4~0); 36393#L1099-1 assume !(0 == ~E_5~0); 36394#L1104-1 assume !(0 == ~E_6~0); 36668#L1109-1 assume !(0 == ~E_7~0); 36184#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36185#L1119-1 assume !(0 == ~E_9~0); 36246#L1124-1 assume !(0 == ~E_10~0); 35665#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35666#L502 assume 1 == ~m_pc~0; 36553#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35794#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35795#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36605#L1273 assume !(0 != activate_threads_~tmp~1#1); 36606#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36990#L521 assume !(1 == ~t1_pc~0); 36907#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35725#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35726#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35869#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 35709#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35710#L540 assume 1 == ~t2_pc~0; 36833#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36512#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36836#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36849#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 36900#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35983#L559 assume 1 == ~t3_pc~0; 35984#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36268#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36269#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36421#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 35812#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35813#L578 assume !(1 == ~t4_pc~0); 35935#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35934#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35701#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35702#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36587#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36588#L597 assume 1 == ~t5_pc~0; 37015#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35746#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35747#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36364#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36535#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36536#L616 assume !(1 == ~t6_pc~0); 36552#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36551#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36964#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36451#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36383#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36384#L635 assume 1 == ~t7_pc~0; 36592#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35715#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36090#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36786#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36524#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36525#L654 assume !(1 == ~t8_pc~0); 36339#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36340#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36901#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36772#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 36773#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35959#L673 assume 1 == ~t9_pc~0; 35960#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35656#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36986#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36735#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36679#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36680#L692 assume !(1 == ~t10_pc~0); 36624#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36623#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36537#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36397#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36398#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36749#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 35872#L1142-2 assume !(1 == ~T1_E~0); 35873#L1147-1 assume !(1 == ~T2_E~0); 37049#L1152-1 assume !(1 == ~T3_E~0); 36274#L1157-1 assume !(1 == ~T4_E~0); 36275#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36425#L1167-1 assume !(1 == ~T6_E~0); 36426#L1172-1 assume !(1 == ~T7_E~0); 36908#L1177-1 assume !(1 == ~T8_E~0); 36909#L1182-1 assume !(1 == ~T9_E~0); 36671#L1187-1 assume !(1 == ~T10_E~0); 36672#L1192-1 assume !(1 == ~E_M~0); 37310#L1197-1 assume !(1 == ~E_1~0); 37309#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37308#L1207-1 assume !(1 == ~E_3~0); 37307#L1212-1 assume !(1 == ~E_4~0); 37306#L1217-1 assume !(1 == ~E_5~0); 37305#L1222-1 assume !(1 == ~E_6~0); 37304#L1227-1 assume !(1 == ~E_7~0); 37303#L1232-1 assume !(1 == ~E_8~0); 37301#L1237-1 assume !(1 == ~E_9~0); 37113#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37096#L1247-1 assume { :end_inline_reset_delta_events } true; 37089#L1553-2 [2021-12-15 17:20:45,011 INFO L793 eck$LassoCheckResult]: Loop: 37089#L1553-2 assume !false; 37083#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37078#L999 assume !false; 37077#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37076#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37065#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37064#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37062#L854 assume !(0 != eval_~tmp~0#1); 37061#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37060#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37058#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37059#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38335#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38332#L1034-3 assume !(0 == ~T3_E~0); 38329#L1039-3 assume !(0 == ~T4_E~0); 38326#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38323#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38320#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38317#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38314#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38311#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38308#L1074-3 assume !(0 == ~E_M~0); 38305#L1079-3 assume !(0 == ~E_1~0); 38302#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38299#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38296#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38293#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38290#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38287#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38284#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38281#L1119-3 assume !(0 == ~E_9~0); 38278#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38275#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38272#L502-36 assume !(1 == ~m_pc~0); 38268#L502-38 is_master_triggered_~__retres1~0#1 := 0; 38263#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38260#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38257#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38254#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38251#L521-36 assume 1 == ~t1_pc~0; 38247#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38242#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38239#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38236#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38233#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38230#L540-36 assume !(1 == ~t2_pc~0); 38226#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 38221#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38218#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38215#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38212#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38209#L559-36 assume 1 == ~t3_pc~0; 38205#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38200#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38197#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38194#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38191#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38188#L578-36 assume !(1 == ~t4_pc~0); 38184#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 38179#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38176#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38173#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38170#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38167#L597-36 assume 1 == ~t5_pc~0; 38163#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38158#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38155#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38152#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 38149#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38146#L616-36 assume 1 == ~t6_pc~0; 38142#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38137#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38134#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38131#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38128#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38125#L635-36 assume 1 == ~t7_pc~0; 38121#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38116#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38113#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38110#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38107#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38104#L654-36 assume 1 == ~t8_pc~0; 38100#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38095#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38092#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38089#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38086#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38083#L673-36 assume 1 == ~t9_pc~0; 38080#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38074#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38071#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38068#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38065#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38062#L692-36 assume 1 == ~t10_pc~0; 38058#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38053#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38050#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38047#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38044#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38041#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36531#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38036#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38033#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36965#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38028#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38026#L1167-3 assume !(1 == ~T6_E~0); 38024#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38022#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38020#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38018#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38015#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38012#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38011#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38010#L1207-3 assume !(1 == ~E_3~0); 38009#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38008#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38007#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38006#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38005#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38004#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38003#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38002#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37340#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37338#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37337#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 37326#L1572 assume !(0 == start_simulation_~tmp~3#1); 36140#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37130#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37120#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37118#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 37116#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37115#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37114#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37097#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 37089#L1553-2 [2021-12-15 17:20:45,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,012 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2021-12-15 17:20:45,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086339313] [2021-12-15 17:20:45,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:45,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:45,040 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:45,040 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086339313] [2021-12-15 17:20:45,041 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086339313] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:45,042 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:45,042 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:45,042 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392636037] [2021-12-15 17:20:45,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:45,043 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:45,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,043 INFO L85 PathProgramCache]: Analyzing trace with hash -23258120, now seen corresponding path program 1 times [2021-12-15 17:20:45,044 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899762730] [2021-12-15 17:20:45,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,044 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:45,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:45,107 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:45,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899762730] [2021-12-15 17:20:45,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899762730] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:45,107 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:45,107 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:45,108 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719436737] [2021-12-15 17:20:45,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:45,108 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:45,108 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:45,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:45,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:45,109 INFO L87 Difference]: Start difference. First operand 4618 states and 6801 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:45,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:45,236 INFO L93 Difference]: Finished difference Result 8652 states and 12712 transitions. [2021-12-15 17:20:45,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:45,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8652 states and 12712 transitions. [2021-12-15 17:20:45,270 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2021-12-15 17:20:45,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8652 states to 8652 states and 12712 transitions. [2021-12-15 17:20:45,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8652 [2021-12-15 17:20:45,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8652 [2021-12-15 17:20:45,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8652 states and 12712 transitions. [2021-12-15 17:20:45,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:45,320 INFO L681 BuchiCegarLoop]: Abstraction has 8652 states and 12712 transitions. [2021-12-15 17:20:45,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8652 states and 12712 transitions. [2021-12-15 17:20:45,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8652 to 8648. [2021-12-15 17:20:45,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:45,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8648 states to 8648 states and 12708 transitions. [2021-12-15 17:20:45,457 INFO L704 BuchiCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2021-12-15 17:20:45,457 INFO L587 BuchiCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2021-12-15 17:20:45,457 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:45,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8648 states and 12708 transitions. [2021-12-15 17:20:45,482 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2021-12-15 17:20:45,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:45,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:45,484 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,484 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:45,484 INFO L791 eck$LassoCheckResult]: Stem: 49883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 48912#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48913#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49811#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 49505#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49506#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49792#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49953#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49676#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49677#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49564#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49565#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49911#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49873#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49797#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49798#L1024 assume !(0 == ~M_E~0); 50056#L1024-2 assume !(0 == ~T1_E~0); 49239#L1029-1 assume !(0 == ~T2_E~0); 49240#L1034-1 assume !(0 == ~T3_E~0); 49346#L1039-1 assume !(0 == ~T4_E~0); 50181#L1044-1 assume !(0 == ~T5_E~0); 49588#L1049-1 assume !(0 == ~T6_E~0); 49589#L1054-1 assume !(0 == ~T7_E~0); 49819#L1059-1 assume !(0 == ~T8_E~0); 49286#L1064-1 assume !(0 == ~T9_E~0); 49287#L1069-1 assume !(0 == ~T10_E~0); 50022#L1074-1 assume !(0 == ~E_M~0); 50090#L1079-1 assume !(0 == ~E_1~0); 50058#L1084-1 assume !(0 == ~E_2~0); 50059#L1089-1 assume !(0 == ~E_3~0); 50110#L1094-1 assume !(0 == ~E_4~0); 49666#L1099-1 assume !(0 == ~E_5~0); 49667#L1104-1 assume !(0 == ~E_6~0); 49930#L1109-1 assume !(0 == ~E_7~0); 49460#L1114-1 assume !(0 == ~E_8~0); 49461#L1119-1 assume !(0 == ~E_9~0); 49516#L1124-1 assume !(0 == ~E_10~0); 48945#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48946#L502 assume 1 == ~m_pc~0; 49817#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49074#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49075#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49868#L1273 assume !(0 != activate_threads_~tmp~1#1); 49869#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50221#L521 assume !(1 == ~t1_pc~0); 50145#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49005#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49006#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49148#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 48987#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48988#L540 assume 1 == ~t2_pc~0; 50072#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49781#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50075#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50088#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 50138#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49261#L559 assume 1 == ~t3_pc~0; 49262#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49541#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49542#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49691#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 49092#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49093#L578 assume !(1 == ~t4_pc~0); 49211#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49210#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48981#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48982#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49850#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49851#L597 assume 1 == ~t5_pc~0; 50238#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49026#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49027#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49634#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 49799#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49800#L616 assume !(1 == ~t6_pc~0); 49815#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49814#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50199#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49723#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 49658#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49659#L635 assume 1 == ~t7_pc~0; 49855#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48995#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49366#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50032#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 49793#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49794#L654 assume !(1 == ~t8_pc~0); 49614#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49615#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50139#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50019#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 50020#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49237#L673 assume 1 == ~t9_pc~0; 49238#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48936#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50216#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49986#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 49940#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49941#L692 assume !(1 == ~t10_pc~0); 49887#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49886#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49803#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49670#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 49671#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50000#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 50272#L1142-2 assume !(1 == ~T1_E~0); 49987#L1147-1 assume !(1 == ~T2_E~0); 49988#L1152-1 assume !(1 == ~T3_E~0); 50408#L1157-1 assume !(1 == ~T4_E~0); 50406#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50404#L1167-1 assume !(1 == ~T6_E~0); 50401#L1172-1 assume !(1 == ~T7_E~0); 50399#L1177-1 assume !(1 == ~T8_E~0); 50397#L1182-1 assume !(1 == ~T9_E~0); 50395#L1187-1 assume !(1 == ~T10_E~0); 50393#L1192-1 assume !(1 == ~E_M~0); 50391#L1197-1 assume !(1 == ~E_1~0); 50388#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50386#L1207-1 assume !(1 == ~E_3~0); 50384#L1212-1 assume !(1 == ~E_4~0); 50378#L1217-1 assume !(1 == ~E_5~0); 50376#L1222-1 assume !(1 == ~E_6~0); 50374#L1227-1 assume !(1 == ~E_7~0); 50369#L1232-1 assume !(1 == ~E_8~0); 50363#L1237-1 assume !(1 == ~E_9~0); 50358#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50314#L1247-1 assume { :end_inline_reset_delta_events } true; 50307#L1553-2 [2021-12-15 17:20:45,485 INFO L793 eck$LassoCheckResult]: Loop: 50307#L1553-2 assume !false; 50301#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50296#L999 assume !false; 50295#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50294#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50283#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50282#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50280#L854 assume !(0 != eval_~tmp~0#1); 50279#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50278#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50276#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50277#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51118#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51116#L1034-3 assume !(0 == ~T3_E~0); 51114#L1039-3 assume !(0 == ~T4_E~0); 51111#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51109#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51000#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50997#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50995#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50993#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50991#L1074-3 assume !(0 == ~E_M~0); 50989#L1079-3 assume !(0 == ~E_1~0); 50987#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50984#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50982#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50980#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50978#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50976#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50974#L1114-3 assume !(0 == ~E_8~0); 50971#L1119-3 assume !(0 == ~E_9~0); 50969#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50967#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50965#L502-36 assume !(1 == ~m_pc~0); 50962#L502-38 is_master_triggered_~__retres1~0#1 := 0; 50960#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50957#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50955#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50953#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50951#L521-36 assume 1 == ~t1_pc~0; 50948#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50946#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50945#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50944#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50942#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50940#L540-36 assume !(1 == ~t2_pc~0); 50937#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 50935#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50934#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50932#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50930#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50928#L559-36 assume 1 == ~t3_pc~0; 50925#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50923#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50922#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50921#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50920#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50919#L578-36 assume !(1 == ~t4_pc~0); 50917#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 50905#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50903#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50901#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50899#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50897#L597-36 assume 1 == ~t5_pc~0; 50878#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50876#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50866#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50858#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 50851#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50848#L616-36 assume 1 == ~t6_pc~0; 50843#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50830#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50827#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50824#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50820#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50817#L635-36 assume 1 == ~t7_pc~0; 50812#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50809#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50806#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50803#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50800#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50797#L654-36 assume 1 == ~t8_pc~0; 50792#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50789#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50786#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50783#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50780#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50777#L673-36 assume !(1 == ~t9_pc~0); 50772#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50769#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50766#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50763#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50760#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50758#L692-36 assume 1 == ~t10_pc~0; 50755#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50752#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50748#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50581#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50578#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50548#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49801#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50545#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50543#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50200#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50538#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50536#L1167-3 assume !(1 == ~T6_E~0); 50534#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50527#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50519#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50514#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50508#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50503#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50499#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50495#L1207-3 assume !(1 == ~E_3~0); 50491#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50487#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50481#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50478#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50470#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50468#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50467#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50466#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50453#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50450#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50447#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 50444#L1572 assume !(0 == start_simulation_~tmp~3#1); 49418#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50440#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50382#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50375#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 50370#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50364#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50359#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50315#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 50307#L1553-2 [2021-12-15 17:20:45,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,485 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2021-12-15 17:20:45,485 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,486 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113366534] [2021-12-15 17:20:45,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,486 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:45,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:45,511 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:45,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113366534] [2021-12-15 17:20:45,511 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113366534] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:45,511 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:45,511 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:45,512 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842916239] [2021-12-15 17:20:45,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:45,513 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:45,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:45,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1798258821, now seen corresponding path program 1 times [2021-12-15 17:20:45,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:45,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510303782] [2021-12-15 17:20:45,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:45,513 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:45,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:45,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:45,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:45,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510303782] [2021-12-15 17:20:45,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510303782] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:45,539 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:45,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:45,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761816120] [2021-12-15 17:20:45,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:45,540 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:45,540 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:45,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:45,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:45,541 INFO L87 Difference]: Start difference. First operand 8648 states and 12708 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:45,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:45,648 INFO L93 Difference]: Finished difference Result 16979 states and 24771 transitions. [2021-12-15 17:20:45,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:45,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16979 states and 24771 transitions. [2021-12-15 17:20:45,715 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16753 [2021-12-15 17:20:45,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16979 states to 16979 states and 24771 transitions. [2021-12-15 17:20:45,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16979 [2021-12-15 17:20:45,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16979 [2021-12-15 17:20:45,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16979 states and 24771 transitions. [2021-12-15 17:20:45,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:45,873 INFO L681 BuchiCegarLoop]: Abstraction has 16979 states and 24771 transitions. [2021-12-15 17:20:45,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16979 states and 24771 transitions. [2021-12-15 17:20:46,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16979 to 16371. [2021-12-15 17:20:46,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16371 states, 16371 states have (on average 1.4608148555372305) internal successors, (23915), 16370 states have internal predecessors, (23915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:46,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16371 states to 16371 states and 23915 transitions. [2021-12-15 17:20:46,078 INFO L704 BuchiCegarLoop]: Abstraction has 16371 states and 23915 transitions. [2021-12-15 17:20:46,079 INFO L587 BuchiCegarLoop]: Abstraction has 16371 states and 23915 transitions. [2021-12-15 17:20:46,079 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:46,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16371 states and 23915 transitions. [2021-12-15 17:20:46,124 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16145 [2021-12-15 17:20:46,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:46,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:46,125 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:46,125 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:46,126 INFO L791 eck$LassoCheckResult]: Stem: 75590#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75591#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 74546#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74547#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75509#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 75163#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75164#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75481#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75673#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75354#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75355#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75230#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75231#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75624#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75579#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75491#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75492#L1024 assume !(0 == ~M_E~0); 75803#L1024-2 assume !(0 == ~T1_E~0); 74883#L1029-1 assume !(0 == ~T2_E~0); 74884#L1034-1 assume !(0 == ~T3_E~0); 74995#L1039-1 assume !(0 == ~T4_E~0); 75963#L1044-1 assume !(0 == ~T5_E~0); 75251#L1049-1 assume !(0 == ~T6_E~0); 75252#L1054-1 assume !(0 == ~T7_E~0); 75516#L1059-1 assume !(0 == ~T8_E~0); 74934#L1064-1 assume !(0 == ~T9_E~0); 74935#L1069-1 assume !(0 == ~T10_E~0); 75761#L1074-1 assume !(0 == ~E_M~0); 75847#L1079-1 assume !(0 == ~E_1~0); 75806#L1084-1 assume !(0 == ~E_2~0); 75807#L1089-1 assume !(0 == ~E_3~0); 75875#L1094-1 assume !(0 == ~E_4~0); 75340#L1099-1 assume !(0 == ~E_5~0); 75341#L1104-1 assume !(0 == ~E_6~0); 75647#L1109-1 assume !(0 == ~E_7~0); 75114#L1114-1 assume !(0 == ~E_8~0); 75115#L1119-1 assume !(0 == ~E_9~0); 75179#L1124-1 assume !(0 == ~E_10~0); 74579#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74580#L502 assume !(1 == ~m_pc~0); 74782#L502-2 is_master_triggered_~__retres1~0#1 := 0; 74713#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74714#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75575#L1273 assume !(0 != activate_threads_~tmp~1#1); 75576#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76045#L521 assume !(1 == ~t1_pc~0); 75918#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74641#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74642#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74787#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 74623#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74624#L540 assume 1 == ~t2_pc~0; 75824#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75464#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75830#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75846#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 75909#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74909#L559 assume 1 == ~t3_pc~0; 74910#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75199#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75200#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75370#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 74729#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74730#L578 assume !(1 == ~t4_pc~0); 74855#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74854#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74615#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74616#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75557#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75558#L597 assume 1 == ~t5_pc~0; 76081#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 74661#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74662#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75308#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 75493#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75494#L616 assume !(1 == ~t6_pc~0); 75513#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75512#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76000#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75402#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 75330#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75331#L635 assume 1 == ~t7_pc~0; 75561#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 74629#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75014#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75774#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 75483#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75484#L654 assume !(1 == ~t8_pc~0); 75277#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75278#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75910#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75757#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 75758#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74881#L673 assume 1 == ~t9_pc~0; 74882#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74572#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76039#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75715#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 75656#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75657#L692 assume !(1 == ~t10_pc~0); 75596#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75595#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75495#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75344#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 75345#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75736#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 74790#L1142-2 assume !(1 == ~T1_E~0); 74791#L1147-1 assume !(1 == ~T2_E~0); 76140#L1152-1 assume !(1 == ~T3_E~0); 75206#L1157-1 assume !(1 == ~T4_E~0); 75207#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77612#L1167-1 assume !(1 == ~T6_E~0); 75898#L1172-1 assume !(1 == ~T7_E~0); 75899#L1177-1 assume !(1 == ~T8_E~0); 77607#L1182-1 assume !(1 == ~T9_E~0); 77604#L1187-1 assume !(1 == ~T10_E~0); 77600#L1192-1 assume !(1 == ~E_M~0); 77179#L1197-1 assume !(1 == ~E_1~0); 77177#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 77163#L1207-1 assume !(1 == ~E_3~0); 77134#L1212-1 assume !(1 == ~E_4~0); 77122#L1217-1 assume !(1 == ~E_5~0); 77107#L1222-1 assume !(1 == ~E_6~0); 77105#L1227-1 assume !(1 == ~E_7~0); 77102#L1232-1 assume !(1 == ~E_8~0); 77082#L1237-1 assume !(1 == ~E_9~0); 77068#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77058#L1247-1 assume { :end_inline_reset_delta_events } true; 77051#L1553-2 [2021-12-15 17:20:46,126 INFO L793 eck$LassoCheckResult]: Loop: 77051#L1553-2 assume !false; 77045#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77040#L999 assume !false; 77039#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77038#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77027#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77026#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 77024#L854 assume !(0 != eval_~tmp~0#1); 77023#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77022#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77019#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77020#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 79623#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79616#L1034-3 assume !(0 == ~T3_E~0); 79610#L1039-3 assume !(0 == ~T4_E~0); 79608#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79606#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79594#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79592#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 79590#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 79587#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 79585#L1074-3 assume !(0 == ~E_M~0); 79583#L1079-3 assume !(0 == ~E_1~0); 79581#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79579#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79577#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 79575#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79573#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79571#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 79569#L1114-3 assume !(0 == ~E_8~0); 79567#L1119-3 assume !(0 == ~E_9~0); 79565#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79563#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79561#L502-36 assume !(1 == ~m_pc~0); 79559#L502-38 is_master_triggered_~__retres1~0#1 := 0; 79557#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79555#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 79553#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79551#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79549#L521-36 assume 1 == ~t1_pc~0; 79545#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 79543#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79541#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 79539#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79537#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79535#L540-36 assume 1 == ~t2_pc~0; 79533#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79530#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79528#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79526#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79524#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79522#L559-36 assume !(1 == ~t3_pc~0); 79515#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 79512#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79510#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79507#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 79505#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79503#L578-36 assume 1 == ~t4_pc~0; 79501#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79498#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79496#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79493#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79491#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79489#L597-36 assume !(1 == ~t5_pc~0); 79487#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 79484#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79482#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79479#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 79477#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79475#L616-36 assume !(1 == ~t6_pc~0); 79473#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 79470#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79468#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79467#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 79466#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79465#L635-36 assume !(1 == ~t7_pc~0); 79463#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 79460#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 79458#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79456#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 79453#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79451#L654-36 assume !(1 == ~t8_pc~0); 79449#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 79446#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 79444#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79442#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 79441#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 79438#L673-36 assume !(1 == ~t9_pc~0); 79435#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 79433#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 79431#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77805#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77802#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77787#L692-36 assume 1 == ~t10_pc~0; 77783#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77774#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77767#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74925#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 74926#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77753#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 75489#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77738#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77730#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76003#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77716#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77711#L1167-3 assume !(1 == ~T6_E~0); 77706#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77700#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77695#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77690#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 77685#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77678#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77675#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77670#L1207-3 assume !(1 == ~E_3~0); 77666#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77662#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77658#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77654#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77650#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77644#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77640#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 77637#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77624#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77180#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77162#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 77161#L1572 assume !(0 == start_simulation_~tmp~3#1); 76640#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77132#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77121#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77106#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 77085#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77083#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77069#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 77059#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 77051#L1553-2 [2021-12-15 17:20:46,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:46,127 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2021-12-15 17:20:46,127 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:46,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526240830] [2021-12-15 17:20:46,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:46,127 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:46,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:46,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:46,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:46,149 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526240830] [2021-12-15 17:20:46,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526240830] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:46,149 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:46,150 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:46,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263531326] [2021-12-15 17:20:46,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:46,150 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:46,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:46,150 INFO L85 PathProgramCache]: Analyzing trace with hash 1442768126, now seen corresponding path program 1 times [2021-12-15 17:20:46,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:46,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664015049] [2021-12-15 17:20:46,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:46,151 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:46,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:46,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:46,173 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:46,173 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664015049] [2021-12-15 17:20:46,173 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664015049] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:46,173 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:46,173 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:46,173 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005828576] [2021-12-15 17:20:46,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:46,174 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:46,174 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:46,174 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:46,174 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:46,174 INFO L87 Difference]: Start difference. First operand 16371 states and 23915 transitions. cyclomatic complexity: 7560 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:46,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:46,525 INFO L93 Difference]: Finished difference Result 45437 states and 65745 transitions. [2021-12-15 17:20:46,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:46,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45437 states and 65745 transitions. [2021-12-15 17:20:46,788 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45053 [2021-12-15 17:20:46,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45437 states to 45437 states and 65745 transitions. [2021-12-15 17:20:46,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45437 [2021-12-15 17:20:46,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45437 [2021-12-15 17:20:46,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45437 states and 65745 transitions. [2021-12-15 17:20:47,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:47,003 INFO L681 BuchiCegarLoop]: Abstraction has 45437 states and 65745 transitions. [2021-12-15 17:20:47,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45437 states and 65745 transitions. [2021-12-15 17:20:47,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45437 to 44317. [2021-12-15 17:20:47,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44317 states, 44317 states have (on average 1.4488570977277342) internal successors, (64209), 44316 states have internal predecessors, (64209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:47,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44317 states to 44317 states and 64209 transitions. [2021-12-15 17:20:47,736 INFO L704 BuchiCegarLoop]: Abstraction has 44317 states and 64209 transitions. [2021-12-15 17:20:47,736 INFO L587 BuchiCegarLoop]: Abstraction has 44317 states and 64209 transitions. [2021-12-15 17:20:47,736 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:47,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44317 states and 64209 transitions. [2021-12-15 17:20:47,855 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44029 [2021-12-15 17:20:47,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:47,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:47,857 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,857 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:47,858 INFO L791 eck$LassoCheckResult]: Stem: 137400#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 137401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 136364#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 136365#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 137319#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 136987#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 136988#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137291#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 137478#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 137170#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 137171#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 137046#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 137047#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 137431#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 137388#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 137303#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 137304#L1024 assume !(0 == ~M_E~0); 137598#L1024-2 assume !(0 == ~T1_E~0); 136700#L1029-1 assume !(0 == ~T2_E~0); 136701#L1034-1 assume !(0 == ~T3_E~0); 136816#L1039-1 assume !(0 == ~T4_E~0); 137749#L1044-1 assume !(0 == ~T5_E~0); 137071#L1049-1 assume !(0 == ~T6_E~0); 137072#L1054-1 assume !(0 == ~T7_E~0); 137329#L1059-1 assume !(0 == ~T8_E~0); 136752#L1064-1 assume !(0 == ~T9_E~0); 136753#L1069-1 assume !(0 == ~T10_E~0); 137554#L1074-1 assume !(0 == ~E_M~0); 137642#L1079-1 assume !(0 == ~E_1~0); 137601#L1084-1 assume !(0 == ~E_2~0); 137602#L1089-1 assume !(0 == ~E_3~0); 137670#L1094-1 assume !(0 == ~E_4~0); 137156#L1099-1 assume !(0 == ~E_5~0); 137157#L1104-1 assume !(0 == ~E_6~0); 137450#L1109-1 assume !(0 == ~E_7~0); 136936#L1114-1 assume !(0 == ~E_8~0); 136937#L1119-1 assume !(0 == ~E_9~0); 136997#L1124-1 assume !(0 == ~E_10~0); 136397#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136398#L502 assume !(1 == ~m_pc~0); 136596#L502-2 is_master_triggered_~__retres1~0#1 := 0; 136529#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136530#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 137383#L1273 assume !(0 != activate_threads_~tmp~1#1); 137384#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137821#L521 assume !(1 == ~t1_pc~0); 137769#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 136457#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136458#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136602#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 136441#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136442#L540 assume !(1 == ~t2_pc~0); 137274#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 137275#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137623#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 137638#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 137704#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136727#L559 assume 1 == ~t3_pc~0; 136728#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 137021#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 137022#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137186#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 136547#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136548#L578 assume !(1 == ~t4_pc~0); 136672#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 136671#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136433#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136434#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 137366#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137367#L597 assume 1 == ~t5_pc~0; 137855#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 136479#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136480#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 137122#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 137305#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137306#L616 assume !(1 == ~t6_pc~0); 137325#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 137324#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137778#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 137217#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 137145#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137146#L635 assume 1 == ~t7_pc~0; 137369#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 136447#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136836#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 137565#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 137295#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 137296#L654 assume !(1 == ~t8_pc~0); 137096#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 137097#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137705#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137551#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 137552#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 136698#L673 assume 1 == ~t9_pc~0; 136699#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 136388#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 137814#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 137517#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 137462#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 137463#L692 assume !(1 == ~t10_pc~0); 137404#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 137403#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 137307#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 137161#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 137162#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137529#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 136606#L1142-2 assume !(1 == ~T1_E~0); 136607#L1147-1 assume !(1 == ~T2_E~0); 137518#L1152-1 assume !(1 == ~T3_E~0); 137908#L1157-1 assume !(1 == ~T4_E~0); 150458#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 150454#L1167-1 assume !(1 == ~T6_E~0); 137693#L1172-1 assume !(1 == ~T7_E~0); 137694#L1177-1 assume !(1 == ~T8_E~0); 137350#L1182-1 assume !(1 == ~T9_E~0); 137351#L1187-1 assume !(1 == ~T10_E~0); 137456#L1192-1 assume !(1 == ~E_M~0); 136885#L1197-1 assume !(1 == ~E_1~0); 136886#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 137281#L1207-1 assume !(1 == ~E_3~0); 137258#L1212-1 assume !(1 == ~E_4~0); 136463#L1217-1 assume !(1 == ~E_5~0); 136464#L1222-1 assume !(1 == ~E_6~0); 137921#L1227-1 assume !(1 == ~E_7~0); 147899#L1232-1 assume !(1 == ~E_8~0); 149904#L1237-1 assume !(1 == ~E_9~0); 149434#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 148735#L1247-1 assume { :end_inline_reset_delta_events } true; 148733#L1553-2 [2021-12-15 17:20:47,858 INFO L793 eck$LassoCheckResult]: Loop: 148733#L1553-2 assume !false; 147832#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 147826#L999 assume !false; 147824#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 147822#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 147810#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 147808#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 147804#L854 assume !(0 != eval_~tmp~0#1); 147805#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159584#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159582#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 159580#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159578#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 159576#L1034-3 assume !(0 == ~T3_E~0); 159573#L1039-3 assume !(0 == ~T4_E~0); 157650#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 139606#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 139600#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 139593#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 139585#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 139578#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 139571#L1074-3 assume !(0 == ~E_M~0); 139565#L1079-3 assume !(0 == ~E_1~0); 139560#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 139393#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 139390#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 139388#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 139385#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 139386#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 153679#L1114-3 assume !(0 == ~E_8~0); 153677#L1119-3 assume !(0 == ~E_9~0); 153675#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 153673#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153671#L502-36 assume !(1 == ~m_pc~0); 153669#L502-38 is_master_triggered_~__retres1~0#1 := 0; 153666#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153664#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 153662#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 153661#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153659#L521-36 assume !(1 == ~t1_pc~0); 152647#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 152645#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152643#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152640#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152638#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152636#L540-36 assume !(1 == ~t2_pc~0); 152634#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 152632#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152630#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152627#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 152625#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152623#L559-36 assume 1 == ~t3_pc~0; 152619#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 152617#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152614#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 152612#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 152610#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152608#L578-36 assume 1 == ~t4_pc~0; 152606#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 152603#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152600#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 152599#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 151373#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151371#L597-36 assume 1 == ~t5_pc~0; 151368#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 151366#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151365#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 151364#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 151360#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151358#L616-36 assume 1 == ~t6_pc~0; 151355#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 151352#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 151350#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 151348#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 151346#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 151344#L635-36 assume !(1 == ~t7_pc~0); 151342#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 151338#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 151336#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 151334#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 151332#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 151330#L654-36 assume 1 == ~t8_pc~0; 151324#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 151322#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 151320#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 151318#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 151316#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 151314#L673-36 assume !(1 == ~t9_pc~0); 151310#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 150298#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 150296#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 150294#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 150292#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 150290#L692-36 assume !(1 == ~t10_pc~0); 150288#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 150284#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 150282#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 150280#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 150278#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150276#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 138102#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 150273#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 149687#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 149683#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 149681#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149679#L1167-3 assume !(1 == ~T6_E~0); 149677#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 149675#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 149673#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 149671#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 148830#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 148826#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 148824#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 148822#L1207-3 assume !(1 == ~E_3~0); 148820#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 148818#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 148816#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 148814#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 148811#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 148807#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 148805#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 148803#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 148777#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 148775#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 148772#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 148770#L1572 assume !(0 == start_simulation_~tmp~3#1); 148767#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 148758#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 148747#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 148745#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 148743#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 148740#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148738#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 148736#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 148733#L1553-2 [2021-12-15 17:20:47,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,858 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2021-12-15 17:20:47,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426290493] [2021-12-15 17:20:47,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,859 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:47,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:47,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:47,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426290493] [2021-12-15 17:20:47,899 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426290493] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:47,899 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:47,899 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:47,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489553959] [2021-12-15 17:20:47,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:47,899 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:47,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:47,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1599527043, now seen corresponding path program 1 times [2021-12-15 17:20:47,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:47,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596462599] [2021-12-15 17:20:47,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:47,900 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:47,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:47,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:47,930 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:47,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596462599] [2021-12-15 17:20:47,931 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [596462599] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:47,931 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:47,932 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:47,932 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786151779] [2021-12-15 17:20:47,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:47,932 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:47,932 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:47,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:47,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:47,933 INFO L87 Difference]: Start difference. First operand 44317 states and 64209 transitions. cyclomatic complexity: 19924 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:48,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:48,771 INFO L93 Difference]: Finished difference Result 124054 states and 178404 transitions. [2021-12-15 17:20:48,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:48,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124054 states and 178404 transitions. [2021-12-15 17:20:49,849 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123287 [2021-12-15 17:20:50,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124054 states to 124054 states and 178404 transitions. [2021-12-15 17:20:50,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124054 [2021-12-15 17:20:50,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124054 [2021-12-15 17:20:50,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124054 states and 178404 transitions. [2021-12-15 17:20:50,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:50,437 INFO L681 BuchiCegarLoop]: Abstraction has 124054 states and 178404 transitions. [2021-12-15 17:20:50,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124054 states and 178404 transitions. [2021-12-15 17:20:51,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124054 to 120998. [2021-12-15 17:20:51,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120998 states, 120998 states have (on average 1.4397923932626986) internal successors, (174212), 120997 states have internal predecessors, (174212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:52,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120998 states to 120998 states and 174212 transitions. [2021-12-15 17:20:52,283 INFO L704 BuchiCegarLoop]: Abstraction has 120998 states and 174212 transitions. [2021-12-15 17:20:52,284 INFO L587 BuchiCegarLoop]: Abstraction has 120998 states and 174212 transitions. [2021-12-15 17:20:52,284 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:52,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120998 states and 174212 transitions. [2021-12-15 17:20:52,592 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 120551 [2021-12-15 17:20:52,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:52,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:52,594 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:52,594 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:52,595 INFO L791 eck$LassoCheckResult]: Stem: 305779#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 305780#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 304744#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 304745#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 305696#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 305364#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 305365#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 305672#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 305863#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 305545#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 305546#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 305429#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 305430#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 305811#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 305769#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 305681#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 305682#L1024 assume !(0 == ~M_E~0); 305990#L1024-2 assume !(0 == ~T1_E~0); 305078#L1029-1 assume !(0 == ~T2_E~0); 305079#L1034-1 assume !(0 == ~T3_E~0); 305190#L1039-1 assume !(0 == ~T4_E~0); 306144#L1044-1 assume !(0 == ~T5_E~0); 305449#L1049-1 assume !(0 == ~T6_E~0); 305450#L1054-1 assume !(0 == ~T7_E~0); 305706#L1059-1 assume !(0 == ~T8_E~0); 305129#L1064-1 assume !(0 == ~T9_E~0); 305130#L1069-1 assume !(0 == ~T10_E~0); 305945#L1074-1 assume !(0 == ~E_M~0); 306034#L1079-1 assume !(0 == ~E_1~0); 305992#L1084-1 assume !(0 == ~E_2~0); 305993#L1089-1 assume !(0 == ~E_3~0); 306063#L1094-1 assume !(0 == ~E_4~0); 305532#L1099-1 assume !(0 == ~E_5~0); 305533#L1104-1 assume !(0 == ~E_6~0); 305833#L1109-1 assume !(0 == ~E_7~0); 305309#L1114-1 assume !(0 == ~E_8~0); 305310#L1119-1 assume !(0 == ~E_9~0); 305378#L1124-1 assume !(0 == ~E_10~0); 304777#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 304778#L502 assume !(1 == ~m_pc~0); 304977#L502-2 is_master_triggered_~__retres1~0#1 := 0; 304907#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 304908#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 305765#L1273 assume !(0 != activate_threads_~tmp~1#1); 305766#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 306212#L521 assume !(1 == ~t1_pc~0); 306164#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 304838#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 304839#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 304982#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 304820#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 304821#L540 assume !(1 == ~t2_pc~0); 305654#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 305655#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 306014#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 306030#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 306096#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 305105#L559 assume !(1 == ~t3_pc~0); 305106#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 305401#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 305402#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 305562#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 304925#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 304926#L578 assume !(1 == ~t4_pc~0); 305050#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 305049#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 304812#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 304813#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 305745#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 305746#L597 assume 1 == ~t5_pc~0; 306245#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 304857#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304858#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 305504#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 305683#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 305684#L616 assume !(1 == ~t6_pc~0); 305703#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 305702#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 306179#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 305594#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 305524#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 305525#L635 assume 1 == ~t7_pc~0; 305749#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 304826#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 305210#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 305958#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 305674#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 305675#L654 assume !(1 == ~t8_pc~0); 305474#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 305475#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306100#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 305941#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 305942#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 305076#L673 assume 1 == ~t9_pc~0; 305077#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 304770#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 306207#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 305902#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 305843#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 305844#L692 assume !(1 == ~t10_pc~0); 305785#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 305784#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 305685#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 305536#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 305537#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 305917#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 304985#L1142-2 assume !(1 == ~T1_E~0); 304986#L1147-1 assume !(1 == ~T2_E~0); 306312#L1152-1 assume !(1 == ~T3_E~0); 306313#L1157-1 assume !(1 == ~T4_E~0); 306001#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 306002#L1167-1 assume !(1 == ~T6_E~0); 306087#L1172-1 assume !(1 == ~T7_E~0); 306088#L1177-1 assume !(1 == ~T8_E~0); 305728#L1182-1 assume !(1 == ~T9_E~0); 305729#L1187-1 assume !(1 == ~T10_E~0); 305891#L1192-1 assume !(1 == ~E_M~0); 305892#L1197-1 assume !(1 == ~E_1~0); 315293#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 315292#L1207-1 assume !(1 == ~E_3~0); 315291#L1212-1 assume !(1 == ~E_4~0); 315290#L1217-1 assume !(1 == ~E_5~0); 315289#L1222-1 assume !(1 == ~E_6~0); 315288#L1227-1 assume !(1 == ~E_7~0); 315287#L1232-1 assume !(1 == ~E_8~0); 313236#L1237-1 assume !(1 == ~E_9~0); 315286#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 315283#L1247-1 assume { :end_inline_reset_delta_events } true; 315271#L1553-2 [2021-12-15 17:20:52,595 INFO L793 eck$LassoCheckResult]: Loop: 315271#L1553-2 assume !false; 315272#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 320571#L999 assume !false; 320570#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 320569#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 320558#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 320557#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 320555#L854 assume !(0 != eval_~tmp~0#1); 320556#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 327303#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 327302#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 327301#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 327300#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 327299#L1034-3 assume !(0 == ~T3_E~0); 327298#L1039-3 assume !(0 == ~T4_E~0); 327297#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 327296#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 327295#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 327294#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 327293#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 327292#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 327291#L1074-3 assume !(0 == ~E_M~0); 327290#L1079-3 assume !(0 == ~E_1~0); 327289#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 327288#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 327287#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 327286#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 327285#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 327284#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 327283#L1114-3 assume !(0 == ~E_8~0); 327282#L1119-3 assume !(0 == ~E_9~0); 327281#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 327280#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 327279#L502-36 assume !(1 == ~m_pc~0); 327278#L502-38 is_master_triggered_~__retres1~0#1 := 0; 327277#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 327276#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 327275#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 327274#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327273#L521-36 assume !(1 == ~t1_pc~0); 327272#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 327271#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 327270#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 327269#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 327268#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 327267#L540-36 assume !(1 == ~t2_pc~0); 327266#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 327265#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 327264#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 327263#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 327262#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 327261#L559-36 assume !(1 == ~t3_pc~0); 327260#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 327259#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 327258#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 327257#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 327256#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 327255#L578-36 assume !(1 == ~t4_pc~0); 327253#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 327252#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 327251#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 327250#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 327249#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 327248#L597-36 assume 1 == ~t5_pc~0; 327246#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 327245#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 327244#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 327243#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 327242#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 327241#L616-36 assume 1 == ~t6_pc~0; 327239#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 327238#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 327237#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 327236#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 327235#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 327234#L635-36 assume 1 == ~t7_pc~0; 327232#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 327231#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 327230#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 327229#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 327228#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 327227#L654-36 assume 1 == ~t8_pc~0; 327225#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 327224#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 327223#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 327222#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 327221#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 327220#L673-36 assume !(1 == ~t9_pc~0); 327218#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 327217#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 327216#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 327215#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 327214#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 327213#L692-36 assume !(1 == ~t10_pc~0); 327212#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 327210#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 327209#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 327208#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 327207#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 324465#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 323923#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 324464#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 323917#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 323916#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 323915#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 323914#L1167-3 assume !(1 == ~T6_E~0); 323913#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 323912#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 323911#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 323910#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 323901#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 323900#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 323899#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 323898#L1207-3 assume !(1 == ~E_3~0); 323897#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 323896#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 323895#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 323894#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 323893#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 323891#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 323890#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 315776#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 315777#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 322063#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 322060#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 322058#L1572 assume !(0 == start_simulation_~tmp~3#1); 322057#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 321924#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 321914#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 321913#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 321912#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 321911#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 321909#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 321905#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 315271#L1553-2 [2021-12-15 17:20:52,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:52,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2021-12-15 17:20:52,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:52,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571729843] [2021-12-15 17:20:52,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:52,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:52,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:52,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:52,624 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:52,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571729843] [2021-12-15 17:20:52,624 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1571729843] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:52,624 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:52,624 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:52,625 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665829427] [2021-12-15 17:20:52,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:52,625 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:52,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:52,625 INFO L85 PathProgramCache]: Analyzing trace with hash 484309566, now seen corresponding path program 1 times [2021-12-15 17:20:52,625 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:52,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241344376] [2021-12-15 17:20:52,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:52,626 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:52,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:52,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:52,647 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:52,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241344376] [2021-12-15 17:20:52,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241344376] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:52,648 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:52,648 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:52,648 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65435566] [2021-12-15 17:20:52,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:52,648 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:52,648 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:52,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:20:52,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:20:52,649 INFO L87 Difference]: Start difference. First operand 120998 states and 174212 transitions. cyclomatic complexity: 53278 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:53,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:53,798 INFO L93 Difference]: Finished difference Result 319068 states and 461666 transitions. [2021-12-15 17:20:53,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:20:53,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319068 states and 461666 transitions. [2021-12-15 17:20:55,314 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 317862 [2021-12-15 17:20:56,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319068 states to 319068 states and 461666 transitions. [2021-12-15 17:20:56,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 319068 [2021-12-15 17:20:56,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 319068 [2021-12-15 17:20:56,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 319068 states and 461666 transitions. [2021-12-15 17:20:56,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:56,548 INFO L681 BuchiCegarLoop]: Abstraction has 319068 states and 461666 transitions. [2021-12-15 17:20:56,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319068 states and 461666 transitions. [2021-12-15 17:20:58,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319068 to 124775. [2021-12-15 17:20:58,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124775 states, 124775 states have (on average 1.4264796633941095) internal successors, (177989), 124774 states have internal predecessors, (177989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124775 states to 124775 states and 177989 transitions. [2021-12-15 17:20:58,856 INFO L704 BuchiCegarLoop]: Abstraction has 124775 states and 177989 transitions. [2021-12-15 17:20:58,856 INFO L587 BuchiCegarLoop]: Abstraction has 124775 states and 177989 transitions. [2021-12-15 17:20:58,856 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:20:58,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124775 states and 177989 transitions. [2021-12-15 17:20:59,223 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124325 [2021-12-15 17:20:59,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:59,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:59,225 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,225 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,225 INFO L791 eck$LassoCheckResult]: Stem: 745836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 745837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 744822#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 744823#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 745760#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 745436#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 745437#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 745737#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 745916#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 745610#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 745611#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 745498#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 745499#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 745865#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 745826#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 745743#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 745744#L1024 assume !(0 == ~M_E~0); 746042#L1024-2 assume !(0 == ~T1_E~0); 745152#L1029-1 assume !(0 == ~T2_E~0); 745153#L1034-1 assume !(0 == ~T3_E~0); 745264#L1039-1 assume !(0 == ~T4_E~0); 746177#L1044-1 assume !(0 == ~T5_E~0); 745520#L1049-1 assume !(0 == ~T6_E~0); 745521#L1054-1 assume !(0 == ~T7_E~0); 745767#L1059-1 assume !(0 == ~T8_E~0); 745203#L1064-1 assume !(0 == ~T9_E~0); 745204#L1069-1 assume !(0 == ~T10_E~0); 746002#L1074-1 assume !(0 == ~E_M~0); 746080#L1079-1 assume !(0 == ~E_1~0); 746044#L1084-1 assume !(0 == ~E_2~0); 746045#L1089-1 assume !(0 == ~E_3~0); 746100#L1094-1 assume !(0 == ~E_4~0); 745598#L1099-1 assume !(0 == ~E_5~0); 745599#L1104-1 assume !(0 == ~E_6~0); 745887#L1109-1 assume !(0 == ~E_7~0); 745387#L1114-1 assume !(0 == ~E_8~0); 745388#L1119-1 assume !(0 == ~E_9~0); 745450#L1124-1 assume !(0 == ~E_10~0); 744855#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 744856#L502 assume !(1 == ~m_pc~0); 745053#L502-2 is_master_triggered_~__retres1~0#1 := 0; 744986#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 744987#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745822#L1273 assume !(0 != activate_threads_~tmp~1#1); 745823#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 746240#L521 assume !(1 == ~t1_pc~0); 746198#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 744916#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 744917#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 745060#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 744898#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 744899#L540 assume !(1 == ~t2_pc~0); 745720#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 745721#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 746061#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 746079#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 746132#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 745178#L559 assume !(1 == ~t3_pc~0); 745179#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 745471#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 745472#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 745625#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 745002#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 745003#L578 assume !(1 == ~t4_pc~0); 745126#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 746006#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 746041#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 746214#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 745804#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 745805#L597 assume 1 == ~t5_pc~0; 746267#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 744936#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 744937#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 745571#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 745745#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 745746#L616 assume !(1 == ~t6_pc~0); 745764#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 745763#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 746204#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 745657#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 745590#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 745591#L635 assume 1 == ~t7_pc~0; 745808#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 744904#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 745285#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 746015#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 745739#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 745740#L654 assume !(1 == ~t8_pc~0); 745544#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 745545#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 746133#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 745999#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 746000#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 745150#L673 assume 1 == ~t9_pc~0; 745151#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 744848#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 746235#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 745960#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 745896#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 745897#L692 assume !(1 == ~t10_pc~0); 745841#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 745840#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 745747#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 745602#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 745603#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 745976#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 745063#L1142-2 assume !(1 == ~T1_E~0); 745064#L1147-1 assume !(1 == ~T2_E~0); 746309#L1152-1 assume !(1 == ~T3_E~0); 745477#L1157-1 assume !(1 == ~T4_E~0); 745478#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 745628#L1167-1 assume !(1 == ~T6_E~0); 745629#L1172-1 assume !(1 == ~T7_E~0); 746124#L1177-1 assume !(1 == ~T8_E~0); 745786#L1182-1 assume !(1 == ~T9_E~0); 745787#L1187-1 assume !(1 == ~T10_E~0); 745890#L1192-1 assume !(1 == ~E_M~0); 745947#L1197-1 assume !(1 == ~E_1~0); 745966#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 745725#L1207-1 assume !(1 == ~E_3~0); 745702#L1212-1 assume !(1 == ~E_4~0); 744920#L1217-1 assume !(1 == ~E_5~0); 744921#L1222-1 assume !(1 == ~E_6~0); 745698#L1227-1 assume !(1 == ~E_7~0); 745699#L1232-1 assume !(1 == ~E_8~0); 744788#L1237-1 assume !(1 == ~E_9~0); 744789#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 745765#L1247-1 assume { :end_inline_reset_delta_events } true; 745766#L1553-2 [2021-12-15 17:20:59,225 INFO L793 eck$LassoCheckResult]: Loop: 745766#L1553-2 assume !false; 851579#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 851574#L999 assume !false; 851493#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 844791#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 844780#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 844779#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 844777#L854 assume !(0 != eval_~tmp~0#1); 844778#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 869311#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 869310#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 869309#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 869308#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 869307#L1034-3 assume !(0 == ~T3_E~0); 869306#L1039-3 assume !(0 == ~T4_E~0); 869305#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 869304#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 869303#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 869302#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 869301#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 869300#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 869299#L1074-3 assume !(0 == ~E_M~0); 869298#L1079-3 assume !(0 == ~E_1~0); 869297#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 868867#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 868865#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 868863#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 868860#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 868858#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 868856#L1114-3 assume !(0 == ~E_8~0); 868854#L1119-3 assume !(0 == ~E_9~0); 868852#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 867891#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 867889#L502-36 assume !(1 == ~m_pc~0); 867887#L502-38 is_master_triggered_~__retres1~0#1 := 0; 867885#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 867882#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 867880#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 867878#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 867876#L521-36 assume !(1 == ~t1_pc~0); 867874#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 867872#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 867871#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 867869#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 867867#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 867865#L540-36 assume !(1 == ~t2_pc~0); 867812#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 867672#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 867669#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 867667#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 867665#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 867663#L559-36 assume !(1 == ~t3_pc~0); 867661#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 867659#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 867656#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 867654#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 867653#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 867652#L578-36 assume !(1 == ~t4_pc~0); 867651#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 867649#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 867647#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 867645#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 867643#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 867642#L597-36 assume !(1 == ~t5_pc~0); 867641#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 867637#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 867547#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 867545#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 867526#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 867524#L616-36 assume !(1 == ~t6_pc~0); 867521#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 867516#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 867513#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 867509#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 867505#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 867501#L635-36 assume !(1 == ~t7_pc~0); 867497#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 867491#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 867487#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 867483#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 867480#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 867476#L654-36 assume 1 == ~t8_pc~0; 867471#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 867466#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 867462#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 867458#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 867454#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 867450#L673-36 assume 1 == ~t9_pc~0; 867447#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 867441#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 867436#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 867369#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 867364#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 867359#L692-36 assume !(1 == ~t10_pc~0); 867119#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 852266#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 852254#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 852252#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 852250#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 852247#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 813248#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 852212#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 852210#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 840246#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 852206#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 852204#L1167-3 assume !(1 == ~T6_E~0); 852202#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 852200#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 852198#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 852195#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 852193#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 842150#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 852190#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 852188#L1207-3 assume !(1 == ~E_3~0); 852186#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 852183#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 852181#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 852179#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 852177#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 827883#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 852174#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 852171#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 852097#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 852095#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 852093#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 852092#L1572 assume !(0 == start_simulation_~tmp~3#1); 852090#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 852087#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 852076#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 852074#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 852072#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 852070#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 851632#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 851631#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 745766#L1553-2 [2021-12-15 17:20:59,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,226 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2021-12-15 17:20:59,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802058143] [2021-12-15 17:20:59,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:59,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:59,251 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:59,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802058143] [2021-12-15 17:20:59,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802058143] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:59,251 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:59,251 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:59,251 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513121545] [2021-12-15 17:20:59,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:59,252 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:59,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,252 INFO L85 PathProgramCache]: Analyzing trace with hash -2142300030, now seen corresponding path program 1 times [2021-12-15 17:20:59,252 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192589251] [2021-12-15 17:20:59,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,252 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:59,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:59,273 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:59,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192589251] [2021-12-15 17:20:59,274 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192589251] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:59,274 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:59,274 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:59,274 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952132892] [2021-12-15 17:20:59,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:59,274 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:59,275 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:59,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:59,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:59,275 INFO L87 Difference]: Start difference. First operand 124775 states and 177989 transitions. cyclomatic complexity: 53278 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:00,818 INFO L93 Difference]: Finished difference Result 348724 states and 494700 transitions. [2021-12-15 17:21:00,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:00,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 348724 states and 494700 transitions. [2021-12-15 17:21:02,700 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 346963 [2021-12-15 17:21:04,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 348724 states to 348724 states and 494700 transitions. [2021-12-15 17:21:04,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 348724 [2021-12-15 17:21:04,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 348724 [2021-12-15 17:21:04,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 348724 states and 494700 transitions. [2021-12-15 17:21:04,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:04,230 INFO L681 BuchiCegarLoop]: Abstraction has 348724 states and 494700 transitions. [2021-12-15 17:21:04,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 348724 states and 494700 transitions. [2021-12-15 17:21:07,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 348724 to 341636. [2021-12-15 17:21:07,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 341636 states, 341636 states have (on average 1.4198386586893652) internal successors, (485068), 341635 states have internal predecessors, (485068), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:09,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 341636 states to 341636 states and 485068 transitions. [2021-12-15 17:21:09,111 INFO L704 BuchiCegarLoop]: Abstraction has 341636 states and 485068 transitions. [2021-12-15 17:21:09,111 INFO L587 BuchiCegarLoop]: Abstraction has 341636 states and 485068 transitions. [2021-12-15 17:21:09,111 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:21:09,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 341636 states and 485068 transitions. [2021-12-15 17:21:10,512 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 340771 [2021-12-15 17:21:10,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:10,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:10,533 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:10,533 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:10,534 INFO L791 eck$LassoCheckResult]: Stem: 1219362#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1219363#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1218331#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1218332#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1219285#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1218951#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1218952#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1219262#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1219451#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1219131#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1219132#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1219014#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1219015#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1219400#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1219350#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1219269#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1219270#L1024 assume !(0 == ~M_E~0); 1219586#L1024-2 assume !(0 == ~T1_E~0); 1218666#L1029-1 assume !(0 == ~T2_E~0); 1218667#L1034-1 assume !(0 == ~T3_E~0); 1218780#L1039-1 assume !(0 == ~T4_E~0); 1219733#L1044-1 assume !(0 == ~T5_E~0); 1219034#L1049-1 assume !(0 == ~T6_E~0); 1219035#L1054-1 assume !(0 == ~T7_E~0); 1219292#L1059-1 assume !(0 == ~T8_E~0); 1218717#L1064-1 assume !(0 == ~T9_E~0); 1218718#L1069-1 assume !(0 == ~T10_E~0); 1219545#L1074-1 assume !(0 == ~E_M~0); 1219628#L1079-1 assume !(0 == ~E_1~0); 1219588#L1084-1 assume !(0 == ~E_2~0); 1219589#L1089-1 assume !(0 == ~E_3~0); 1219653#L1094-1 assume !(0 == ~E_4~0); 1219118#L1099-1 assume !(0 == ~E_5~0); 1219119#L1104-1 assume !(0 == ~E_6~0); 1219422#L1109-1 assume !(0 == ~E_7~0); 1218899#L1114-1 assume !(0 == ~E_8~0); 1218900#L1119-1 assume !(0 == ~E_9~0); 1218964#L1124-1 assume !(0 == ~E_10~0); 1218364#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1218365#L502 assume !(1 == ~m_pc~0); 1218563#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1218495#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1218496#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1219346#L1273 assume !(0 != activate_threads_~tmp~1#1); 1219347#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1219801#L521 assume !(1 == ~t1_pc~0); 1219755#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1218425#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1218426#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1218570#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1218407#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1218408#L540 assume !(1 == ~t2_pc~0); 1219241#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1219242#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1219611#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1219627#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1219680#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1218692#L559 assume !(1 == ~t3_pc~0); 1218693#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1218985#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1218986#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1219147#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1218511#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1218512#L578 assume !(1 == ~t4_pc~0); 1218639#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1219549#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1219925#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1219776#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1219327#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1219328#L597 assume !(1 == ~t5_pc~0); 1219278#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1218445#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1218446#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1219088#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1219271#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1219272#L616 assume !(1 == ~t6_pc~0); 1219289#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1219288#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1219767#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1219179#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1219110#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1219111#L635 assume 1 == ~t7_pc~0; 1219333#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1218413#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1218800#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1219557#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1219264#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1219265#L654 assume !(1 == ~t8_pc~0); 1219059#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1219060#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1219681#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1219541#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1219542#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1218664#L673 assume 1 == ~t9_pc~0; 1218665#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1218357#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1219793#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1219494#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1219434#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1219435#L692 assume !(1 == ~t10_pc~0); 1219372#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1219371#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1219273#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1219123#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1219124#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1219519#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1218573#L1142-2 assume !(1 == ~T1_E~0); 1218574#L1147-1 assume !(1 == ~T2_E~0); 1219893#L1152-1 assume !(1 == ~T3_E~0); 1218992#L1157-1 assume !(1 == ~T4_E~0); 1218993#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1219150#L1167-1 assume !(1 == ~T6_E~0); 1219151#L1172-1 assume !(1 == ~T7_E~0); 1219692#L1177-1 assume !(1 == ~T8_E~0); 1219693#L1182-1 assume !(1 == ~T9_E~0); 1219425#L1187-1 assume !(1 == ~T10_E~0); 1219426#L1192-1 assume !(1 == ~E_M~0); 1239944#L1197-1 assume !(1 == ~E_1~0); 1239942#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1239940#L1207-1 assume !(1 == ~E_3~0); 1239938#L1212-1 assume !(1 == ~E_4~0); 1239936#L1217-1 assume !(1 == ~E_5~0); 1239934#L1222-1 assume !(1 == ~E_6~0); 1219218#L1227-1 assume !(1 == ~E_7~0); 1219219#L1232-1 assume !(1 == ~E_8~0); 1239922#L1237-1 assume !(1 == ~E_9~0); 1239921#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1239917#L1247-1 assume { :end_inline_reset_delta_events } true; 1239918#L1553-2 [2021-12-15 17:21:10,534 INFO L793 eck$LassoCheckResult]: Loop: 1239918#L1553-2 assume !false; 1304410#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1444023#L999 assume !false; 1444022#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1304248#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1239585#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1239586#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1239559#L854 assume !(0 != eval_~tmp~0#1); 1239561#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1242615#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1242613#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1242611#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1242609#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1242607#L1034-3 assume !(0 == ~T3_E~0); 1242605#L1039-3 assume !(0 == ~T4_E~0); 1242603#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1242601#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1242599#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1242597#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1242595#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1242593#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1242591#L1074-3 assume !(0 == ~E_M~0); 1242589#L1079-3 assume !(0 == ~E_1~0); 1242587#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1242585#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1242583#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1242581#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1242579#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1242577#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1242575#L1114-3 assume !(0 == ~E_8~0); 1242573#L1119-3 assume !(0 == ~E_9~0); 1242571#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1242569#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1242567#L502-36 assume !(1 == ~m_pc~0); 1242565#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1242563#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1242561#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1242559#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1242557#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1242555#L521-36 assume !(1 == ~t1_pc~0); 1242551#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1242549#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1242547#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1242545#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1242542#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1242540#L540-36 assume !(1 == ~t2_pc~0); 1242538#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1242536#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1242534#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1242532#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1242530#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1242528#L559-36 assume !(1 == ~t3_pc~0); 1242526#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1242523#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1242521#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1242519#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1242517#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1242515#L578-36 assume 1 == ~t4_pc~0; 1242513#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1242514#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1242627#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1242503#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1242501#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1242499#L597-36 assume !(1 == ~t5_pc~0); 1242497#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1242494#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1242492#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1242490#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 1242488#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1242486#L616-36 assume 1 == ~t6_pc~0; 1242483#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1242480#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1242478#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1242476#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1242474#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1242472#L635-36 assume !(1 == ~t7_pc~0); 1242470#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1242466#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1242464#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1242462#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1242460#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1242458#L654-36 assume 1 == ~t8_pc~0; 1242455#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1242453#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1242451#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1242449#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1242447#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1242445#L673-36 assume !(1 == ~t9_pc~0); 1242442#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1242440#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1242438#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1242436#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1242434#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1242433#L692-36 assume !(1 == ~t10_pc~0); 1242432#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1242430#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1242429#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1242427#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1242425#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1242423#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1240221#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1242418#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1242416#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1240212#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1242413#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1242411#L1167-3 assume !(1 == ~T6_E~0); 1242409#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1242407#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1242405#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1242403#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1242401#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1242397#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1242395#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1242393#L1207-3 assume !(1 == ~E_3~0); 1242391#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1242388#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1242389#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1305127#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1242381#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1242376#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1242374#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1242369#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1242202#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1242194#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1242186#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1242179#L1572 assume !(0 == start_simulation_~tmp~3#1); 1242173#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1242044#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1241919#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1241698#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1241699#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1448222#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1304416#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1304411#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1239918#L1553-2 [2021-12-15 17:21:10,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:10,535 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2021-12-15 17:21:10,535 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:10,535 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102275038] [2021-12-15 17:21:10,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:10,535 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:10,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:10,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:10,584 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:10,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102275038] [2021-12-15 17:21:10,584 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102275038] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:10,584 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:10,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:10,585 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825523054] [2021-12-15 17:21:10,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:10,585 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:10,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:10,585 INFO L85 PathProgramCache]: Analyzing trace with hash -660028673, now seen corresponding path program 1 times [2021-12-15 17:21:10,586 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:10,586 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264941345] [2021-12-15 17:21:10,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:10,586 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:10,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:10,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:10,609 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:10,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264941345] [2021-12-15 17:21:10,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264941345] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:10,609 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:10,609 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:10,610 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985653752] [2021-12-15 17:21:10,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:10,610 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:10,610 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:10,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:10,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:10,611 INFO L87 Difference]: Start difference. First operand 341636 states and 485068 transitions. cyclomatic complexity: 143560 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:14,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:14,986 INFO L93 Difference]: Finished difference Result 977357 states and 1378839 transitions. [2021-12-15 17:21:14,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:14,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 977357 states and 1378839 transitions. [2021-12-15 17:21:20,204 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 972941 [2021-12-15 17:21:23,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 977357 states to 977357 states and 1378839 transitions. [2021-12-15 17:21:23,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 977357