./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:52,536 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:52,546 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:52,592 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:52,593 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:52,596 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:52,598 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:52,600 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:52,602 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:52,606 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:52,607 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:52,608 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:52,608 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:52,610 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:52,611 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:52,615 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:52,616 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:52,616 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:52,620 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:52,622 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:52,624 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:52,625 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:52,627 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:52,627 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:52,630 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:52,632 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:52,632 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:52,633 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:52,634 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:52,635 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:52,635 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:52,636 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:52,637 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:52,638 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:52,639 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:52,639 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:52,639 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:52,640 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:52,640 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:52,640 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:52,641 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:52,642 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:52,679 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:52,680 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:52,680 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:52,680 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:52,681 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:52,681 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:52,681 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:52,681 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:52,681 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:52,681 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:52,681 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:52,681 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:52,681 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:52,682 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:52,682 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:52,683 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:52,683 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:52,683 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:52,683 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:52,683 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:52,683 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:52,683 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:52,684 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:52,684 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2021-12-15 17:20:52,896 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:52,918 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:52,920 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:52,921 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:52,921 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:52,922 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2021-12-15 17:20:52,977 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5d4e0a380/7315ed72c2fd42f0bcab15206e26ceca/FLAG41ea38ab7 [2021-12-15 17:20:53,367 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:53,367 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2021-12-15 17:20:53,382 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5d4e0a380/7315ed72c2fd42f0bcab15206e26ceca/FLAG41ea38ab7 [2021-12-15 17:20:53,724 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5d4e0a380/7315ed72c2fd42f0bcab15206e26ceca [2021-12-15 17:20:53,726 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:53,739 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:53,740 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:53,740 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:53,745 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:53,745 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:53" (1/1) ... [2021-12-15 17:20:53,746 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14cbed0b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:53, skipping insertion in model container [2021-12-15 17:20:53,746 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:53" (1/1) ... [2021-12-15 17:20:53,763 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:53,798 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:53,950 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2021-12-15 17:20:54,073 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:54,088 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:54,098 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2021-12-15 17:20:54,169 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:54,189 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:54,189 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54 WrapperNode [2021-12-15 17:20:54,190 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:54,191 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:54,191 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:54,191 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:54,196 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,218 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,291 INFO L137 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 238, statements flattened = 3645 [2021-12-15 17:20:54,291 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:54,292 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:54,292 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:54,292 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:54,299 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,299 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,307 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,308 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,344 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,375 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,381 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,397 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:54,397 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:54,398 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:54,398 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:54,398 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (1/1) ... [2021-12-15 17:20:54,407 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:54,415 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:54,425 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:54,431 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:54,452 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:54,453 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:54,453 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:54,453 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:54,562 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:54,563 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:20:55,815 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:20:55,826 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:20:55,826 INFO L301 CfgBuilder]: Removed 14 assume(true) statements. [2021-12-15 17:20:55,829 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:55 BoogieIcfgContainer [2021-12-15 17:20:55,829 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:20:55,830 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:20:55,830 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:20:55,832 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:20:55,833 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:55,833 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:53" (1/3) ... [2021-12-15 17:20:55,834 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38fed2a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:55, skipping insertion in model container [2021-12-15 17:20:55,834 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:55,834 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:54" (2/3) ... [2021-12-15 17:20:55,835 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38fed2a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:20:55, skipping insertion in model container [2021-12-15 17:20:55,835 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:20:55,835 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:20:55" (3/3) ... [2021-12-15 17:20:55,836 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2021-12-15 17:20:55,868 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:20:55,869 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:20:55,869 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:20:55,869 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:20:55,869 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:20:55,869 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:20:55,869 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:20:55,869 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:20:55,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:55,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2021-12-15 17:20:55,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:55,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:56,001 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,002 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:20:56,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2021-12-15 17:20:56,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:56,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:56,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,041 INFO L791 eck$LassoCheckResult]: Stem: 395#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1507#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1131#L1641true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1514#L773true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1152#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1400#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1084#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1398#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 303#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 572#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1095#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1031#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 255#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 727#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 195#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 928#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1453#L1109true assume !(0 == ~M_E~0); 963#L1109-2true assume !(0 == ~T1_E~0); 199#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1523#L1119-1true assume !(0 == ~T3_E~0); 1036#L1124-1true assume !(0 == ~T4_E~0); 27#L1129-1true assume !(0 == ~T5_E~0); 350#L1134-1true assume !(0 == ~T6_E~0); 945#L1139-1true assume !(0 == ~T7_E~0); 1021#L1144-1true assume !(0 == ~T8_E~0); 784#L1149-1true assume !(0 == ~T9_E~0); 75#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 920#L1159-1true assume !(0 == ~T11_E~0); 769#L1164-1true assume !(0 == ~E_M~0); 282#L1169-1true assume !(0 == ~E_1~0); 224#L1174-1true assume !(0 == ~E_2~0); 155#L1179-1true assume !(0 == ~E_3~0); 116#L1184-1true assume !(0 == ~E_4~0); 134#L1189-1true assume !(0 == ~E_5~0); 180#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 791#L1199-1true assume !(0 == ~E_7~0); 969#L1204-1true assume !(0 == ~E_8~0); 723#L1209-1true assume !(0 == ~E_9~0); 1177#L1214-1true assume !(0 == ~E_10~0); 1526#L1219-1true assume !(0 == ~E_11~0); 1470#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293#L544true assume 1 == ~m_pc~0; 1029#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1188#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 798#L556true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96#L1379true assume !(0 != activate_threads_~tmp~1#1); 1393#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 557#L563true assume !(1 == ~t1_pc~0); 1184#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 32#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1107#L575true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 665#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 30#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405#L582true assume 1 == ~t2_pc~0; 886#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 675#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 783#L594true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 843#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 46#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 757#L601true assume !(1 == ~t3_pc~0); 463#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1016#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1219#L613true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 706#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1410#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 655#L620true assume 1 == ~t4_pc~0; 37#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 364#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 329#L632true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 569#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 759#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 740#L639true assume 1 == ~t5_pc~0; 630#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 183#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 590#L651true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 584#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 849#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 529#L658true assume !(1 == ~t6_pc~0); 291#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 697#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1136#L670true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1477#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 710#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 205#L677true assume 1 == ~t7_pc~0; 1245#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 889#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1341#L689true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1071#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1230#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1304#L696true assume !(1 == ~t8_pc~0); 324#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1150#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1196#L708true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1347#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1521#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 618#L715true assume 1 == ~t9_pc~0; 1222#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 381#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 323#L727true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 605#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1391#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 887#L734true assume !(1 == ~t10_pc~0); 1038#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 268#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 277#L746true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 813#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1257#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 311#L753true assume 1 == ~t11_pc~0; 716#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1570#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 377#L765true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 475#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 777#L1467-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 514#L1237true assume !(1 == ~M_E~0); 1299#L1237-2true assume !(1 == ~T1_E~0); 1420#L1242-1true assume !(1 == ~T2_E~0); 361#L1247-1true assume !(1 == ~T3_E~0); 1067#L1252-1true assume !(1 == ~T4_E~0); 235#L1257-1true assume !(1 == ~T5_E~0); 908#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1054#L1267-1true assume !(1 == ~T7_E~0); 1055#L1272-1true assume !(1 == ~T8_E~0); 411#L1277-1true assume !(1 == ~T9_E~0); 823#L1282-1true assume !(1 == ~T10_E~0); 751#L1287-1true assume !(1 == ~T11_E~0); 792#L1292-1true assume !(1 == ~E_M~0); 709#L1297-1true assume !(1 == ~E_1~0); 307#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1040#L1307-1true assume !(1 == ~E_3~0); 1357#L1312-1true assume !(1 == ~E_4~0); 438#L1317-1true assume !(1 == ~E_5~0); 613#L1322-1true assume !(1 == ~E_6~0); 275#L1327-1true assume !(1 == ~E_7~0); 664#L1332-1true assume !(1 == ~E_8~0); 1336#L1337-1true assume !(1 == ~E_9~0); 609#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1234#L1347-1true assume !(1 == ~E_11~0); 1039#L1352-1true assume { :end_inline_reset_delta_events } true; 1564#L1678-2true [2021-12-15 17:20:56,048 INFO L793 eck$LassoCheckResult]: Loop: 1564#L1678-2true assume !false; 656#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 817#L1084true assume !true; 171#L1099true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105#L773-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1423#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 38#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1215#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 711#L1119-3true assume !(0 == ~T3_E~0); 1559#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 736#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 954#L1134-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1115#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1027#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 298#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1551#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 443#L1159-3true assume !(0 == ~T11_E~0); 1538#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 652#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 986#L1174-3true assume 0 == ~E_2~0;~E_2~0 := 1; 699#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1306#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 870#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 551#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 168#L1199-3true assume !(0 == ~E_7~0); 794#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 288#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 15#L1214-3true assume 0 == ~E_10~0;~E_10~0 := 1; 602#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 386#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 644#L544-39true assume !(1 == ~m_pc~0); 5#L544-41true is_master_triggered_~__retres1~0#1 := 0; 738#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124#L556-13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 209#L1379-39true assume !(0 != activate_threads_~tmp~1#1); 848#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1317#L563-39true assume !(1 == ~t1_pc~0); 73#L563-41true is_transmit1_triggered_~__retres1~1#1 := 0; 1539#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 625#L575-13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1434#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1446#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1003#L582-39true assume 1 == ~t2_pc~0; 243#L583-13true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 761#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 667#L594-13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 971#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 120#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20#L601-39true assume 1 == ~t3_pc~0; 1236#L602-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 807#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 985#L613-13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1492#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 856#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527#L620-39true assume 1 == ~t4_pc~0; 695#L621-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 940#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1500#L632-13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 821#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1546#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1543#L639-39true assume 1 == ~t5_pc~0; 978#L640-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 365#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127#L651-13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33#L1419-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1380#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 555#L658-39true assume 1 == ~t6_pc~0; 540#L659-13true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1065#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10#L670-13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 720#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 692#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238#L677-39true assume 1 == ~t7_pc~0; 659#L678-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 992#L689-13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 145#L1435-39true assume !(0 != activate_threads_~tmp___6~0#1); 1369#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 477#L696-39true assume !(1 == ~t8_pc~0); 781#L696-41true is_transmit8_triggered_~__retres1~8#1 := 0; 375#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1495#L708-13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 578#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 547#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 461#L715-39true assume !(1 == ~t9_pc~0); 1058#L715-41true is_transmit9_triggered_~__retres1~9#1 := 0; 815#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1569#L727-13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1568#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 742#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1141#L734-39true assume !(1 == ~t10_pc~0); 281#L734-41true is_transmit10_triggered_~__retres1~10#1 := 0; 478#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 746#L746-13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1460#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1091#L753-39true assume !(1 == ~t11_pc~0); 56#L753-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1019#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1147#L765-13true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 455#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 750#L1467-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 525#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1086#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 773#L1242-3true assume !(1 == ~T2_E~0); 1511#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1053#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 689#L1257-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1022#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1098#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1528#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1334#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 130#L1282-3true assume !(1 == ~T10_E~0); 666#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 82#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1489#L1297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 900#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1227#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1509#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1503#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 795#L1322-3true assume !(1 == ~E_6~0); 1556#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 112#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 99#L1337-3true assume 1 == ~E_9~0;~E_9~0 := 2; 504#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 943#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 604#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 891#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 214#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 698#L911-1true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 741#L1697true assume !(0 == start_simulation_~tmp~3#1); 520#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1309#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 857#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 619#L911-2true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1119#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 574#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#L1660true start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 888#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1564#L1678-2true [2021-12-15 17:20:56,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,053 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2021-12-15 17:20:56,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554069025] [2021-12-15 17:20:56,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,062 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,268 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554069025] [2021-12-15 17:20:56,268 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554069025] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,268 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,269 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707184871] [2021-12-15 17:20:56,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,273 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:56,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,273 INFO L85 PathProgramCache]: Analyzing trace with hash -356606326, now seen corresponding path program 1 times [2021-12-15 17:20:56,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131035256] [2021-12-15 17:20:56,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131035256] [2021-12-15 17:20:56,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131035256] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:56,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864601357] [2021-12-15 17:20:56,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,326 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:56,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:56,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-15 17:20:56,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-15 17:20:56,356 INFO L87 Difference]: Start difference. First operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:56,387 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2021-12-15 17:20:56,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-15 17:20:56,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2021-12-15 17:20:56,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:56,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1566 states and 2325 transitions. [2021-12-15 17:20:56,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:56,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:56,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2325 transitions. [2021-12-15 17:20:56,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:56,416 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2021-12-15 17:20:56,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2325 transitions. [2021-12-15 17:20:56,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:56,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2325 transitions. [2021-12-15 17:20:56,504 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2021-12-15 17:20:56,504 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2021-12-15 17:20:56,504 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:20:56,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2325 transitions. [2021-12-15 17:20:56,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:56,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:56,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:56,516 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,516 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,516 INFO L791 eck$LassoCheckResult]: Stem: 3887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4616#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4617#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3390#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3391#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4626#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4591#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4592#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3739#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3740#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4146#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4564#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3651#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3652#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3537#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3538#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4490#L1109 assume !(0 == ~M_E~0); 4512#L1109-2 assume !(0 == ~T1_E~0); 3544#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3545#L1119-1 assume !(0 == ~T3_E~0); 4568#L1124-1 assume !(0 == ~T4_E~0); 3205#L1129-1 assume !(0 == ~T5_E~0); 3206#L1134-1 assume !(0 == ~T6_E~0); 3819#L1139-1 assume !(0 == ~T7_E~0); 4496#L1144-1 assume !(0 == ~T8_E~0); 4368#L1149-1 assume !(0 == ~T9_E~0); 3312#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3313#L1159-1 assume !(0 == ~T11_E~0); 4354#L1164-1 assume !(0 == ~E_M~0); 3705#L1169-1 assume !(0 == ~E_1~0); 3594#L1174-1 assume !(0 == ~E_2~0); 3467#L1179-1 assume !(0 == ~E_3~0); 3394#L1184-1 assume !(0 == ~E_4~0); 3395#L1189-1 assume !(0 == ~E_5~0); 3426#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3513#L1199-1 assume !(0 == ~E_7~0); 4376#L1204-1 assume !(0 == ~E_8~0); 4312#L1209-1 assume !(0 == ~E_9~0); 4313#L1214-1 assume !(0 == ~E_10~0); 4638#L1219-1 assume !(0 == ~E_11~0); 4711#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3722#L544 assume 1 == ~m_pc~0; 3723#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4555#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4383#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3356#L1379 assume !(0 != activate_threads_~tmp~1#1); 3357#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4129#L563 assume !(1 == ~t1_pc~0); 3929#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3215#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4252#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3211#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3212#L582 assume 1 == ~t2_pc~0; 3907#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4262#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4263#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4367#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3244#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3245#L601 assume !(1 == ~t3_pc~0); 3923#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3922#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4556#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4298#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4299#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4242#L620 assume 1 == ~t4_pc~0; 3225#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3226#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3787#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3788#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4143#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4330#L639 assume 1 == ~t5_pc~0; 4213#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3517#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3518#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4164#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4165#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4094#L658 assume !(1 == ~t6_pc~0); 3719#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3720#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4288#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4618#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4302#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3557#L677 assume 1 == ~t7_pc~0; 3558#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3460#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4461#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4585#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4586#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4657#L696 assume !(1 == ~t8_pc~0); 3777#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3778#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4625#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4646#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4692#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4196#L715 assume 1 == ~t9_pc~0; 4197#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3867#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3775#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3776#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4185#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4457#L734 assume !(1 == ~t10_pc~0); 4458#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3677#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3678#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3696#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4401#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3753#L753 assume 1 == ~t11_pc~0; 3754#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4307#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3862#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3863#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4012#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4069#L1237 assume !(1 == ~M_E~0); 4070#L1237-2 assume !(1 == ~T1_E~0); 4682#L1242-1 assume !(1 == ~T2_E~0); 3833#L1247-1 assume !(1 == ~T3_E~0); 3834#L1252-1 assume !(1 == ~T4_E~0); 3617#L1257-1 assume !(1 == ~T5_E~0); 3618#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4473#L1267-1 assume !(1 == ~T7_E~0); 4578#L1272-1 assume !(1 == ~T8_E~0); 3916#L1277-1 assume !(1 == ~T9_E~0); 3917#L1282-1 assume !(1 == ~T10_E~0); 4339#L1287-1 assume !(1 == ~T11_E~0); 4340#L1292-1 assume !(1 == ~E_M~0); 4301#L1297-1 assume !(1 == ~E_1~0); 3748#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3749#L1307-1 assume !(1 == ~E_3~0); 4571#L1312-1 assume !(1 == ~E_4~0); 3959#L1317-1 assume !(1 == ~E_5~0); 3960#L1322-1 assume !(1 == ~E_6~0); 3692#L1327-1 assume !(1 == ~E_7~0); 3693#L1332-1 assume !(1 == ~E_8~0); 4251#L1337-1 assume !(1 == ~E_9~0); 4188#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4189#L1347-1 assume !(1 == ~E_11~0); 4570#L1352-1 assume { :end_inline_reset_delta_events } true; 4460#L1678-2 [2021-12-15 17:20:56,517 INFO L793 eck$LassoCheckResult]: Loop: 4460#L1678-2 assume !false; 4243#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4244#L1084 assume !false; 4027#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4028#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3331#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4345#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3257#L925 assume !(0 != eval_~tmp~0#1); 3259#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3373#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3374#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3228#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3229#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4303#L1119-3 assume !(0 == ~T3_E~0); 4304#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4325#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4326#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4504#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4562#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3732#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3733#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3968#L1159-3 assume !(0 == ~T11_E~0); 3969#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4239#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4240#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4290#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4291#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4446#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4123#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3490#L1199-3 assume !(0 == ~E_7~0); 3491#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3714#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3176#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3177#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3875#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3876#L544-39 assume !(1 == ~m_pc~0); 3157#L544-41 is_master_triggered_~__retres1~0#1 := 0; 3158#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3408#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3409#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 3565#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4433#L563-39 assume 1 == ~t1_pc~0; 4439#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3308#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4207#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4208#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4705#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4548#L582-39 assume !(1 == ~t2_pc~0); 3632#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 3633#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4253#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4254#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3401#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3188#L601-39 assume 1 == ~t3_pc~0; 3189#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3239#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4397#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4533#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4437#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4089#L620-39 assume !(1 == ~t4_pc~0); 4090#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4287#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4495#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4410#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4411#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4716#L639-39 assume 1 == ~t5_pc~0; 4523#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3837#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3414#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3217#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3218#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4126#L658-39 assume 1 == ~t6_pc~0; 4108#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4109#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3167#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3168#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4283#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4284#L677-39 assume 1 == ~t7_pc~0; 4246#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3392#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3393#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3448#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 3449#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4014#L696-39 assume 1 == ~t8_pc~0; 3979#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3859#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3860#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4155#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4119#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3994#L715-39 assume 1 == ~t9_pc~0; 3193#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3194#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4403#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4717#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4332#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4333#L734-39 assume 1 == ~t10_pc~0; 4258#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3704#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4015#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3346#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3347#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4595#L753-39 assume !(1 == ~t11_pc~0); 3266#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 3267#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4559#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3984#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3985#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4086#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4087#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4357#L1242-3 assume !(1 == ~T2_E~0); 4358#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4577#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4277#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4278#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4560#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4601#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4689#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3418#L1282-3 assume !(1 == ~T10_E~0); 3419#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3328#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3329#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4466#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4467#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4655#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4379#L1322-3 assume !(1 == ~E_6~0); 4380#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3387#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3362#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3363#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4055#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4183#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4184#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3310#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3575#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4289#L1697 assume !(0 == start_simulation_~tmp~3#1); 4076#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4077#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3434#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4199#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 4200#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4149#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3746#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3747#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4460#L1678-2 [2021-12-15 17:20:56,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,518 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2021-12-15 17:20:56,518 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995074384] [2021-12-15 17:20:56,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,519 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,554 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995074384] [2021-12-15 17:20:56,554 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995074384] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,554 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,554 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,555 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545404253] [2021-12-15 17:20:56,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,555 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:56,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1065978444, now seen corresponding path program 1 times [2021-12-15 17:20:56,556 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581672531] [2021-12-15 17:20:56,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,557 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,620 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581672531] [2021-12-15 17:20:56,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581672531] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,621 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,621 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,621 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806883717] [2021-12-15 17:20:56,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,622 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:56,622 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:56,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:56,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:56,623 INFO L87 Difference]: Start difference. First operand 1566 states and 2325 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:56,648 INFO L93 Difference]: Finished difference Result 1566 states and 2324 transitions. [2021-12-15 17:20:56,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:56,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2324 transitions. [2021-12-15 17:20:56,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:56,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2324 transitions. [2021-12-15 17:20:56,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:56,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:56,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2324 transitions. [2021-12-15 17:20:56,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:56,665 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2021-12-15 17:20:56,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2324 transitions. [2021-12-15 17:20:56,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:56,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2324 transitions. [2021-12-15 17:20:56,686 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2021-12-15 17:20:56,686 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2021-12-15 17:20:56,686 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:20:56,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2324 transitions. [2021-12-15 17:20:56,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:56,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:56,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:56,693 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,693 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,694 INFO L791 eck$LassoCheckResult]: Stem: 7026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 7027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7755#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7756#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6529#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 6530#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7765#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7730#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7731#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6878#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6879#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7285#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7703#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6790#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6791#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6676#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6677#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7629#L1109 assume !(0 == ~M_E~0); 7651#L1109-2 assume !(0 == ~T1_E~0); 6683#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6684#L1119-1 assume !(0 == ~T3_E~0); 7707#L1124-1 assume !(0 == ~T4_E~0); 6344#L1129-1 assume !(0 == ~T5_E~0); 6345#L1134-1 assume !(0 == ~T6_E~0); 6958#L1139-1 assume !(0 == ~T7_E~0); 7635#L1144-1 assume !(0 == ~T8_E~0); 7507#L1149-1 assume !(0 == ~T9_E~0); 6451#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6452#L1159-1 assume !(0 == ~T11_E~0); 7493#L1164-1 assume !(0 == ~E_M~0); 6844#L1169-1 assume !(0 == ~E_1~0); 6733#L1174-1 assume !(0 == ~E_2~0); 6606#L1179-1 assume !(0 == ~E_3~0); 6533#L1184-1 assume !(0 == ~E_4~0); 6534#L1189-1 assume !(0 == ~E_5~0); 6565#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6652#L1199-1 assume !(0 == ~E_7~0); 7515#L1204-1 assume !(0 == ~E_8~0); 7451#L1209-1 assume !(0 == ~E_9~0); 7452#L1214-1 assume !(0 == ~E_10~0); 7777#L1219-1 assume !(0 == ~E_11~0); 7850#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6861#L544 assume 1 == ~m_pc~0; 6862#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7694#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7522#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6495#L1379 assume !(0 != activate_threads_~tmp~1#1); 6496#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7268#L563 assume !(1 == ~t1_pc~0); 7068#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6354#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6355#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7391#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 6350#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6351#L582 assume 1 == ~t2_pc~0; 7046#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7401#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7402#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7506#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 6383#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6384#L601 assume !(1 == ~t3_pc~0); 7062#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7061#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7695#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7437#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 7438#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7381#L620 assume 1 == ~t4_pc~0; 6364#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6365#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6927#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 7282#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7469#L639 assume 1 == ~t5_pc~0; 7352#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6656#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6657#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7303#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 7304#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7233#L658 assume !(1 == ~t6_pc~0); 6858#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6859#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7427#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7757#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7441#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6696#L677 assume 1 == ~t7_pc~0; 6697#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6599#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7600#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7724#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 7725#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7796#L696 assume !(1 == ~t8_pc~0); 6916#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6917#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7764#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7785#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 7831#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7335#L715 assume 1 == ~t9_pc~0; 7336#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7006#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6914#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6915#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 7324#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7596#L734 assume !(1 == ~t10_pc~0); 7597#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6816#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6817#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6835#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 7540#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6892#L753 assume 1 == ~t11_pc~0; 6893#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7446#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7001#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7002#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 7151#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7208#L1237 assume !(1 == ~M_E~0); 7209#L1237-2 assume !(1 == ~T1_E~0); 7821#L1242-1 assume !(1 == ~T2_E~0); 6972#L1247-1 assume !(1 == ~T3_E~0); 6973#L1252-1 assume !(1 == ~T4_E~0); 6756#L1257-1 assume !(1 == ~T5_E~0); 6757#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7612#L1267-1 assume !(1 == ~T7_E~0); 7717#L1272-1 assume !(1 == ~T8_E~0); 7055#L1277-1 assume !(1 == ~T9_E~0); 7056#L1282-1 assume !(1 == ~T10_E~0); 7478#L1287-1 assume !(1 == ~T11_E~0); 7479#L1292-1 assume !(1 == ~E_M~0); 7440#L1297-1 assume !(1 == ~E_1~0); 6887#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6888#L1307-1 assume !(1 == ~E_3~0); 7710#L1312-1 assume !(1 == ~E_4~0); 7098#L1317-1 assume !(1 == ~E_5~0); 7099#L1322-1 assume !(1 == ~E_6~0); 6831#L1327-1 assume !(1 == ~E_7~0); 6832#L1332-1 assume !(1 == ~E_8~0); 7390#L1337-1 assume !(1 == ~E_9~0); 7327#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7328#L1347-1 assume !(1 == ~E_11~0); 7709#L1352-1 assume { :end_inline_reset_delta_events } true; 7599#L1678-2 [2021-12-15 17:20:56,694 INFO L793 eck$LassoCheckResult]: Loop: 7599#L1678-2 assume !false; 7382#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7383#L1084 assume !false; 7166#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7167#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6470#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7484#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6396#L925 assume !(0 != eval_~tmp~0#1); 6398#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6512#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6513#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6367#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6368#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7442#L1119-3 assume !(0 == ~T3_E~0); 7443#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7464#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7465#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7643#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7701#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6871#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6872#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7107#L1159-3 assume !(0 == ~T11_E~0); 7108#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7378#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7379#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7429#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7430#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7585#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7262#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6629#L1199-3 assume !(0 == ~E_7~0); 6630#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6853#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6315#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6316#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7014#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7015#L544-39 assume !(1 == ~m_pc~0); 6296#L544-41 is_master_triggered_~__retres1~0#1 := 0; 6297#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6547#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6548#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 6704#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7572#L563-39 assume 1 == ~t1_pc~0; 7578#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6447#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7346#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7347#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7844#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7687#L582-39 assume 1 == ~t2_pc~0; 6770#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6772#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7392#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7393#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6540#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6327#L601-39 assume 1 == ~t3_pc~0; 6328#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6378#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7536#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7672#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7576#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7228#L620-39 assume !(1 == ~t4_pc~0); 7229#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7426#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7634#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7549#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7550#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7855#L639-39 assume 1 == ~t5_pc~0; 7662#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6976#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6553#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6356#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6357#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7265#L658-39 assume !(1 == ~t6_pc~0); 7249#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 7248#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6306#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6307#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7422#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7423#L677-39 assume 1 == ~t7_pc~0; 7385#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6531#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6532#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6587#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 6588#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7153#L696-39 assume 1 == ~t8_pc~0; 7118#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6998#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6999#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7294#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7258#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7133#L715-39 assume 1 == ~t9_pc~0; 6332#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6333#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7542#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7856#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7471#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7472#L734-39 assume 1 == ~t10_pc~0; 7397#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6843#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7154#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6485#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6486#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7734#L753-39 assume !(1 == ~t11_pc~0); 6405#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 6406#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7698#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7123#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7124#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7225#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7226#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7496#L1242-3 assume !(1 == ~T2_E~0); 7497#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7716#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7416#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7417#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7699#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7740#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7828#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6557#L1282-3 assume !(1 == ~T10_E~0); 6558#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6467#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6468#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7605#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7606#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7794#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7852#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7518#L1322-3 assume !(1 == ~E_6~0); 7519#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6526#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6501#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6502#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7194#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7322#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7323#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6449#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6714#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 7428#L1697 assume !(0 == start_simulation_~tmp~3#1); 7215#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7216#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6573#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7338#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 7339#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7288#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6885#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 6886#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 7599#L1678-2 [2021-12-15 17:20:56,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,695 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2021-12-15 17:20:56,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009009022] [2021-12-15 17:20:56,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,696 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,733 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009009022] [2021-12-15 17:20:56,733 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009009022] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,733 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,734 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,734 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642088905] [2021-12-15 17:20:56,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,734 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:56,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,735 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 1 times [2021-12-15 17:20:56,735 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059446954] [2021-12-15 17:20:56,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,736 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,773 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,773 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059446954] [2021-12-15 17:20:56,774 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059446954] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,774 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,774 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,774 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037347154] [2021-12-15 17:20:56,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,775 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:56,775 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:56,775 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:56,775 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:56,775 INFO L87 Difference]: Start difference. First operand 1566 states and 2324 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:56,793 INFO L93 Difference]: Finished difference Result 1566 states and 2323 transitions. [2021-12-15 17:20:56,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:56,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2323 transitions. [2021-12-15 17:20:56,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:56,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2323 transitions. [2021-12-15 17:20:56,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:56,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:56,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2323 transitions. [2021-12-15 17:20:56,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:56,845 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2021-12-15 17:20:56,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2323 transitions. [2021-12-15 17:20:56,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:56,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2323 transitions. [2021-12-15 17:20:56,865 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2021-12-15 17:20:56,865 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2021-12-15 17:20:56,865 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:20:56,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2323 transitions. [2021-12-15 17:20:56,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:56,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:56,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:56,872 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:56,872 INFO L791 eck$LassoCheckResult]: Stem: 10165#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 10166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10894#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10895#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9668#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9669#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10904#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10869#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10870#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10017#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10018#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10424#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10842#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9929#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9930#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9815#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9816#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10770#L1109 assume !(0 == ~M_E~0); 10790#L1109-2 assume !(0 == ~T1_E~0); 9822#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9823#L1119-1 assume !(0 == ~T3_E~0); 10846#L1124-1 assume !(0 == ~T4_E~0); 9485#L1129-1 assume !(0 == ~T5_E~0); 9486#L1134-1 assume !(0 == ~T6_E~0); 10097#L1139-1 assume !(0 == ~T7_E~0); 10774#L1144-1 assume !(0 == ~T8_E~0); 10646#L1149-1 assume !(0 == ~T9_E~0); 9592#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9593#L1159-1 assume !(0 == ~T11_E~0); 10632#L1164-1 assume !(0 == ~E_M~0); 9983#L1169-1 assume !(0 == ~E_1~0); 9872#L1174-1 assume !(0 == ~E_2~0); 9748#L1179-1 assume !(0 == ~E_3~0); 9672#L1184-1 assume !(0 == ~E_4~0); 9673#L1189-1 assume !(0 == ~E_5~0); 9704#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9793#L1199-1 assume !(0 == ~E_7~0); 10654#L1204-1 assume !(0 == ~E_8~0); 10591#L1209-1 assume !(0 == ~E_9~0); 10592#L1214-1 assume !(0 == ~E_10~0); 10916#L1219-1 assume !(0 == ~E_11~0); 10989#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10002#L544 assume 1 == ~m_pc~0; 10003#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10833#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10663#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9634#L1379 assume !(0 != activate_threads_~tmp~1#1); 9635#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10410#L563 assume !(1 == ~t1_pc~0); 10207#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9493#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9494#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10530#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9489#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9490#L582 assume 1 == ~t2_pc~0; 10185#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10540#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10541#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10645#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9522#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9523#L601 assume !(1 == ~t3_pc~0); 10201#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10200#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10834#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10576#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10577#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10520#L620 assume 1 == ~t4_pc~0; 9503#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9504#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10065#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10066#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10421#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10609#L639 assume 1 == ~t5_pc~0; 10494#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9795#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9796#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10442#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10443#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10374#L658 assume !(1 == ~t6_pc~0); 9997#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9998#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10567#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10896#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10580#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9837#L677 assume 1 == ~t7_pc~0; 9838#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9741#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10739#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10863#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10864#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10935#L696 assume !(1 == ~t8_pc~0); 10056#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10057#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10903#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10924#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 10970#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10474#L715 assume 1 == ~t9_pc~0; 10475#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10145#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10053#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10054#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10463#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10736#L734 assume !(1 == ~t10_pc~0); 10737#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9955#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9956#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9976#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10679#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10031#L753 assume 1 == ~t11_pc~0; 10032#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10585#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10140#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10141#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10292#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10349#L1237 assume !(1 == ~M_E~0); 10350#L1237-2 assume !(1 == ~T1_E~0); 10961#L1242-1 assume !(1 == ~T2_E~0); 10111#L1247-1 assume !(1 == ~T3_E~0); 10112#L1252-1 assume !(1 == ~T4_E~0); 9895#L1257-1 assume !(1 == ~T5_E~0); 9896#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10752#L1267-1 assume !(1 == ~T7_E~0); 10856#L1272-1 assume !(1 == ~T8_E~0); 10194#L1277-1 assume !(1 == ~T9_E~0); 10195#L1282-1 assume !(1 == ~T10_E~0); 10617#L1287-1 assume !(1 == ~T11_E~0); 10618#L1292-1 assume !(1 == ~E_M~0); 10579#L1297-1 assume !(1 == ~E_1~0); 10026#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10027#L1307-1 assume !(1 == ~E_3~0); 10849#L1312-1 assume !(1 == ~E_4~0); 10237#L1317-1 assume !(1 == ~E_5~0); 10238#L1322-1 assume !(1 == ~E_6~0); 9970#L1327-1 assume !(1 == ~E_7~0); 9971#L1332-1 assume !(1 == ~E_8~0); 10529#L1337-1 assume !(1 == ~E_9~0); 10466#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10467#L1347-1 assume !(1 == ~E_11~0); 10848#L1352-1 assume { :end_inline_reset_delta_events } true; 10735#L1678-2 [2021-12-15 17:20:56,872 INFO L793 eck$LassoCheckResult]: Loop: 10735#L1678-2 assume !false; 10522#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10523#L1084 assume !false; 10306#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10307#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9609#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10624#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9535#L925 assume !(0 != eval_~tmp~0#1); 9537#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9651#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9652#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9506#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9507#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10581#L1119-3 assume !(0 == ~T3_E~0); 10582#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10603#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10604#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10782#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10840#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10010#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10011#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10248#L1159-3 assume !(0 == ~T11_E~0); 10249#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10517#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10518#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10568#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10569#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10724#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9768#L1199-3 assume !(0 == ~E_7~0); 9769#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9992#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9454#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9455#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10153#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10154#L544-39 assume !(1 == ~m_pc~0); 9435#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9436#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9684#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9685#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 9843#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10711#L563-39 assume !(1 == ~t1_pc~0); 9585#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 9586#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10485#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10486#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10983#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10826#L582-39 assume 1 == ~t2_pc~0; 9909#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9911#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10531#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10532#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9679#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9466#L601-39 assume 1 == ~t3_pc~0; 9467#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9517#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10675#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10811#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10715#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10367#L620-39 assume !(1 == ~t4_pc~0); 10368#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10565#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10773#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10688#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10689#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10994#L639-39 assume 1 == ~t5_pc~0; 10801#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10115#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9692#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9495#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9496#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10404#L658-39 assume 1 == ~t6_pc~0; 10386#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10387#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9445#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9446#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10561#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10562#L677-39 assume !(1 == ~t7_pc~0); 10192#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 9670#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9671#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9726#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 9727#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10291#L696-39 assume 1 == ~t8_pc~0; 10257#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10137#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10138#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10433#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10397#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10272#L715-39 assume !(1 == ~t9_pc~0); 9473#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9472#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10681#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10995#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10610#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10611#L734-39 assume 1 == ~t10_pc~0; 10536#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9982#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10293#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9624#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9625#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10873#L753-39 assume !(1 == ~t11_pc~0); 9544#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9545#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10837#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10262#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10263#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10364#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10365#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10635#L1242-3 assume !(1 == ~T2_E~0); 10636#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10855#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10555#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10556#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10838#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10879#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10967#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9696#L1282-3 assume !(1 == ~T10_E~0); 9697#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9606#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9607#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10744#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10745#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10933#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10991#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10657#L1322-3 assume !(1 == ~E_6~0); 10658#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9665#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9640#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9641#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10333#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10461#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10462#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9588#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9853#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 10566#L1697 assume !(0 == start_simulation_~tmp~3#1); 10354#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10355#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9712#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10477#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 10478#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10427#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10024#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10025#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10735#L1678-2 [2021-12-15 17:20:56,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2021-12-15 17:20:56,874 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472467259] [2021-12-15 17:20:56,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,875 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,935 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472467259] [2021-12-15 17:20:56,935 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472467259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,935 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,935 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,935 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507869699] [2021-12-15 17:20:56,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,935 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:56,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:56,936 INFO L85 PathProgramCache]: Analyzing trace with hash 1977169166, now seen corresponding path program 1 times [2021-12-15 17:20:56,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:56,936 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989056383] [2021-12-15 17:20:56,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:56,936 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:56,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:56,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:56,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:56,974 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989056383] [2021-12-15 17:20:56,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989056383] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:56,975 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:56,975 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:56,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73052743] [2021-12-15 17:20:56,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:56,975 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:56,976 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:56,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:56,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:56,977 INFO L87 Difference]: Start difference. First operand 1566 states and 2323 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:56,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:56,998 INFO L93 Difference]: Finished difference Result 1566 states and 2322 transitions. [2021-12-15 17:20:56,998 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:56,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2322 transitions. [2021-12-15 17:20:57,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2322 transitions. [2021-12-15 17:20:57,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2322 transitions. [2021-12-15 17:20:57,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,015 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2021-12-15 17:20:57,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2322 transitions. [2021-12-15 17:20:57,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2322 transitions. [2021-12-15 17:20:57,036 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2021-12-15 17:20:57,036 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2021-12-15 17:20:57,036 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:20:57,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2322 transitions. [2021-12-15 17:20:57,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,043 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,043 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,043 INFO L791 eck$LassoCheckResult]: Stem: 13304#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 13305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 14033#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14034#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12807#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 12808#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14043#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14008#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14009#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13156#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13157#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13563#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13981#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13068#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13069#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12954#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12955#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13907#L1109 assume !(0 == ~M_E~0); 13929#L1109-2 assume !(0 == ~T1_E~0); 12961#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12962#L1119-1 assume !(0 == ~T3_E~0); 13985#L1124-1 assume !(0 == ~T4_E~0); 12624#L1129-1 assume !(0 == ~T5_E~0); 12625#L1134-1 assume !(0 == ~T6_E~0); 13236#L1139-1 assume !(0 == ~T7_E~0); 13913#L1144-1 assume !(0 == ~T8_E~0); 13785#L1149-1 assume !(0 == ~T9_E~0); 12729#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12730#L1159-1 assume !(0 == ~T11_E~0); 13771#L1164-1 assume !(0 == ~E_M~0); 13122#L1169-1 assume !(0 == ~E_1~0); 13011#L1174-1 assume !(0 == ~E_2~0); 12884#L1179-1 assume !(0 == ~E_3~0); 12811#L1184-1 assume !(0 == ~E_4~0); 12812#L1189-1 assume !(0 == ~E_5~0); 12843#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12930#L1199-1 assume !(0 == ~E_7~0); 13793#L1204-1 assume !(0 == ~E_8~0); 13729#L1209-1 assume !(0 == ~E_9~0); 13730#L1214-1 assume !(0 == ~E_10~0); 14055#L1219-1 assume !(0 == ~E_11~0); 14128#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13139#L544 assume 1 == ~m_pc~0; 13140#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13972#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13800#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12773#L1379 assume !(0 != activate_threads_~tmp~1#1); 12774#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13546#L563 assume !(1 == ~t1_pc~0); 13346#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12632#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12633#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13669#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 12628#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12629#L582 assume 1 == ~t2_pc~0; 13324#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13679#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13680#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13784#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 12661#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12662#L601 assume !(1 == ~t3_pc~0); 13340#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13339#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13973#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13715#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 13716#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13659#L620 assume 1 == ~t4_pc~0; 12642#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12643#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13204#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13205#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 13560#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13748#L639 assume 1 == ~t5_pc~0; 13631#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12934#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12935#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13581#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 13582#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13511#L658 assume !(1 == ~t6_pc~0); 13136#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13137#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13706#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14035#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13719#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12974#L677 assume 1 == ~t7_pc~0; 12975#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12877#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13878#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14002#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 14003#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14074#L696 assume !(1 == ~t8_pc~0); 13194#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13195#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14042#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14063#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 14109#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13613#L715 assume 1 == ~t9_pc~0; 13614#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13284#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13192#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13193#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 13602#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13875#L734 assume !(1 == ~t10_pc~0); 13876#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13094#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13095#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13113#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 13818#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13170#L753 assume 1 == ~t11_pc~0; 13171#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13724#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13279#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13280#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 13429#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13486#L1237 assume !(1 == ~M_E~0); 13487#L1237-2 assume !(1 == ~T1_E~0); 14099#L1242-1 assume !(1 == ~T2_E~0); 13250#L1247-1 assume !(1 == ~T3_E~0); 13251#L1252-1 assume !(1 == ~T4_E~0); 13034#L1257-1 assume !(1 == ~T5_E~0); 13035#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13890#L1267-1 assume !(1 == ~T7_E~0); 13995#L1272-1 assume !(1 == ~T8_E~0); 13333#L1277-1 assume !(1 == ~T9_E~0); 13334#L1282-1 assume !(1 == ~T10_E~0); 13756#L1287-1 assume !(1 == ~T11_E~0); 13757#L1292-1 assume !(1 == ~E_M~0); 13718#L1297-1 assume !(1 == ~E_1~0); 13165#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13166#L1307-1 assume !(1 == ~E_3~0); 13988#L1312-1 assume !(1 == ~E_4~0); 13376#L1317-1 assume !(1 == ~E_5~0); 13377#L1322-1 assume !(1 == ~E_6~0); 13109#L1327-1 assume !(1 == ~E_7~0); 13110#L1332-1 assume !(1 == ~E_8~0); 13668#L1337-1 assume !(1 == ~E_9~0); 13605#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13606#L1347-1 assume !(1 == ~E_11~0); 13987#L1352-1 assume { :end_inline_reset_delta_events } true; 13874#L1678-2 [2021-12-15 17:20:57,043 INFO L793 eck$LassoCheckResult]: Loop: 13874#L1678-2 assume !false; 13660#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13661#L1084 assume !false; 13444#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13445#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12748#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13762#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12674#L925 assume !(0 != eval_~tmp~0#1); 12676#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12790#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12791#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12645#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12646#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13720#L1119-3 assume !(0 == ~T3_E~0); 13721#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13742#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13743#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13921#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13979#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13149#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13150#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13385#L1159-3 assume !(0 == ~T11_E~0); 13386#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13656#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13657#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13707#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13708#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13863#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13540#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12907#L1199-3 assume !(0 == ~E_7~0); 12908#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13133#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12593#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12594#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13292#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13293#L544-39 assume 1 == ~m_pc~0; 13648#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12575#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12825#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12826#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 12982#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13850#L563-39 assume 1 == ~t1_pc~0; 13856#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12728#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13624#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13625#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14122#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13965#L582-39 assume 1 == ~t2_pc~0; 13048#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13050#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13670#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13671#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12818#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12605#L601-39 assume 1 == ~t3_pc~0; 12606#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12656#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13814#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13950#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13854#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13506#L620-39 assume !(1 == ~t4_pc~0); 13507#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 13704#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13912#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13827#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13828#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14133#L639-39 assume 1 == ~t5_pc~0; 13940#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13254#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12831#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12634#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12635#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13543#L658-39 assume 1 == ~t6_pc~0; 13525#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13526#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12584#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12585#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13700#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13701#L677-39 assume !(1 == ~t7_pc~0); 13331#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 12809#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12810#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12865#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 12866#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13431#L696-39 assume 1 == ~t8_pc~0; 13396#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13276#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13277#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13572#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13536#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13409#L715-39 assume 1 == ~t9_pc~0; 12608#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12609#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13820#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14134#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13749#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13750#L734-39 assume 1 == ~t10_pc~0; 13675#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13120#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13432#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12763#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12764#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14011#L753-39 assume !(1 == ~t11_pc~0); 12683#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 12684#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13976#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13401#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13402#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13499#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13500#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13774#L1242-3 assume !(1 == ~T2_E~0); 13775#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13994#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13694#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13695#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13977#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14018#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14106#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12834#L1282-3 assume !(1 == ~T10_E~0); 12835#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12745#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12746#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13881#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13882#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14072#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14130#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13796#L1322-3 assume !(1 == ~E_6~0); 13797#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12804#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12779#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12780#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13472#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13600#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13601#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12722#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12992#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13705#L1697 assume !(0 == start_simulation_~tmp~3#1); 13493#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13494#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12851#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13616#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 13617#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13566#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13161#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13162#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 13874#L1678-2 [2021-12-15 17:20:57,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,044 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2021-12-15 17:20:57,044 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952808734] [2021-12-15 17:20:57,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,045 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952808734] [2021-12-15 17:20:57,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952808734] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,065 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,066 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,066 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268951182] [2021-12-15 17:20:57,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,066 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,067 INFO L85 PathProgramCache]: Analyzing trace with hash 1734525003, now seen corresponding path program 1 times [2021-12-15 17:20:57,067 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918394098] [2021-12-15 17:20:57,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,067 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,111 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918394098] [2021-12-15 17:20:57,111 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918394098] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,111 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,111 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,112 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375844431] [2021-12-15 17:20:57,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,112 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,112 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,113 INFO L87 Difference]: Start difference. First operand 1566 states and 2322 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,134 INFO L93 Difference]: Finished difference Result 1566 states and 2321 transitions. [2021-12-15 17:20:57,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2321 transitions. [2021-12-15 17:20:57,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2321 transitions. [2021-12-15 17:20:57,181 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2321 transitions. [2021-12-15 17:20:57,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,183 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2021-12-15 17:20:57,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2321 transitions. [2021-12-15 17:20:57,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2321 transitions. [2021-12-15 17:20:57,202 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2021-12-15 17:20:57,203 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2021-12-15 17:20:57,203 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:20:57,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2321 transitions. [2021-12-15 17:20:57,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,211 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,211 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,211 INFO L791 eck$LassoCheckResult]: Stem: 16443#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16444#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 17172#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17173#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15946#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 15947#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17182#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17147#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17148#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16295#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16296#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16702#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17120#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16207#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16208#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16093#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16094#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17046#L1109 assume !(0 == ~M_E~0); 17068#L1109-2 assume !(0 == ~T1_E~0); 16100#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16101#L1119-1 assume !(0 == ~T3_E~0); 17124#L1124-1 assume !(0 == ~T4_E~0); 15761#L1129-1 assume !(0 == ~T5_E~0); 15762#L1134-1 assume !(0 == ~T6_E~0); 16375#L1139-1 assume !(0 == ~T7_E~0); 17052#L1144-1 assume !(0 == ~T8_E~0); 16924#L1149-1 assume !(0 == ~T9_E~0); 15868#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15869#L1159-1 assume !(0 == ~T11_E~0); 16910#L1164-1 assume !(0 == ~E_M~0); 16261#L1169-1 assume !(0 == ~E_1~0); 16150#L1174-1 assume !(0 == ~E_2~0); 16023#L1179-1 assume !(0 == ~E_3~0); 15950#L1184-1 assume !(0 == ~E_4~0); 15951#L1189-1 assume !(0 == ~E_5~0); 15982#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16069#L1199-1 assume !(0 == ~E_7~0); 16932#L1204-1 assume !(0 == ~E_8~0); 16868#L1209-1 assume !(0 == ~E_9~0); 16869#L1214-1 assume !(0 == ~E_10~0); 17194#L1219-1 assume !(0 == ~E_11~0); 17267#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16278#L544 assume 1 == ~m_pc~0; 16279#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17111#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16939#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15912#L1379 assume !(0 != activate_threads_~tmp~1#1); 15913#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16685#L563 assume !(1 == ~t1_pc~0); 16485#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15771#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15772#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16808#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15767#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15768#L582 assume 1 == ~t2_pc~0; 16463#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16818#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16819#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16923#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15800#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15801#L601 assume !(1 == ~t3_pc~0); 16479#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16478#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17112#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16854#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16855#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16798#L620 assume 1 == ~t4_pc~0; 15781#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15782#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16343#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16344#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16699#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16886#L639 assume 1 == ~t5_pc~0; 16769#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16073#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16074#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16720#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16721#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16650#L658 assume !(1 == ~t6_pc~0); 16275#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16276#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16844#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17174#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16858#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16113#L677 assume 1 == ~t7_pc~0; 16114#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16016#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17017#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17141#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17142#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17213#L696 assume !(1 == ~t8_pc~0); 16333#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16334#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17181#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17202#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17248#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16752#L715 assume 1 == ~t9_pc~0; 16753#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16423#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16331#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16332#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16741#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17013#L734 assume !(1 == ~t10_pc~0); 17014#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16233#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16234#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16252#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 16957#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16309#L753 assume 1 == ~t11_pc~0; 16310#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16863#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16418#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16419#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16568#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16625#L1237 assume !(1 == ~M_E~0); 16626#L1237-2 assume !(1 == ~T1_E~0); 17238#L1242-1 assume !(1 == ~T2_E~0); 16389#L1247-1 assume !(1 == ~T3_E~0); 16390#L1252-1 assume !(1 == ~T4_E~0); 16173#L1257-1 assume !(1 == ~T5_E~0); 16174#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17029#L1267-1 assume !(1 == ~T7_E~0); 17134#L1272-1 assume !(1 == ~T8_E~0); 16472#L1277-1 assume !(1 == ~T9_E~0); 16473#L1282-1 assume !(1 == ~T10_E~0); 16895#L1287-1 assume !(1 == ~T11_E~0); 16896#L1292-1 assume !(1 == ~E_M~0); 16857#L1297-1 assume !(1 == ~E_1~0); 16304#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16305#L1307-1 assume !(1 == ~E_3~0); 17127#L1312-1 assume !(1 == ~E_4~0); 16515#L1317-1 assume !(1 == ~E_5~0); 16516#L1322-1 assume !(1 == ~E_6~0); 16248#L1327-1 assume !(1 == ~E_7~0); 16249#L1332-1 assume !(1 == ~E_8~0); 16807#L1337-1 assume !(1 == ~E_9~0); 16744#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16745#L1347-1 assume !(1 == ~E_11~0); 17126#L1352-1 assume { :end_inline_reset_delta_events } true; 17016#L1678-2 [2021-12-15 17:20:57,212 INFO L793 eck$LassoCheckResult]: Loop: 17016#L1678-2 assume !false; 16799#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16800#L1084 assume !false; 16583#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16584#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15887#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16901#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15813#L925 assume !(0 != eval_~tmp~0#1); 15815#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15929#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15930#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15784#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15785#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16859#L1119-3 assume !(0 == ~T3_E~0); 16860#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16881#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16882#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17060#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17118#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16288#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16289#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16524#L1159-3 assume !(0 == ~T11_E~0); 16525#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16795#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16796#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16846#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16847#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17002#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16679#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16046#L1199-3 assume !(0 == ~E_7~0); 16047#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16270#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15732#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15733#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16431#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16432#L544-39 assume !(1 == ~m_pc~0); 15713#L544-41 is_master_triggered_~__retres1~0#1 := 0; 15714#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15964#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15965#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 16121#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16989#L563-39 assume 1 == ~t1_pc~0; 16995#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15864#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16763#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16764#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17261#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17104#L582-39 assume 1 == ~t2_pc~0; 16187#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16189#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16809#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16810#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15957#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15744#L601-39 assume 1 == ~t3_pc~0; 15745#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15795#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16953#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17089#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16993#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16645#L620-39 assume !(1 == ~t4_pc~0); 16646#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 16843#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17051#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16966#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16967#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17272#L639-39 assume 1 == ~t5_pc~0; 17079#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16393#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15970#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15773#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15774#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16682#L658-39 assume 1 == ~t6_pc~0; 16664#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16665#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15723#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15724#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16839#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16840#L677-39 assume 1 == ~t7_pc~0; 16802#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15948#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15949#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16004#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 16005#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16570#L696-39 assume 1 == ~t8_pc~0; 16535#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16415#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16416#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16711#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16675#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16550#L715-39 assume 1 == ~t9_pc~0; 15749#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15750#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16959#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17273#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16888#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16889#L734-39 assume !(1 == ~t10_pc~0); 16259#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 16260#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16571#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15902#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 15903#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17151#L753-39 assume !(1 == ~t11_pc~0); 15822#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15823#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17115#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16540#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16541#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16642#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16643#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16913#L1242-3 assume !(1 == ~T2_E~0); 16914#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17133#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16833#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16834#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17116#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17157#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17245#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15974#L1282-3 assume !(1 == ~T10_E~0); 15975#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15884#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15885#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17022#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17023#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17211#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17269#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16935#L1322-3 assume !(1 == ~E_6~0); 16936#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15943#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15918#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15919#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16611#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16739#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16740#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15866#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16131#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16845#L1697 assume !(0 == start_simulation_~tmp~3#1); 16632#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16633#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15990#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16755#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 16756#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16705#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16302#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 16303#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17016#L1678-2 [2021-12-15 17:20:57,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,213 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2021-12-15 17:20:57,213 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825417485] [2021-12-15 17:20:57,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,213 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825417485] [2021-12-15 17:20:57,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825417485] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,236 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,236 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,236 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1842634324] [2021-12-15 17:20:57,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,237 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,239 INFO L85 PathProgramCache]: Analyzing trace with hash 100626508, now seen corresponding path program 1 times [2021-12-15 17:20:57,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361162281] [2021-12-15 17:20:57,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361162281] [2021-12-15 17:20:57,276 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361162281] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,276 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,276 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,276 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771684981] [2021-12-15 17:20:57,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,277 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,277 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,278 INFO L87 Difference]: Start difference. First operand 1566 states and 2321 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,296 INFO L93 Difference]: Finished difference Result 1566 states and 2320 transitions. [2021-12-15 17:20:57,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2320 transitions. [2021-12-15 17:20:57,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2320 transitions. [2021-12-15 17:20:57,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2320 transitions. [2021-12-15 17:20:57,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,313 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2021-12-15 17:20:57,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2320 transitions. [2021-12-15 17:20:57,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2320 transitions. [2021-12-15 17:20:57,332 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2021-12-15 17:20:57,334 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2021-12-15 17:20:57,334 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:20:57,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2320 transitions. [2021-12-15 17:20:57,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,339 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,339 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,339 INFO L791 eck$LassoCheckResult]: Stem: 19582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20311#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20312#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19085#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 19086#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20321#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20286#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20287#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19434#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19435#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19841#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20259#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19346#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19347#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19232#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19233#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20185#L1109 assume !(0 == ~M_E~0); 20207#L1109-2 assume !(0 == ~T1_E~0); 19239#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19240#L1119-1 assume !(0 == ~T3_E~0); 20263#L1124-1 assume !(0 == ~T4_E~0); 18900#L1129-1 assume !(0 == ~T5_E~0); 18901#L1134-1 assume !(0 == ~T6_E~0); 19514#L1139-1 assume !(0 == ~T7_E~0); 20191#L1144-1 assume !(0 == ~T8_E~0); 20063#L1149-1 assume !(0 == ~T9_E~0); 19007#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19008#L1159-1 assume !(0 == ~T11_E~0); 20049#L1164-1 assume !(0 == ~E_M~0); 19400#L1169-1 assume !(0 == ~E_1~0); 19289#L1174-1 assume !(0 == ~E_2~0); 19162#L1179-1 assume !(0 == ~E_3~0); 19089#L1184-1 assume !(0 == ~E_4~0); 19090#L1189-1 assume !(0 == ~E_5~0); 19121#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19208#L1199-1 assume !(0 == ~E_7~0); 20071#L1204-1 assume !(0 == ~E_8~0); 20007#L1209-1 assume !(0 == ~E_9~0); 20008#L1214-1 assume !(0 == ~E_10~0); 20333#L1219-1 assume !(0 == ~E_11~0); 20406#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19417#L544 assume 1 == ~m_pc~0; 19418#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20250#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20078#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19051#L1379 assume !(0 != activate_threads_~tmp~1#1); 19052#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19824#L563 assume !(1 == ~t1_pc~0); 19624#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18910#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18911#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19947#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 18906#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18907#L582 assume 1 == ~t2_pc~0; 19602#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19957#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19958#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20062#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 18939#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18940#L601 assume !(1 == ~t3_pc~0); 19618#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19617#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20251#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19993#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 19994#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19937#L620 assume 1 == ~t4_pc~0; 18920#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18921#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19482#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19483#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 19838#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20025#L639 assume 1 == ~t5_pc~0; 19908#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19212#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19213#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19859#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 19860#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19789#L658 assume !(1 == ~t6_pc~0); 19414#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19415#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19983#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20313#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19997#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19252#L677 assume 1 == ~t7_pc~0; 19253#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19155#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20156#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20280#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 20281#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20352#L696 assume !(1 == ~t8_pc~0); 19472#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19473#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20320#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20341#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 20387#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19891#L715 assume 1 == ~t9_pc~0; 19892#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19562#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19470#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19471#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 19880#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20152#L734 assume !(1 == ~t10_pc~0); 20153#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19372#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19373#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19391#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 20096#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19448#L753 assume 1 == ~t11_pc~0; 19449#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20002#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19557#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19558#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 19707#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19764#L1237 assume !(1 == ~M_E~0); 19765#L1237-2 assume !(1 == ~T1_E~0); 20377#L1242-1 assume !(1 == ~T2_E~0); 19528#L1247-1 assume !(1 == ~T3_E~0); 19529#L1252-1 assume !(1 == ~T4_E~0); 19312#L1257-1 assume !(1 == ~T5_E~0); 19313#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20168#L1267-1 assume !(1 == ~T7_E~0); 20273#L1272-1 assume !(1 == ~T8_E~0); 19611#L1277-1 assume !(1 == ~T9_E~0); 19612#L1282-1 assume !(1 == ~T10_E~0); 20034#L1287-1 assume !(1 == ~T11_E~0); 20035#L1292-1 assume !(1 == ~E_M~0); 19996#L1297-1 assume !(1 == ~E_1~0); 19443#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19444#L1307-1 assume !(1 == ~E_3~0); 20266#L1312-1 assume !(1 == ~E_4~0); 19654#L1317-1 assume !(1 == ~E_5~0); 19655#L1322-1 assume !(1 == ~E_6~0); 19387#L1327-1 assume !(1 == ~E_7~0); 19388#L1332-1 assume !(1 == ~E_8~0); 19946#L1337-1 assume !(1 == ~E_9~0); 19883#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19884#L1347-1 assume !(1 == ~E_11~0); 20265#L1352-1 assume { :end_inline_reset_delta_events } true; 20155#L1678-2 [2021-12-15 17:20:57,340 INFO L793 eck$LassoCheckResult]: Loop: 20155#L1678-2 assume !false; 19938#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19939#L1084 assume !false; 19722#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19723#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19026#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20040#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18952#L925 assume !(0 != eval_~tmp~0#1); 18954#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19068#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19069#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18923#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18924#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19998#L1119-3 assume !(0 == ~T3_E~0); 19999#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20020#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20021#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20199#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20257#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19427#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19428#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19663#L1159-3 assume !(0 == ~T11_E~0); 19664#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19934#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19935#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19985#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19986#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20141#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19818#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19185#L1199-3 assume !(0 == ~E_7~0); 19186#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19409#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18871#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18872#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19570#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19571#L544-39 assume !(1 == ~m_pc~0); 18852#L544-41 is_master_triggered_~__retres1~0#1 := 0; 18853#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19103#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19104#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 19260#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20128#L563-39 assume 1 == ~t1_pc~0; 20134#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19003#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19902#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19903#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20400#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20243#L582-39 assume 1 == ~t2_pc~0; 19326#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19328#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19948#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19949#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19096#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18883#L601-39 assume 1 == ~t3_pc~0; 18884#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18934#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20092#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20228#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20132#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19784#L620-39 assume !(1 == ~t4_pc~0); 19785#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 19982#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20190#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20105#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20106#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20411#L639-39 assume 1 == ~t5_pc~0; 20218#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19532#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19109#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18912#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18913#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19821#L658-39 assume 1 == ~t6_pc~0; 19803#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19804#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18862#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18863#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19978#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19979#L677-39 assume 1 == ~t7_pc~0; 19941#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19087#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19088#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19143#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 19144#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19709#L696-39 assume 1 == ~t8_pc~0; 19674#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19554#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19555#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19850#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19814#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19689#L715-39 assume 1 == ~t9_pc~0; 18888#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18889#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20098#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20412#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20027#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20028#L734-39 assume 1 == ~t10_pc~0; 19953#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19399#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19710#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19041#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19042#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20290#L753-39 assume !(1 == ~t11_pc~0); 18961#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 18962#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20254#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19679#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19680#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19781#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19782#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20052#L1242-3 assume !(1 == ~T2_E~0); 20053#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20272#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19972#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19973#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20255#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20296#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20384#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19113#L1282-3 assume !(1 == ~T10_E~0); 19114#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19023#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19024#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20161#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20162#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20350#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20408#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20074#L1322-3 assume !(1 == ~E_6~0); 20075#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19082#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19057#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19058#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19750#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19878#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19879#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19005#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19270#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19984#L1697 assume !(0 == start_simulation_~tmp~3#1); 19771#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19772#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19129#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19894#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 19895#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19844#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19441#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 19442#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 20155#L1678-2 [2021-12-15 17:20:57,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,340 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2021-12-15 17:20:57,340 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,341 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842851836] [2021-12-15 17:20:57,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,341 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,362 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842851836] [2021-12-15 17:20:57,363 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842851836] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,363 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,363 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,363 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180594249] [2021-12-15 17:20:57,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,364 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1367576821, now seen corresponding path program 1 times [2021-12-15 17:20:57,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628906743] [2021-12-15 17:20:57,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,365 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,392 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628906743] [2021-12-15 17:20:57,392 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [628906743] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,392 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,392 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,392 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386960123] [2021-12-15 17:20:57,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,393 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,393 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,394 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,394 INFO L87 Difference]: Start difference. First operand 1566 states and 2320 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,411 INFO L93 Difference]: Finished difference Result 1566 states and 2319 transitions. [2021-12-15 17:20:57,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2319 transitions. [2021-12-15 17:20:57,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2319 transitions. [2021-12-15 17:20:57,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2319 transitions. [2021-12-15 17:20:57,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,449 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2021-12-15 17:20:57,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2319 transitions. [2021-12-15 17:20:57,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2319 transitions. [2021-12-15 17:20:57,467 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2021-12-15 17:20:57,467 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2021-12-15 17:20:57,468 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:20:57,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2319 transitions. [2021-12-15 17:20:57,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,473 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,473 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,473 INFO L791 eck$LassoCheckResult]: Stem: 22721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23450#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23451#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22224#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22225#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23460#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23425#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23426#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22573#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22574#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22980#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23398#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22485#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22486#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22371#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22372#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23326#L1109 assume !(0 == ~M_E~0); 23347#L1109-2 assume !(0 == ~T1_E~0); 22378#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22379#L1119-1 assume !(0 == ~T3_E~0); 23402#L1124-1 assume !(0 == ~T4_E~0); 22041#L1129-1 assume !(0 == ~T5_E~0); 22042#L1134-1 assume !(0 == ~T6_E~0); 22653#L1139-1 assume !(0 == ~T7_E~0); 23330#L1144-1 assume !(0 == ~T8_E~0); 23202#L1149-1 assume !(0 == ~T9_E~0); 22148#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22149#L1159-1 assume !(0 == ~T11_E~0); 23188#L1164-1 assume !(0 == ~E_M~0); 22539#L1169-1 assume !(0 == ~E_1~0); 22428#L1174-1 assume !(0 == ~E_2~0); 22304#L1179-1 assume !(0 == ~E_3~0); 22228#L1184-1 assume !(0 == ~E_4~0); 22229#L1189-1 assume !(0 == ~E_5~0); 22260#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22349#L1199-1 assume !(0 == ~E_7~0); 23210#L1204-1 assume !(0 == ~E_8~0); 23147#L1209-1 assume !(0 == ~E_9~0); 23148#L1214-1 assume !(0 == ~E_10~0); 23472#L1219-1 assume !(0 == ~E_11~0); 23545#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22558#L544 assume 1 == ~m_pc~0; 22559#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23389#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23219#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22192#L1379 assume !(0 != activate_threads_~tmp~1#1); 22193#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22966#L563 assume !(1 == ~t1_pc~0); 22763#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22049#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22050#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23086#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22045#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22046#L582 assume 1 == ~t2_pc~0; 22741#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23097#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23098#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23201#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22078#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22079#L601 assume !(1 == ~t3_pc~0); 22757#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22756#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23390#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23132#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23133#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23076#L620 assume 1 == ~t4_pc~0; 22059#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22060#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22621#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22622#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 22977#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23164#L639 assume 1 == ~t5_pc~0; 23047#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22351#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22352#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22998#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 22999#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22928#L658 assume !(1 == ~t6_pc~0); 22553#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22554#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23122#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23452#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23136#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22391#L677 assume 1 == ~t7_pc~0; 22392#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22294#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23295#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23419#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23420#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23491#L696 assume !(1 == ~t8_pc~0); 22611#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22612#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23459#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23480#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23526#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23030#L715 assume 1 == ~t9_pc~0; 23031#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22701#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22609#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22610#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23019#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23291#L734 assume !(1 == ~t10_pc~0); 23292#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22511#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22512#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22530#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23235#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22587#L753 assume 1 == ~t11_pc~0; 22588#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23141#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22696#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22697#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 22846#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22903#L1237 assume !(1 == ~M_E~0); 22904#L1237-2 assume !(1 == ~T1_E~0); 23516#L1242-1 assume !(1 == ~T2_E~0); 22667#L1247-1 assume !(1 == ~T3_E~0); 22668#L1252-1 assume !(1 == ~T4_E~0); 22451#L1257-1 assume !(1 == ~T5_E~0); 22452#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23307#L1267-1 assume !(1 == ~T7_E~0); 23412#L1272-1 assume !(1 == ~T8_E~0); 22750#L1277-1 assume !(1 == ~T9_E~0); 22751#L1282-1 assume !(1 == ~T10_E~0); 23173#L1287-1 assume !(1 == ~T11_E~0); 23174#L1292-1 assume !(1 == ~E_M~0); 23135#L1297-1 assume !(1 == ~E_1~0); 22582#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22583#L1307-1 assume !(1 == ~E_3~0); 23405#L1312-1 assume !(1 == ~E_4~0); 22793#L1317-1 assume !(1 == ~E_5~0); 22794#L1322-1 assume !(1 == ~E_6~0); 22526#L1327-1 assume !(1 == ~E_7~0); 22527#L1332-1 assume !(1 == ~E_8~0); 23085#L1337-1 assume !(1 == ~E_9~0); 23022#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23023#L1347-1 assume !(1 == ~E_11~0); 23404#L1352-1 assume { :end_inline_reset_delta_events } true; 23294#L1678-2 [2021-12-15 17:20:57,475 INFO L793 eck$LassoCheckResult]: Loop: 23294#L1678-2 assume !false; 23077#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23078#L1084 assume !false; 22861#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22862#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22165#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23179#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22091#L925 assume !(0 != eval_~tmp~0#1); 22093#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22207#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22208#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22062#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22063#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23137#L1119-3 assume !(0 == ~T3_E~0); 23138#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23159#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23160#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23338#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23396#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22566#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22567#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22802#L1159-3 assume !(0 == ~T11_E~0); 22803#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23073#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23074#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23124#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23125#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23280#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22957#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22324#L1199-3 assume !(0 == ~E_7~0); 22325#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22548#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22010#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22011#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22709#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22710#L544-39 assume !(1 == ~m_pc~0); 21991#L544-41 is_master_triggered_~__retres1~0#1 := 0; 21992#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22242#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22243#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 22399#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23267#L563-39 assume 1 == ~t1_pc~0; 23273#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22142#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23041#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23042#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23539#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23382#L582-39 assume 1 == ~t2_pc~0; 22465#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22467#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23087#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23088#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22235#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22022#L601-39 assume 1 == ~t3_pc~0; 22023#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22073#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23231#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23367#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23271#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22923#L620-39 assume !(1 == ~t4_pc~0); 22924#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 23121#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23329#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23244#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23245#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23550#L639-39 assume 1 == ~t5_pc~0; 23357#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22671#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22248#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22051#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22052#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22960#L658-39 assume !(1 == ~t6_pc~0); 22944#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22943#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22001#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22002#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23117#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23118#L677-39 assume 1 == ~t7_pc~0; 23080#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22226#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22227#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22282#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 22283#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22848#L696-39 assume 1 == ~t8_pc~0; 22813#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22693#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22694#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22989#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22953#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22828#L715-39 assume 1 == ~t9_pc~0; 22027#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22028#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23237#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23551#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23166#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23167#L734-39 assume 1 == ~t10_pc~0; 23092#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22538#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22849#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22180#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22181#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23429#L753-39 assume !(1 == ~t11_pc~0); 22100#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 22101#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23393#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22818#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22819#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22920#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22921#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23191#L1242-3 assume !(1 == ~T2_E~0); 23192#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23411#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23111#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23112#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23394#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23435#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23523#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22252#L1282-3 assume !(1 == ~T10_E~0); 22253#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22162#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22163#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23300#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23301#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23489#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23547#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23213#L1322-3 assume !(1 == ~E_6~0); 23214#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22221#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22196#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22197#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22889#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23017#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23018#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22144#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22409#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23123#L1697 assume !(0 == start_simulation_~tmp~3#1); 22910#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22911#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22268#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23033#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 23034#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22983#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22580#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22581#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23294#L1678-2 [2021-12-15 17:20:57,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,476 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2021-12-15 17:20:57,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,476 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647395774] [2021-12-15 17:20:57,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,477 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,502 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,502 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647395774] [2021-12-15 17:20:57,503 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647395774] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,503 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687981396] [2021-12-15 17:20:57,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,504 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,505 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 2 times [2021-12-15 17:20:57,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476174363] [2021-12-15 17:20:57,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,553 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476174363] [2021-12-15 17:20:57,554 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476174363] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,554 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,554 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,555 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832600005] [2021-12-15 17:20:57,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,555 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,556 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,556 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,556 INFO L87 Difference]: Start difference. First operand 1566 states and 2319 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,574 INFO L93 Difference]: Finished difference Result 1566 states and 2318 transitions. [2021-12-15 17:20:57,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2318 transitions. [2021-12-15 17:20:57,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2318 transitions. [2021-12-15 17:20:57,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2318 transitions. [2021-12-15 17:20:57,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,590 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2021-12-15 17:20:57,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2318 transitions. [2021-12-15 17:20:57,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2318 transitions. [2021-12-15 17:20:57,616 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2021-12-15 17:20:57,616 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2021-12-15 17:20:57,616 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:20:57,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2318 transitions. [2021-12-15 17:20:57,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,621 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,621 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,621 INFO L791 eck$LassoCheckResult]: Stem: 25860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26589#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26590#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25363#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 25364#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26599#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26564#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26565#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25712#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25713#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26119#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26537#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25624#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25625#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25510#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25511#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26463#L1109 assume !(0 == ~M_E~0); 26485#L1109-2 assume !(0 == ~T1_E~0); 25517#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25518#L1119-1 assume !(0 == ~T3_E~0); 26541#L1124-1 assume !(0 == ~T4_E~0); 25180#L1129-1 assume !(0 == ~T5_E~0); 25181#L1134-1 assume !(0 == ~T6_E~0); 25792#L1139-1 assume !(0 == ~T7_E~0); 26469#L1144-1 assume !(0 == ~T8_E~0); 26341#L1149-1 assume !(0 == ~T9_E~0); 25287#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25288#L1159-1 assume !(0 == ~T11_E~0); 26327#L1164-1 assume !(0 == ~E_M~0); 25678#L1169-1 assume !(0 == ~E_1~0); 25567#L1174-1 assume !(0 == ~E_2~0); 25440#L1179-1 assume !(0 == ~E_3~0); 25367#L1184-1 assume !(0 == ~E_4~0); 25368#L1189-1 assume !(0 == ~E_5~0); 25399#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25486#L1199-1 assume !(0 == ~E_7~0); 26349#L1204-1 assume !(0 == ~E_8~0); 26285#L1209-1 assume !(0 == ~E_9~0); 26286#L1214-1 assume !(0 == ~E_10~0); 26611#L1219-1 assume !(0 == ~E_11~0); 26684#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25695#L544 assume 1 == ~m_pc~0; 25696#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26528#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26356#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25329#L1379 assume !(0 != activate_threads_~tmp~1#1); 25330#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26102#L563 assume !(1 == ~t1_pc~0); 25902#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25188#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25189#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26225#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 25184#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25185#L582 assume 1 == ~t2_pc~0; 25880#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26235#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26236#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26340#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 25217#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25218#L601 assume !(1 == ~t3_pc~0); 25896#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25895#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26529#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26271#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 26272#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26215#L620 assume 1 == ~t4_pc~0; 25198#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25199#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25760#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25761#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 26116#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26304#L639 assume 1 == ~t5_pc~0; 26187#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25490#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25491#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26137#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 26138#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26067#L658 assume !(1 == ~t6_pc~0); 25692#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25693#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26262#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26591#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26275#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25530#L677 assume 1 == ~t7_pc~0; 25531#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25433#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26434#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26558#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 26559#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26630#L696 assume !(1 == ~t8_pc~0); 25751#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25752#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26598#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26619#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 26665#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26169#L715 assume 1 == ~t9_pc~0; 26170#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25840#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25748#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25749#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 26158#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26431#L734 assume !(1 == ~t10_pc~0); 26432#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25650#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25651#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25669#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 26374#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25726#L753 assume 1 == ~t11_pc~0; 25727#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26280#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25835#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25836#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 25987#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26042#L1237 assume !(1 == ~M_E~0); 26043#L1237-2 assume !(1 == ~T1_E~0); 26656#L1242-1 assume !(1 == ~T2_E~0); 25806#L1247-1 assume !(1 == ~T3_E~0); 25807#L1252-1 assume !(1 == ~T4_E~0); 25590#L1257-1 assume !(1 == ~T5_E~0); 25591#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26446#L1267-1 assume !(1 == ~T7_E~0); 26551#L1272-1 assume !(1 == ~T8_E~0); 25889#L1277-1 assume !(1 == ~T9_E~0); 25890#L1282-1 assume !(1 == ~T10_E~0); 26312#L1287-1 assume !(1 == ~T11_E~0); 26313#L1292-1 assume !(1 == ~E_M~0); 26274#L1297-1 assume !(1 == ~E_1~0); 25721#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25722#L1307-1 assume !(1 == ~E_3~0); 26544#L1312-1 assume !(1 == ~E_4~0); 25932#L1317-1 assume !(1 == ~E_5~0); 25933#L1322-1 assume !(1 == ~E_6~0); 25665#L1327-1 assume !(1 == ~E_7~0); 25666#L1332-1 assume !(1 == ~E_8~0); 26224#L1337-1 assume !(1 == ~E_9~0); 26161#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26162#L1347-1 assume !(1 == ~E_11~0); 26543#L1352-1 assume { :end_inline_reset_delta_events } true; 26430#L1678-2 [2021-12-15 17:20:57,622 INFO L793 eck$LassoCheckResult]: Loop: 26430#L1678-2 assume !false; 26216#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26217#L1084 assume !false; 26001#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26002#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25304#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26319#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25230#L925 assume !(0 != eval_~tmp~0#1); 25232#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25346#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25347#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25201#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25202#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26276#L1119-3 assume !(0 == ~T3_E~0); 26277#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26298#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26299#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26477#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26535#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25705#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25706#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25942#L1159-3 assume !(0 == ~T11_E~0); 25943#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26212#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26213#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26263#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26264#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26419#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26096#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25466#L1199-3 assume !(0 == ~E_7~0); 25467#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25691#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25152#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25153#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25848#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25849#L544-39 assume !(1 == ~m_pc~0); 25130#L544-41 is_master_triggered_~__retres1~0#1 := 0; 25131#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25381#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25382#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 25538#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26406#L563-39 assume !(1 == ~t1_pc~0); 25283#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 25284#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26180#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26181#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26678#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26521#L582-39 assume 1 == ~t2_pc~0; 25604#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25606#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26226#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26227#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25376#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25161#L601-39 assume 1 == ~t3_pc~0; 25162#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25212#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26370#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26506#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26410#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26064#L620-39 assume !(1 == ~t4_pc~0); 26065#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 26260#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26468#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26383#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26384#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26689#L639-39 assume 1 == ~t5_pc~0; 26496#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25810#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25387#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25190#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25191#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26099#L658-39 assume 1 == ~t6_pc~0; 26081#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26082#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25138#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25139#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26256#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26257#L677-39 assume 1 == ~t7_pc~0; 26219#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25365#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25366#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25421#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 25422#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25986#L696-39 assume 1 == ~t8_pc~0; 25952#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25832#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25833#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26128#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26092#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25967#L715-39 assume 1 == ~t9_pc~0; 25164#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25165#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26376#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26690#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26305#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26306#L734-39 assume 1 == ~t10_pc~0; 26231#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25677#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25988#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25319#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25320#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26568#L753-39 assume !(1 == ~t11_pc~0); 25239#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 25240#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26532#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25957#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25958#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26055#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26056#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26330#L1242-3 assume !(1 == ~T2_E~0); 26331#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26550#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26250#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26251#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26533#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26574#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26662#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25390#L1282-3 assume !(1 == ~T10_E~0); 25391#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25301#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25302#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26438#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26439#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26628#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26686#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26352#L1322-3 assume !(1 == ~E_6~0); 26353#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25360#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25335#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25336#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26028#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26156#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26157#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25278#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25548#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 26261#L1697 assume !(0 == start_simulation_~tmp~3#1); 26049#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26050#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25407#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26172#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 26173#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26122#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25717#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 25718#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 26430#L1678-2 [2021-12-15 17:20:57,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,623 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2021-12-15 17:20:57,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054931621] [2021-12-15 17:20:57,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,623 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054931621] [2021-12-15 17:20:57,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054931621] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,643 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237891600] [2021-12-15 17:20:57,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,644 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,645 INFO L85 PathProgramCache]: Analyzing trace with hash 947803532, now seen corresponding path program 1 times [2021-12-15 17:20:57,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331482640] [2021-12-15 17:20:57,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,645 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,672 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331482640] [2021-12-15 17:20:57,672 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331482640] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,672 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,672 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,673 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465632584] [2021-12-15 17:20:57,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,673 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,673 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,674 INFO L87 Difference]: Start difference. First operand 1566 states and 2318 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,693 INFO L93 Difference]: Finished difference Result 1566 states and 2317 transitions. [2021-12-15 17:20:57,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2317 transitions. [2021-12-15 17:20:57,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2317 transitions. [2021-12-15 17:20:57,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2317 transitions. [2021-12-15 17:20:57,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,707 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2021-12-15 17:20:57,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2317 transitions. [2021-12-15 17:20:57,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2317 transitions. [2021-12-15 17:20:57,738 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2021-12-15 17:20:57,738 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2021-12-15 17:20:57,738 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:20:57,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2317 transitions. [2021-12-15 17:20:57,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,743 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,743 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,744 INFO L791 eck$LassoCheckResult]: Stem: 28999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 29000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29728#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29729#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28502#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28503#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29738#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29703#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29704#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28851#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28852#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29258#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29676#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28763#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28764#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28649#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28650#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29602#L1109 assume !(0 == ~M_E~0); 29624#L1109-2 assume !(0 == ~T1_E~0); 28656#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28657#L1119-1 assume !(0 == ~T3_E~0); 29680#L1124-1 assume !(0 == ~T4_E~0); 28317#L1129-1 assume !(0 == ~T5_E~0); 28318#L1134-1 assume !(0 == ~T6_E~0); 28931#L1139-1 assume !(0 == ~T7_E~0); 29608#L1144-1 assume !(0 == ~T8_E~0); 29480#L1149-1 assume !(0 == ~T9_E~0); 28424#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28425#L1159-1 assume !(0 == ~T11_E~0); 29466#L1164-1 assume !(0 == ~E_M~0); 28817#L1169-1 assume !(0 == ~E_1~0); 28706#L1174-1 assume !(0 == ~E_2~0); 28579#L1179-1 assume !(0 == ~E_3~0); 28506#L1184-1 assume !(0 == ~E_4~0); 28507#L1189-1 assume !(0 == ~E_5~0); 28538#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28625#L1199-1 assume !(0 == ~E_7~0); 29488#L1204-1 assume !(0 == ~E_8~0); 29424#L1209-1 assume !(0 == ~E_9~0); 29425#L1214-1 assume !(0 == ~E_10~0); 29750#L1219-1 assume !(0 == ~E_11~0); 29823#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28834#L544 assume 1 == ~m_pc~0; 28835#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29667#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29495#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28468#L1379 assume !(0 != activate_threads_~tmp~1#1); 28469#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29241#L563 assume !(1 == ~t1_pc~0); 29041#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28327#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28328#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29364#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28323#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28324#L582 assume 1 == ~t2_pc~0; 29019#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29374#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29375#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29479#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28356#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28357#L601 assume !(1 == ~t3_pc~0); 29035#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29034#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29668#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29410#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29411#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29354#L620 assume 1 == ~t4_pc~0; 28337#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28338#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28899#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28900#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29255#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29442#L639 assume 1 == ~t5_pc~0; 29325#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28629#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28630#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29276#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29277#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29206#L658 assume !(1 == ~t6_pc~0); 28831#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28832#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29400#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29730#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29414#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28669#L677 assume 1 == ~t7_pc~0; 28670#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28572#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29573#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29697#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29698#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29769#L696 assume !(1 == ~t8_pc~0); 28889#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28890#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29737#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29758#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 29804#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29308#L715 assume 1 == ~t9_pc~0; 29309#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28979#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28887#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28888#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29297#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29569#L734 assume !(1 == ~t10_pc~0); 29570#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28789#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28790#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28808#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29513#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28865#L753 assume 1 == ~t11_pc~0; 28866#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29419#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28974#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28975#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29124#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29181#L1237 assume !(1 == ~M_E~0); 29182#L1237-2 assume !(1 == ~T1_E~0); 29794#L1242-1 assume !(1 == ~T2_E~0); 28945#L1247-1 assume !(1 == ~T3_E~0); 28946#L1252-1 assume !(1 == ~T4_E~0); 28729#L1257-1 assume !(1 == ~T5_E~0); 28730#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29585#L1267-1 assume !(1 == ~T7_E~0); 29690#L1272-1 assume !(1 == ~T8_E~0); 29028#L1277-1 assume !(1 == ~T9_E~0); 29029#L1282-1 assume !(1 == ~T10_E~0); 29451#L1287-1 assume !(1 == ~T11_E~0); 29452#L1292-1 assume !(1 == ~E_M~0); 29413#L1297-1 assume !(1 == ~E_1~0); 28860#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28861#L1307-1 assume !(1 == ~E_3~0); 29683#L1312-1 assume !(1 == ~E_4~0); 29071#L1317-1 assume !(1 == ~E_5~0); 29072#L1322-1 assume !(1 == ~E_6~0); 28804#L1327-1 assume !(1 == ~E_7~0); 28805#L1332-1 assume !(1 == ~E_8~0); 29363#L1337-1 assume !(1 == ~E_9~0); 29300#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29301#L1347-1 assume !(1 == ~E_11~0); 29682#L1352-1 assume { :end_inline_reset_delta_events } true; 29572#L1678-2 [2021-12-15 17:20:57,744 INFO L793 eck$LassoCheckResult]: Loop: 29572#L1678-2 assume !false; 29355#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29356#L1084 assume !false; 29139#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29140#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28443#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29457#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28369#L925 assume !(0 != eval_~tmp~0#1); 28371#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28485#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28486#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28340#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28341#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29415#L1119-3 assume !(0 == ~T3_E~0); 29416#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29437#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29438#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29616#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29674#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28844#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28845#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29080#L1159-3 assume !(0 == ~T11_E~0); 29081#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29351#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29352#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29402#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29403#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29558#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29235#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28602#L1199-3 assume !(0 == ~E_7~0); 28603#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28826#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28288#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28289#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28987#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28988#L544-39 assume !(1 == ~m_pc~0); 28269#L544-41 is_master_triggered_~__retres1~0#1 := 0; 28270#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28520#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28521#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 28677#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29545#L563-39 assume !(1 == ~t1_pc~0); 28419#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 28420#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29319#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29320#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29817#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29660#L582-39 assume 1 == ~t2_pc~0; 28743#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28745#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29365#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29366#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28513#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28300#L601-39 assume 1 == ~t3_pc~0; 28301#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28351#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29509#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29645#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29549#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29201#L620-39 assume !(1 == ~t4_pc~0); 29202#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 29399#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29607#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29522#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29523#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29828#L639-39 assume 1 == ~t5_pc~0; 29635#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28949#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28526#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28329#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28330#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29238#L658-39 assume 1 == ~t6_pc~0; 29220#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29221#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28279#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28280#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29395#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29396#L677-39 assume !(1 == ~t7_pc~0); 29026#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 28504#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28505#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28560#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 28561#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29126#L696-39 assume 1 == ~t8_pc~0; 29091#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28971#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28972#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29267#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29231#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29106#L715-39 assume 1 == ~t9_pc~0; 28305#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28306#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29515#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29829#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29444#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29445#L734-39 assume 1 == ~t10_pc~0; 29370#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28816#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29127#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28458#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28459#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29707#L753-39 assume !(1 == ~t11_pc~0); 28378#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28379#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29671#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29096#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29097#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29198#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29199#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29469#L1242-3 assume !(1 == ~T2_E~0); 29470#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29689#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29389#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29390#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29672#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29713#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29801#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28530#L1282-3 assume !(1 == ~T10_E~0); 28531#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28440#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28441#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29578#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29579#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29767#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29825#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29491#L1322-3 assume !(1 == ~E_6~0); 29492#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28499#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28474#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28475#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29167#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29295#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29296#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28422#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28687#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 29401#L1697 assume !(0 == start_simulation_~tmp~3#1); 29188#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29189#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28546#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29311#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 29312#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29261#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28858#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28859#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29572#L1678-2 [2021-12-15 17:20:57,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,745 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2021-12-15 17:20:57,745 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36694080] [2021-12-15 17:20:57,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,745 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,767 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36694080] [2021-12-15 17:20:57,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36694080] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,767 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834447194] [2021-12-15 17:20:57,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,768 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1209669491, now seen corresponding path program 1 times [2021-12-15 17:20:57,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888590451] [2021-12-15 17:20:57,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,792 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,792 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888590451] [2021-12-15 17:20:57,793 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888590451] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,793 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,793 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,793 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869400174] [2021-12-15 17:20:57,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,793 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,793 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,794 INFO L87 Difference]: Start difference. First operand 1566 states and 2317 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,813 INFO L93 Difference]: Finished difference Result 1566 states and 2316 transitions. [2021-12-15 17:20:57,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2316 transitions. [2021-12-15 17:20:57,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2316 transitions. [2021-12-15 17:20:57,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,824 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2316 transitions. [2021-12-15 17:20:57,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,825 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2021-12-15 17:20:57,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2316 transitions. [2021-12-15 17:20:57,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2316 transitions. [2021-12-15 17:20:57,843 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2021-12-15 17:20:57,843 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2021-12-15 17:20:57,843 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:20:57,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2316 transitions. [2021-12-15 17:20:57,846 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,848 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,848 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,848 INFO L791 eck$LassoCheckResult]: Stem: 32138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 32139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32867#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32868#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31641#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 31642#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32877#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32842#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32843#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31990#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31991#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32397#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32815#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31902#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31903#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 31788#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31789#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32741#L1109 assume !(0 == ~M_E~0); 32763#L1109-2 assume !(0 == ~T1_E~0); 31795#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31796#L1119-1 assume !(0 == ~T3_E~0); 32819#L1124-1 assume !(0 == ~T4_E~0); 31456#L1129-1 assume !(0 == ~T5_E~0); 31457#L1134-1 assume !(0 == ~T6_E~0); 32070#L1139-1 assume !(0 == ~T7_E~0); 32747#L1144-1 assume !(0 == ~T8_E~0); 32619#L1149-1 assume !(0 == ~T9_E~0); 31563#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31564#L1159-1 assume !(0 == ~T11_E~0); 32605#L1164-1 assume !(0 == ~E_M~0); 31956#L1169-1 assume !(0 == ~E_1~0); 31845#L1174-1 assume !(0 == ~E_2~0); 31718#L1179-1 assume !(0 == ~E_3~0); 31645#L1184-1 assume !(0 == ~E_4~0); 31646#L1189-1 assume !(0 == ~E_5~0); 31677#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 31764#L1199-1 assume !(0 == ~E_7~0); 32627#L1204-1 assume !(0 == ~E_8~0); 32563#L1209-1 assume !(0 == ~E_9~0); 32564#L1214-1 assume !(0 == ~E_10~0); 32889#L1219-1 assume !(0 == ~E_11~0); 32962#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31973#L544 assume 1 == ~m_pc~0; 31974#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32806#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32634#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31607#L1379 assume !(0 != activate_threads_~tmp~1#1); 31608#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32380#L563 assume !(1 == ~t1_pc~0); 32180#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31466#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31467#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32503#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 31462#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31463#L582 assume 1 == ~t2_pc~0; 32158#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32513#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32514#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32618#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 31495#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31496#L601 assume !(1 == ~t3_pc~0); 32174#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32173#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32807#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32549#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 32550#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32493#L620 assume 1 == ~t4_pc~0; 31476#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31477#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32038#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32039#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 32394#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32581#L639 assume 1 == ~t5_pc~0; 32464#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31768#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31769#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32415#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 32416#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32345#L658 assume !(1 == ~t6_pc~0); 31970#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31971#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32539#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32869#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32553#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31808#L677 assume 1 == ~t7_pc~0; 31809#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31711#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32712#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32836#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 32837#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32908#L696 assume !(1 == ~t8_pc~0); 32028#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32029#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32876#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32897#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 32943#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32447#L715 assume 1 == ~t9_pc~0; 32448#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32118#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32026#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32027#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 32436#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32708#L734 assume !(1 == ~t10_pc~0); 32709#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31928#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31929#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31947#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 32652#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32004#L753 assume 1 == ~t11_pc~0; 32005#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32558#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32113#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32114#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 32263#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32320#L1237 assume !(1 == ~M_E~0); 32321#L1237-2 assume !(1 == ~T1_E~0); 32933#L1242-1 assume !(1 == ~T2_E~0); 32084#L1247-1 assume !(1 == ~T3_E~0); 32085#L1252-1 assume !(1 == ~T4_E~0); 31868#L1257-1 assume !(1 == ~T5_E~0); 31869#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32724#L1267-1 assume !(1 == ~T7_E~0); 32829#L1272-1 assume !(1 == ~T8_E~0); 32167#L1277-1 assume !(1 == ~T9_E~0); 32168#L1282-1 assume !(1 == ~T10_E~0); 32590#L1287-1 assume !(1 == ~T11_E~0); 32591#L1292-1 assume !(1 == ~E_M~0); 32552#L1297-1 assume !(1 == ~E_1~0); 31999#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32000#L1307-1 assume !(1 == ~E_3~0); 32822#L1312-1 assume !(1 == ~E_4~0); 32210#L1317-1 assume !(1 == ~E_5~0); 32211#L1322-1 assume !(1 == ~E_6~0); 31943#L1327-1 assume !(1 == ~E_7~0); 31944#L1332-1 assume !(1 == ~E_8~0); 32502#L1337-1 assume !(1 == ~E_9~0); 32439#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32440#L1347-1 assume !(1 == ~E_11~0); 32821#L1352-1 assume { :end_inline_reset_delta_events } true; 32711#L1678-2 [2021-12-15 17:20:57,848 INFO L793 eck$LassoCheckResult]: Loop: 32711#L1678-2 assume !false; 32494#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32495#L1084 assume !false; 32278#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32279#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31582#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32596#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31508#L925 assume !(0 != eval_~tmp~0#1); 31510#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31624#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31625#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31479#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31480#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32554#L1119-3 assume !(0 == ~T3_E~0); 32555#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32576#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32577#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32755#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32813#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31983#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31984#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32219#L1159-3 assume !(0 == ~T11_E~0); 32220#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32490#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32491#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32541#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32542#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32697#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32374#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31741#L1199-3 assume !(0 == ~E_7~0); 31742#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31965#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31427#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31428#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32126#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32127#L544-39 assume !(1 == ~m_pc~0); 31408#L544-41 is_master_triggered_~__retres1~0#1 := 0; 31409#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31659#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31660#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 31816#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32684#L563-39 assume 1 == ~t1_pc~0; 32690#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31559#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32458#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32459#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32956#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32799#L582-39 assume 1 == ~t2_pc~0; 31882#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31884#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32504#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32505#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31652#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31439#L601-39 assume 1 == ~t3_pc~0; 31440#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31490#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32648#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32784#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32688#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32340#L620-39 assume !(1 == ~t4_pc~0); 32341#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 32538#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32746#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32661#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32662#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32967#L639-39 assume 1 == ~t5_pc~0; 32774#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32088#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31665#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31468#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31469#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32377#L658-39 assume 1 == ~t6_pc~0; 32359#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32360#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31418#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31419#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32534#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32535#L677-39 assume 1 == ~t7_pc~0; 32497#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31643#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31644#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31699#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 31700#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32265#L696-39 assume 1 == ~t8_pc~0; 32230#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32110#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32111#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32406#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32370#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32245#L715-39 assume 1 == ~t9_pc~0; 31444#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31445#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32654#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32968#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32583#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32584#L734-39 assume !(1 == ~t10_pc~0); 31954#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 31955#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32266#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31597#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31598#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32846#L753-39 assume !(1 == ~t11_pc~0); 31517#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 31518#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32810#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32235#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32236#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32337#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32338#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32608#L1242-3 assume !(1 == ~T2_E~0); 32609#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32828#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32528#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32529#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32811#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32852#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32940#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31669#L1282-3 assume !(1 == ~T10_E~0); 31670#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31579#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31580#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32717#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32718#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32906#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32964#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32630#L1322-3 assume !(1 == ~E_6~0); 32631#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31638#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31613#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31614#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32306#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32434#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32435#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31561#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31826#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 32540#L1697 assume !(0 == start_simulation_~tmp~3#1); 32327#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32328#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31685#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32450#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 32451#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32400#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31997#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31998#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 32711#L1678-2 [2021-12-15 17:20:57,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,849 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2021-12-15 17:20:57,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854438917] [2021-12-15 17:20:57,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,867 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,867 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854438917] [2021-12-15 17:20:57,867 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854438917] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,868 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,868 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,868 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611363619] [2021-12-15 17:20:57,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,868 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,868 INFO L85 PathProgramCache]: Analyzing trace with hash 100626508, now seen corresponding path program 2 times [2021-12-15 17:20:57,868 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814472853] [2021-12-15 17:20:57,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,869 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,892 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,892 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814472853] [2021-12-15 17:20:57,892 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814472853] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,892 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,892 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,892 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [88861450] [2021-12-15 17:20:57,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,893 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,893 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:57,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:57,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:57,893 INFO L87 Difference]: Start difference. First operand 1566 states and 2316 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:57,911 INFO L93 Difference]: Finished difference Result 1566 states and 2315 transitions. [2021-12-15 17:20:57,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:57,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2315 transitions. [2021-12-15 17:20:57,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2315 transitions. [2021-12-15 17:20:57,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-12-15 17:20:57,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-12-15 17:20:57,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2315 transitions. [2021-12-15 17:20:57,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:57,924 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2021-12-15 17:20:57,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2315 transitions. [2021-12-15 17:20:57,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-12-15 17:20:57,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:57,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2315 transitions. [2021-12-15 17:20:57,941 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2021-12-15 17:20:57,941 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2021-12-15 17:20:57,941 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:20:57,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2315 transitions. [2021-12-15 17:20:57,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-12-15 17:20:57,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:57,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:57,946 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,946 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:57,946 INFO L791 eck$LassoCheckResult]: Stem: 35277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 36006#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36007#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34780#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 34781#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36016#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35981#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35982#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35129#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35130#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35536#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35954#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35041#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35042#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34927#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 34928#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35880#L1109 assume !(0 == ~M_E~0); 35902#L1109-2 assume !(0 == ~T1_E~0); 34934#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34935#L1119-1 assume !(0 == ~T3_E~0); 35958#L1124-1 assume !(0 == ~T4_E~0); 34595#L1129-1 assume !(0 == ~T5_E~0); 34596#L1134-1 assume !(0 == ~T6_E~0); 35209#L1139-1 assume !(0 == ~T7_E~0); 35886#L1144-1 assume !(0 == ~T8_E~0); 35758#L1149-1 assume !(0 == ~T9_E~0); 34702#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34703#L1159-1 assume !(0 == ~T11_E~0); 35744#L1164-1 assume !(0 == ~E_M~0); 35095#L1169-1 assume !(0 == ~E_1~0); 34984#L1174-1 assume !(0 == ~E_2~0); 34857#L1179-1 assume !(0 == ~E_3~0); 34784#L1184-1 assume !(0 == ~E_4~0); 34785#L1189-1 assume !(0 == ~E_5~0); 34816#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 34903#L1199-1 assume !(0 == ~E_7~0); 35766#L1204-1 assume !(0 == ~E_8~0); 35702#L1209-1 assume !(0 == ~E_9~0); 35703#L1214-1 assume !(0 == ~E_10~0); 36028#L1219-1 assume !(0 == ~E_11~0); 36101#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35112#L544 assume 1 == ~m_pc~0; 35113#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35945#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35773#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34746#L1379 assume !(0 != activate_threads_~tmp~1#1); 34747#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35519#L563 assume !(1 == ~t1_pc~0); 35319#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34605#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34606#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35642#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34601#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34602#L582 assume 1 == ~t2_pc~0; 35297#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35652#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35653#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35757#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34634#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34635#L601 assume !(1 == ~t3_pc~0); 35313#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35312#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35946#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35688#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35689#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35632#L620 assume 1 == ~t4_pc~0; 34615#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34616#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35177#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35178#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35533#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35720#L639 assume 1 == ~t5_pc~0; 35603#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34907#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34908#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35554#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35555#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35484#L658 assume !(1 == ~t6_pc~0); 35109#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35110#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35678#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36008#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35692#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34947#L677 assume 1 == ~t7_pc~0; 34948#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34850#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35851#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35975#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 35976#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36047#L696 assume !(1 == ~t8_pc~0); 35167#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35168#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36015#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36036#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36082#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35586#L715 assume 1 == ~t9_pc~0; 35587#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35257#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35165#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35166#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35575#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35847#L734 assume !(1 == ~t10_pc~0); 35848#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35067#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35068#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35086#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 35791#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35143#L753 assume 1 == ~t11_pc~0; 35144#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35697#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35252#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35253#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35402#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35459#L1237 assume !(1 == ~M_E~0); 35460#L1237-2 assume !(1 == ~T1_E~0); 36072#L1242-1 assume !(1 == ~T2_E~0); 35223#L1247-1 assume !(1 == ~T3_E~0); 35224#L1252-1 assume !(1 == ~T4_E~0); 35007#L1257-1 assume !(1 == ~T5_E~0); 35008#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35863#L1267-1 assume !(1 == ~T7_E~0); 35968#L1272-1 assume !(1 == ~T8_E~0); 35306#L1277-1 assume !(1 == ~T9_E~0); 35307#L1282-1 assume !(1 == ~T10_E~0); 35729#L1287-1 assume !(1 == ~T11_E~0); 35730#L1292-1 assume !(1 == ~E_M~0); 35691#L1297-1 assume !(1 == ~E_1~0); 35138#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35139#L1307-1 assume !(1 == ~E_3~0); 35961#L1312-1 assume !(1 == ~E_4~0); 35349#L1317-1 assume !(1 == ~E_5~0); 35350#L1322-1 assume !(1 == ~E_6~0); 35082#L1327-1 assume !(1 == ~E_7~0); 35083#L1332-1 assume !(1 == ~E_8~0); 35641#L1337-1 assume !(1 == ~E_9~0); 35578#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35579#L1347-1 assume !(1 == ~E_11~0); 35960#L1352-1 assume { :end_inline_reset_delta_events } true; 35850#L1678-2 [2021-12-15 17:20:57,946 INFO L793 eck$LassoCheckResult]: Loop: 35850#L1678-2 assume !false; 35633#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35634#L1084 assume !false; 35417#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35418#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34721#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35735#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34647#L925 assume !(0 != eval_~tmp~0#1); 34649#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34763#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34764#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34618#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34619#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35693#L1119-3 assume !(0 == ~T3_E~0); 35694#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35715#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35716#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35894#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35952#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35122#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35123#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35358#L1159-3 assume !(0 == ~T11_E~0); 35359#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35629#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35630#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35680#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35681#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35836#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35513#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34880#L1199-3 assume !(0 == ~E_7~0); 34881#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35104#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34566#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34567#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35265#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35266#L544-39 assume !(1 == ~m_pc~0); 34547#L544-41 is_master_triggered_~__retres1~0#1 := 0; 34548#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34798#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34799#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 34955#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35823#L563-39 assume 1 == ~t1_pc~0; 35829#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34698#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35597#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35598#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36095#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35938#L582-39 assume 1 == ~t2_pc~0; 35021#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35023#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35643#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35644#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34791#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34578#L601-39 assume 1 == ~t3_pc~0; 34579#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34629#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35787#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35923#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35827#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35479#L620-39 assume !(1 == ~t4_pc~0); 35480#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 35677#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35885#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35800#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35801#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36106#L639-39 assume 1 == ~t5_pc~0; 35913#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35227#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34804#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34607#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34608#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35516#L658-39 assume 1 == ~t6_pc~0; 35498#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35499#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34557#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34558#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35673#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35674#L677-39 assume 1 == ~t7_pc~0; 35636#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34782#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34783#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34838#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 34839#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35404#L696-39 assume 1 == ~t8_pc~0; 35369#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35249#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35250#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35545#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35509#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35384#L715-39 assume 1 == ~t9_pc~0; 34583#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34584#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35793#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36107#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35722#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35723#L734-39 assume 1 == ~t10_pc~0; 35648#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35094#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35405#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34736#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34737#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35985#L753-39 assume !(1 == ~t11_pc~0); 34656#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34657#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35949#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35374#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35375#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35476#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35477#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35747#L1242-3 assume !(1 == ~T2_E~0); 35748#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35967#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35667#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35668#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35950#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35991#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36079#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34808#L1282-3 assume !(1 == ~T10_E~0); 34809#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34718#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34719#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35856#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35857#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36045#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36103#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35769#L1322-3 assume !(1 == ~E_6~0); 35770#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34777#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34752#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34753#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35445#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35573#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35574#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34700#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34965#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 35679#L1697 assume !(0 == start_simulation_~tmp~3#1); 35466#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35467#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34824#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35589#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 35590#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35539#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35136#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 35137#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 35850#L1678-2 [2021-12-15 17:20:57,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,947 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2021-12-15 17:20:57,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178117780] [2021-12-15 17:20:57,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,973 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,973 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178117780] [2021-12-15 17:20:57,973 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178117780] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,973 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,973 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295850819] [2021-12-15 17:20:57,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,974 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:57,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:57,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1367576821, now seen corresponding path program 2 times [2021-12-15 17:20:57,974 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:57,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750514542] [2021-12-15 17:20:57,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:57,975 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:57,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:57,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:57,998 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:57,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [750514542] [2021-12-15 17:20:57,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [750514542] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:57,999 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:57,999 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:57,999 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941695900] [2021-12-15 17:20:57,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:57,999 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:57,999 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:58,000 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:58,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:58,000 INFO L87 Difference]: Start difference. First operand 1566 states and 2315 transitions. cyclomatic complexity: 750 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:58,070 INFO L93 Difference]: Finished difference Result 2895 states and 4265 transitions. [2021-12-15 17:20:58,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:58,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2895 states and 4265 transitions. [2021-12-15 17:20:58,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2021-12-15 17:20:58,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2895 states to 2895 states and 4265 transitions. [2021-12-15 17:20:58,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2895 [2021-12-15 17:20:58,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2895 [2021-12-15 17:20:58,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2895 states and 4265 transitions. [2021-12-15 17:20:58,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:58,092 INFO L681 BuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2021-12-15 17:20:58,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2895 states and 4265 transitions. [2021-12-15 17:20:58,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2895 to 2895. [2021-12-15 17:20:58,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2895 states to 2895 states and 4265 transitions. [2021-12-15 17:20:58,127 INFO L704 BuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2021-12-15 17:20:58,127 INFO L587 BuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2021-12-15 17:20:58,127 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:20:58,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2895 states and 4265 transitions. [2021-12-15 17:20:58,133 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2021-12-15 17:20:58,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:58,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:58,134 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,134 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,134 INFO L791 eck$LassoCheckResult]: Stem: 39748#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40512#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40513#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39251#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 39252#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40525#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40484#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40485#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39600#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39601#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40013#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40455#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39512#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39513#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39398#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39399#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40378#L1109 assume !(0 == ~M_E~0); 40400#L1109-2 assume !(0 == ~T1_E~0); 39405#L1114-1 assume !(0 == ~T2_E~0); 39406#L1119-1 assume !(0 == ~T3_E~0); 40459#L1124-1 assume !(0 == ~T4_E~0); 39068#L1129-1 assume !(0 == ~T5_E~0); 39069#L1134-1 assume !(0 == ~T6_E~0); 39680#L1139-1 assume !(0 == ~T7_E~0); 40383#L1144-1 assume !(0 == ~T8_E~0); 40243#L1149-1 assume !(0 == ~T9_E~0); 39175#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39176#L1159-1 assume !(0 == ~T11_E~0); 40227#L1164-1 assume !(0 == ~E_M~0); 39566#L1169-1 assume !(0 == ~E_1~0); 39455#L1174-1 assume !(0 == ~E_2~0); 39328#L1179-1 assume !(0 == ~E_3~0); 39255#L1184-1 assume !(0 == ~E_4~0); 39256#L1189-1 assume !(0 == ~E_5~0); 39287#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39376#L1199-1 assume !(0 == ~E_7~0); 40251#L1204-1 assume !(0 == ~E_8~0); 40185#L1209-1 assume !(0 == ~E_9~0); 40186#L1214-1 assume !(0 == ~E_10~0); 40539#L1219-1 assume !(0 == ~E_11~0); 40626#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39585#L544 assume 1 == ~m_pc~0; 39586#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40446#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40260#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39217#L1379 assume !(0 != activate_threads_~tmp~1#1); 39218#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39999#L563 assume !(1 == ~t1_pc~0); 39791#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39076#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39077#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40121#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 39072#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39073#L582 assume 1 == ~t2_pc~0; 39769#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40131#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40132#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40242#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 39105#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39106#L601 assume !(1 == ~t3_pc~0); 39785#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39784#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40447#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40167#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 40168#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40111#L620 assume 1 == ~t4_pc~0; 39086#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39087#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39648#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39649#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 40010#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40203#L639 assume 1 == ~t5_pc~0; 40082#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39378#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39379#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40032#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 40033#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39961#L658 assume !(1 == ~t6_pc~0); 39580#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39581#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40158#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40515#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40174#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39420#L677 assume 1 == ~t7_pc~0; 39421#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39324#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40344#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40477#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 40478#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40562#L696 assume !(1 == ~t8_pc~0); 39639#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39640#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40524#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40547#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 40601#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40064#L715 assume 1 == ~t9_pc~0; 40065#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39728#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39636#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39637#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 40053#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40341#L734 assume !(1 == ~t10_pc~0); 40342#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39538#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39539#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39557#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 40277#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39614#L753 assume 1 == ~t11_pc~0; 39615#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40179#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39723#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39724#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 39878#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39936#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 39937#L1237-2 assume !(1 == ~T1_E~0); 40591#L1242-1 assume !(1 == ~T2_E~0); 39694#L1247-1 assume !(1 == ~T3_E~0); 39695#L1252-1 assume !(1 == ~T4_E~0); 39478#L1257-1 assume !(1 == ~T5_E~0); 39479#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40359#L1267-1 assume !(1 == ~T7_E~0); 40470#L1272-1 assume !(1 == ~T8_E~0); 39778#L1277-1 assume !(1 == ~T9_E~0); 39779#L1282-1 assume !(1 == ~T10_E~0); 40211#L1287-1 assume !(1 == ~T11_E~0); 40212#L1292-1 assume !(1 == ~E_M~0); 40172#L1297-1 assume !(1 == ~E_1~0); 40173#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 40462#L1307-1 assume !(1 == ~E_3~0); 40463#L1312-1 assume !(1 == ~E_4~0); 39821#L1317-1 assume !(1 == ~E_5~0); 39822#L1322-1 assume !(1 == ~E_6~0); 39553#L1327-1 assume !(1 == ~E_7~0); 39554#L1332-1 assume !(1 == ~E_8~0); 40120#L1337-1 assume !(1 == ~E_9~0); 40056#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40057#L1347-1 assume !(1 == ~E_11~0); 40566#L1352-1 assume { :end_inline_reset_delta_events } true; 40658#L1678-2 [2021-12-15 17:20:58,135 INFO L793 eck$LassoCheckResult]: Loop: 40658#L1678-2 assume !false; 40656#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40653#L1084 assume !false; 40652#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40558#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39192#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40614#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40638#L925 assume !(0 != eval_~tmp~0#1); 40637#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40636#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40635#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39089#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39090#L1114-3 assume !(0 == ~T2_E~0); 40175#L1119-3 assume !(0 == ~T3_E~0); 40176#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40197#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40198#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40392#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40453#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39593#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39594#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39832#L1159-3 assume !(0 == ~T11_E~0); 39833#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40108#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40109#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40159#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40160#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40328#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39990#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39351#L1199-3 assume !(0 == ~E_7~0); 39352#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39575#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39037#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39038#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39736#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39737#L544-39 assume 1 == ~m_pc~0; 40097#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39016#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39267#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39268#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 39426#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40309#L563-39 assume !(1 == ~t1_pc~0); 39168#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 39169#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40075#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40076#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40619#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40439#L582-39 assume 1 == ~t2_pc~0; 39492#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39494#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40122#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40123#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39262#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39049#L601-39 assume 1 == ~t3_pc~0; 39050#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39100#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40273#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40422#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40314#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39956#L620-39 assume !(1 == ~t4_pc~0); 39957#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 40156#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40381#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40286#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40287#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40631#L639-39 assume 1 == ~t5_pc~0; 40411#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39698#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39275#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39078#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39079#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39993#L658-39 assume 1 == ~t6_pc~0; 39975#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39976#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39028#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39029#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40152#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40153#L677-39 assume !(1 == ~t7_pc~0); 39776#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 39253#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39254#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41232#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 41230#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41228#L696-39 assume 1 == ~t8_pc~0; 41225#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41223#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41220#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41218#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41217#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41216#L715-39 assume !(1 == ~t9_pc~0); 39056#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 39055#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40279#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40634#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40204#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40205#L734-39 assume 1 == ~t10_pc~0; 41201#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41199#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41196#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41194#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41192#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41190#L753-39 assume !(1 == ~t11_pc~0); 41187#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 41185#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41182#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41180#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41178#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41176#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39953#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41173#L1242-3 assume !(1 == ~T2_E~0); 40232#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41169#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41167#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41165#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41163#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41162#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41161#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41160#L1282-3 assume !(1 == ~T10_E~0); 41159#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41158#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41157#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41156#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41155#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41154#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41153#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41152#L1322-3 assume !(1 == ~E_6~0); 41151#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41150#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41149#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41148#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41147#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41146#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41136#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41133#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41132#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41131#L1697 assume !(0 == start_simulation_~tmp~3#1); 40431#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41127#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41118#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40067#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 40068#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40723#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39607#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 39608#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 40658#L1678-2 [2021-12-15 17:20:58,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2021-12-15 17:20:58,135 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134199703] [2021-12-15 17:20:58,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,135 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:58,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:58,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:58,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134199703] [2021-12-15 17:20:58,156 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134199703] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:58,156 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:58,156 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:58,156 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774027013] [2021-12-15 17:20:58,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:58,157 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:58,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,157 INFO L85 PathProgramCache]: Analyzing trace with hash -1064371189, now seen corresponding path program 1 times [2021-12-15 17:20:58,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37893802] [2021-12-15 17:20:58,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,157 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:58,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:58,208 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:58,208 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37893802] [2021-12-15 17:20:58,208 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37893802] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:58,208 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:58,209 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:58,209 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208044979] [2021-12-15 17:20:58,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:58,209 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:58,210 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:58,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:58,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:58,210 INFO L87 Difference]: Start difference. First operand 2895 states and 4265 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:58,284 INFO L93 Difference]: Finished difference Result 5541 states and 8142 transitions. [2021-12-15 17:20:58,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:58,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5541 states and 8142 transitions. [2021-12-15 17:20:58,303 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2021-12-15 17:20:58,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5541 states to 5541 states and 8142 transitions. [2021-12-15 17:20:58,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5541 [2021-12-15 17:20:58,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5541 [2021-12-15 17:20:58,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5541 states and 8142 transitions. [2021-12-15 17:20:58,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:58,332 INFO L681 BuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2021-12-15 17:20:58,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5541 states and 8142 transitions. [2021-12-15 17:20:58,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5541 to 5541. [2021-12-15 17:20:58,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5541 states to 5541 states and 8142 transitions. [2021-12-15 17:20:58,408 INFO L704 BuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2021-12-15 17:20:58,408 INFO L587 BuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2021-12-15 17:20:58,408 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:20:58,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5541 states and 8142 transitions. [2021-12-15 17:20:58,423 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2021-12-15 17:20:58,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:58,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:58,424 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,424 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,425 INFO L791 eck$LassoCheckResult]: Stem: 48203#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 49012#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49013#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47697#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 47698#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49024#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48977#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48978#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48052#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48053#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48470#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48941#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47962#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47963#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47848#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47849#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48849#L1109 assume !(0 == ~M_E~0); 48875#L1109-2 assume !(0 == ~T1_E~0); 47855#L1114-1 assume !(0 == ~T2_E~0); 47856#L1119-1 assume !(0 == ~T3_E~0); 48947#L1124-1 assume !(0 == ~T4_E~0); 47512#L1129-1 assume !(0 == ~T5_E~0); 47513#L1134-1 assume !(0 == ~T6_E~0); 48135#L1139-1 assume !(0 == ~T7_E~0); 48857#L1144-1 assume !(0 == ~T8_E~0); 48714#L1149-1 assume !(0 == ~T9_E~0); 47619#L1154-1 assume !(0 == ~T10_E~0); 47620#L1159-1 assume !(0 == ~T11_E~0); 48699#L1164-1 assume !(0 == ~E_M~0); 48016#L1169-1 assume !(0 == ~E_1~0); 47905#L1174-1 assume !(0 == ~E_2~0); 47776#L1179-1 assume !(0 == ~E_3~0); 47701#L1184-1 assume !(0 == ~E_4~0); 47702#L1189-1 assume !(0 == ~E_5~0); 47734#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 47823#L1199-1 assume !(0 == ~E_7~0); 48722#L1204-1 assume !(0 == ~E_8~0); 48655#L1209-1 assume !(0 == ~E_9~0); 48656#L1214-1 assume !(0 == ~E_10~0); 49039#L1219-1 assume !(0 == ~E_11~0); 49149#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48033#L544 assume 1 == ~m_pc~0; 48034#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48931#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48730#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47663#L1379 assume !(0 != activate_threads_~tmp~1#1); 47664#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48452#L563 assume !(1 == ~t1_pc~0); 48245#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47522#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47523#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48586#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 47518#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47519#L582 assume 1 == ~t2_pc~0; 48223#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48598#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48599#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48713#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 47551#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47552#L601 assume !(1 == ~t3_pc~0); 48239#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48238#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48932#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48636#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 48637#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48576#L620 assume 1 == ~t4_pc~0; 47532#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47533#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48100#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48101#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 48467#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48673#L639 assume 1 == ~t5_pc~0; 48545#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47827#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47828#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48489#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 48490#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48415#L658 assume !(1 == ~t6_pc~0); 48030#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48031#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48626#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49014#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48640#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47868#L677 assume 1 == ~t7_pc~0; 47869#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47768#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48816#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48969#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 48970#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49061#L696 assume !(1 == ~t8_pc~0); 48090#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48091#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49023#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49048#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 49118#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48524#L715 assume 1 == ~t9_pc~0; 48525#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48183#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48088#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48089#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 48510#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48811#L734 assume !(1 == ~t10_pc~0); 48812#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47988#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47989#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48007#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 48748#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48066#L753 assume 1 == ~t11_pc~0; 48067#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48648#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48178#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48179#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 48328#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48388#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 48389#L1237-2 assume !(1 == ~T1_E~0); 49098#L1242-1 assume !(1 == ~T2_E~0); 49139#L1247-1 assume !(1 == ~T3_E~0); 48966#L1252-1 assume !(1 == ~T4_E~0); 48967#L1257-1 assume !(1 == ~T5_E~0); 49490#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49488#L1267-1 assume !(1 == ~T7_E~0); 49486#L1272-1 assume !(1 == ~T8_E~0); 49451#L1277-1 assume !(1 == ~T9_E~0); 49449#L1282-1 assume !(1 == ~T10_E~0); 49445#L1287-1 assume !(1 == ~T11_E~0); 49443#L1292-1 assume !(1 == ~E_M~0); 49408#L1297-1 assume !(1 == ~E_1~0); 49365#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49326#L1307-1 assume !(1 == ~E_3~0); 49321#L1312-1 assume !(1 == ~E_4~0); 49303#L1317-1 assume !(1 == ~E_5~0); 49286#L1322-1 assume !(1 == ~E_6~0); 49273#L1327-1 assume !(1 == ~E_7~0); 49253#L1332-1 assume !(1 == ~E_8~0); 49232#L1337-1 assume !(1 == ~E_9~0); 49230#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49216#L1347-1 assume !(1 == ~E_11~0); 49207#L1352-1 assume { :end_inline_reset_delta_events } true; 49199#L1678-2 [2021-12-15 17:20:58,425 INFO L793 eck$LassoCheckResult]: Loop: 49199#L1678-2 assume !false; 49192#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49189#L1084 assume !false; 49188#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49178#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49175#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49174#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49172#L925 assume !(0 != eval_~tmp~0#1); 49171#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49170#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49168#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49169#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50494#L1114-3 assume !(0 == ~T2_E~0); 50493#L1119-3 assume !(0 == ~T3_E~0); 50492#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50491#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50490#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50489#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50488#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50487#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50486#L1154-3 assume !(0 == ~T10_E~0); 50485#L1159-3 assume !(0 == ~T11_E~0); 50484#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50483#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50482#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50480#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50478#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50477#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50473#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50474#L1199-3 assume !(0 == ~E_7~0); 52124#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 52122#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50464#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50463#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50462#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48564#L544-39 assume 1 == ~m_pc~0; 48565#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47465#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47715#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47716#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 47876#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48784#L563-39 assume 1 == ~t1_pc~0; 49107#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51761#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48538#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48539#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49140#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49143#L582-39 assume 1 == ~t2_pc~0; 47942#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47944#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48693#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48882#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48883#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50255#L601-39 assume 1 == ~t3_pc~0; 50252#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50250#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50248#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50246#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50244#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48410#L620-39 assume !(1 == ~t4_pc~0); 48411#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 48625#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50048#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50045#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50043#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50001#L639-39 assume 1 == ~t5_pc~0; 49997#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49995#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49993#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49949#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49947#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49945#L658-39 assume !(1 == ~t6_pc~0); 49942#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 49900#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49897#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49895#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49893#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49854#L677-39 assume 1 == ~t7_pc~0; 49809#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49807#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49773#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49771#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 49770#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49710#L696-39 assume 1 == ~t8_pc~0; 49707#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49705#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49702#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49700#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49698#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49697#L715-39 assume !(1 == ~t9_pc~0); 49696#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 49694#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49693#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49692#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49691#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49690#L734-39 assume 1 == ~t10_pc~0; 49688#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49687#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49684#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49682#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49680#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49678#L753-39 assume !(1 == ~t11_pc~0); 47573#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 47574#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48935#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49584#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49582#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49580#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48407#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49578#L1242-3 assume !(1 == ~T2_E~0); 48704#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49575#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49537#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49535#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49533#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49502#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49499#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49461#L1282-3 assume !(1 == ~T10_E~0); 49423#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49391#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49388#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49386#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49385#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49384#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49383#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49382#L1322-3 assume !(1 == ~E_6~0); 49381#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49380#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49379#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49378#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49377#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49375#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49338#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49335#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49333#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49331#L1697 assume !(0 == start_simulation_~tmp~3#1); 48910#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49282#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49272#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49252#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 49231#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49229#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49215#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49206#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 49199#L1678-2 [2021-12-15 17:20:58,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,425 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2021-12-15 17:20:58,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649718470] [2021-12-15 17:20:58,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:58,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:58,448 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:58,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [649718470] [2021-12-15 17:20:58,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [649718470] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:58,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:58,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:58,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379835491] [2021-12-15 17:20:58,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:58,448 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:58,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,449 INFO L85 PathProgramCache]: Analyzing trace with hash 1856747400, now seen corresponding path program 1 times [2021-12-15 17:20:58,449 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715270436] [2021-12-15 17:20:58,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,449 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:58,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:58,472 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:58,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715270436] [2021-12-15 17:20:58,472 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715270436] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:58,472 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:58,472 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:58,472 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353716870] [2021-12-15 17:20:58,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:58,473 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:58,473 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:58,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:58,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:58,474 INFO L87 Difference]: Start difference. First operand 5541 states and 8142 transitions. cyclomatic complexity: 2605 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:58,606 INFO L93 Difference]: Finished difference Result 10453 states and 15329 transitions. [2021-12-15 17:20:58,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:20:58,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10453 states and 15329 transitions. [2021-12-15 17:20:58,646 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2021-12-15 17:20:58,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10453 states to 10453 states and 15329 transitions. [2021-12-15 17:20:58,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10453 [2021-12-15 17:20:58,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10453 [2021-12-15 17:20:58,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10453 states and 15329 transitions. [2021-12-15 17:20:58,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:58,695 INFO L681 BuchiCegarLoop]: Abstraction has 10453 states and 15329 transitions. [2021-12-15 17:20:58,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10453 states and 15329 transitions. [2021-12-15 17:20:58,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10453 to 10449. [2021-12-15 17:20:58,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:58,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10449 states to 10449 states and 15325 transitions. [2021-12-15 17:20:58,909 INFO L704 BuchiCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2021-12-15 17:20:58,909 INFO L587 BuchiCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2021-12-15 17:20:58,909 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:20:58,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10449 states and 15325 transitions. [2021-12-15 17:20:58,934 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2021-12-15 17:20:58,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:58,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:58,936 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,936 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:58,936 INFO L791 eck$LassoCheckResult]: Stem: 64200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 64959#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64960#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63701#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 63702#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64969#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64933#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64934#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64052#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64053#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64465#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64897#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63963#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63964#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63849#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63850#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64820#L1109 assume !(0 == ~M_E~0); 64843#L1109-2 assume !(0 == ~T1_E~0); 63856#L1114-1 assume !(0 == ~T2_E~0); 63857#L1119-1 assume !(0 == ~T3_E~0); 64901#L1124-1 assume !(0 == ~T4_E~0); 63516#L1129-1 assume !(0 == ~T5_E~0); 63517#L1134-1 assume !(0 == ~T6_E~0); 64132#L1139-1 assume !(0 == ~T7_E~0); 64826#L1144-1 assume !(0 == ~T8_E~0); 64694#L1149-1 assume !(0 == ~T9_E~0); 63623#L1154-1 assume !(0 == ~T10_E~0); 63624#L1159-1 assume !(0 == ~T11_E~0); 64679#L1164-1 assume !(0 == ~E_M~0); 64017#L1169-1 assume !(0 == ~E_1~0); 63906#L1174-1 assume !(0 == ~E_2~0); 63779#L1179-1 assume !(0 == ~E_3~0); 63705#L1184-1 assume !(0 == ~E_4~0); 63706#L1189-1 assume !(0 == ~E_5~0); 63738#L1194-1 assume !(0 == ~E_6~0); 63825#L1199-1 assume !(0 == ~E_7~0); 64702#L1204-1 assume !(0 == ~E_8~0); 64636#L1209-1 assume !(0 == ~E_9~0); 64637#L1214-1 assume !(0 == ~E_10~0); 64982#L1219-1 assume !(0 == ~E_11~0); 65076#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64035#L544 assume 1 == ~m_pc~0; 64036#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64888#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64710#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63667#L1379 assume !(0 != activate_threads_~tmp~1#1); 63668#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64448#L563 assume !(1 == ~t1_pc~0); 64243#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63526#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63527#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64575#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 63522#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63523#L582 assume 1 == ~t2_pc~0; 64221#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64586#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64587#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64693#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 63555#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63556#L601 assume !(1 == ~t3_pc~0); 64237#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64236#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64889#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64622#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 64623#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64565#L620 assume 1 == ~t4_pc~0; 63536#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63537#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64100#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64101#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 64462#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64654#L639 assume 1 == ~t5_pc~0; 64535#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63829#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63830#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64483#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 64484#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64413#L658 assume !(1 == ~t6_pc~0); 64032#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64033#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64612#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64961#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64626#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63869#L677 assume 1 == ~t7_pc~0; 63870#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63772#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64790#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64926#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 64927#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65004#L696 assume !(1 == ~t8_pc~0); 64090#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64091#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64968#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64990#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 65045#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64518#L715 assume 1 == ~t9_pc~0; 64519#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64180#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64088#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64089#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 64504#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64786#L734 assume !(1 == ~t10_pc~0); 64787#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 63989#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63990#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64008#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 64728#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64066#L753 assume 1 == ~t11_pc~0; 64067#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64631#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64175#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64176#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 64327#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64386#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 64387#L1237-2 assume !(1 == ~T1_E~0); 65058#L1242-1 assume !(1 == ~T2_E~0); 64146#L1247-1 assume !(1 == ~T3_E~0); 64147#L1252-1 assume !(1 == ~T4_E~0); 65493#L1257-1 assume !(1 == ~T5_E~0); 65491#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65489#L1267-1 assume !(1 == ~T7_E~0); 65442#L1272-1 assume !(1 == ~T8_E~0); 65439#L1277-1 assume !(1 == ~T9_E~0); 65384#L1282-1 assume !(1 == ~T10_E~0); 65332#L1287-1 assume !(1 == ~T11_E~0); 65293#L1292-1 assume !(1 == ~E_M~0); 65291#L1297-1 assume !(1 == ~E_1~0); 65251#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65249#L1307-1 assume !(1 == ~E_3~0); 65213#L1312-1 assume !(1 == ~E_4~0); 65211#L1317-1 assume !(1 == ~E_5~0); 65210#L1322-1 assume !(1 == ~E_6~0); 65181#L1327-1 assume !(1 == ~E_7~0); 65177#L1332-1 assume !(1 == ~E_8~0); 65176#L1337-1 assume !(1 == ~E_9~0); 65155#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65137#L1347-1 assume !(1 == ~E_11~0); 65128#L1352-1 assume { :end_inline_reset_delta_events } true; 65120#L1678-2 [2021-12-15 17:20:58,937 INFO L793 eck$LassoCheckResult]: Loop: 65120#L1678-2 assume !false; 65113#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65110#L1084 assume !false; 65109#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65099#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65096#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65095#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65093#L925 assume !(0 != eval_~tmp~0#1); 65092#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65091#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65089#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65090#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67577#L1114-3 assume !(0 == ~T2_E~0); 67576#L1119-3 assume !(0 == ~T3_E~0); 67574#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67572#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67570#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67221#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67219#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67217#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67215#L1154-3 assume !(0 == ~T10_E~0); 67213#L1159-3 assume !(0 == ~T11_E~0); 67211#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67209#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67207#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67205#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67203#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67201#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67198#L1194-3 assume !(0 == ~E_6~0); 67196#L1199-3 assume !(0 == ~E_7~0); 67194#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67192#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67190#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67188#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67185#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67183#L544-39 assume !(1 == ~m_pc~0); 67181#L544-41 is_master_triggered_~__retres1~0#1 := 0; 67179#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67177#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67174#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 66609#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66607#L563-39 assume !(1 == ~t1_pc~0); 66605#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 66603#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66602#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66599#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66597#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66595#L582-39 assume 1 == ~t2_pc~0; 66593#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66590#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66588#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66585#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66583#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66581#L601-39 assume !(1 == ~t3_pc~0); 66579#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 66577#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66576#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66575#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66573#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66571#L620-39 assume 1 == ~t4_pc~0; 66569#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66566#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66564#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64737#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64738#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65087#L639-39 assume 1 == ~t5_pc~0; 64854#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64150#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63725#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63528#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63529#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64445#L658-39 assume 1 == ~t6_pc~0; 64427#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64428#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63478#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63479#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64607#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64608#L677-39 assume !(1 == ~t7_pc~0); 64228#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 63703#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63704#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63760#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 63761#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64331#L696-39 assume 1 == ~t8_pc~0; 64293#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64172#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64173#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64474#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64438#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64309#L715-39 assume 1 == ~t9_pc~0; 63504#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63505#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64730#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65088#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64656#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64657#L734-39 assume 1 == ~t10_pc~0; 64582#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64016#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64332#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63657#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63658#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64937#L753-39 assume !(1 == ~t11_pc~0); 63577#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 63578#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64892#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64299#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64300#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65767#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64405#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65672#L1242-3 assume !(1 == ~T2_E~0); 64684#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65616#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65549#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65547#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65545#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65495#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65494#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65448#L1282-3 assume !(1 == ~T10_E~0); 65397#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65395#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65393#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65353#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65351#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65349#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65347#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65342#L1322-3 assume !(1 == ~E_6~0); 65341#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65340#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65339#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65338#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65337#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65336#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65301#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65297#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65273#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 65272#L1697 assume !(0 == start_simulation_~tmp~3#1); 64872#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65240#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65200#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65198#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 65175#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65154#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65136#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65127#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 65120#L1678-2 [2021-12-15 17:20:58,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,937 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2021-12-15 17:20:58,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973337189] [2021-12-15 17:20:58,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,937 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:58,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:58,960 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:58,960 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973337189] [2021-12-15 17:20:58,960 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973337189] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:58,960 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:58,960 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:20:58,960 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604660366] [2021-12-15 17:20:58,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:58,961 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:58,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:58,961 INFO L85 PathProgramCache]: Analyzing trace with hash -250116089, now seen corresponding path program 1 times [2021-12-15 17:20:58,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:58,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385297649] [2021-12-15 17:20:58,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:58,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:58,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:58,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:58,983 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:58,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385297649] [2021-12-15 17:20:58,983 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1385297649] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:58,983 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:58,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:58,983 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111786381] [2021-12-15 17:20:58,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:58,983 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:58,983 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:58,984 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:20:58,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:20:58,984 INFO L87 Difference]: Start difference. First operand 10449 states and 15325 transitions. cyclomatic complexity: 4884 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:59,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:20:59,106 INFO L93 Difference]: Finished difference Result 20537 states and 29910 transitions. [2021-12-15 17:20:59,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:20:59,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20537 states and 29910 transitions. [2021-12-15 17:20:59,185 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20279 [2021-12-15 17:20:59,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20537 states to 20537 states and 29910 transitions. [2021-12-15 17:20:59,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20537 [2021-12-15 17:20:59,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20537 [2021-12-15 17:20:59,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20537 states and 29910 transitions. [2021-12-15 17:20:59,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:20:59,361 INFO L681 BuchiCegarLoop]: Abstraction has 20537 states and 29910 transitions. [2021-12-15 17:20:59,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20537 states and 29910 transitions. [2021-12-15 17:20:59,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20537 to 19873. [2021-12-15 17:20:59,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19873 states, 19873 states have (on average 1.4579580335128064) internal successors, (28974), 19872 states have internal predecessors, (28974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:20:59,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19873 states to 19873 states and 28974 transitions. [2021-12-15 17:20:59,667 INFO L704 BuchiCegarLoop]: Abstraction has 19873 states and 28974 transitions. [2021-12-15 17:20:59,667 INFO L587 BuchiCegarLoop]: Abstraction has 19873 states and 28974 transitions. [2021-12-15 17:20:59,667 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:20:59,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19873 states and 28974 transitions. [2021-12-15 17:20:59,718 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19615 [2021-12-15 17:20:59,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:20:59,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:20:59,720 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,721 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:20:59,722 INFO L791 eck$LassoCheckResult]: Stem: 95208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96055#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96056#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94696#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 94697#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96067#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96022#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96023#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95053#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95054#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95490#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95983#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 94962#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 94963#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94846#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94847#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95888#L1109 assume !(0 == ~M_E~0); 95915#L1109-2 assume !(0 == ~T1_E~0); 94853#L1114-1 assume !(0 == ~T2_E~0); 94854#L1119-1 assume !(0 == ~T3_E~0); 95987#L1124-1 assume !(0 == ~T4_E~0); 94510#L1129-1 assume !(0 == ~T5_E~0); 94511#L1134-1 assume !(0 == ~T6_E~0); 95136#L1139-1 assume !(0 == ~T7_E~0); 95897#L1144-1 assume !(0 == ~T8_E~0); 95744#L1149-1 assume !(0 == ~T9_E~0); 94618#L1154-1 assume !(0 == ~T10_E~0); 94619#L1159-1 assume !(0 == ~T11_E~0); 95729#L1164-1 assume !(0 == ~E_M~0); 95018#L1169-1 assume !(0 == ~E_1~0); 94903#L1174-1 assume !(0 == ~E_2~0); 94775#L1179-1 assume !(0 == ~E_3~0); 94700#L1184-1 assume !(0 == ~E_4~0); 94701#L1189-1 assume !(0 == ~E_5~0); 94733#L1194-1 assume !(0 == ~E_6~0); 94822#L1199-1 assume !(0 == ~E_7~0); 95752#L1204-1 assume !(0 == ~E_8~0); 95681#L1209-1 assume !(0 == ~E_9~0); 95682#L1214-1 assume !(0 == ~E_10~0); 96089#L1219-1 assume !(0 == ~E_11~0); 96227#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95036#L544 assume !(1 == ~m_pc~0); 95037#L544-2 is_master_triggered_~__retres1~0#1 := 0; 95972#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95759#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94661#L1379 assume !(0 != activate_threads_~tmp~1#1); 94662#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95470#L563 assume !(1 == ~t1_pc~0); 95251#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94520#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94521#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95615#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 94516#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94517#L582 assume 1 == ~t2_pc~0; 95228#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95627#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95628#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95743#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 94550#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94551#L601 assume !(1 == ~t3_pc~0); 95245#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95244#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95973#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95666#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 95667#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95605#L620 assume 1 == ~t4_pc~0; 94530#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94531#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95104#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95105#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 95484#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95703#L639 assume 1 == ~t5_pc~0; 95573#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94826#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94827#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95508#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 95509#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95432#L658 assume !(1 == ~t6_pc~0); 95033#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95034#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95656#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96057#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95670#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94866#L677 assume 1 == ~t7_pc~0; 94867#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94767#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95854#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96013#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 96014#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96117#L696 assume !(1 == ~t8_pc~0); 95094#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95095#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96066#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96100#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 96180#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95555#L715 assume 1 == ~t9_pc~0; 95556#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95187#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95092#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95093#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 95536#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95850#L734 assume !(1 == ~t10_pc~0); 95851#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 94990#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94991#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95009#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 95779#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95069#L753 assume 1 == ~t11_pc~0; 95070#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95675#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95182#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95183#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 95344#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95402#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 95403#L1237-2 assume !(1 == ~T1_E~0); 96163#L1242-1 assume !(1 == ~T2_E~0); 106415#L1247-1 assume !(1 == ~T3_E~0); 106413#L1252-1 assume !(1 == ~T4_E~0); 106411#L1257-1 assume !(1 == ~T5_E~0); 106409#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 106407#L1267-1 assume !(1 == ~T7_E~0); 106405#L1272-1 assume !(1 == ~T8_E~0); 106404#L1277-1 assume !(1 == ~T9_E~0); 95794#L1282-1 assume !(1 == ~T10_E~0); 95795#L1287-1 assume !(1 == ~T11_E~0); 112622#L1292-1 assume !(1 == ~E_M~0); 112619#L1297-1 assume !(1 == ~E_1~0); 112617#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 112615#L1307-1 assume !(1 == ~E_3~0); 112613#L1312-1 assume !(1 == ~E_4~0); 95285#L1317-1 assume !(1 == ~E_5~0); 95286#L1322-1 assume !(1 == ~E_6~0); 95548#L1327-1 assume !(1 == ~E_7~0); 111874#L1332-1 assume !(1 == ~E_8~0); 111872#L1337-1 assume !(1 == ~E_9~0); 111870#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 111850#L1347-1 assume !(1 == ~E_11~0); 111841#L1352-1 assume { :end_inline_reset_delta_events } true; 111833#L1678-2 [2021-12-15 17:20:59,722 INFO L793 eck$LassoCheckResult]: Loop: 111833#L1678-2 assume !false; 111826#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111823#L1084 assume !false; 111822#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 111812#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 111809#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 111808#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 111807#L925 assume !(0 != eval_~tmp~0#1); 94805#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94679#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94680#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 113863#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 114032#L1114-3 assume !(0 == ~T2_E~0); 114031#L1119-3 assume !(0 == ~T3_E~0); 114030#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 114029#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 95905#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95906#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95981#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 95045#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 95046#L1154-3 assume !(0 == ~T10_E~0); 95295#L1159-3 assume !(0 == ~T11_E~0); 95296#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 95601#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95602#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95658#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 95659#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 95839#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 95461#L1194-3 assume !(0 == ~E_6~0); 94798#L1199-3 assume !(0 == ~E_7~0); 94799#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 95028#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 94481#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 94482#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 95195#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95196#L544-39 assume !(1 == ~m_pc~0); 94458#L544-41 is_master_triggered_~__retres1~0#1 := 0; 94459#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94714#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94715#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 94874#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95822#L563-39 assume !(1 == ~t1_pc~0); 94613#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 94614#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95567#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95568#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96212#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95960#L582-39 assume !(1 == ~t2_pc~0); 94943#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 94944#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95617#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95618#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94707#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94493#L601-39 assume !(1 == ~t3_pc~0); 94495#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 94544#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 113960#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 113959#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95828#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95427#L620-39 assume 1 == ~t4_pc~0; 95429#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95894#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95895#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96241#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96257#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96258#L639-39 assume 1 == ~t5_pc~0; 113955#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95157#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94720#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94721#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 113953#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95465#L658-39 assume !(1 == ~t6_pc~0); 95467#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 113952#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94471#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94472#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95680#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113950#L677-39 assume !(1 == ~t7_pc~0); 113949#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 113947#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 113946#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94755#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 94756#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95346#L696-39 assume 1 == ~t8_pc~0; 95307#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 95178#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 95179#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95499#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 95458#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95323#L715-39 assume 1 == ~t9_pc~0; 95325#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95781#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95782#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113936#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 113935#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 113934#L734-39 assume !(1 == ~t10_pc~0); 113933#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 113931#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 113930#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 113929#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 113928#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 113927#L753-39 assume !(1 == ~t11_pc~0); 113925#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 95977#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95978#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95313#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 95314#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95424#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 95425#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 95733#L1242-3 assume !(1 == ~T2_E~0); 95734#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96003#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95643#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95644#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95979#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 96033#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 96175#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94725#L1282-3 assume !(1 == ~T10_E~0); 94726#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 113911#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 96238#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 95859#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 95860#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 96114#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96242#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 95755#L1322-3 assume !(1 == ~E_6~0); 95756#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 112665#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 112661#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 112660#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 112659#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 112658#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 112648#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 112644#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 112642#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 112102#L1697 assume !(0 == start_simulation_~tmp~3#1); 95952#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 111884#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 111875#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 111873#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 111871#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 111869#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 111849#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 111840#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 111833#L1678-2 [2021-12-15 17:20:59,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,723 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2021-12-15 17:20:59,723 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785840135] [2021-12-15 17:20:59,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:59,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:59,752 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:59,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785840135] [2021-12-15 17:20:59,752 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785840135] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:59,752 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:59,752 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:20:59,752 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50999554] [2021-12-15 17:20:59,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:59,753 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:20:59,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:20:59,753 INFO L85 PathProgramCache]: Analyzing trace with hash 1488663242, now seen corresponding path program 1 times [2021-12-15 17:20:59,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:20:59,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574466914] [2021-12-15 17:20:59,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:20:59,754 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:20:59,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:20:59,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:20:59,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:20:59,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574466914] [2021-12-15 17:20:59,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574466914] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:20:59,799 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:20:59,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:20:59,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936310113] [2021-12-15 17:20:59,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:20:59,799 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:20:59,800 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:20:59,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:20:59,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:20:59,801 INFO L87 Difference]: Start difference. First operand 19873 states and 28974 transitions. cyclomatic complexity: 9117 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:00,113 INFO L93 Difference]: Finished difference Result 55583 states and 80268 transitions. [2021-12-15 17:21:00,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:00,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55583 states and 80268 transitions. [2021-12-15 17:21:00,469 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 55167 [2021-12-15 17:21:00,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55583 states to 55583 states and 80268 transitions. [2021-12-15 17:21:00,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55583 [2021-12-15 17:21:00,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55583 [2021-12-15 17:21:00,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55583 states and 80268 transitions. [2021-12-15 17:21:00,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:00,790 INFO L681 BuchiCegarLoop]: Abstraction has 55583 states and 80268 transitions. [2021-12-15 17:21:00,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55583 states and 80268 transitions. [2021-12-15 17:21:01,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55583 to 54351. [2021-12-15 17:21:01,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54351 states, 54351 states have (on average 1.4456403746021231) internal successors, (78572), 54350 states have internal predecessors, (78572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54351 states to 54351 states and 78572 transitions. [2021-12-15 17:21:01,447 INFO L704 BuchiCegarLoop]: Abstraction has 54351 states and 78572 transitions. [2021-12-15 17:21:01,447 INFO L587 BuchiCegarLoop]: Abstraction has 54351 states and 78572 transitions. [2021-12-15 17:21:01,447 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:21:01,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54351 states and 78572 transitions. [2021-12-15 17:21:01,697 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54031 [2021-12-15 17:21:01,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:01,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:01,699 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,699 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,699 INFO L791 eck$LassoCheckResult]: Stem: 170685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 170686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 171562#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 171563#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170166#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 170167#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 171576#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 171528#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 171529#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 170525#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 170526#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 170965#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 171488#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 170435#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 170436#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 170318#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 170319#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 171390#L1109 assume !(0 == ~M_E~0); 171420#L1109-2 assume !(0 == ~T1_E~0); 170325#L1114-1 assume !(0 == ~T2_E~0); 170326#L1119-1 assume !(0 == ~T3_E~0); 171492#L1124-1 assume !(0 == ~T4_E~0); 169980#L1129-1 assume !(0 == ~T5_E~0); 169981#L1134-1 assume !(0 == ~T6_E~0); 170613#L1139-1 assume !(0 == ~T7_E~0); 171396#L1144-1 assume !(0 == ~T8_E~0); 171234#L1149-1 assume !(0 == ~T9_E~0); 170088#L1154-1 assume !(0 == ~T10_E~0); 170089#L1159-1 assume !(0 == ~T11_E~0); 171219#L1164-1 assume !(0 == ~E_M~0); 170490#L1169-1 assume !(0 == ~E_1~0); 170375#L1174-1 assume !(0 == ~E_2~0); 170249#L1179-1 assume !(0 == ~E_3~0); 170170#L1184-1 assume !(0 == ~E_4~0); 170171#L1189-1 assume !(0 == ~E_5~0); 170203#L1194-1 assume !(0 == ~E_6~0); 170296#L1199-1 assume !(0 == ~E_7~0); 171243#L1204-1 assume !(0 == ~E_8~0); 171163#L1209-1 assume !(0 == ~E_9~0); 171164#L1214-1 assume !(0 == ~E_10~0); 171592#L1219-1 assume !(0 == ~E_11~0); 171752#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 170510#L544 assume !(1 == ~m_pc~0); 170511#L544-2 is_master_triggered_~__retres1~0#1 := 0; 171476#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 171253#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 170133#L1379 assume !(0 != activate_threads_~tmp~1#1); 170134#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 170947#L563 assume !(1 == ~t1_pc~0); 170948#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169988#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169989#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 171096#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 169984#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169985#L582 assume !(1 == ~t2_pc~0); 170705#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 171107#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171108#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 171233#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 170018#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170019#L601 assume !(1 == ~t3_pc~0); 170722#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 170721#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171479#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 171144#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 171145#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171085#L620 assume 1 == ~t4_pc~0; 170000#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 170001#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 170578#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 170579#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 170959#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171189#L639 assume 1 == ~t5_pc~0; 171052#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 170298#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 170299#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 170984#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 170985#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 170905#L658 assume !(1 == ~t6_pc~0); 170504#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 170505#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171136#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 171565#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 171149#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 170340#L677 assume 1 == ~t7_pc~0; 170341#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 170242#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 171353#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 171520#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 171521#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 171623#L696 assume !(1 == ~t8_pc~0); 170569#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 170570#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 171575#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 171605#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 171699#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 171031#L715 assume 1 == ~t9_pc~0; 171032#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 170663#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 170564#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 170565#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 171015#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 171350#L734 assume !(1 == ~t10_pc~0); 171351#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 170462#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 170463#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 170483#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 171271#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 170540#L753 assume 1 == ~t11_pc~0; 170541#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 171154#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 170658#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 170659#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 170819#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 170877#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 170878#L1237-2 assume !(1 == ~T1_E~0); 171680#L1242-1 assume !(1 == ~T2_E~0); 171730#L1247-1 assume !(1 == ~T3_E~0); 175670#L1252-1 assume !(1 == ~T4_E~0); 175668#L1257-1 assume !(1 == ~T5_E~0); 175665#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175663#L1267-1 assume !(1 == ~T7_E~0); 175661#L1272-1 assume !(1 == ~T8_E~0); 175659#L1277-1 assume !(1 == ~T9_E~0); 175657#L1282-1 assume !(1 == ~T10_E~0); 175655#L1287-1 assume !(1 == ~T11_E~0); 175652#L1292-1 assume !(1 == ~E_M~0); 175650#L1297-1 assume !(1 == ~E_1~0); 175648#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 175646#L1307-1 assume !(1 == ~E_3~0); 175644#L1312-1 assume !(1 == ~E_4~0); 175642#L1317-1 assume !(1 == ~E_5~0); 175084#L1322-1 assume !(1 == ~E_6~0); 175080#L1327-1 assume !(1 == ~E_7~0); 175078#L1332-1 assume !(1 == ~E_8~0); 175075#L1337-1 assume !(1 == ~E_9~0); 175074#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 175073#L1347-1 assume !(1 == ~E_11~0); 175069#L1352-1 assume { :end_inline_reset_delta_events } true; 175066#L1678-2 [2021-12-15 17:21:01,700 INFO L793 eck$LassoCheckResult]: Loop: 175066#L1678-2 assume !false; 175062#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175059#L1084 assume !false; 175058#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 175047#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 175043#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 175041#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 175038#L925 assume !(0 != eval_~tmp~0#1); 175039#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 187602#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 187600#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 187597#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 187595#L1114-3 assume !(0 == ~T2_E~0); 187593#L1119-3 assume !(0 == ~T3_E~0); 187591#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 187589#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 187587#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 187584#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 187582#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 187580#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 187578#L1154-3 assume !(0 == ~T10_E~0); 187576#L1159-3 assume !(0 == ~T11_E~0); 187574#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 187571#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 187569#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 187567#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 187565#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 187563#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 187562#L1194-3 assume !(0 == ~E_6~0); 187558#L1199-3 assume !(0 == ~E_7~0); 187556#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 187554#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 187553#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 187547#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 187545#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 187543#L544-39 assume !(1 == ~m_pc~0); 187542#L544-41 is_master_triggered_~__retres1~0#1 := 0; 187541#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 187540#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 187539#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 187538#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 187537#L563-39 assume !(1 == ~t1_pc~0); 187536#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 187535#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 187534#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 187533#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 187520#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187518#L582-39 assume !(1 == ~t2_pc~0); 187516#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 187513#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187511#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 187508#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 187505#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 187504#L601-39 assume !(1 == ~t3_pc~0); 187502#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 187500#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 187499#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 187498#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 187497#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 187496#L620-39 assume !(1 == ~t4_pc~0); 187494#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 187493#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 187492#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 187491#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 187490#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 187489#L639-39 assume !(1 == ~t5_pc~0); 187488#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 187486#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 187485#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 187483#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 187480#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 187478#L658-39 assume !(1 == ~t6_pc~0); 187475#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 187473#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 187471#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 187469#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 187467#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 187465#L677-39 assume 1 == ~t7_pc~0; 187462#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 187460#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 187458#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 187456#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 187454#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 187452#L696-39 assume !(1 == ~t8_pc~0); 187450#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 187447#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 187445#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 187443#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 187440#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 187438#L715-39 assume 1 == ~t9_pc~0; 187435#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 187433#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 187431#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 187429#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 187426#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 187424#L734-39 assume !(1 == ~t10_pc~0); 187422#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 187419#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 187417#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 187415#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 187412#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 187410#L753-39 assume 1 == ~t11_pc~0; 187408#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 186566#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 177599#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 177597#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 177595#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177593#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 176251#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 176875#L1242-3 assume !(1 == ~T2_E~0); 176873#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 176871#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 176869#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 176866#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 176864#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 176862#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 176860#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 176454#L1282-3 assume !(1 == ~T10_E~0); 176452#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 176450#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 176448#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 176446#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 176444#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 176442#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176440#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 176205#L1322-3 assume !(1 == ~E_6~0); 176203#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 176201#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 176199#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 176197#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 176194#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 176192#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 176169#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 176165#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 176163#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 176125#L1697 assume !(0 == start_simulation_~tmp~3#1); 176123#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 175570#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 175559#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 175557#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 175555#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 175553#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 175551#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 175068#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 175066#L1678-2 [2021-12-15 17:21:01,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,700 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2021-12-15 17:21:01,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114707169] [2021-12-15 17:21:01,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,738 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114707169] [2021-12-15 17:21:01,739 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114707169] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,739 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,739 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:01,739 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139817862] [2021-12-15 17:21:01,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,740 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:01,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,740 INFO L85 PathProgramCache]: Analyzing trace with hash 621924299, now seen corresponding path program 1 times [2021-12-15 17:21:01,740 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596429690] [2021-12-15 17:21:01,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,741 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,769 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596429690] [2021-12-15 17:21:01,769 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [596429690] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,769 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,769 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:01,770 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140560254] [2021-12-15 17:21:01,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,770 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:01,770 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:01,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:01,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:01,771 INFO L87 Difference]: Start difference. First operand 54351 states and 78572 transitions. cyclomatic complexity: 24253 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,465 INFO L93 Difference]: Finished difference Result 153004 states and 219519 transitions. [2021-12-15 17:21:02,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:02,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153004 states and 219519 transitions. [2021-12-15 17:21:03,148 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 152205 [2021-12-15 17:21:03,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153004 states to 153004 states and 219519 transitions. [2021-12-15 17:21:03,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153004 [2021-12-15 17:21:03,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153004 [2021-12-15 17:21:03,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153004 states and 219519 transitions. [2021-12-15 17:21:03,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:03,754 INFO L681 BuchiCegarLoop]: Abstraction has 153004 states and 219519 transitions. [2021-12-15 17:21:03,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153004 states and 219519 transitions. [2021-12-15 17:21:05,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153004 to 149948. [2021-12-15 17:21:05,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149948 states, 149948 states have (on average 1.4360111505321844) internal successors, (215327), 149947 states have internal predecessors, (215327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:05,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149948 states to 149948 states and 215327 transitions. [2021-12-15 17:21:05,735 INFO L704 BuchiCegarLoop]: Abstraction has 149948 states and 215327 transitions. [2021-12-15 17:21:05,735 INFO L587 BuchiCegarLoop]: Abstraction has 149948 states and 215327 transitions. [2021-12-15 17:21:05,735 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:21:05,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149948 states and 215327 transitions. [2021-12-15 17:21:06,200 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 149469 [2021-12-15 17:21:06,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:06,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:06,202 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,202 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,203 INFO L791 eck$LassoCheckResult]: Stem: 378038#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 378039#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 378908#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 378909#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 377527#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 377528#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 378925#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 378878#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 378879#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 377885#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 377886#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 378316#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 378838#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 377794#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 377795#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 377677#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 377678#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 378736#L1109 assume !(0 == ~M_E~0); 378766#L1109-2 assume !(0 == ~T1_E~0); 377684#L1114-1 assume !(0 == ~T2_E~0); 377685#L1119-1 assume !(0 == ~T3_E~0); 378842#L1124-1 assume !(0 == ~T4_E~0); 377345#L1129-1 assume !(0 == ~T5_E~0); 377346#L1134-1 assume !(0 == ~T6_E~0); 377966#L1139-1 assume !(0 == ~T7_E~0); 378745#L1144-1 assume !(0 == ~T8_E~0); 378580#L1149-1 assume !(0 == ~T9_E~0); 377449#L1154-1 assume !(0 == ~T10_E~0); 377450#L1159-1 assume !(0 == ~T11_E~0); 378562#L1164-1 assume !(0 == ~E_M~0); 377849#L1169-1 assume !(0 == ~E_1~0); 377734#L1174-1 assume !(0 == ~E_2~0); 377607#L1179-1 assume !(0 == ~E_3~0); 377531#L1184-1 assume !(0 == ~E_4~0); 377532#L1189-1 assume !(0 == ~E_5~0); 377564#L1194-1 assume !(0 == ~E_6~0); 377656#L1199-1 assume !(0 == ~E_7~0); 378589#L1204-1 assume !(0 == ~E_8~0); 378513#L1209-1 assume !(0 == ~E_9~0); 378514#L1214-1 assume !(0 == ~E_10~0); 378938#L1219-1 assume !(0 == ~E_11~0); 379077#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 377870#L544 assume !(1 == ~m_pc~0); 377871#L544-2 is_master_triggered_~__retres1~0#1 := 0; 378824#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 378598#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 377493#L1379 assume !(0 != activate_threads_~tmp~1#1); 377494#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 378299#L563 assume !(1 == ~t1_pc~0); 378300#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 377353#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 377354#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 378441#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 377349#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 377350#L582 assume !(1 == ~t2_pc~0); 378058#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 378453#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 378454#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378579#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 377379#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 377380#L601 assume !(1 == ~t3_pc~0); 378075#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 378074#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378828#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 378492#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 378493#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378429#L620 assume !(1 == ~t4_pc~0); 378430#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 377983#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 377929#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 377930#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 378313#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 378536#L639 assume 1 == ~t5_pc~0; 378399#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 377658#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 377659#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 378335#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 378336#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 378253#L658 assume !(1 == ~t6_pc~0); 377865#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 377866#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 378484#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 378912#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 378500#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 377699#L677 assume 1 == ~t7_pc~0; 377700#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 377601#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 378694#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 378865#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 378866#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 378970#L696 assume !(1 == ~t8_pc~0); 377922#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 377923#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 378924#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 378951#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 379038#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 378377#L715 assume 1 == ~t9_pc~0; 378378#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 378018#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 377919#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 377920#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 378360#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 378691#L734 assume !(1 == ~t10_pc~0); 378692#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 377821#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 377822#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 377842#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 378615#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 377898#L753 assume 1 == ~t11_pc~0; 377899#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 378505#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 378010#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 378011#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 378168#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 378226#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 378227#L1237-2 assume !(1 == ~T1_E~0); 379014#L1242-1 assume !(1 == ~T2_E~0); 377979#L1247-1 assume !(1 == ~T3_E~0); 377980#L1252-1 assume !(1 == ~T4_E~0); 377757#L1257-1 assume !(1 == ~T5_E~0); 377758#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 378715#L1267-1 assume !(1 == ~T7_E~0); 378858#L1272-1 assume !(1 == ~T8_E~0); 378068#L1277-1 assume !(1 == ~T9_E~0); 378069#L1282-1 assume !(1 == ~T10_E~0); 378626#L1287-1 assume !(1 == ~T11_E~0); 491186#L1292-1 assume !(1 == ~E_M~0); 491185#L1297-1 assume !(1 == ~E_1~0); 491184#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 491183#L1307-1 assume !(1 == ~E_3~0); 491182#L1312-1 assume !(1 == ~E_4~0); 491181#L1317-1 assume !(1 == ~E_5~0); 491180#L1322-1 assume !(1 == ~E_6~0); 378371#L1327-1 assume !(1 == ~E_7~0); 491179#L1332-1 assume !(1 == ~E_8~0); 491178#L1337-1 assume !(1 == ~E_9~0); 491177#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 491176#L1347-1 assume !(1 == ~E_11~0); 491175#L1352-1 assume { :end_inline_reset_delta_events } true; 491172#L1678-2 [2021-12-15 17:21:06,203 INFO L793 eck$LassoCheckResult]: Loop: 491172#L1678-2 assume !false; 491173#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 517713#L1084 assume !false; 517712#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 482507#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 482504#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 482502#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 482499#L925 assume !(0 != eval_~tmp~0#1); 482500#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 491966#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 491965#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 491964#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 491963#L1114-3 assume !(0 == ~T2_E~0); 491962#L1119-3 assume !(0 == ~T3_E~0); 491961#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 491960#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 491959#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 491958#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 491957#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 491956#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 491955#L1154-3 assume !(0 == ~T10_E~0); 491954#L1159-3 assume !(0 == ~T11_E~0); 491953#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 491952#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 491951#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 491950#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 491949#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 491948#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 491946#L1194-3 assume !(0 == ~E_6~0); 491944#L1199-3 assume !(0 == ~E_7~0); 491942#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 491940#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 491938#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 491936#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 491934#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 491932#L544-39 assume !(1 == ~m_pc~0); 491930#L544-41 is_master_triggered_~__retres1~0#1 := 0; 491928#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 491926#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 491924#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 491922#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 491920#L563-39 assume !(1 == ~t1_pc~0); 491918#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 491916#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 491914#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 491912#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 491910#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 491908#L582-39 assume !(1 == ~t2_pc~0); 491905#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 491903#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 491901#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 491899#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 491897#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 491895#L601-39 assume !(1 == ~t3_pc~0); 491893#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 491890#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 491888#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 491886#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 491884#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 491882#L620-39 assume !(1 == ~t4_pc~0); 491879#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 491877#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 491875#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 491873#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 491871#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 491869#L639-39 assume !(1 == ~t5_pc~0); 491866#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 491863#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 491861#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 491859#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 491857#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 491855#L658-39 assume 1 == ~t6_pc~0; 491852#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 491849#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 491847#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 491845#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 491843#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 491841#L677-39 assume !(1 == ~t7_pc~0); 491838#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 491835#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 491833#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 491831#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 491829#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 491827#L696-39 assume !(1 == ~t8_pc~0); 491824#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 491821#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 491819#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 491817#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 491815#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 491813#L715-39 assume !(1 == ~t9_pc~0); 491810#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 491807#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 491805#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 491803#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 491801#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 491799#L734-39 assume !(1 == ~t10_pc~0); 491796#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 491793#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 491791#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 491789#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 491786#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 491785#L753-39 assume 1 == ~t11_pc~0; 491779#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 491775#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 491772#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 491766#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 491765#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 491764#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 450312#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 491466#L1242-3 assume !(1 == ~T2_E~0); 491464#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 491463#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 491461#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 491459#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 491457#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 491455#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 491452#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 491453#L1282-3 assume !(1 == ~T10_E~0); 518396#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 518395#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 518394#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 518393#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 518392#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 518391#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 518390#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 518389#L1322-3 assume !(1 == ~E_6~0); 512679#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 518388#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 518387#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 518386#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 518385#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 491426#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 491427#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 491401#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 491402#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 491224#L1697 assume !(0 == start_simulation_~tmp~3#1); 491225#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 491211#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 491202#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 491197#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 491195#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 491192#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 491191#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 491174#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 491172#L1678-2 [2021-12-15 17:21:06,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,204 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2021-12-15 17:21:06,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724989640] [2021-12-15 17:21:06,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:06,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:06,229 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:06,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724989640] [2021-12-15 17:21:06,230 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724989640] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:06,230 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:06,230 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:06,230 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226800909] [2021-12-15 17:21:06,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:06,230 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:06,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,231 INFO L85 PathProgramCache]: Analyzing trace with hash -480698100, now seen corresponding path program 1 times [2021-12-15 17:21:06,231 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245396325] [2021-12-15 17:21:06,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:06,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:06,253 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:06,253 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245396325] [2021-12-15 17:21:06,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245396325] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:06,253 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:06,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:06,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468327707] [2021-12-15 17:21:06,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:06,254 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:06,254 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:06,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:06,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:06,254 INFO L87 Difference]: Start difference. First operand 149948 states and 215327 transitions. cyclomatic complexity: 65443 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:08,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:08,069 INFO L93 Difference]: Finished difference Result 431521 states and 615034 transitions. [2021-12-15 17:21:08,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:08,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 431521 states and 615034 transitions. [2021-12-15 17:21:10,027 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 429731 [2021-12-15 17:21:11,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 431521 states to 431521 states and 615034 transitions. [2021-12-15 17:21:11,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 431521 [2021-12-15 17:21:11,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 431521 [2021-12-15 17:21:11,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 431521 states and 615034 transitions. [2021-12-15 17:21:11,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:11,537 INFO L681 BuchiCegarLoop]: Abstraction has 431521 states and 615034 transitions. [2021-12-15 17:21:11,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431521 states and 615034 transitions. [2021-12-15 17:21:15,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431521 to 427025. [2021-12-15 17:21:16,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 427025 states, 427025 states have (on average 1.425982085358) internal successors, (608930), 427024 states have internal predecessors, (608930), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:17,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427025 states to 427025 states and 608930 transitions. [2021-12-15 17:21:17,379 INFO L704 BuchiCegarLoop]: Abstraction has 427025 states and 608930 transitions. [2021-12-15 17:21:17,379 INFO L587 BuchiCegarLoop]: Abstraction has 427025 states and 608930 transitions. [2021-12-15 17:21:17,379 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:21:17,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 427025 states and 608930 transitions. [2021-12-15 17:21:18,923 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 426131 [2021-12-15 17:21:18,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:18,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:18,924 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:18,924 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:18,925 INFO L791 eck$LassoCheckResult]: Stem: 959511#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 959512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 960373#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 960374#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 959005#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 959006#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 960388#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 960340#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 960341#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 959359#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 959360#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 959785#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 960293#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 959270#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 959271#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 959154#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 959155#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 960191#L1109 assume !(0 == ~M_E~0); 960223#L1109-2 assume !(0 == ~T1_E~0); 959161#L1114-1 assume !(0 == ~T2_E~0); 959162#L1119-1 assume !(0 == ~T3_E~0); 960298#L1124-1 assume !(0 == ~T4_E~0); 958822#L1129-1 assume !(0 == ~T5_E~0); 958823#L1134-1 assume !(0 == ~T6_E~0); 959440#L1139-1 assume !(0 == ~T7_E~0); 960203#L1144-1 assume !(0 == ~T8_E~0); 960036#L1149-1 assume !(0 == ~T9_E~0); 958926#L1154-1 assume !(0 == ~T10_E~0); 958927#L1159-1 assume !(0 == ~T11_E~0); 960021#L1164-1 assume !(0 == ~E_M~0); 959323#L1169-1 assume !(0 == ~E_1~0); 959211#L1174-1 assume !(0 == ~E_2~0); 959082#L1179-1 assume !(0 == ~E_3~0); 959009#L1184-1 assume !(0 == ~E_4~0); 959010#L1189-1 assume !(0 == ~E_5~0); 959041#L1194-1 assume !(0 == ~E_6~0); 959130#L1199-1 assume !(0 == ~E_7~0); 960045#L1204-1 assume !(0 == ~E_8~0); 959976#L1209-1 assume !(0 == ~E_9~0); 959977#L1214-1 assume !(0 == ~E_10~0); 960408#L1219-1 assume !(0 == ~E_11~0); 960555#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 959341#L544 assume !(1 == ~m_pc~0); 959342#L544-2 is_master_triggered_~__retres1~0#1 := 0; 960281#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 960054#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 958971#L1379 assume !(0 != activate_threads_~tmp~1#1); 958972#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 959764#L563 assume !(1 == ~t1_pc~0); 959765#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 958832#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 958833#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 959899#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 958828#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 958829#L582 assume !(1 == ~t2_pc~0); 959531#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 959909#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 959910#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 960035#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 958858#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 958859#L601 assume !(1 == ~t3_pc~0); 959546#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 959545#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 960282#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 959954#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 959955#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 959888#L620 assume !(1 == ~t4_pc~0); 959889#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 959457#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 959405#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 959406#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 959782#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 959994#L639 assume !(1 == ~t5_pc~0); 959995#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 959134#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 959135#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 959803#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 959804#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 959722#L658 assume !(1 == ~t6_pc~0); 959338#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 959339#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 959943#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 960375#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 959961#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 959174#L677 assume 1 == ~t7_pc~0; 959175#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 959075#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 960154#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 960328#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 960329#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 960443#L696 assume !(1 == ~t8_pc~0); 959397#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 959398#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 960387#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 960425#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 960509#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 959837#L715 assume 1 == ~t9_pc~0; 959838#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 959491#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 959395#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 959396#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 959825#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 960150#L734 assume !(1 == ~t10_pc~0); 960151#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 959296#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 959297#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 959315#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 960071#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 959374#L753 assume 1 == ~t11_pc~0; 959375#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 959971#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 959483#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 959484#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 959635#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 959696#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 959697#L1237-2 assume !(1 == ~T1_E~0); 960538#L1242-1 assume !(1 == ~T2_E~0); 960539#L1247-1 assume !(1 == ~T3_E~0); 960325#L1252-1 assume !(1 == ~T4_E~0); 960326#L1257-1 assume !(1 == ~T5_E~0); 960174#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 960175#L1267-1 assume !(1 == ~T7_E~0); 960317#L1272-1 assume !(1 == ~T8_E~0); 960318#L1277-1 assume !(1 == ~T9_E~0); 960082#L1282-1 assume !(1 == ~T10_E~0); 960005#L1287-1 assume !(1 == ~T11_E~0); 960006#L1292-1 assume !(1 == ~E_M~0); 959960#L1297-1 assume !(1 == ~E_1~0); 959367#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 959368#L1307-1 assume !(1 == ~E_3~0); 960302#L1312-1 assume !(1 == ~E_4~0); 959581#L1317-1 assume !(1 == ~E_5~0); 959582#L1322-1 assume !(1 == ~E_6~0); 959311#L1327-1 assume !(1 == ~E_7~0); 959312#L1332-1 assume !(1 == ~E_8~0); 959898#L1337-1 assume !(1 == ~E_9~0); 959829#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 959830#L1347-1 assume !(1 == ~E_11~0); 960300#L1352-1 assume { :end_inline_reset_delta_events } true; 960301#L1678-2 [2021-12-15 17:21:18,925 INFO L793 eck$LassoCheckResult]: Loop: 960301#L1678-2 assume !false; 1270716#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1270714#L1084 assume !false; 1313401#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1270698#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1270693#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1270690#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1270686#L925 assume !(0 != eval_~tmp~0#1); 1270687#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1319943#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1319942#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1319941#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1319940#L1114-3 assume !(0 == ~T2_E~0); 1319939#L1119-3 assume !(0 == ~T3_E~0); 1319938#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1319937#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1319936#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1319935#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1319934#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1319933#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1319932#L1154-3 assume !(0 == ~T10_E~0); 1319931#L1159-3 assume !(0 == ~T11_E~0); 1319930#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1319929#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1319928#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1319927#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1319926#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1319925#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1319924#L1194-3 assume !(0 == ~E_6~0); 1319923#L1199-3 assume !(0 == ~E_7~0); 1319922#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1319921#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1319920#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1319919#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1319918#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1319917#L544-39 assume !(1 == ~m_pc~0); 1319916#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1319915#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1319914#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1319913#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 1319912#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1319911#L563-39 assume !(1 == ~t1_pc~0); 1319910#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1319909#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1319908#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1319907#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1319906#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1319905#L582-39 assume !(1 == ~t2_pc~0); 1319904#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1319903#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1319902#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1319901#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1319900#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1319899#L601-39 assume 1 == ~t3_pc~0; 1319897#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1319896#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1319895#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1319894#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1319893#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1319892#L620-39 assume !(1 == ~t4_pc~0); 1319891#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1319890#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1319889#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1319888#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1319887#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1319886#L639-39 assume !(1 == ~t5_pc~0); 1319885#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1319884#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1319883#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1319882#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1319881#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1319880#L658-39 assume !(1 == ~t6_pc~0); 1319878#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1319877#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1319876#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1319875#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1319874#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1319873#L677-39 assume !(1 == ~t7_pc~0); 1319872#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1319870#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1319869#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1319868#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 1319867#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1319866#L696-39 assume 1 == ~t8_pc~0; 1319864#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1319863#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1319862#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1319861#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1319860#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1319859#L715-39 assume 1 == ~t9_pc~0; 1319857#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1319856#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1319855#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1319854#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1319853#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1319852#L734-39 assume 1 == ~t10_pc~0; 1319850#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1319849#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1319848#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1319847#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1319846#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1319845#L753-39 assume 1 == ~t11_pc~0; 1319844#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1319842#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1319841#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1319840#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1319839#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1319838#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1154043#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1313585#L1242-3 assume !(1 == ~T2_E~0); 1313584#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1313583#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1313582#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1313581#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1313580#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1313579#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1313578#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1313577#L1282-3 assume !(1 == ~T10_E~0); 1303689#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1313576#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1313575#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1313574#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1313573#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1313572#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1313571#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1313570#L1322-3 assume !(1 == ~E_6~0); 1285023#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1313569#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1313568#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1313567#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1313566#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1313565#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1313555#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1313552#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1313551#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1313431#L1697 assume !(0 == start_simulation_~tmp~3#1); 1313430#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1313424#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1313415#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1313414#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1313413#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1313412#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1313411#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1313410#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 960301#L1678-2 [2021-12-15 17:21:18,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:18,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2021-12-15 17:21:18,926 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:18,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311937087] [2021-12-15 17:21:18,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:18,926 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:18,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:18,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:18,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:18,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311937087] [2021-12-15 17:21:18,953 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [311937087] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:18,953 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:18,953 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:18,953 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125872316] [2021-12-15 17:21:18,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:18,954 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:18,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:18,954 INFO L85 PathProgramCache]: Analyzing trace with hash 1423530441, now seen corresponding path program 1 times [2021-12-15 17:21:18,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:18,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622782281] [2021-12-15 17:21:18,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:18,954 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:18,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:18,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:18,977 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:18,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622782281] [2021-12-15 17:21:18,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622782281] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:18,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:18,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:18,977 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119481019] [2021-12-15 17:21:18,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:18,978 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:18,978 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:18,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:18,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:18,978 INFO L87 Difference]: Start difference. First operand 427025 states and 608930 transitions. cyclomatic complexity: 182033 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:22,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:22,381 INFO L93 Difference]: Finished difference Result 1078723 states and 1549126 transitions. [2021-12-15 17:21:22,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:22,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1078723 states and 1549126 transitions. [2021-12-15 17:21:28,448 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1076208 [2021-12-15 17:21:31,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1078723 states to 1078723 states and 1549126 transitions. [2021-12-15 17:21:31,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1078723 [2021-12-15 17:21:32,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1078723 [2021-12-15 17:21:32,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1078723 states and 1549126 transitions.