./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.12.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.12.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:20:57,000 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:20:57,032 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:20:57,073 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:20:57,074 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:20:57,077 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:20:57,078 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:20:57,080 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:20:57,082 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:20:57,087 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:20:57,087 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:20:57,088 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:20:57,089 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:20:57,091 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:20:57,092 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:20:57,095 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:20:57,097 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:20:57,097 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:20:57,099 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:20:57,103 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:20:57,104 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:20:57,105 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:20:57,107 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:20:57,107 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:20:57,110 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:20:57,111 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:20:57,111 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:20:57,113 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:20:57,113 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:20:57,114 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:20:57,114 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:20:57,115 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:20:57,116 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:20:57,117 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:20:57,117 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:20:57,118 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:20:57,118 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:20:57,118 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:20:57,118 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:20:57,119 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:20:57,119 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:20:57,120 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:20:57,153 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:20:57,154 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:20:57,154 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:20:57,154 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:20:57,156 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:20:57,156 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:20:57,156 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:20:57,156 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:20:57,156 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:20:57,156 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:20:57,157 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:20:57,157 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:20:57,157 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:20:57,158 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:20:57,158 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:20:57,158 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:20:57,158 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:20:57,158 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:20:57,158 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:20:57,158 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:20:57,159 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:20:57,159 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:20:57,159 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:20:57,159 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:20:57,159 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:20:57,159 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:20:57,159 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:20:57,160 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:20:57,160 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:20:57,160 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:20:57,160 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:20:57,161 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:20:57,161 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:20:57,162 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a [2021-12-15 17:20:57,350 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:20:57,370 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:20:57,372 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:20:57,373 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:20:57,373 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:20:57,374 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2021-12-15 17:20:57,440 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4947058de/04d658bdb81b432dbdca9d34cab0824d/FLAG861e8f8c7 [2021-12-15 17:20:57,840 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:20:57,840 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2021-12-15 17:20:57,852 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4947058de/04d658bdb81b432dbdca9d34cab0824d/FLAG861e8f8c7 [2021-12-15 17:20:58,250 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4947058de/04d658bdb81b432dbdca9d34cab0824d [2021-12-15 17:20:58,253 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:20:58,256 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:20:58,257 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:58,257 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:20:58,259 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:20:58,260 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,261 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@37c2f62c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58, skipping insertion in model container [2021-12-15 17:20:58,261 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,266 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:20:58,307 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:20:58,444 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-2.c[671,684] [2021-12-15 17:20:58,586 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:58,599 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:20:58,609 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-2.c[671,684] [2021-12-15 17:20:58,683 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:20:58,702 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:20:58,703 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58 WrapperNode [2021-12-15 17:20:58,703 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:20:58,704 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:58,704 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:20:58,704 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:20:58,709 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,729 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,813 INFO L137 Inliner]: procedures = 52, calls = 67, calls flagged for inlining = 62, calls inlined = 269, statements flattened = 4134 [2021-12-15 17:20:58,814 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:20:58,815 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:20:58,815 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:20:58,815 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:20:58,821 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,822 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,831 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,831 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,871 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,899 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,910 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,936 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:20:58,937 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:20:58,937 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:20:58,937 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:20:58,938 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (1/1) ... [2021-12-15 17:20:58,944 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:20:58,952 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:20:58,981 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:20:58,987 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:20:59,006 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:20:59,006 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:20:59,006 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:20:59,007 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:20:59,135 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:20:59,136 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:21:00,519 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:21:00,538 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:21:00,539 INFO L301 CfgBuilder]: Removed 15 assume(true) statements. [2021-12-15 17:21:00,542 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:00 BoogieIcfgContainer [2021-12-15 17:21:00,542 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:21:00,543 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:21:00,543 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:21:00,545 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:21:00,546 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:00,546 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:20:58" (1/3) ... [2021-12-15 17:21:00,547 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61aed2d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:00, skipping insertion in model container [2021-12-15 17:21:00,547 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:00,547 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:20:58" (2/3) ... [2021-12-15 17:21:00,548 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61aed2d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:00, skipping insertion in model container [2021-12-15 17:21:00,548 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:00,548 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:00" (3/3) ... [2021-12-15 17:21:00,549 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-2.c [2021-12-15 17:21:00,586 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:21:00,586 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:21:00,586 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:21:00,586 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:21:00,587 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:21:00,587 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:21:00,587 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:21:00,587 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:21:00,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1624 [2021-12-15 17:21:00,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:00,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:00,686 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,686 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,686 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:21:00,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:00,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1624 [2021-12-15 17:21:00,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:00,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:00,705 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,705 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:00,737 INFO L791 eck$LassoCheckResult]: Stem: 423#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1707#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1158#L1766true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1468#L834true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157#L841true assume !(1 == ~m_i~0);~m_st~0 := 2; 549#L841-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 109#L846-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1722#L851-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1026#L856-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 450#L861-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 484#L866-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L871-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 752#L876-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 744#L881-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1316#L886-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 251#L891-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1303#L896-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 509#L901-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1191#L1194true assume !(0 == ~M_E~0); 608#L1194-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 879#L1199-1true assume !(0 == ~T2_E~0); 1068#L1204-1true assume !(0 == ~T3_E~0); 797#L1209-1true assume !(0 == ~T4_E~0); 1355#L1214-1true assume !(0 == ~T5_E~0); 1735#L1219-1true assume !(0 == ~T6_E~0); 1657#L1224-1true assume !(0 == ~T7_E~0); 291#L1229-1true assume !(0 == ~T8_E~0); 69#L1234-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 496#L1239-1true assume !(0 == ~T10_E~0); 88#L1244-1true assume !(0 == ~T11_E~0); 1452#L1249-1true assume !(0 == ~T12_E~0); 473#L1254-1true assume !(0 == ~E_M~0); 43#L1259-1true assume !(0 == ~E_1~0); 26#L1264-1true assume !(0 == ~E_2~0); 1782#L1269-1true assume !(0 == ~E_3~0); 1710#L1274-1true assume 0 == ~E_4~0;~E_4~0 := 1; 1442#L1279-1true assume !(0 == ~E_5~0); 126#L1284-1true assume !(0 == ~E_6~0); 1568#L1289-1true assume !(0 == ~E_7~0); 515#L1294-1true assume !(0 == ~E_8~0); 522#L1299-1true assume !(0 == ~E_9~0); 1629#L1304-1true assume !(0 == ~E_10~0); 1671#L1309-1true assume !(0 == ~E_11~0); 1647#L1314-1true assume 0 == ~E_12~0;~E_12~0 := 1; 104#L1319-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68#L586true assume 1 == ~m_pc~0; 1224#L587true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 770#L597true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1775#L598true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 204#L1485true assume !(0 != activate_threads_~tmp~1#1); 1036#L1485-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1727#L605true assume !(1 == ~t1_pc~0); 1181#L605-2true is_transmit1_triggered_~__retres1~1#1 := 0; 408#L616true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1280#L617true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1347#L1493true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 849#L1493-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 358#L624true assume 1 == ~t2_pc~0; 91#L625true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 456#L635true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1328#L636true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1431#L1501true assume !(0 != activate_threads_~tmp___1~0#1); 1091#L1501-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 925#L643true assume !(1 == ~t3_pc~0); 766#L643-2true is_transmit3_triggered_~__retres1~3#1 := 0; 532#L654true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 470#L655true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 257#L1509true assume !(0 != activate_threads_~tmp___2~0#1); 1270#L1509-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136#L662true assume 1 == ~t4_pc~0; 445#L663true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 117#L673true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1575#L674true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 553#L1517true assume !(0 != activate_threads_~tmp___3~0#1); 62#L1517-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 376#L681true assume !(1 == ~t5_pc~0); 3#L681-2true is_transmit5_triggered_~__retres1~5#1 := 0; 589#L692true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1361#L693true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1268#L1525true assume !(0 != activate_threads_~tmp___4~0#1); 264#L1525-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 723#L700true assume 1 == ~t6_pc~0; 1781#L701true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 131#L711true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 377#L712true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 158#L1533true assume !(0 != activate_threads_~tmp___5~0#1); 1161#L1533-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1293#L719true assume 1 == ~t7_pc~0; 1583#L720true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1602#L730true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 755#L731true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1404#L1541true assume !(0 != activate_threads_~tmp___6~0#1); 9#L1541-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1603#L738true assume !(1 == ~t8_pc~0); 886#L738-2true is_transmit8_triggered_~__retres1~8#1 := 0; 790#L749true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 187#L750true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 606#L1549true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1200#L1549-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 945#L757true assume 1 == ~t9_pc~0; 1640#L758true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7#L768true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 709#L769true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1062#L1557true assume !(0 != activate_threads_~tmp___8~0#1); 583#L1557-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1584#L776true assume !(1 == ~t10_pc~0); 1102#L776-2true is_transmit10_triggered_~__retres1~10#1 := 0; 206#L787true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1003#L788true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 127#L1565true assume !(0 != activate_threads_~tmp___9~0#1); 760#L1565-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 105#L795true assume 1 == ~t11_pc~0; 274#L796true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1059#L806true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1014#L807true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1325#L1573true assume !(0 != activate_threads_~tmp___10~0#1); 762#L1573-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 747#L814true assume !(1 == ~t12_pc~0); 908#L814-2true is_transmit12_triggered_~__retres1~12#1 := 0; 994#L825true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1151#L826true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1315#L1581true assume !(0 != activate_threads_~tmp___11~0#1); 231#L1581-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1108#L1332true assume !(1 == ~M_E~0); 1498#L1332-2true assume !(1 == ~T1_E~0); 1522#L1337-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 685#L1342-1true assume !(1 == ~T3_E~0); 1436#L1347-1true assume !(1 == ~T4_E~0); 1141#L1352-1true assume !(1 == ~T5_E~0); 950#L1357-1true assume !(1 == ~T6_E~0); 390#L1362-1true assume !(1 == ~T7_E~0); 1210#L1367-1true assume !(1 == ~T8_E~0); 174#L1372-1true assume !(1 == ~T9_E~0); 488#L1377-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 344#L1382-1true assume !(1 == ~T11_E~0); 847#L1387-1true assume !(1 == ~T12_E~0); 1384#L1392-1true assume !(1 == ~E_M~0); 359#L1397-1true assume !(1 == ~E_1~0); 1502#L1402-1true assume !(1 == ~E_2~0); 180#L1407-1true assume !(1 == ~E_3~0); 1621#L1412-1true assume !(1 == ~E_4~0); 1058#L1417-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1793#L1422-1true assume !(1 == ~E_6~0); 1501#L1427-1true assume !(1 == ~E_7~0); 275#L1432-1true assume !(1 == ~E_8~0); 1389#L1437-1true assume !(1 == ~E_9~0); 986#L1442-1true assume !(1 == ~E_10~0); 1298#L1447-1true assume !(1 == ~E_11~0); 835#L1452-1true assume !(1 == ~E_12~0); 76#L1457-1true assume { :end_inline_reset_delta_events } true; 1437#L1803-2true [2021-12-15 17:21:00,739 INFO L793 eck$LassoCheckResult]: Loop: 1437#L1803-2true assume !false; 242#L1804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 316#L1169true assume false; 631#L1184true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1611#L834-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 609#L1194-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1639#L1194-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 162#L1199-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 885#L1204-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 288#L1209-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 13#L1214-3true assume !(0 == ~T5_E~0); 672#L1219-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 407#L1224-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1788#L1229-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 424#L1234-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 93#L1239-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 322#L1244-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 703#L1249-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1543#L1254-3true assume !(0 == ~E_M~0); 1348#L1259-3true assume 0 == ~E_1~0;~E_1~0 := 1; 819#L1264-3true assume 0 == ~E_2~0;~E_2~0 := 1; 96#L1269-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1608#L1274-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1435#L1279-3true assume 0 == ~E_5~0;~E_5~0 := 1; 406#L1284-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1494#L1289-3true assume 0 == ~E_7~0;~E_7~0 := 1; 395#L1294-3true assume !(0 == ~E_8~0); 1660#L1299-3true assume 0 == ~E_9~0;~E_9~0 := 1; 651#L1304-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1012#L1309-3true assume 0 == ~E_11~0;~E_11~0 := 1; 345#L1314-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1736#L1319-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349#L586-42true assume !(1 == ~m_pc~0); 892#L586-44true is_master_triggered_~__retres1~0#1 := 0; 130#L597-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1362#L598-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1427#L1485-42true assume !(0 != activate_threads_~tmp~1#1); 419#L1485-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 894#L605-42true assume 1 == ~t1_pc~0; 961#L606-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 624#L616-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 985#L617-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 420#L1493-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 471#L1493-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 426#L624-42true assume !(1 == ~t2_pc~0); 521#L624-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1447#L635-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55#L636-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1689#L1501-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 320#L1501-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1285#L643-42true assume 1 == ~t3_pc~0; 533#L644-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 508#L654-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 674#L655-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 403#L1509-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 995#L1509-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1310#L662-42true assume 1 == ~t4_pc~0; 1353#L663-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 141#L673-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 461#L674-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1474#L1517-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1414#L1517-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1327#L681-42true assume 1 == ~t5_pc~0; 540#L682-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 745#L692-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253#L693-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1622#L1525-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1067#L1525-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 337#L700-42true assume 1 == ~t6_pc~0; 513#L701-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 952#L711-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1772#L712-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1082#L1533-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1694#L1533-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1459#L719-42true assume 1 == ~t7_pc~0; 741#L720-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 371#L730-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 194#L731-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 531#L1541-42true assume !(0 != activate_threads_~tmp___6~0#1); 380#L1541-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1441#L738-42true assume !(1 == ~t8_pc~0); 1197#L738-44true is_transmit8_triggered_~__retres1~8#1 := 0; 354#L749-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115#L750-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95#L1549-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 373#L1549-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1242#L757-42true assume !(1 == ~t9_pc~0); 1332#L757-44true is_transmit9_triggered_~__retres1~9#1 := 0; 186#L768-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 259#L769-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 633#L1557-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 246#L1557-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1039#L776-42true assume 1 == ~t10_pc~0; 982#L777-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1027#L787-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1661#L788-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1599#L1565-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1786#L1565-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 789#L795-42true assume !(1 == ~t11_pc~0); 896#L795-44true is_transmit11_triggered_~__retres1~11#1 := 0; 167#L806-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1562#L807-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 213#L1573-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 386#L1573-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1119#L814-42true assume 1 == ~t12_pc~0; 1042#L815-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 122#L825-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1594#L826-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31#L1581-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1737#L1581-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103#L1332-3true assume 1 == ~M_E~0;~M_E~0 := 2; 699#L1332-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 90#L1337-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 554#L1342-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1034#L1347-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 676#L1352-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1193#L1357-3true assume !(1 == ~T6_E~0); 1779#L1362-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1644#L1367-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1612#L1372-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 22#L1377-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 429#L1382-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 333#L1387-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 992#L1392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1701#L1397-3true assume !(1 == ~E_1~0); 1493#L1402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 636#L1407-3true assume 1 == ~E_3~0;~E_3~0 := 2; 146#L1412-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1228#L1417-3true assume 1 == ~E_5~0;~E_5~0 := 2; 567#L1422-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1188#L1427-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1391#L1432-3true assume 1 == ~E_8~0;~E_8~0 := 2; 875#L1437-3true assume !(1 == ~E_9~0); 653#L1442-3true assume 1 == ~E_10~0;~E_10~0 := 2; 888#L1447-3true assume 1 == ~E_11~0;~E_11~0 := 2; 48#L1452-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1749#L1457-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 365#L914-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1402#L981-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 859#L982-1true start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 139#L1822true assume !(0 == start_simulation_~tmp~3#1); 736#L1822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 761#L914-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 271#L981-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 604#L982-2true stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 691#L1777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 792#L1784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 650#L1785true start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1235#L1835true assume !(0 != start_simulation_~tmp___0~1#1); 1437#L1803-2true [2021-12-15 17:21:00,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:00,749 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2021-12-15 17:21:00,754 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:00,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986713582] [2021-12-15 17:21:00,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:00,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:00,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:00,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:00,955 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:00,955 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986713582] [2021-12-15 17:21:00,956 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986713582] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:00,956 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:00,956 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:00,957 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015593833] [2021-12-15 17:21:00,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:00,961 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:00,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:00,962 INFO L85 PathProgramCache]: Analyzing trace with hash -481792425, now seen corresponding path program 1 times [2021-12-15 17:21:00,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:00,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953592860] [2021-12-15 17:21:00,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:00,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:00,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:00,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:00,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:00,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953592860] [2021-12-15 17:21:01,000 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953592860] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,000 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:01,000 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589697694] [2021-12-15 17:21:01,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,002 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:01,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:01,022 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-15 17:21:01,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-15 17:21:01,026 INFO L87 Difference]: Start difference. First operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:01,103 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2021-12-15 17:21:01,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-15 17:21:01,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2021-12-15 17:21:01,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:01,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1785 states and 2646 transitions. [2021-12-15 17:21:01,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:01,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:01,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2646 transitions. [2021-12-15 17:21:01,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:01,179 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2021-12-15 17:21:01,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2646 transitions. [2021-12-15 17:21:01,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:01,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4823529411764707) internal successors, (2646), 1784 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2646 transitions. [2021-12-15 17:21:01,256 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2021-12-15 17:21:01,256 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2021-12-15 17:21:01,256 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:21:01,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2646 transitions. [2021-12-15 17:21:01,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:01,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:01,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:01,265 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,266 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,266 INFO L791 eck$LassoCheckResult]: Stem: 4391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5173#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5174#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3911#L841 assume !(1 == ~m_i~0);~m_st~0 := 2; 3912#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3814#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3815#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5093#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4433#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4434#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4338#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4339#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4841#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4842#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4100#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4101#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4524#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4525#L1194 assume !(0 == ~M_E~0); 4673#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4674#L1199-1 assume !(0 == ~T2_E~0); 4971#L1204-1 assume !(0 == ~T3_E~0); 4895#L1209-1 assume !(0 == ~T4_E~0); 4896#L1214-1 assume !(0 == ~T5_E~0); 5281#L1219-1 assume !(0 == ~T6_E~0); 5369#L1224-1 assume !(0 == ~T7_E~0); 4174#L1229-1 assume !(0 == ~T8_E~0); 3731#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3732#L1239-1 assume !(0 == ~T10_E~0); 3774#L1244-1 assume !(0 == ~T11_E~0); 3775#L1249-1 assume !(0 == ~T12_E~0); 4468#L1254-1 assume !(0 == ~E_M~0); 3678#L1259-1 assume !(0 == ~E_1~0); 3642#L1264-1 assume !(0 == ~E_2~0); 3643#L1269-1 assume !(0 == ~E_3~0); 5372#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5311#L1279-1 assume !(0 == ~E_5~0); 3852#L1284-1 assume !(0 == ~E_6~0); 3853#L1289-1 assume !(0 == ~E_7~0); 4531#L1294-1 assume !(0 == ~E_8~0); 4532#L1299-1 assume !(0 == ~E_9~0); 4542#L1304-1 assume !(0 == ~E_10~0); 5363#L1309-1 assume !(0 == ~E_11~0); 5367#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3806#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3728#L586 assume 1 == ~m_pc~0; 3729#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3800#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4865#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4008#L1485 assume !(0 != activate_threads_~tmp~1#1); 4009#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5096#L605 assume !(1 == ~t1_pc~0); 4612#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4363#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4364#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5246#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4942#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4281#L624 assume 1 == ~t2_pc~0; 3780#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3781#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4441#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5270#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 5133#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5011#L643 assume !(1 == ~t3_pc~0); 4858#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4554#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4467#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4110#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 4111#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3872#L662 assume 1 == ~t4_pc~0; 3873#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3831#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3832#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4586#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 3715#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3716#L681 assume !(1 == ~t5_pc~0); 3590#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3591#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4638#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5240#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 4122#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4123#L700 assume 1 == ~t6_pc~0; 4822#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3863#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3864#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3913#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 3914#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5177#L719 assume 1 == ~t7_pc~0; 5251#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4080#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4850#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4851#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 3604#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3605#L738 assume !(1 == ~t8_pc~0); 4977#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4887#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3973#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3974#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4670#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5034#L757 assume 1 == ~t9_pc~0; 5035#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3599#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3600#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4802#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 4630#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4631#L776 assume !(1 == ~t10_pc~0); 3624#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3623#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4012#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3854#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 3855#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3807#L795 assume 1 == ~t11_pc~0; 3808#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4141#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5085#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5086#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 4856#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4844#L814 assume !(1 == ~t12_pc~0); 4699#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4700#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5070#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5170#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 4065#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4066#L1332 assume !(1 == ~M_E~0); 5144#L1332-2 assume !(1 == ~T1_E~0); 5327#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4769#L1342-1 assume !(1 == ~T3_E~0); 4770#L1347-1 assume !(1 == ~T4_E~0); 5165#L1352-1 assume !(1 == ~T5_E~0); 5040#L1357-1 assume !(1 == ~T6_E~0); 4334#L1362-1 assume !(1 == ~T7_E~0); 4335#L1367-1 assume !(1 == ~T8_E~0); 3948#L1372-1 assume !(1 == ~T9_E~0); 3949#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4254#L1382-1 assume !(1 == ~T11_E~0); 4255#L1387-1 assume !(1 == ~T12_E~0); 4940#L1392-1 assume !(1 == ~E_M~0); 4282#L1397-1 assume !(1 == ~E_1~0); 4283#L1402-1 assume !(1 == ~E_2~0); 3959#L1407-1 assume !(1 == ~E_3~0); 3960#L1412-1 assume !(1 == ~E_4~0); 5111#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5112#L1422-1 assume !(1 == ~E_6~0); 5328#L1427-1 assume !(1 == ~E_7~0); 4142#L1432-1 assume !(1 == ~E_8~0); 4143#L1437-1 assume !(1 == ~E_9~0); 5061#L1442-1 assume !(1 == ~E_10~0); 5062#L1447-1 assume !(1 == ~E_11~0); 4930#L1452-1 assume !(1 == ~E_12~0); 3748#L1457-1 assume { :end_inline_reset_delta_events } true; 3749#L1803-2 [2021-12-15 17:21:01,267 INFO L793 eck$LassoCheckResult]: Loop: 3749#L1803-2 assume !false; 4085#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3621#L1169 assume !false; 4210#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4315#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3816#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3817#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4592#L996 assume !(0 != eval_~tmp~0#1); 4704#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4705#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4675#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4676#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3920#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3921#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4169#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3613#L1214-3 assume !(0 == ~T5_E~0); 3614#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4361#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4362#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4393#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3786#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3787#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4218#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4795#L1254-3 assume !(0 == ~E_M~0); 5275#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4910#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3792#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3793#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5307#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4359#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4360#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4343#L1294-3 assume !(0 == ~E_8~0); 4344#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4726#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4727#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4256#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4257#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4265#L586-42 assume !(1 == ~m_pc~0); 4266#L586-44 is_master_triggered_~__retres1~0#1 := 0; 3861#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3862#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5286#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 4383#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4384#L605-42 assume 1 == ~t1_pc~0; 4981#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4689#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4690#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4385#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4386#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4397#L624-42 assume !(1 == ~t2_pc~0); 4398#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4541#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3701#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3702#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4215#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4216#L643-42 assume 1 == ~t3_pc~0; 4557#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4522#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4523#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4355#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4356#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5071#L662-42 assume !(1 == ~t4_pc~0); 5264#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3884#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3885#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4451#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5303#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5269#L681-42 assume !(1 == ~t5_pc~0); 3744#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 3745#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4104#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4105#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5119#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4241#L700-42 assume 1 == ~t6_pc~0; 4242#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4052#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5041#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5127#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5128#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5317#L719-42 assume !(1 == ~t7_pc~0); 3936#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 3937#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3987#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3988#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 4318#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4319#L738-42 assume !(1 == ~t8_pc~0); 4512#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4274#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3827#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3790#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3791#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4311#L757-42 assume 1 == ~t9_pc~0; 4647#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3971#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3972#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4115#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4089#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4090#L776-42 assume 1 == ~t10_pc~0; 5060#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5047#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5094#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5356#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5357#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4884#L795-42 assume !(1 == ~t11_pc~0); 4885#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3931#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3932#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4027#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4028#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4328#L814-42 assume 1 == ~t12_pc~0; 5099#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3843#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3844#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3652#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3653#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3804#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3805#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3778#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3779#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4587#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4758#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4759#L1357-3 assume !(1 == ~T6_E~0); 5197#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5365#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5361#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3633#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3634#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4237#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4238#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5068#L1397-3 assume !(1 == ~E_1~0); 5326#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4709#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3889#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3890#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4606#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4607#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5196#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4965#L1437-3 assume !(1 == ~E_9~0); 4728#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4729#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3687#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3688#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4293#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4139#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4951#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 3880#L1822 assume !(0 == start_simulation_~tmp~3#1); 3881#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4830#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4135#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4136#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 4667#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4779#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4724#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4725#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 3749#L1803-2 [2021-12-15 17:21:01,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,268 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2021-12-15 17:21:01,268 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962539562] [2021-12-15 17:21:01,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,269 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,319 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,319 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962539562] [2021-12-15 17:21:01,320 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962539562] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,320 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,320 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:01,320 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537969761] [2021-12-15 17:21:01,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,321 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:01,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,322 INFO L85 PathProgramCache]: Analyzing trace with hash 213897014, now seen corresponding path program 1 times [2021-12-15 17:21:01,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217682022] [2021-12-15 17:21:01,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,471 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217682022] [2021-12-15 17:21:01,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217682022] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,471 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,471 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:01,472 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493339947] [2021-12-15 17:21:01,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,472 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:01,472 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:01,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:01,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:01,473 INFO L87 Difference]: Start difference. First operand 1785 states and 2646 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:01,585 INFO L93 Difference]: Finished difference Result 1785 states and 2645 transitions. [2021-12-15 17:21:01,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:01,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2645 transitions. [2021-12-15 17:21:01,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:01,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2645 transitions. [2021-12-15 17:21:01,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:01,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:01,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2645 transitions. [2021-12-15 17:21:01,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:01,615 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2021-12-15 17:21:01,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2645 transitions. [2021-12-15 17:21:01,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:01,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4817927170868348) internal successors, (2645), 1784 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2645 transitions. [2021-12-15 17:21:01,640 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2021-12-15 17:21:01,640 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2021-12-15 17:21:01,640 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:21:01,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2645 transitions. [2021-12-15 17:21:01,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:01,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:01,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:01,651 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,651 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,653 INFO L791 eck$LassoCheckResult]: Stem: 7968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8750#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8751#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7488#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 7489#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7391#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7392#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8670#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8010#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8011#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7915#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7916#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8418#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8419#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7677#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7678#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8101#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8102#L1194 assume !(0 == ~M_E~0); 8250#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8251#L1199-1 assume !(0 == ~T2_E~0); 8548#L1204-1 assume !(0 == ~T3_E~0); 8472#L1209-1 assume !(0 == ~T4_E~0); 8473#L1214-1 assume !(0 == ~T5_E~0); 8858#L1219-1 assume !(0 == ~T6_E~0); 8946#L1224-1 assume !(0 == ~T7_E~0); 7751#L1229-1 assume !(0 == ~T8_E~0); 7308#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7309#L1239-1 assume !(0 == ~T10_E~0); 7351#L1244-1 assume !(0 == ~T11_E~0); 7352#L1249-1 assume !(0 == ~T12_E~0); 8045#L1254-1 assume !(0 == ~E_M~0); 7255#L1259-1 assume !(0 == ~E_1~0); 7219#L1264-1 assume !(0 == ~E_2~0); 7220#L1269-1 assume !(0 == ~E_3~0); 8949#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8888#L1279-1 assume !(0 == ~E_5~0); 7429#L1284-1 assume !(0 == ~E_6~0); 7430#L1289-1 assume !(0 == ~E_7~0); 8108#L1294-1 assume !(0 == ~E_8~0); 8109#L1299-1 assume !(0 == ~E_9~0); 8119#L1304-1 assume !(0 == ~E_10~0); 8940#L1309-1 assume !(0 == ~E_11~0); 8944#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7383#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7305#L586 assume 1 == ~m_pc~0; 7306#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7377#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8442#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7585#L1485 assume !(0 != activate_threads_~tmp~1#1); 7586#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8673#L605 assume !(1 == ~t1_pc~0); 8189#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7940#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7941#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8823#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8519#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7858#L624 assume 1 == ~t2_pc~0; 7357#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7358#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8018#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8847#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 8710#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8588#L643 assume !(1 == ~t3_pc~0); 8435#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8131#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8044#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7687#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 7688#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7449#L662 assume 1 == ~t4_pc~0; 7450#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7408#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7409#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8163#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 7292#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7293#L681 assume !(1 == ~t5_pc~0); 7167#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7168#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8215#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8817#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 7699#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7700#L700 assume 1 == ~t6_pc~0; 8399#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7440#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7441#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7490#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 7491#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8754#L719 assume 1 == ~t7_pc~0; 8828#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7657#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8427#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8428#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 7181#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7182#L738 assume !(1 == ~t8_pc~0); 8554#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8464#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7550#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7551#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8247#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8611#L757 assume 1 == ~t9_pc~0; 8612#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7176#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7177#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8379#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 8207#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8208#L776 assume !(1 == ~t10_pc~0); 7201#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7200#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7589#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7431#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 7432#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7384#L795 assume 1 == ~t11_pc~0; 7385#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7718#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8662#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8663#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 8433#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8421#L814 assume !(1 == ~t12_pc~0); 8276#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8277#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8647#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8747#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 7642#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7643#L1332 assume !(1 == ~M_E~0); 8721#L1332-2 assume !(1 == ~T1_E~0); 8904#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8346#L1342-1 assume !(1 == ~T3_E~0); 8347#L1347-1 assume !(1 == ~T4_E~0); 8742#L1352-1 assume !(1 == ~T5_E~0); 8617#L1357-1 assume !(1 == ~T6_E~0); 7911#L1362-1 assume !(1 == ~T7_E~0); 7912#L1367-1 assume !(1 == ~T8_E~0); 7525#L1372-1 assume !(1 == ~T9_E~0); 7526#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7831#L1382-1 assume !(1 == ~T11_E~0); 7832#L1387-1 assume !(1 == ~T12_E~0); 8517#L1392-1 assume !(1 == ~E_M~0); 7859#L1397-1 assume !(1 == ~E_1~0); 7860#L1402-1 assume !(1 == ~E_2~0); 7536#L1407-1 assume !(1 == ~E_3~0); 7537#L1412-1 assume !(1 == ~E_4~0); 8688#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8689#L1422-1 assume !(1 == ~E_6~0); 8905#L1427-1 assume !(1 == ~E_7~0); 7719#L1432-1 assume !(1 == ~E_8~0); 7720#L1437-1 assume !(1 == ~E_9~0); 8638#L1442-1 assume !(1 == ~E_10~0); 8639#L1447-1 assume !(1 == ~E_11~0); 8507#L1452-1 assume !(1 == ~E_12~0); 7325#L1457-1 assume { :end_inline_reset_delta_events } true; 7326#L1803-2 [2021-12-15 17:21:01,653 INFO L793 eck$LassoCheckResult]: Loop: 7326#L1803-2 assume !false; 7662#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7198#L1169 assume !false; 7787#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7892#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7393#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7394#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8169#L996 assume !(0 != eval_~tmp~0#1); 8281#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8282#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8252#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8253#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7497#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7498#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7746#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7190#L1214-3 assume !(0 == ~T5_E~0); 7191#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7938#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7939#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7970#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7363#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7364#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7795#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8372#L1254-3 assume !(0 == ~E_M~0); 8852#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8487#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7369#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7370#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8884#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7936#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7937#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7920#L1294-3 assume !(0 == ~E_8~0); 7921#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8303#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8304#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7833#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7834#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7842#L586-42 assume !(1 == ~m_pc~0); 7843#L586-44 is_master_triggered_~__retres1~0#1 := 0; 7438#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7439#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8863#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 7960#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7961#L605-42 assume 1 == ~t1_pc~0; 8558#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8266#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8267#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7962#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7963#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L624-42 assume !(1 == ~t2_pc~0); 7975#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8118#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7278#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7279#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7792#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7793#L643-42 assume 1 == ~t3_pc~0; 8134#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8099#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8100#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7932#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7933#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8648#L662-42 assume !(1 == ~t4_pc~0); 8841#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7461#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7462#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8028#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8880#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8846#L681-42 assume 1 == ~t5_pc~0; 8144#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7322#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7681#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7682#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8696#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7818#L700-42 assume 1 == ~t6_pc~0; 7819#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7629#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8618#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8704#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8705#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8894#L719-42 assume !(1 == ~t7_pc~0); 7513#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7514#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7564#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7565#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 7895#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7896#L738-42 assume 1 == ~t8_pc~0; 8088#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7851#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7404#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7367#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7368#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7888#L757-42 assume 1 == ~t9_pc~0; 8224#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7548#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7549#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7692#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7666#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7667#L776-42 assume 1 == ~t10_pc~0; 8637#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8624#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8671#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8933#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8934#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8461#L795-42 assume !(1 == ~t11_pc~0); 8462#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7508#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7509#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7604#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7605#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7905#L814-42 assume 1 == ~t12_pc~0; 8676#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7420#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7421#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7229#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7230#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7381#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7382#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7355#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7356#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8164#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8335#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8336#L1357-3 assume !(1 == ~T6_E~0); 8774#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8942#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8938#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7210#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7211#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7814#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 7815#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8645#L1397-3 assume !(1 == ~E_1~0); 8903#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8286#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7466#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7467#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8183#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8184#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8773#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8542#L1437-3 assume !(1 == ~E_9~0); 8305#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8306#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7264#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7265#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7870#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7716#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8528#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7457#L1822 assume !(0 == start_simulation_~tmp~3#1); 7458#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8407#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7712#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7713#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 8244#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8356#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8301#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8302#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 7326#L1803-2 [2021-12-15 17:21:01,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,656 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2021-12-15 17:21:01,656 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,656 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752351914] [2021-12-15 17:21:01,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,657 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752351914] [2021-12-15 17:21:01,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752351914] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,715 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,716 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:01,716 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101339535] [2021-12-15 17:21:01,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,717 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:01,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,718 INFO L85 PathProgramCache]: Analyzing trace with hash 561508340, now seen corresponding path program 1 times [2021-12-15 17:21:01,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895529560] [2021-12-15 17:21:01,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,802 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895529560] [2021-12-15 17:21:01,802 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895529560] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,803 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,803 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:01,803 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280316946] [2021-12-15 17:21:01,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,803 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:01,804 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:01,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:01,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:01,805 INFO L87 Difference]: Start difference. First operand 1785 states and 2645 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:01,825 INFO L93 Difference]: Finished difference Result 1785 states and 2644 transitions. [2021-12-15 17:21:01,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:01,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2644 transitions. [2021-12-15 17:21:01,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:01,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2644 transitions. [2021-12-15 17:21:01,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:01,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:01,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2644 transitions. [2021-12-15 17:21:01,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:01,846 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2021-12-15 17:21:01,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2644 transitions. [2021-12-15 17:21:01,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:01,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.481232492997199) internal successors, (2644), 1784 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:01,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2644 transitions. [2021-12-15 17:21:01,871 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2021-12-15 17:21:01,871 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2021-12-15 17:21:01,871 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:21:01,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2644 transitions. [2021-12-15 17:21:01,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:01,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:01,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:01,884 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:01,884 INFO L791 eck$LassoCheckResult]: Stem: 11545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 12327#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12328#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11065#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 11066#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10968#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10969#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12247#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11587#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11588#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11492#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11493#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11995#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11996#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11254#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11255#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11678#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11679#L1194 assume !(0 == ~M_E~0); 11827#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11828#L1199-1 assume !(0 == ~T2_E~0); 12125#L1204-1 assume !(0 == ~T3_E~0); 12049#L1209-1 assume !(0 == ~T4_E~0); 12050#L1214-1 assume !(0 == ~T5_E~0); 12435#L1219-1 assume !(0 == ~T6_E~0); 12523#L1224-1 assume !(0 == ~T7_E~0); 11328#L1229-1 assume !(0 == ~T8_E~0); 10885#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10886#L1239-1 assume !(0 == ~T10_E~0); 10928#L1244-1 assume !(0 == ~T11_E~0); 10929#L1249-1 assume !(0 == ~T12_E~0); 11622#L1254-1 assume !(0 == ~E_M~0); 10832#L1259-1 assume !(0 == ~E_1~0); 10796#L1264-1 assume !(0 == ~E_2~0); 10797#L1269-1 assume !(0 == ~E_3~0); 12526#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12465#L1279-1 assume !(0 == ~E_5~0); 11006#L1284-1 assume !(0 == ~E_6~0); 11007#L1289-1 assume !(0 == ~E_7~0); 11685#L1294-1 assume !(0 == ~E_8~0); 11686#L1299-1 assume !(0 == ~E_9~0); 11696#L1304-1 assume !(0 == ~E_10~0); 12517#L1309-1 assume !(0 == ~E_11~0); 12521#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 10960#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10882#L586 assume 1 == ~m_pc~0; 10883#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10954#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12019#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11162#L1485 assume !(0 != activate_threads_~tmp~1#1); 11163#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12250#L605 assume !(1 == ~t1_pc~0); 11766#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11517#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11518#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12400#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12096#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11435#L624 assume 1 == ~t2_pc~0; 10934#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10935#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11595#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12424#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 12287#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12165#L643 assume !(1 == ~t3_pc~0); 12012#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11708#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11621#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11264#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 11265#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11026#L662 assume 1 == ~t4_pc~0; 11027#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10985#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10986#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11740#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 10869#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10870#L681 assume !(1 == ~t5_pc~0); 10744#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10745#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11792#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12394#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 11276#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11277#L700 assume 1 == ~t6_pc~0; 11976#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11017#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11018#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11067#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 11068#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12331#L719 assume 1 == ~t7_pc~0; 12405#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11234#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12004#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12005#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 10758#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10759#L738 assume !(1 == ~t8_pc~0); 12131#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12041#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11127#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11128#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11824#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12188#L757 assume 1 == ~t9_pc~0; 12189#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10753#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10754#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11956#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 11784#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11785#L776 assume !(1 == ~t10_pc~0); 10778#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10777#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11166#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11008#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 11009#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10961#L795 assume 1 == ~t11_pc~0; 10962#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11295#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12239#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12240#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 12010#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11998#L814 assume !(1 == ~t12_pc~0); 11853#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11854#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12224#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12324#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 11219#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11220#L1332 assume !(1 == ~M_E~0); 12298#L1332-2 assume !(1 == ~T1_E~0); 12481#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11923#L1342-1 assume !(1 == ~T3_E~0); 11924#L1347-1 assume !(1 == ~T4_E~0); 12319#L1352-1 assume !(1 == ~T5_E~0); 12194#L1357-1 assume !(1 == ~T6_E~0); 11488#L1362-1 assume !(1 == ~T7_E~0); 11489#L1367-1 assume !(1 == ~T8_E~0); 11102#L1372-1 assume !(1 == ~T9_E~0); 11103#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11408#L1382-1 assume !(1 == ~T11_E~0); 11409#L1387-1 assume !(1 == ~T12_E~0); 12094#L1392-1 assume !(1 == ~E_M~0); 11436#L1397-1 assume !(1 == ~E_1~0); 11437#L1402-1 assume !(1 == ~E_2~0); 11113#L1407-1 assume !(1 == ~E_3~0); 11114#L1412-1 assume !(1 == ~E_4~0); 12265#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12266#L1422-1 assume !(1 == ~E_6~0); 12482#L1427-1 assume !(1 == ~E_7~0); 11296#L1432-1 assume !(1 == ~E_8~0); 11297#L1437-1 assume !(1 == ~E_9~0); 12215#L1442-1 assume !(1 == ~E_10~0); 12216#L1447-1 assume !(1 == ~E_11~0); 12084#L1452-1 assume !(1 == ~E_12~0); 10902#L1457-1 assume { :end_inline_reset_delta_events } true; 10903#L1803-2 [2021-12-15 17:21:01,885 INFO L793 eck$LassoCheckResult]: Loop: 10903#L1803-2 assume !false; 11239#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10775#L1169 assume !false; 11364#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11469#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10970#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10971#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11746#L996 assume !(0 != eval_~tmp~0#1); 11858#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11859#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11829#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11830#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11074#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11075#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11323#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10767#L1214-3 assume !(0 == ~T5_E~0); 10768#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11515#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11516#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11547#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10940#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10941#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11372#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11949#L1254-3 assume !(0 == ~E_M~0); 12429#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12064#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10946#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10947#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12461#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11513#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11514#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11497#L1294-3 assume !(0 == ~E_8~0); 11498#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11880#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11881#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11410#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11411#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11419#L586-42 assume !(1 == ~m_pc~0); 11420#L586-44 is_master_triggered_~__retres1~0#1 := 0; 11015#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11016#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12440#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 11537#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11538#L605-42 assume 1 == ~t1_pc~0; 12135#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11843#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11844#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11539#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11540#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11551#L624-42 assume !(1 == ~t2_pc~0); 11552#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11695#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10855#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10856#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11369#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11370#L643-42 assume !(1 == ~t3_pc~0); 11712#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 11676#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11677#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11509#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11510#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12225#L662-42 assume !(1 == ~t4_pc~0); 12418#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 11038#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11039#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11605#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12457#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12423#L681-42 assume !(1 == ~t5_pc~0); 10898#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 10899#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11258#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11259#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12273#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11395#L700-42 assume 1 == ~t6_pc~0; 11396#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11206#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12195#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12281#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12282#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12471#L719-42 assume !(1 == ~t7_pc~0); 11090#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11091#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11141#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11142#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 11472#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11473#L738-42 assume 1 == ~t8_pc~0; 11665#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11428#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10981#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10944#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10945#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11465#L757-42 assume 1 == ~t9_pc~0; 11801#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11125#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11126#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11269#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11243#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11244#L776-42 assume 1 == ~t10_pc~0; 12214#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12201#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12248#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12510#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12511#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12038#L795-42 assume !(1 == ~t11_pc~0); 12039#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11085#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11086#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11181#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11182#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11482#L814-42 assume 1 == ~t12_pc~0; 12253#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10997#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10998#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10806#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10807#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10958#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10959#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10932#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10933#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11741#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11912#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11913#L1357-3 assume !(1 == ~T6_E~0); 12351#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12519#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12515#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10787#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10788#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11391#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11392#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12222#L1397-3 assume !(1 == ~E_1~0); 12480#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11863#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11043#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11044#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11760#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11761#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12350#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12119#L1437-3 assume !(1 == ~E_9~0); 11882#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11883#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10841#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 10842#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11447#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11293#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 12105#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11034#L1822 assume !(0 == start_simulation_~tmp~3#1); 11035#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11984#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11289#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11290#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 11821#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11933#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11878#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11879#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 10903#L1803-2 [2021-12-15 17:21:01,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,886 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2021-12-15 17:21:01,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937160485] [2021-12-15 17:21:01,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,922 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,923 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937160485] [2021-12-15 17:21:01,923 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937160485] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,923 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,924 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:01,926 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771362318] [2021-12-15 17:21:01,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,926 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:01,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:01,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1260668790, now seen corresponding path program 1 times [2021-12-15 17:21:01,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:01,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911598611] [2021-12-15 17:21:01,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:01,930 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:01,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:01,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:01,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:01,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911598611] [2021-12-15 17:21:01,976 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911598611] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:01,976 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:01,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:01,977 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414485770] [2021-12-15 17:21:01,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:01,977 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:01,977 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:01,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:01,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:01,979 INFO L87 Difference]: Start difference. First operand 1785 states and 2644 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,029 INFO L93 Difference]: Finished difference Result 1785 states and 2643 transitions. [2021-12-15 17:21:02,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:02,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2643 transitions. [2021-12-15 17:21:02,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2643 transitions. [2021-12-15 17:21:02,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:02,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:02,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2643 transitions. [2021-12-15 17:21:02,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,049 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2021-12-15 17:21:02,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2643 transitions. [2021-12-15 17:21:02,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:02,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.480672268907563) internal successors, (2643), 1784 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2643 transitions. [2021-12-15 17:21:02,075 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2021-12-15 17:21:02,075 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2021-12-15 17:21:02,075 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:21:02,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2643 transitions. [2021-12-15 17:21:02,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,083 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,083 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,084 INFO L791 eck$LassoCheckResult]: Stem: 15122#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15904#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15905#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14642#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 14643#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14545#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14546#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15824#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15164#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15165#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15069#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15070#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15572#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15573#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14831#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14832#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15255#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15256#L1194 assume !(0 == ~M_E~0); 15404#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15405#L1199-1 assume !(0 == ~T2_E~0); 15702#L1204-1 assume !(0 == ~T3_E~0); 15626#L1209-1 assume !(0 == ~T4_E~0); 15627#L1214-1 assume !(0 == ~T5_E~0); 16012#L1219-1 assume !(0 == ~T6_E~0); 16100#L1224-1 assume !(0 == ~T7_E~0); 14905#L1229-1 assume !(0 == ~T8_E~0); 14462#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14463#L1239-1 assume !(0 == ~T10_E~0); 14505#L1244-1 assume !(0 == ~T11_E~0); 14506#L1249-1 assume !(0 == ~T12_E~0); 15199#L1254-1 assume !(0 == ~E_M~0); 14409#L1259-1 assume !(0 == ~E_1~0); 14373#L1264-1 assume !(0 == ~E_2~0); 14374#L1269-1 assume !(0 == ~E_3~0); 16103#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16042#L1279-1 assume !(0 == ~E_5~0); 14583#L1284-1 assume !(0 == ~E_6~0); 14584#L1289-1 assume !(0 == ~E_7~0); 15262#L1294-1 assume !(0 == ~E_8~0); 15263#L1299-1 assume !(0 == ~E_9~0); 15273#L1304-1 assume !(0 == ~E_10~0); 16094#L1309-1 assume !(0 == ~E_11~0); 16098#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14537#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14459#L586 assume 1 == ~m_pc~0; 14460#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14531#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15596#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14739#L1485 assume !(0 != activate_threads_~tmp~1#1); 14740#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15827#L605 assume !(1 == ~t1_pc~0); 15343#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15094#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15095#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15977#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15673#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15012#L624 assume 1 == ~t2_pc~0; 14511#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14512#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15172#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16001#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 15864#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15742#L643 assume !(1 == ~t3_pc~0); 15589#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15285#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15198#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14841#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 14842#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14603#L662 assume 1 == ~t4_pc~0; 14604#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14562#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14563#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15317#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 14446#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14447#L681 assume !(1 == ~t5_pc~0); 14321#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14322#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15369#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15971#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 14853#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14854#L700 assume 1 == ~t6_pc~0; 15553#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14594#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14595#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14644#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 14645#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15908#L719 assume 1 == ~t7_pc~0; 15982#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14811#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15581#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15582#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 14335#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14336#L738 assume !(1 == ~t8_pc~0); 15708#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15618#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14704#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14705#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15401#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15765#L757 assume 1 == ~t9_pc~0; 15766#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14330#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14331#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15533#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 15361#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15362#L776 assume !(1 == ~t10_pc~0); 14355#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14354#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14743#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14585#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 14586#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14538#L795 assume 1 == ~t11_pc~0; 14539#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14872#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15816#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15817#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 15587#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15575#L814 assume !(1 == ~t12_pc~0); 15430#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15431#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15801#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15901#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 14796#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14797#L1332 assume !(1 == ~M_E~0); 15875#L1332-2 assume !(1 == ~T1_E~0); 16058#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15500#L1342-1 assume !(1 == ~T3_E~0); 15501#L1347-1 assume !(1 == ~T4_E~0); 15896#L1352-1 assume !(1 == ~T5_E~0); 15771#L1357-1 assume !(1 == ~T6_E~0); 15065#L1362-1 assume !(1 == ~T7_E~0); 15066#L1367-1 assume !(1 == ~T8_E~0); 14679#L1372-1 assume !(1 == ~T9_E~0); 14680#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14985#L1382-1 assume !(1 == ~T11_E~0); 14986#L1387-1 assume !(1 == ~T12_E~0); 15671#L1392-1 assume !(1 == ~E_M~0); 15013#L1397-1 assume !(1 == ~E_1~0); 15014#L1402-1 assume !(1 == ~E_2~0); 14690#L1407-1 assume !(1 == ~E_3~0); 14691#L1412-1 assume !(1 == ~E_4~0); 15842#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15843#L1422-1 assume !(1 == ~E_6~0); 16059#L1427-1 assume !(1 == ~E_7~0); 14873#L1432-1 assume !(1 == ~E_8~0); 14874#L1437-1 assume !(1 == ~E_9~0); 15792#L1442-1 assume !(1 == ~E_10~0); 15793#L1447-1 assume !(1 == ~E_11~0); 15661#L1452-1 assume !(1 == ~E_12~0); 14479#L1457-1 assume { :end_inline_reset_delta_events } true; 14480#L1803-2 [2021-12-15 17:21:02,084 INFO L793 eck$LassoCheckResult]: Loop: 14480#L1803-2 assume !false; 14816#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14352#L1169 assume !false; 14941#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15046#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14547#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14548#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15323#L996 assume !(0 != eval_~tmp~0#1); 15435#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15436#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15406#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15407#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14651#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14652#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14900#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14344#L1214-3 assume !(0 == ~T5_E~0); 14345#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15092#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15093#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15124#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14517#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14518#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14949#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 15526#L1254-3 assume !(0 == ~E_M~0); 16006#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15641#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14523#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14524#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16038#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15090#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15091#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15074#L1294-3 assume !(0 == ~E_8~0); 15075#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15457#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15458#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14987#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14988#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14996#L586-42 assume !(1 == ~m_pc~0); 14997#L586-44 is_master_triggered_~__retres1~0#1 := 0; 14592#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14593#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16017#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 15114#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15115#L605-42 assume 1 == ~t1_pc~0; 15712#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15420#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15421#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15116#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15117#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15128#L624-42 assume !(1 == ~t2_pc~0); 15129#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15272#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14432#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14433#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14946#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14947#L643-42 assume 1 == ~t3_pc~0; 15288#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15253#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15254#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15086#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15087#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15802#L662-42 assume !(1 == ~t4_pc~0); 15995#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14615#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14616#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15182#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16034#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16000#L681-42 assume 1 == ~t5_pc~0; 15298#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14476#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14835#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14836#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15850#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14972#L700-42 assume 1 == ~t6_pc~0; 14973#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14783#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15772#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15858#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15859#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16048#L719-42 assume 1 == ~t7_pc~0; 15569#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14668#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14718#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14719#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 15049#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15050#L738-42 assume 1 == ~t8_pc~0; 15242#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15005#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14558#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14521#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14522#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15042#L757-42 assume 1 == ~t9_pc~0; 15378#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14702#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14703#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14846#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14820#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14821#L776-42 assume !(1 == ~t10_pc~0); 15777#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 15778#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15825#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16087#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16088#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15615#L795-42 assume !(1 == ~t11_pc~0); 15616#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 14662#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14663#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14758#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14759#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15059#L814-42 assume 1 == ~t12_pc~0; 15830#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14574#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14575#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14383#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14384#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14535#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14536#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14509#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14510#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15318#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15489#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15490#L1357-3 assume !(1 == ~T6_E~0); 15928#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16096#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16092#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14364#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14365#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14968#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14969#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15799#L1397-3 assume !(1 == ~E_1~0); 16057#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15440#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14620#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14621#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15337#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15338#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15927#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15696#L1437-3 assume !(1 == ~E_9~0); 15459#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15460#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14418#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14419#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15024#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14870#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15682#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14611#L1822 assume !(0 == start_simulation_~tmp~3#1); 14612#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15561#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14866#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14867#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 15398#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15510#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15455#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15456#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 14480#L1803-2 [2021-12-15 17:21:02,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,085 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2021-12-15 17:21:02,085 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026840562] [2021-12-15 17:21:02,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,085 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,111 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2026840562] [2021-12-15 17:21:02,111 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2026840562] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,111 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,111 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,111 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237907199] [2021-12-15 17:21:02,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,112 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:02,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,112 INFO L85 PathProgramCache]: Analyzing trace with hash 660676148, now seen corresponding path program 1 times [2021-12-15 17:21:02,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,113 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522780412] [2021-12-15 17:21:02,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,145 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,146 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522780412] [2021-12-15 17:21:02,146 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522780412] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,146 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,146 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,146 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867808763] [2021-12-15 17:21:02,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,147 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:02,147 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:02,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:02,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:02,148 INFO L87 Difference]: Start difference. First operand 1785 states and 2643 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,168 INFO L93 Difference]: Finished difference Result 1785 states and 2642 transitions. [2021-12-15 17:21:02,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:02,170 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2642 transitions. [2021-12-15 17:21:02,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2642 transitions. [2021-12-15 17:21:02,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:02,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:02,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2642 transitions. [2021-12-15 17:21:02,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,192 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2021-12-15 17:21:02,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2642 transitions. [2021-12-15 17:21:02,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:02,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4801120448179272) internal successors, (2642), 1784 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2642 transitions. [2021-12-15 17:21:02,217 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2021-12-15 17:21:02,217 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2021-12-15 17:21:02,217 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:21:02,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2642 transitions. [2021-12-15 17:21:02,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,224 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,224 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,224 INFO L791 eck$LassoCheckResult]: Stem: 18706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19481#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19482#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18219#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 18220#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18122#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18123#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19401#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18741#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18742#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18646#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18647#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19149#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19150#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18408#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18409#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18834#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18835#L1194 assume !(0 == ~M_E~0); 18981#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18982#L1199-1 assume !(0 == ~T2_E~0); 19279#L1204-1 assume !(0 == ~T3_E~0); 19203#L1209-1 assume !(0 == ~T4_E~0); 19204#L1214-1 assume !(0 == ~T5_E~0); 19589#L1219-1 assume !(0 == ~T6_E~0); 19677#L1224-1 assume !(0 == ~T7_E~0); 18482#L1229-1 assume !(0 == ~T8_E~0); 18047#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18048#L1239-1 assume !(0 == ~T10_E~0); 18086#L1244-1 assume !(0 == ~T11_E~0); 18087#L1249-1 assume !(0 == ~T12_E~0); 18776#L1254-1 assume !(0 == ~E_M~0); 17986#L1259-1 assume !(0 == ~E_1~0); 17950#L1264-1 assume !(0 == ~E_2~0); 17951#L1269-1 assume !(0 == ~E_3~0); 19680#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19619#L1279-1 assume !(0 == ~E_5~0); 18160#L1284-1 assume !(0 == ~E_6~0); 18161#L1289-1 assume !(0 == ~E_7~0); 18840#L1294-1 assume !(0 == ~E_8~0); 18841#L1299-1 assume !(0 == ~E_9~0); 18852#L1304-1 assume !(0 == ~E_10~0); 19671#L1309-1 assume !(0 == ~E_11~0); 19675#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18115#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18036#L586 assume 1 == ~m_pc~0; 18037#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18108#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19175#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18316#L1485 assume !(0 != activate_threads_~tmp~1#1); 18317#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19404#L605 assume !(1 == ~t1_pc~0); 18920#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18671#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18672#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19554#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19251#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18589#L624 assume 1 == ~t2_pc~0; 18091#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18092#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18749#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19578#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 19441#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19319#L643 assume !(1 == ~t3_pc~0); 19166#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18868#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18775#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18418#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 18419#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18180#L662 assume 1 == ~t4_pc~0; 18181#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18141#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18142#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18894#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 18025#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18026#L681 assume !(1 == ~t5_pc~0); 17898#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17899#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18946#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19549#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 18430#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18431#L700 assume 1 == ~t6_pc~0; 19130#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18171#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18172#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18221#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 18222#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19485#L719 assume 1 == ~t7_pc~0; 19562#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18388#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19159#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19160#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 17912#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17913#L738 assume !(1 == ~t8_pc~0); 19285#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19195#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18281#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18282#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18978#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19342#L757 assume 1 == ~t9_pc~0; 19343#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17907#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17908#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19111#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 18938#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18939#L776 assume !(1 == ~t10_pc~0); 17932#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17931#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18323#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18162#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 18163#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18116#L795 assume 1 == ~t11_pc~0; 18117#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18451#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19393#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19394#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 19164#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19152#L814 assume !(1 == ~t12_pc~0); 19007#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19008#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19379#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19478#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 18373#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18374#L1332 assume !(1 == ~M_E~0); 19452#L1332-2 assume !(1 == ~T1_E~0); 19635#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19079#L1342-1 assume !(1 == ~T3_E~0); 19080#L1347-1 assume !(1 == ~T4_E~0); 19474#L1352-1 assume !(1 == ~T5_E~0); 19348#L1357-1 assume !(1 == ~T6_E~0); 18644#L1362-1 assume !(1 == ~T7_E~0); 18645#L1367-1 assume !(1 == ~T8_E~0); 18256#L1372-1 assume !(1 == ~T9_E~0); 18257#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18562#L1382-1 assume !(1 == ~T11_E~0); 18563#L1387-1 assume !(1 == ~T12_E~0); 19248#L1392-1 assume !(1 == ~E_M~0); 18590#L1397-1 assume !(1 == ~E_1~0); 18591#L1402-1 assume !(1 == ~E_2~0); 18269#L1407-1 assume !(1 == ~E_3~0); 18270#L1412-1 assume !(1 == ~E_4~0); 19419#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19420#L1422-1 assume !(1 == ~E_6~0); 19636#L1427-1 assume !(1 == ~E_7~0); 18452#L1432-1 assume !(1 == ~E_8~0); 18453#L1437-1 assume !(1 == ~E_9~0); 19369#L1442-1 assume !(1 == ~E_10~0); 19370#L1447-1 assume !(1 == ~E_11~0); 19239#L1452-1 assume !(1 == ~E_12~0); 18056#L1457-1 assume { :end_inline_reset_delta_events } true; 18057#L1803-2 [2021-12-15 17:21:02,225 INFO L793 eck$LassoCheckResult]: Loop: 18057#L1803-2 assume !false; 18393#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17929#L1169 assume !false; 18520#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18625#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18124#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18125#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18900#L996 assume !(0 != eval_~tmp~0#1); 19012#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19013#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18983#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18984#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18228#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18229#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18477#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17925#L1214-3 assume !(0 == ~T5_E~0); 17926#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18669#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18670#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18699#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18094#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18095#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18526#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 19103#L1254-3 assume !(0 == ~E_M~0); 19583#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19218#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18100#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18101#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19615#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18667#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18668#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18651#L1294-3 assume !(0 == ~E_8~0); 18652#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19034#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19035#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18564#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18565#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18573#L586-42 assume !(1 == ~m_pc~0); 18574#L586-44 is_master_triggered_~__retres1~0#1 := 0; 18169#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18170#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19594#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 18691#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18692#L605-42 assume 1 == ~t1_pc~0; 19289#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18997#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18998#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18693#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18694#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18703#L624-42 assume !(1 == ~t2_pc~0); 18704#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18849#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18009#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18010#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18523#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18524#L643-42 assume 1 == ~t3_pc~0; 18864#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18830#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18831#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18663#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18664#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19378#L662-42 assume !(1 == ~t4_pc~0); 19572#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18192#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18193#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18759#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19611#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19577#L681-42 assume !(1 == ~t5_pc~0); 18052#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 18053#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18412#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18413#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19427#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18549#L700-42 assume 1 == ~t6_pc~0; 18550#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18360#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19349#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19435#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19436#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19625#L719-42 assume !(1 == ~t7_pc~0); 18244#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18245#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18295#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18296#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 18626#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18627#L738-42 assume 1 == ~t8_pc~0; 18819#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18582#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18135#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18098#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18099#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18619#L757-42 assume 1 == ~t9_pc~0; 18955#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18279#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18280#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18423#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18396#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18397#L776-42 assume 1 == ~t10_pc~0; 19368#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19355#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19402#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19664#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19665#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19192#L795-42 assume !(1 == ~t11_pc~0); 19193#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 18239#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18240#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18335#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18336#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18636#L814-42 assume !(1 == ~t12_pc~0); 18513#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 18151#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18152#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17960#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17961#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18112#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18113#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18084#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18085#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18895#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19066#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19067#L1357-3 assume !(1 == ~T6_E~0); 19505#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19673#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19669#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17941#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17942#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18545#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18546#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19376#L1397-3 assume !(1 == ~E_1~0); 19634#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19017#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18197#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18198#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18914#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18915#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19504#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19273#L1437-3 assume !(1 == ~E_9~0); 19036#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19037#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17995#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17996#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18601#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18447#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19259#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18188#L1822 assume !(0 == start_simulation_~tmp~3#1); 18189#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19138#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18443#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18444#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 18975#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19087#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19030#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19031#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 18057#L1803-2 [2021-12-15 17:21:02,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,229 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2021-12-15 17:21:02,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922624612] [2021-12-15 17:21:02,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,230 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,252 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922624612] [2021-12-15 17:21:02,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922624612] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,252 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273586443] [2021-12-15 17:21:02,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,254 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:02,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,256 INFO L85 PathProgramCache]: Analyzing trace with hash -1797209546, now seen corresponding path program 1 times [2021-12-15 17:21:02,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,259 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082529041] [2021-12-15 17:21:02,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,260 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,291 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082529041] [2021-12-15 17:21:02,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082529041] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,292 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,292 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,293 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580248726] [2021-12-15 17:21:02,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,293 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:02,293 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:02,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:02,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:02,294 INFO L87 Difference]: Start difference. First operand 1785 states and 2642 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,315 INFO L93 Difference]: Finished difference Result 1785 states and 2641 transitions. [2021-12-15 17:21:02,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:02,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2641 transitions. [2021-12-15 17:21:02,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2641 transitions. [2021-12-15 17:21:02,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:02,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:02,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2641 transitions. [2021-12-15 17:21:02,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,360 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2021-12-15 17:21:02,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2641 transitions. [2021-12-15 17:21:02,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:02,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4795518207282914) internal successors, (2641), 1784 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2641 transitions. [2021-12-15 17:21:02,387 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2021-12-15 17:21:02,387 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2021-12-15 17:21:02,387 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:21:02,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2641 transitions. [2021-12-15 17:21:02,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,394 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,394 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,394 INFO L791 eck$LassoCheckResult]: Stem: 22279#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 23058#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23059#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21796#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 21797#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21699#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21700#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22978#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22318#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22319#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22223#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22224#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22726#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22727#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21985#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21986#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22411#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22412#L1194 assume !(0 == ~M_E~0); 22558#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22559#L1199-1 assume !(0 == ~T2_E~0); 22856#L1204-1 assume !(0 == ~T3_E~0); 22780#L1209-1 assume !(0 == ~T4_E~0); 22781#L1214-1 assume !(0 == ~T5_E~0); 23166#L1219-1 assume !(0 == ~T6_E~0); 23254#L1224-1 assume !(0 == ~T7_E~0); 22059#L1229-1 assume !(0 == ~T8_E~0); 21624#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21625#L1239-1 assume !(0 == ~T10_E~0); 21661#L1244-1 assume !(0 == ~T11_E~0); 21662#L1249-1 assume !(0 == ~T12_E~0); 22353#L1254-1 assume !(0 == ~E_M~0); 21563#L1259-1 assume !(0 == ~E_1~0); 21527#L1264-1 assume !(0 == ~E_2~0); 21528#L1269-1 assume !(0 == ~E_3~0); 23257#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 23196#L1279-1 assume !(0 == ~E_5~0); 21737#L1284-1 assume !(0 == ~E_6~0); 21738#L1289-1 assume !(0 == ~E_7~0); 22416#L1294-1 assume !(0 == ~E_8~0); 22417#L1299-1 assume !(0 == ~E_9~0); 22429#L1304-1 assume !(0 == ~E_10~0); 23248#L1309-1 assume !(0 == ~E_11~0); 23252#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21692#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21613#L586 assume 1 == ~m_pc~0; 21614#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21685#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22752#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21893#L1485 assume !(0 != activate_threads_~tmp~1#1); 21894#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22981#L605 assume !(1 == ~t1_pc~0); 22497#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22248#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22249#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23131#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22828#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22166#L624 assume 1 == ~t2_pc~0; 21668#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21669#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22326#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23155#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 23018#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22896#L643 assume !(1 == ~t3_pc~0); 22743#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22445#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22352#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21995#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 21996#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21757#L662 assume 1 == ~t4_pc~0; 21758#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21718#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21719#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22471#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 21602#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21603#L681 assume !(1 == ~t5_pc~0); 21475#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21476#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22523#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23126#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 22007#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22008#L700 assume 1 == ~t6_pc~0; 22707#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21748#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21749#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21798#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 21799#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23062#L719 assume 1 == ~t7_pc~0; 23136#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21965#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22736#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22737#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 21489#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21490#L738 assume !(1 == ~t8_pc~0); 22862#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22772#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21858#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21859#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22555#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22919#L757 assume 1 == ~t9_pc~0; 22920#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21484#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21485#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22687#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 22515#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22516#L776 assume !(1 == ~t10_pc~0); 21509#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21508#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21897#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21739#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 21740#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21693#L795 assume 1 == ~t11_pc~0; 21694#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22026#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22970#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22971#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 22741#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22729#L814 assume !(1 == ~t12_pc~0); 22584#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22585#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22956#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23055#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 21950#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21951#L1332 assume !(1 == ~M_E~0); 23029#L1332-2 assume !(1 == ~T1_E~0); 23212#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22654#L1342-1 assume !(1 == ~T3_E~0); 22655#L1347-1 assume !(1 == ~T4_E~0); 23050#L1352-1 assume !(1 == ~T5_E~0); 22925#L1357-1 assume !(1 == ~T6_E~0); 22221#L1362-1 assume !(1 == ~T7_E~0); 22222#L1367-1 assume !(1 == ~T8_E~0); 21833#L1372-1 assume !(1 == ~T9_E~0); 21834#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22139#L1382-1 assume !(1 == ~T11_E~0); 22140#L1387-1 assume !(1 == ~T12_E~0); 22825#L1392-1 assume !(1 == ~E_M~0); 22167#L1397-1 assume !(1 == ~E_1~0); 22168#L1402-1 assume !(1 == ~E_2~0); 21846#L1407-1 assume !(1 == ~E_3~0); 21847#L1412-1 assume !(1 == ~E_4~0); 22996#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22997#L1422-1 assume !(1 == ~E_6~0); 23213#L1427-1 assume !(1 == ~E_7~0); 22027#L1432-1 assume !(1 == ~E_8~0); 22028#L1437-1 assume !(1 == ~E_9~0); 22946#L1442-1 assume !(1 == ~E_10~0); 22947#L1447-1 assume !(1 == ~E_11~0); 22815#L1452-1 assume !(1 == ~E_12~0); 21633#L1457-1 assume { :end_inline_reset_delta_events } true; 21634#L1803-2 [2021-12-15 17:21:02,395 INFO L793 eck$LassoCheckResult]: Loop: 21634#L1803-2 assume !false; 21970#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21506#L1169 assume !false; 22097#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22202#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21701#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21702#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22477#L996 assume !(0 != eval_~tmp~0#1); 22589#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22590#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22560#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22561#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21805#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21806#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22054#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21502#L1214-3 assume !(0 == ~T5_E~0); 21503#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22246#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22247#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22281#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21671#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21672#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22103#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22680#L1254-3 assume !(0 == ~E_M~0); 23160#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22795#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21677#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21678#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23192#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22244#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22245#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22228#L1294-3 assume !(0 == ~E_8~0); 22229#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22611#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22612#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22141#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22142#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22150#L586-42 assume !(1 == ~m_pc~0); 22151#L586-44 is_master_triggered_~__retres1~0#1 := 0; 21746#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21747#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23171#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 22268#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22269#L605-42 assume 1 == ~t1_pc~0; 22867#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22576#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22577#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22274#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22275#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22276#L624-42 assume !(1 == ~t2_pc~0); 22277#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22423#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21586#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21587#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22099#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22100#L643-42 assume 1 == ~t3_pc~0; 22441#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22407#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22408#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22240#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22241#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22955#L662-42 assume !(1 == ~t4_pc~0); 23146#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21769#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21770#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22336#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23188#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23154#L681-42 assume 1 == ~t5_pc~0; 22452#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21630#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21989#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21990#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23004#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22126#L700-42 assume !(1 == ~t6_pc~0); 21936#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21937#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22926#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23012#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23013#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23202#L719-42 assume 1 == ~t7_pc~0; 22723#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21822#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21872#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21873#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 22203#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22204#L738-42 assume 1 == ~t8_pc~0; 22396#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22159#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21712#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21675#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21676#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22196#L757-42 assume 1 == ~t9_pc~0; 22529#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21856#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21857#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22000#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21973#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21974#L776-42 assume 1 == ~t10_pc~0; 22945#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22932#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22979#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23241#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23242#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22769#L795-42 assume !(1 == ~t11_pc~0); 22770#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21816#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21817#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21910#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21911#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22213#L814-42 assume 1 == ~t12_pc~0; 22984#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21728#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21729#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21537#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21538#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21689#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21690#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21659#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21660#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22472#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22643#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22644#L1357-3 assume !(1 == ~T6_E~0); 23082#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23250#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23246#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21518#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21519#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22122#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22123#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22953#L1397-3 assume !(1 == ~E_1~0); 23211#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22594#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21774#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21775#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22491#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22492#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23081#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22849#L1437-3 assume !(1 == ~E_9~0); 22613#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22614#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21572#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21573#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22178#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22024#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22836#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 21765#L1822 assume !(0 == start_simulation_~tmp~3#1); 21766#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22715#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22017#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22018#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 22552#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22664#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22607#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22608#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 21634#L1803-2 [2021-12-15 17:21:02,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,395 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2021-12-15 17:21:02,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056652995] [2021-12-15 17:21:02,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,417 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056652995] [2021-12-15 17:21:02,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2056652995] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,417 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,418 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278962986] [2021-12-15 17:21:02,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,418 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:02,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1880402740, now seen corresponding path program 1 times [2021-12-15 17:21:02,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865981635] [2021-12-15 17:21:02,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,460 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865981635] [2021-12-15 17:21:02,460 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865981635] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,460 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,460 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,460 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308157419] [2021-12-15 17:21:02,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,461 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:02,461 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:02,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:02,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:02,461 INFO L87 Difference]: Start difference. First operand 1785 states and 2641 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,482 INFO L93 Difference]: Finished difference Result 1785 states and 2640 transitions. [2021-12-15 17:21:02,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:02,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2640 transitions. [2021-12-15 17:21:02,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2640 transitions. [2021-12-15 17:21:02,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:02,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:02,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2640 transitions. [2021-12-15 17:21:02,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,503 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2021-12-15 17:21:02,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2640 transitions. [2021-12-15 17:21:02,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:02,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4789915966386555) internal successors, (2640), 1784 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2640 transitions. [2021-12-15 17:21:02,528 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2021-12-15 17:21:02,528 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2021-12-15 17:21:02,528 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:21:02,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2640 transitions. [2021-12-15 17:21:02,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,535 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,535 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,535 INFO L791 eck$LassoCheckResult]: Stem: 25853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26635#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26636#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25373#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 25374#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25276#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25277#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26555#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25895#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25896#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25800#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25801#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26303#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26304#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25562#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25563#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25988#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25989#L1194 assume !(0 == ~M_E~0); 26135#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26136#L1199-1 assume !(0 == ~T2_E~0); 26433#L1204-1 assume !(0 == ~T3_E~0); 26357#L1209-1 assume !(0 == ~T4_E~0); 26358#L1214-1 assume !(0 == ~T5_E~0); 26743#L1219-1 assume !(0 == ~T6_E~0); 26831#L1224-1 assume !(0 == ~T7_E~0); 25636#L1229-1 assume !(0 == ~T8_E~0); 25199#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25200#L1239-1 assume !(0 == ~T10_E~0); 25238#L1244-1 assume !(0 == ~T11_E~0); 25239#L1249-1 assume !(0 == ~T12_E~0); 25930#L1254-1 assume !(0 == ~E_M~0); 25140#L1259-1 assume !(0 == ~E_1~0); 25104#L1264-1 assume !(0 == ~E_2~0); 25105#L1269-1 assume !(0 == ~E_3~0); 26834#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26773#L1279-1 assume !(0 == ~E_5~0); 25314#L1284-1 assume !(0 == ~E_6~0); 25315#L1289-1 assume !(0 == ~E_7~0); 25993#L1294-1 assume !(0 == ~E_8~0); 25994#L1299-1 assume !(0 == ~E_9~0); 26004#L1304-1 assume !(0 == ~E_10~0); 26825#L1309-1 assume !(0 == ~E_11~0); 26829#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25269#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25190#L586 assume 1 == ~m_pc~0; 25191#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25262#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26327#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25470#L1485 assume !(0 != activate_threads_~tmp~1#1); 25471#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26558#L605 assume !(1 == ~t1_pc~0); 26074#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25825#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25826#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26708#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26405#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25743#L624 assume 1 == ~t2_pc~0; 25245#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25246#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25903#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26732#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 26595#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26473#L643 assume !(1 == ~t3_pc~0); 26320#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26018#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25929#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25572#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 25573#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25334#L662 assume 1 == ~t4_pc~0; 25335#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25295#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25296#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26048#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 25179#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25180#L681 assume !(1 == ~t5_pc~0); 25052#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25053#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26100#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26703#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 25584#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25585#L700 assume 1 == ~t6_pc~0; 26284#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25325#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25326#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25375#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 25376#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26639#L719 assume 1 == ~t7_pc~0; 26713#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25542#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26313#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26314#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 25066#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25067#L738 assume !(1 == ~t8_pc~0); 26439#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26349#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25435#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25436#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26132#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26496#L757 assume 1 == ~t9_pc~0; 26497#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25061#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25062#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26264#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 26092#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26093#L776 assume !(1 == ~t10_pc~0); 25086#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25085#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25474#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25316#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 25317#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25270#L795 assume 1 == ~t11_pc~0; 25271#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25603#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26547#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26548#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 26318#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26306#L814 assume !(1 == ~t12_pc~0); 26161#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26162#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26532#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26632#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 25527#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25528#L1332 assume !(1 == ~M_E~0); 26606#L1332-2 assume !(1 == ~T1_E~0); 26789#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26231#L1342-1 assume !(1 == ~T3_E~0); 26232#L1347-1 assume !(1 == ~T4_E~0); 26627#L1352-1 assume !(1 == ~T5_E~0); 26502#L1357-1 assume !(1 == ~T6_E~0); 25796#L1362-1 assume !(1 == ~T7_E~0); 25797#L1367-1 assume !(1 == ~T8_E~0); 25410#L1372-1 assume !(1 == ~T9_E~0); 25411#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25716#L1382-1 assume !(1 == ~T11_E~0); 25717#L1387-1 assume !(1 == ~T12_E~0); 26402#L1392-1 assume !(1 == ~E_M~0); 25744#L1397-1 assume !(1 == ~E_1~0); 25745#L1402-1 assume !(1 == ~E_2~0); 25421#L1407-1 assume !(1 == ~E_3~0); 25422#L1412-1 assume !(1 == ~E_4~0); 26573#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26574#L1422-1 assume !(1 == ~E_6~0); 26790#L1427-1 assume !(1 == ~E_7~0); 25604#L1432-1 assume !(1 == ~E_8~0); 25605#L1437-1 assume !(1 == ~E_9~0); 26523#L1442-1 assume !(1 == ~E_10~0); 26524#L1447-1 assume !(1 == ~E_11~0); 26392#L1452-1 assume !(1 == ~E_12~0); 25210#L1457-1 assume { :end_inline_reset_delta_events } true; 25211#L1803-2 [2021-12-15 17:21:02,538 INFO L793 eck$LassoCheckResult]: Loop: 25211#L1803-2 assume !false; 25547#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25083#L1169 assume !false; 25672#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25779#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25278#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25279#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26054#L996 assume !(0 != eval_~tmp~0#1); 26166#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26167#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26137#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26138#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25382#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25383#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25631#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25079#L1214-3 assume !(0 == ~T5_E~0); 25080#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25823#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25824#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25855#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25248#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25249#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25680#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26257#L1254-3 assume !(0 == ~E_M~0); 26737#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26372#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25254#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25255#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26769#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25821#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25822#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25805#L1294-3 assume !(0 == ~E_8~0); 25806#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26188#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26189#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25718#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25719#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25727#L586-42 assume !(1 == ~m_pc~0); 25728#L586-44 is_master_triggered_~__retres1~0#1 := 0; 25323#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25324#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26748#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 25845#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25846#L605-42 assume 1 == ~t1_pc~0; 26444#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26151#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26152#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25849#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25850#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25859#L624-42 assume !(1 == ~t2_pc~0); 25860#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26003#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25163#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25164#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25677#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25678#L643-42 assume 1 == ~t3_pc~0; 26021#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25984#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25985#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25817#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25818#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26533#L662-42 assume !(1 == ~t4_pc~0); 26726#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25346#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25347#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25913#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26765#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26731#L681-42 assume 1 == ~t5_pc~0; 26032#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25207#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25566#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25567#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26581#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25703#L700-42 assume 1 == ~t6_pc~0; 25704#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25514#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26503#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26589#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26590#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26779#L719-42 assume !(1 == ~t7_pc~0); 25395#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25396#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25449#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25450#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 25780#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25781#L738-42 assume 1 == ~t8_pc~0; 25973#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25734#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25289#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25252#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25253#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25773#L757-42 assume 1 == ~t9_pc~0; 26106#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25433#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25434#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25577#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25550#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25551#L776-42 assume 1 == ~t10_pc~0; 26522#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26509#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26556#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26818#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26819#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26346#L795-42 assume !(1 == ~t11_pc~0); 26347#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25393#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25394#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25487#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25488#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25790#L814-42 assume 1 == ~t12_pc~0; 26561#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25305#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25306#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25114#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25115#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25266#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25267#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25236#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25237#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26049#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26220#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26221#L1357-3 assume !(1 == ~T6_E~0); 26659#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26827#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26823#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25095#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25096#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25696#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25697#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26530#L1397-3 assume !(1 == ~E_1~0); 26788#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26171#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25351#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25352#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26068#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26069#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26658#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26426#L1437-3 assume !(1 == ~E_9~0); 26190#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26191#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25149#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25150#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25753#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25601#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26413#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25342#L1822 assume !(0 == start_simulation_~tmp~3#1); 25343#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26292#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25594#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25595#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 26129#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26241#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26184#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 26185#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 25211#L1803-2 [2021-12-15 17:21:02,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,539 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2021-12-15 17:21:02,539 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742068014] [2021-12-15 17:21:02,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,539 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,561 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,561 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742068014] [2021-12-15 17:21:02,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742068014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,562 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,562 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,562 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594554363] [2021-12-15 17:21:02,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,563 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:02,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,563 INFO L85 PathProgramCache]: Analyzing trace with hash 561508340, now seen corresponding path program 2 times [2021-12-15 17:21:02,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675019486] [2021-12-15 17:21:02,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,593 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675019486] [2021-12-15 17:21:02,596 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675019486] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,596 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,596 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,596 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361845561] [2021-12-15 17:21:02,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,597 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:02,597 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:02,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:02,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:02,598 INFO L87 Difference]: Start difference. First operand 1785 states and 2640 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,620 INFO L93 Difference]: Finished difference Result 1785 states and 2639 transitions. [2021-12-15 17:21:02,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:02,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2639 transitions. [2021-12-15 17:21:02,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2639 transitions. [2021-12-15 17:21:02,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:02,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:02,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2639 transitions. [2021-12-15 17:21:02,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,642 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2021-12-15 17:21:02,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2639 transitions. [2021-12-15 17:21:02,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:02,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4784313725490197) internal successors, (2639), 1784 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2639 transitions. [2021-12-15 17:21:02,708 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2021-12-15 17:21:02,708 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2021-12-15 17:21:02,708 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:21:02,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2639 transitions. [2021-12-15 17:21:02,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,715 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,715 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,716 INFO L791 eck$LassoCheckResult]: Stem: 29430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30212#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30213#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28950#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 28951#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28853#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28854#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30132#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29472#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29473#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29377#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29378#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29880#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29881#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29139#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29140#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29563#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29564#L1194 assume !(0 == ~M_E~0); 29712#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29713#L1199-1 assume !(0 == ~T2_E~0); 30010#L1204-1 assume !(0 == ~T3_E~0); 29934#L1209-1 assume !(0 == ~T4_E~0); 29935#L1214-1 assume !(0 == ~T5_E~0); 30320#L1219-1 assume !(0 == ~T6_E~0); 30408#L1224-1 assume !(0 == ~T7_E~0); 29213#L1229-1 assume !(0 == ~T8_E~0); 28770#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28771#L1239-1 assume !(0 == ~T10_E~0); 28813#L1244-1 assume !(0 == ~T11_E~0); 28814#L1249-1 assume !(0 == ~T12_E~0); 29507#L1254-1 assume !(0 == ~E_M~0); 28717#L1259-1 assume !(0 == ~E_1~0); 28681#L1264-1 assume !(0 == ~E_2~0); 28682#L1269-1 assume !(0 == ~E_3~0); 30411#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30350#L1279-1 assume !(0 == ~E_5~0); 28891#L1284-1 assume !(0 == ~E_6~0); 28892#L1289-1 assume !(0 == ~E_7~0); 29570#L1294-1 assume !(0 == ~E_8~0); 29571#L1299-1 assume !(0 == ~E_9~0); 29581#L1304-1 assume !(0 == ~E_10~0); 30402#L1309-1 assume !(0 == ~E_11~0); 30406#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 28845#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28767#L586 assume 1 == ~m_pc~0; 28768#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28839#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29904#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29047#L1485 assume !(0 != activate_threads_~tmp~1#1); 29048#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30135#L605 assume !(1 == ~t1_pc~0); 29651#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29402#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29403#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30285#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29981#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29320#L624 assume 1 == ~t2_pc~0; 28819#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28820#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29480#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30309#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 30172#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30050#L643 assume !(1 == ~t3_pc~0); 29897#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29593#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29506#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29149#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 29150#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28911#L662 assume 1 == ~t4_pc~0; 28912#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28870#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28871#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29625#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 28754#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28755#L681 assume !(1 == ~t5_pc~0); 28629#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28630#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29677#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30279#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 29161#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29162#L700 assume 1 == ~t6_pc~0; 29861#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28902#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28903#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28952#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 28953#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30216#L719 assume 1 == ~t7_pc~0; 30290#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29119#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29889#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29890#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 28643#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28644#L738 assume !(1 == ~t8_pc~0); 30016#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29926#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29012#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29013#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29709#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30073#L757 assume 1 == ~t9_pc~0; 30074#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28638#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28639#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29841#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 29669#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29670#L776 assume !(1 == ~t10_pc~0); 28663#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28662#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29051#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28893#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 28894#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28846#L795 assume 1 == ~t11_pc~0; 28847#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29180#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30124#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30125#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 29895#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29883#L814 assume !(1 == ~t12_pc~0); 29738#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29739#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30109#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30209#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 29104#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29105#L1332 assume !(1 == ~M_E~0); 30183#L1332-2 assume !(1 == ~T1_E~0); 30366#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29808#L1342-1 assume !(1 == ~T3_E~0); 29809#L1347-1 assume !(1 == ~T4_E~0); 30204#L1352-1 assume !(1 == ~T5_E~0); 30079#L1357-1 assume !(1 == ~T6_E~0); 29373#L1362-1 assume !(1 == ~T7_E~0); 29374#L1367-1 assume !(1 == ~T8_E~0); 28987#L1372-1 assume !(1 == ~T9_E~0); 28988#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29293#L1382-1 assume !(1 == ~T11_E~0); 29294#L1387-1 assume !(1 == ~T12_E~0); 29979#L1392-1 assume !(1 == ~E_M~0); 29321#L1397-1 assume !(1 == ~E_1~0); 29322#L1402-1 assume !(1 == ~E_2~0); 28998#L1407-1 assume !(1 == ~E_3~0); 28999#L1412-1 assume !(1 == ~E_4~0); 30150#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30151#L1422-1 assume !(1 == ~E_6~0); 30367#L1427-1 assume !(1 == ~E_7~0); 29181#L1432-1 assume !(1 == ~E_8~0); 29182#L1437-1 assume !(1 == ~E_9~0); 30100#L1442-1 assume !(1 == ~E_10~0); 30101#L1447-1 assume !(1 == ~E_11~0); 29969#L1452-1 assume !(1 == ~E_12~0); 28787#L1457-1 assume { :end_inline_reset_delta_events } true; 28788#L1803-2 [2021-12-15 17:21:02,716 INFO L793 eck$LassoCheckResult]: Loop: 28788#L1803-2 assume !false; 29124#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28660#L1169 assume !false; 29249#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29354#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28855#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28856#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29631#L996 assume !(0 != eval_~tmp~0#1); 29743#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29744#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29714#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29715#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28959#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28960#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29208#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28652#L1214-3 assume !(0 == ~T5_E~0); 28653#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29400#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29401#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29432#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28825#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28826#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29257#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29834#L1254-3 assume !(0 == ~E_M~0); 30314#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29949#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28831#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28832#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30346#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29398#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29399#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29382#L1294-3 assume !(0 == ~E_8~0); 29383#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29765#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29766#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29295#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29296#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29304#L586-42 assume !(1 == ~m_pc~0); 29305#L586-44 is_master_triggered_~__retres1~0#1 := 0; 28900#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28901#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30325#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 29422#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29423#L605-42 assume 1 == ~t1_pc~0; 30020#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29728#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29729#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29424#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29425#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29436#L624-42 assume !(1 == ~t2_pc~0); 29437#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29580#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28740#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28741#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29254#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29255#L643-42 assume 1 == ~t3_pc~0; 29596#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29561#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29562#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29394#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29395#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30110#L662-42 assume 1 == ~t4_pc~0; 30304#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28923#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28924#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29490#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30342#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30308#L681-42 assume 1 == ~t5_pc~0; 29606#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28784#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29143#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29144#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30158#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29280#L700-42 assume 1 == ~t6_pc~0; 29281#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29091#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30080#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30166#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30167#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30356#L719-42 assume 1 == ~t7_pc~0; 29877#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28976#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29026#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29027#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 29357#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29358#L738-42 assume 1 == ~t8_pc~0; 29550#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29313#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28866#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28829#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28830#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29350#L757-42 assume 1 == ~t9_pc~0; 29686#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29010#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29011#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29154#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29128#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29129#L776-42 assume 1 == ~t10_pc~0; 30099#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30086#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30133#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30395#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30396#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29923#L795-42 assume !(1 == ~t11_pc~0); 29924#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 28970#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28971#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29066#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29067#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29367#L814-42 assume 1 == ~t12_pc~0; 30138#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28882#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28883#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28691#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28692#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28843#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28844#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28817#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28818#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29626#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29797#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29798#L1357-3 assume !(1 == ~T6_E~0); 30236#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30404#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30400#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28672#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28673#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29276#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29277#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30107#L1397-3 assume !(1 == ~E_1~0); 30365#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29748#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28928#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28929#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29645#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29646#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30235#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30004#L1437-3 assume !(1 == ~E_9~0); 29767#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29768#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28726#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28727#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29332#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29178#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29990#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 28919#L1822 assume !(0 == start_simulation_~tmp~3#1); 28920#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29869#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29174#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29175#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 29706#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29818#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29763#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29764#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 28788#L1803-2 [2021-12-15 17:21:02,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,717 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2021-12-15 17:21:02,717 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,717 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879547698] [2021-12-15 17:21:02,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,717 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,740 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,740 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879547698] [2021-12-15 17:21:02,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879547698] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,740 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,740 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553362291] [2021-12-15 17:21:02,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,741 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:02,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,741 INFO L85 PathProgramCache]: Analyzing trace with hash -696776142, now seen corresponding path program 1 times [2021-12-15 17:21:02,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,742 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077026338] [2021-12-15 17:21:02,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,742 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,769 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077026338] [2021-12-15 17:21:02,769 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077026338] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,770 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,770 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,770 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933449788] [2021-12-15 17:21:02,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,770 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:02,770 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:02,771 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:02,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:02,771 INFO L87 Difference]: Start difference. First operand 1785 states and 2639 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,792 INFO L93 Difference]: Finished difference Result 1785 states and 2638 transitions. [2021-12-15 17:21:02,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:02,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2638 transitions. [2021-12-15 17:21:02,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2638 transitions. [2021-12-15 17:21:02,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:02,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:02,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2638 transitions. [2021-12-15 17:21:02,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,810 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2021-12-15 17:21:02,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2638 transitions. [2021-12-15 17:21:02,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:02,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4778711484593838) internal successors, (2638), 1784 states have internal predecessors, (2638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2638 transitions. [2021-12-15 17:21:02,834 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2021-12-15 17:21:02,835 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2021-12-15 17:21:02,835 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:21:02,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2638 transitions. [2021-12-15 17:21:02,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,841 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,841 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,842 INFO L791 eck$LassoCheckResult]: Stem: 33007#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33008#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33789#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33790#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32527#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 32528#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32430#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32431#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33709#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33049#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33050#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32954#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32955#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33457#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33458#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32716#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32717#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33140#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33141#L1194 assume !(0 == ~M_E~0); 33289#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33290#L1199-1 assume !(0 == ~T2_E~0); 33587#L1204-1 assume !(0 == ~T3_E~0); 33511#L1209-1 assume !(0 == ~T4_E~0); 33512#L1214-1 assume !(0 == ~T5_E~0); 33897#L1219-1 assume !(0 == ~T6_E~0); 33985#L1224-1 assume !(0 == ~T7_E~0); 32790#L1229-1 assume !(0 == ~T8_E~0); 32347#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32348#L1239-1 assume !(0 == ~T10_E~0); 32390#L1244-1 assume !(0 == ~T11_E~0); 32391#L1249-1 assume !(0 == ~T12_E~0); 33084#L1254-1 assume !(0 == ~E_M~0); 32294#L1259-1 assume !(0 == ~E_1~0); 32258#L1264-1 assume !(0 == ~E_2~0); 32259#L1269-1 assume !(0 == ~E_3~0); 33988#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33927#L1279-1 assume !(0 == ~E_5~0); 32468#L1284-1 assume !(0 == ~E_6~0); 32469#L1289-1 assume !(0 == ~E_7~0); 33147#L1294-1 assume !(0 == ~E_8~0); 33148#L1299-1 assume !(0 == ~E_9~0); 33158#L1304-1 assume !(0 == ~E_10~0); 33979#L1309-1 assume !(0 == ~E_11~0); 33983#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32422#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32344#L586 assume 1 == ~m_pc~0; 32345#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32416#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33481#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32624#L1485 assume !(0 != activate_threads_~tmp~1#1); 32625#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33712#L605 assume !(1 == ~t1_pc~0); 33228#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32979#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32980#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33862#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33558#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32897#L624 assume 1 == ~t2_pc~0; 32396#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32397#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33057#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33886#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 33749#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33627#L643 assume !(1 == ~t3_pc~0); 33474#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33170#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33083#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32726#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 32727#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32488#L662 assume 1 == ~t4_pc~0; 32489#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32447#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32448#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33202#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 32331#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32332#L681 assume !(1 == ~t5_pc~0); 32206#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32207#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33254#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33856#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 32738#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32739#L700 assume 1 == ~t6_pc~0; 33438#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32479#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32480#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32529#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 32530#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33793#L719 assume 1 == ~t7_pc~0; 33867#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32696#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33466#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33467#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 32220#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32221#L738 assume !(1 == ~t8_pc~0); 33593#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33503#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32589#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32590#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33286#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33650#L757 assume 1 == ~t9_pc~0; 33651#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32215#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32216#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33418#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 33246#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33247#L776 assume !(1 == ~t10_pc~0); 32240#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32239#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32628#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32470#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 32471#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32423#L795 assume 1 == ~t11_pc~0; 32424#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32757#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33701#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33702#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 33472#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33460#L814 assume !(1 == ~t12_pc~0); 33315#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33316#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33686#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33786#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 32681#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32682#L1332 assume !(1 == ~M_E~0); 33760#L1332-2 assume !(1 == ~T1_E~0); 33943#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33385#L1342-1 assume !(1 == ~T3_E~0); 33386#L1347-1 assume !(1 == ~T4_E~0); 33781#L1352-1 assume !(1 == ~T5_E~0); 33656#L1357-1 assume !(1 == ~T6_E~0); 32950#L1362-1 assume !(1 == ~T7_E~0); 32951#L1367-1 assume !(1 == ~T8_E~0); 32564#L1372-1 assume !(1 == ~T9_E~0); 32565#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32870#L1382-1 assume !(1 == ~T11_E~0); 32871#L1387-1 assume !(1 == ~T12_E~0); 33556#L1392-1 assume !(1 == ~E_M~0); 32898#L1397-1 assume !(1 == ~E_1~0); 32899#L1402-1 assume !(1 == ~E_2~0); 32575#L1407-1 assume !(1 == ~E_3~0); 32576#L1412-1 assume !(1 == ~E_4~0); 33727#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33728#L1422-1 assume !(1 == ~E_6~0); 33944#L1427-1 assume !(1 == ~E_7~0); 32758#L1432-1 assume !(1 == ~E_8~0); 32759#L1437-1 assume !(1 == ~E_9~0); 33677#L1442-1 assume !(1 == ~E_10~0); 33678#L1447-1 assume !(1 == ~E_11~0); 33546#L1452-1 assume !(1 == ~E_12~0); 32364#L1457-1 assume { :end_inline_reset_delta_events } true; 32365#L1803-2 [2021-12-15 17:21:02,842 INFO L793 eck$LassoCheckResult]: Loop: 32365#L1803-2 assume !false; 32701#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32237#L1169 assume !false; 32826#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32931#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32432#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32433#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33208#L996 assume !(0 != eval_~tmp~0#1); 33320#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33321#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33291#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33292#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32536#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32537#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32785#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32229#L1214-3 assume !(0 == ~T5_E~0); 32230#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32977#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32978#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33009#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32402#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32403#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32834#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33411#L1254-3 assume !(0 == ~E_M~0); 33891#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33526#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32408#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32409#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33923#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32975#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32976#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32959#L1294-3 assume !(0 == ~E_8~0); 32960#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33342#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33343#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32872#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32873#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32881#L586-42 assume !(1 == ~m_pc~0); 32882#L586-44 is_master_triggered_~__retres1~0#1 := 0; 32477#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32478#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33902#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 32999#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33000#L605-42 assume 1 == ~t1_pc~0; 33597#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33305#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33306#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33001#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33002#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33013#L624-42 assume !(1 == ~t2_pc~0); 33014#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33157#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32317#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32318#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32831#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32832#L643-42 assume 1 == ~t3_pc~0; 33173#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33138#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33139#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32971#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32972#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33687#L662-42 assume !(1 == ~t4_pc~0); 33880#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32500#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32501#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33067#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33919#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33885#L681-42 assume !(1 == ~t5_pc~0); 32360#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 32361#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32720#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32721#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33735#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32857#L700-42 assume 1 == ~t6_pc~0; 32858#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32668#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33657#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33743#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33744#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33933#L719-42 assume !(1 == ~t7_pc~0); 32552#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 32553#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32603#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32604#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 32934#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32935#L738-42 assume 1 == ~t8_pc~0; 33127#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32890#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32443#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32406#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32407#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32927#L757-42 assume !(1 == ~t9_pc~0); 33264#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 32587#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32588#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32731#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32705#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32706#L776-42 assume 1 == ~t10_pc~0; 33676#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33663#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33710#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33972#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33973#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33500#L795-42 assume !(1 == ~t11_pc~0); 33501#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 32547#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32548#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32643#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32644#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32944#L814-42 assume 1 == ~t12_pc~0; 33715#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32459#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32460#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32268#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32269#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32420#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32421#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32394#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32395#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33203#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33374#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33375#L1357-3 assume !(1 == ~T6_E~0); 33813#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33981#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33977#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32249#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32250#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32853#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32854#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33684#L1397-3 assume !(1 == ~E_1~0); 33942#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33325#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32505#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32506#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33222#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33223#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33812#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33581#L1437-3 assume !(1 == ~E_9~0); 33344#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33345#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32303#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32304#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32909#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32755#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33567#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32496#L1822 assume !(0 == start_simulation_~tmp~3#1); 32497#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33446#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32751#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32752#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 33283#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33395#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33340#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33341#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 32365#L1803-2 [2021-12-15 17:21:02,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,843 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2021-12-15 17:21:02,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116427867] [2021-12-15 17:21:02,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,843 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116427867] [2021-12-15 17:21:02,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116427867] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,864 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310459541] [2021-12-15 17:21:02,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,865 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:02,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,865 INFO L85 PathProgramCache]: Analyzing trace with hash -346803210, now seen corresponding path program 1 times [2021-12-15 17:21:02,865 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17615501] [2021-12-15 17:21:02,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,866 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,892 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,892 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17615501] [2021-12-15 17:21:02,892 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17615501] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,892 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,892 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,892 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819869730] [2021-12-15 17:21:02,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,893 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:02,893 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:02,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:02,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:02,894 INFO L87 Difference]: Start difference. First operand 1785 states and 2638 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:02,913 INFO L93 Difference]: Finished difference Result 1785 states and 2637 transitions. [2021-12-15 17:21:02,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:02,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2637 transitions. [2021-12-15 17:21:02,919 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,925 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2637 transitions. [2021-12-15 17:21:02,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:02,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:02,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2637 transitions. [2021-12-15 17:21:02,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:02,928 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2021-12-15 17:21:02,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2637 transitions. [2021-12-15 17:21:02,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:02,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.477310924369748) internal successors, (2637), 1784 states have internal predecessors, (2637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:02,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2637 transitions. [2021-12-15 17:21:02,954 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2021-12-15 17:21:02,954 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2021-12-15 17:21:02,954 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:21:02,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2637 transitions. [2021-12-15 17:21:02,959 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:02,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:02,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:02,961 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,961 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:02,961 INFO L791 eck$LassoCheckResult]: Stem: 36584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37366#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37367#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36104#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 36105#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36007#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36008#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37286#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36626#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36627#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36531#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36532#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37034#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37035#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36293#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36294#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36717#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36718#L1194 assume !(0 == ~M_E~0); 36866#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36867#L1199-1 assume !(0 == ~T2_E~0); 37164#L1204-1 assume !(0 == ~T3_E~0); 37088#L1209-1 assume !(0 == ~T4_E~0); 37089#L1214-1 assume !(0 == ~T5_E~0); 37474#L1219-1 assume !(0 == ~T6_E~0); 37562#L1224-1 assume !(0 == ~T7_E~0); 36367#L1229-1 assume !(0 == ~T8_E~0); 35924#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35925#L1239-1 assume !(0 == ~T10_E~0); 35967#L1244-1 assume !(0 == ~T11_E~0); 35968#L1249-1 assume !(0 == ~T12_E~0); 36661#L1254-1 assume !(0 == ~E_M~0); 35871#L1259-1 assume !(0 == ~E_1~0); 35835#L1264-1 assume !(0 == ~E_2~0); 35836#L1269-1 assume !(0 == ~E_3~0); 37565#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37504#L1279-1 assume !(0 == ~E_5~0); 36045#L1284-1 assume !(0 == ~E_6~0); 36046#L1289-1 assume !(0 == ~E_7~0); 36724#L1294-1 assume !(0 == ~E_8~0); 36725#L1299-1 assume !(0 == ~E_9~0); 36735#L1304-1 assume !(0 == ~E_10~0); 37556#L1309-1 assume !(0 == ~E_11~0); 37560#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 35999#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35921#L586 assume 1 == ~m_pc~0; 35922#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35993#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37058#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36201#L1485 assume !(0 != activate_threads_~tmp~1#1); 36202#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37289#L605 assume !(1 == ~t1_pc~0); 36805#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36556#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36557#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37439#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37135#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36474#L624 assume 1 == ~t2_pc~0; 35973#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35974#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36634#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37463#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 37326#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37204#L643 assume !(1 == ~t3_pc~0); 37051#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36747#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36660#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36303#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 36304#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36065#L662 assume 1 == ~t4_pc~0; 36066#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36024#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36025#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36779#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 35908#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35909#L681 assume !(1 == ~t5_pc~0); 35783#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 35784#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36831#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37433#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 36315#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36316#L700 assume 1 == ~t6_pc~0; 37015#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36056#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36057#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36106#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 36107#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37370#L719 assume 1 == ~t7_pc~0; 37444#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36273#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37043#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37044#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 35797#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35798#L738 assume !(1 == ~t8_pc~0); 37170#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37080#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36166#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36167#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36863#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37227#L757 assume 1 == ~t9_pc~0; 37228#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35792#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35793#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36995#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 36823#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36824#L776 assume !(1 == ~t10_pc~0); 35817#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35816#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36205#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36047#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 36048#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36000#L795 assume 1 == ~t11_pc~0; 36001#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36334#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37278#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37279#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 37049#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37037#L814 assume !(1 == ~t12_pc~0); 36892#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36893#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37263#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37363#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 36258#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36259#L1332 assume !(1 == ~M_E~0); 37337#L1332-2 assume !(1 == ~T1_E~0); 37520#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36962#L1342-1 assume !(1 == ~T3_E~0); 36963#L1347-1 assume !(1 == ~T4_E~0); 37358#L1352-1 assume !(1 == ~T5_E~0); 37233#L1357-1 assume !(1 == ~T6_E~0); 36527#L1362-1 assume !(1 == ~T7_E~0); 36528#L1367-1 assume !(1 == ~T8_E~0); 36141#L1372-1 assume !(1 == ~T9_E~0); 36142#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36447#L1382-1 assume !(1 == ~T11_E~0); 36448#L1387-1 assume !(1 == ~T12_E~0); 37133#L1392-1 assume !(1 == ~E_M~0); 36475#L1397-1 assume !(1 == ~E_1~0); 36476#L1402-1 assume !(1 == ~E_2~0); 36152#L1407-1 assume !(1 == ~E_3~0); 36153#L1412-1 assume !(1 == ~E_4~0); 37304#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37305#L1422-1 assume !(1 == ~E_6~0); 37521#L1427-1 assume !(1 == ~E_7~0); 36335#L1432-1 assume !(1 == ~E_8~0); 36336#L1437-1 assume !(1 == ~E_9~0); 37254#L1442-1 assume !(1 == ~E_10~0); 37255#L1447-1 assume !(1 == ~E_11~0); 37123#L1452-1 assume !(1 == ~E_12~0); 35941#L1457-1 assume { :end_inline_reset_delta_events } true; 35942#L1803-2 [2021-12-15 17:21:02,962 INFO L793 eck$LassoCheckResult]: Loop: 35942#L1803-2 assume !false; 36278#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35814#L1169 assume !false; 36403#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36508#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36009#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36010#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 36785#L996 assume !(0 != eval_~tmp~0#1); 36897#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36898#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36868#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36869#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36113#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36114#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36362#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35806#L1214-3 assume !(0 == ~T5_E~0); 35807#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36554#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36555#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36586#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35979#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35980#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36411#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36988#L1254-3 assume !(0 == ~E_M~0); 37468#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37103#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35985#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35986#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37500#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36552#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36553#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36536#L1294-3 assume !(0 == ~E_8~0); 36537#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36919#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36920#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36449#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36450#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36458#L586-42 assume !(1 == ~m_pc~0); 36459#L586-44 is_master_triggered_~__retres1~0#1 := 0; 36054#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36055#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37479#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 36576#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36577#L605-42 assume 1 == ~t1_pc~0; 37174#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36882#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36883#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36578#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36579#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36590#L624-42 assume 1 == ~t2_pc~0; 36592#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36734#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35894#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35895#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36408#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36409#L643-42 assume 1 == ~t3_pc~0; 36750#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36715#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36716#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36548#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36549#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37264#L662-42 assume !(1 == ~t4_pc~0); 37457#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36077#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36078#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36644#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37496#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37462#L681-42 assume !(1 == ~t5_pc~0); 35937#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 35938#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36297#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36298#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37312#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36434#L700-42 assume 1 == ~t6_pc~0; 36435#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36245#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37234#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37320#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37321#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37510#L719-42 assume !(1 == ~t7_pc~0); 36129#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 36130#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36180#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36181#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 36511#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36512#L738-42 assume 1 == ~t8_pc~0; 36704#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36467#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36020#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35983#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35984#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36504#L757-42 assume 1 == ~t9_pc~0; 36840#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36164#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36165#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36308#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36282#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36283#L776-42 assume 1 == ~t10_pc~0; 37253#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37240#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37287#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37549#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37550#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37077#L795-42 assume !(1 == ~t11_pc~0); 37078#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 36124#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36125#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36220#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36221#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36521#L814-42 assume 1 == ~t12_pc~0; 37292#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36036#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36037#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35845#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 35846#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35997#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35998#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35971#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35972#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36780#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36951#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36952#L1357-3 assume !(1 == ~T6_E~0); 37390#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37558#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37554#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35826#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35827#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36430#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36431#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37261#L1397-3 assume !(1 == ~E_1~0); 37519#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36902#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36082#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36083#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36799#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36800#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37389#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37158#L1437-3 assume !(1 == ~E_9~0); 36921#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36922#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35880#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35881#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36486#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36332#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37144#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36073#L1822 assume !(0 == start_simulation_~tmp~3#1); 36074#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37023#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36328#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36329#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 36860#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36972#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36917#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36918#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 35942#L1803-2 [2021-12-15 17:21:02,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,962 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2021-12-15 17:21:02,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641115504] [2021-12-15 17:21:02,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:02,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:02,986 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:02,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641115504] [2021-12-15 17:21:02,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1641115504] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:02,987 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:02,987 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:02,987 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966999501] [2021-12-15 17:21:02,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:02,988 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:02,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:02,988 INFO L85 PathProgramCache]: Analyzing trace with hash -1211191756, now seen corresponding path program 1 times [2021-12-15 17:21:02,988 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:02,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232980518] [2021-12-15 17:21:02,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:02,989 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:02,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232980518] [2021-12-15 17:21:03,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232980518] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206446658] [2021-12-15 17:21:03,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,017 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:03,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:03,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:03,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:03,018 INFO L87 Difference]: Start difference. First operand 1785 states and 2637 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:03,036 INFO L93 Difference]: Finished difference Result 1785 states and 2636 transitions. [2021-12-15 17:21:03,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:03,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2636 transitions. [2021-12-15 17:21:03,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:03,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2636 transitions. [2021-12-15 17:21:03,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:03,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:03,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2636 transitions. [2021-12-15 17:21:03,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:03,050 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2021-12-15 17:21:03,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2636 transitions. [2021-12-15 17:21:03,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:03,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4767507002801121) internal successors, (2636), 1784 states have internal predecessors, (2636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2636 transitions. [2021-12-15 17:21:03,070 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2021-12-15 17:21:03,070 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2021-12-15 17:21:03,070 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:21:03,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2636 transitions. [2021-12-15 17:21:03,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:03,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:03,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:03,076 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,076 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,076 INFO L791 eck$LassoCheckResult]: Stem: 40161#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40943#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40944#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39681#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 39682#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39584#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39585#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40863#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40203#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40204#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40108#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40109#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40611#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40612#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39870#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39871#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40294#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40295#L1194 assume !(0 == ~M_E~0); 40443#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40444#L1199-1 assume !(0 == ~T2_E~0); 40741#L1204-1 assume !(0 == ~T3_E~0); 40665#L1209-1 assume !(0 == ~T4_E~0); 40666#L1214-1 assume !(0 == ~T5_E~0); 41051#L1219-1 assume !(0 == ~T6_E~0); 41139#L1224-1 assume !(0 == ~T7_E~0); 39944#L1229-1 assume !(0 == ~T8_E~0); 39501#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39502#L1239-1 assume !(0 == ~T10_E~0); 39544#L1244-1 assume !(0 == ~T11_E~0); 39545#L1249-1 assume !(0 == ~T12_E~0); 40238#L1254-1 assume !(0 == ~E_M~0); 39448#L1259-1 assume !(0 == ~E_1~0); 39412#L1264-1 assume !(0 == ~E_2~0); 39413#L1269-1 assume !(0 == ~E_3~0); 41142#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41081#L1279-1 assume !(0 == ~E_5~0); 39622#L1284-1 assume !(0 == ~E_6~0); 39623#L1289-1 assume !(0 == ~E_7~0); 40301#L1294-1 assume !(0 == ~E_8~0); 40302#L1299-1 assume !(0 == ~E_9~0); 40312#L1304-1 assume !(0 == ~E_10~0); 41133#L1309-1 assume !(0 == ~E_11~0); 41137#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39576#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39498#L586 assume 1 == ~m_pc~0; 39499#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39570#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40635#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39778#L1485 assume !(0 != activate_threads_~tmp~1#1); 39779#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40866#L605 assume !(1 == ~t1_pc~0); 40382#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40133#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40134#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41016#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40712#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40051#L624 assume 1 == ~t2_pc~0; 39550#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39551#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40211#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41040#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 40903#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40781#L643 assume !(1 == ~t3_pc~0); 40628#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40324#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40237#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39880#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 39881#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39642#L662 assume 1 == ~t4_pc~0; 39643#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39601#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39602#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40356#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 39485#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39486#L681 assume !(1 == ~t5_pc~0); 39360#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39361#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40408#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41010#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 39892#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39893#L700 assume 1 == ~t6_pc~0; 40592#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39633#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39634#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39683#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 39684#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40947#L719 assume 1 == ~t7_pc~0; 41021#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39850#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40620#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40621#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 39374#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39375#L738 assume !(1 == ~t8_pc~0); 40747#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40657#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39743#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39744#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40440#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40804#L757 assume 1 == ~t9_pc~0; 40805#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39369#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39370#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40572#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 40400#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40401#L776 assume !(1 == ~t10_pc~0); 39394#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39393#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39782#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39624#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 39625#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39577#L795 assume 1 == ~t11_pc~0; 39578#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39911#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40855#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40856#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 40626#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40614#L814 assume !(1 == ~t12_pc~0); 40469#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40470#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40840#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40940#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 39835#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39836#L1332 assume !(1 == ~M_E~0); 40914#L1332-2 assume !(1 == ~T1_E~0); 41097#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40539#L1342-1 assume !(1 == ~T3_E~0); 40540#L1347-1 assume !(1 == ~T4_E~0); 40935#L1352-1 assume !(1 == ~T5_E~0); 40810#L1357-1 assume !(1 == ~T6_E~0); 40104#L1362-1 assume !(1 == ~T7_E~0); 40105#L1367-1 assume !(1 == ~T8_E~0); 39718#L1372-1 assume !(1 == ~T9_E~0); 39719#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40024#L1382-1 assume !(1 == ~T11_E~0); 40025#L1387-1 assume !(1 == ~T12_E~0); 40710#L1392-1 assume !(1 == ~E_M~0); 40052#L1397-1 assume !(1 == ~E_1~0); 40053#L1402-1 assume !(1 == ~E_2~0); 39729#L1407-1 assume !(1 == ~E_3~0); 39730#L1412-1 assume !(1 == ~E_4~0); 40881#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40882#L1422-1 assume !(1 == ~E_6~0); 41098#L1427-1 assume !(1 == ~E_7~0); 39912#L1432-1 assume !(1 == ~E_8~0); 39913#L1437-1 assume !(1 == ~E_9~0); 40831#L1442-1 assume !(1 == ~E_10~0); 40832#L1447-1 assume !(1 == ~E_11~0); 40700#L1452-1 assume !(1 == ~E_12~0); 39518#L1457-1 assume { :end_inline_reset_delta_events } true; 39519#L1803-2 [2021-12-15 17:21:03,076 INFO L793 eck$LassoCheckResult]: Loop: 39519#L1803-2 assume !false; 39855#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39391#L1169 assume !false; 39980#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40085#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39586#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39587#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40362#L996 assume !(0 != eval_~tmp~0#1); 40474#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40475#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40445#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40446#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39690#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39691#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39939#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39383#L1214-3 assume !(0 == ~T5_E~0); 39384#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40131#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40132#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40163#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39556#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39557#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39988#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40565#L1254-3 assume !(0 == ~E_M~0); 41045#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40680#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39562#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39563#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41077#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40129#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40130#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40113#L1294-3 assume !(0 == ~E_8~0); 40114#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40496#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40497#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40026#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40027#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40035#L586-42 assume !(1 == ~m_pc~0); 40036#L586-44 is_master_triggered_~__retres1~0#1 := 0; 39631#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39632#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41056#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 40153#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40154#L605-42 assume !(1 == ~t1_pc~0); 40752#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 40459#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40460#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40155#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40156#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40167#L624-42 assume !(1 == ~t2_pc~0); 40168#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40311#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39471#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39472#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39985#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39986#L643-42 assume 1 == ~t3_pc~0; 40327#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40292#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40293#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40125#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40126#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40841#L662-42 assume !(1 == ~t4_pc~0); 41034#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39654#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39655#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40221#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41073#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41039#L681-42 assume 1 == ~t5_pc~0; 40337#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39515#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39874#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39875#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40889#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40011#L700-42 assume 1 == ~t6_pc~0; 40012#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39822#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40811#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40897#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40898#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41087#L719-42 assume 1 == ~t7_pc~0; 40608#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39707#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39757#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39758#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 40088#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40089#L738-42 assume 1 == ~t8_pc~0; 40281#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40044#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39597#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39560#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39561#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40081#L757-42 assume 1 == ~t9_pc~0; 40417#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39741#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39742#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39885#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39859#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39860#L776-42 assume !(1 == ~t10_pc~0); 40816#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 40817#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40864#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41126#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41127#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40654#L795-42 assume 1 == ~t11_pc~0; 40656#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39701#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39702#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39797#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39798#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40098#L814-42 assume 1 == ~t12_pc~0; 40869#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 39613#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39614#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39422#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39423#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39574#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39575#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39548#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39549#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40357#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40528#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40529#L1357-3 assume !(1 == ~T6_E~0); 40967#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41135#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41131#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39403#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39404#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40007#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40008#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40838#L1397-3 assume !(1 == ~E_1~0); 41096#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40479#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39659#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39660#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40376#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40377#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40966#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40735#L1437-3 assume !(1 == ~E_9~0); 40498#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40499#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39457#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39458#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40063#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39909#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40721#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39650#L1822 assume !(0 == start_simulation_~tmp~3#1); 39651#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40600#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39905#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39906#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 40437#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40549#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40494#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40495#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 39519#L1803-2 [2021-12-15 17:21:03,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,077 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2021-12-15 17:21:03,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573322288] [2021-12-15 17:21:03,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,095 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573322288] [2021-12-15 17:21:03,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573322288] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,095 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,096 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81553492] [2021-12-15 17:21:03,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,096 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:03,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,096 INFO L85 PathProgramCache]: Analyzing trace with hash -808370508, now seen corresponding path program 1 times [2021-12-15 17:21:03,097 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934147195] [2021-12-15 17:21:03,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,097 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,122 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,122 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934147195] [2021-12-15 17:21:03,122 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934147195] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,122 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,122 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,122 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1119988761] [2021-12-15 17:21:03,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,123 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:03,123 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:03,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:03,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:03,123 INFO L87 Difference]: Start difference. First operand 1785 states and 2636 transitions. cyclomatic complexity: 852 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:03,167 INFO L93 Difference]: Finished difference Result 1785 states and 2635 transitions. [2021-12-15 17:21:03,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:03,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2635 transitions. [2021-12-15 17:21:03,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:03,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2635 transitions. [2021-12-15 17:21:03,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2021-12-15 17:21:03,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2021-12-15 17:21:03,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2635 transitions. [2021-12-15 17:21:03,180 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:03,180 INFO L681 BuchiCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2021-12-15 17:21:03,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2635 transitions. [2021-12-15 17:21:03,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2021-12-15 17:21:03,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4761904761904763) internal successors, (2635), 1784 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2635 transitions. [2021-12-15 17:21:03,199 INFO L704 BuchiCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2021-12-15 17:21:03,199 INFO L587 BuchiCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2021-12-15 17:21:03,199 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:21:03,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2635 transitions. [2021-12-15 17:21:03,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2021-12-15 17:21:03,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:03,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:03,204 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,204 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,205 INFO L791 eck$LassoCheckResult]: Stem: 43738#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44520#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44521#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43258#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 43259#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43161#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43162#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44440#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43780#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43781#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43685#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43686#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44188#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44189#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43447#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43448#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 43871#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43872#L1194 assume !(0 == ~M_E~0); 44020#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44021#L1199-1 assume !(0 == ~T2_E~0); 44318#L1204-1 assume !(0 == ~T3_E~0); 44242#L1209-1 assume !(0 == ~T4_E~0); 44243#L1214-1 assume !(0 == ~T5_E~0); 44628#L1219-1 assume !(0 == ~T6_E~0); 44716#L1224-1 assume !(0 == ~T7_E~0); 43521#L1229-1 assume !(0 == ~T8_E~0); 43078#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43079#L1239-1 assume !(0 == ~T10_E~0); 43121#L1244-1 assume !(0 == ~T11_E~0); 43122#L1249-1 assume !(0 == ~T12_E~0); 43815#L1254-1 assume !(0 == ~E_M~0); 43025#L1259-1 assume !(0 == ~E_1~0); 42989#L1264-1 assume !(0 == ~E_2~0); 42990#L1269-1 assume !(0 == ~E_3~0); 44719#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44658#L1279-1 assume !(0 == ~E_5~0); 43199#L1284-1 assume !(0 == ~E_6~0); 43200#L1289-1 assume !(0 == ~E_7~0); 43878#L1294-1 assume !(0 == ~E_8~0); 43879#L1299-1 assume !(0 == ~E_9~0); 43889#L1304-1 assume !(0 == ~E_10~0); 44710#L1309-1 assume !(0 == ~E_11~0); 44714#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43153#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43075#L586 assume 1 == ~m_pc~0; 43076#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43147#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44212#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43355#L1485 assume !(0 != activate_threads_~tmp~1#1); 43356#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44443#L605 assume !(1 == ~t1_pc~0); 43959#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43710#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43711#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44593#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44289#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43628#L624 assume 1 == ~t2_pc~0; 43127#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43128#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43788#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44617#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 44480#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44358#L643 assume !(1 == ~t3_pc~0); 44205#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43901#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43814#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43457#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 43458#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43219#L662 assume 1 == ~t4_pc~0; 43220#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43178#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43179#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43933#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 43062#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43063#L681 assume !(1 == ~t5_pc~0); 42937#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42938#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43985#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44587#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 43469#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43470#L700 assume 1 == ~t6_pc~0; 44169#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43210#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43211#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43260#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 43261#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44524#L719 assume 1 == ~t7_pc~0; 44598#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43427#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44197#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44198#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 42951#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42952#L738 assume !(1 == ~t8_pc~0); 44324#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44234#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43320#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43321#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44017#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44381#L757 assume 1 == ~t9_pc~0; 44382#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42946#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42947#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44149#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 43977#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43978#L776 assume !(1 == ~t10_pc~0); 42971#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42970#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43359#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43201#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 43202#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43154#L795 assume 1 == ~t11_pc~0; 43155#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43488#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44432#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44433#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 44203#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44191#L814 assume !(1 == ~t12_pc~0); 44046#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44047#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44417#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44517#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 43412#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43413#L1332 assume !(1 == ~M_E~0); 44491#L1332-2 assume !(1 == ~T1_E~0); 44674#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44116#L1342-1 assume !(1 == ~T3_E~0); 44117#L1347-1 assume !(1 == ~T4_E~0); 44512#L1352-1 assume !(1 == ~T5_E~0); 44387#L1357-1 assume !(1 == ~T6_E~0); 43681#L1362-1 assume !(1 == ~T7_E~0); 43682#L1367-1 assume !(1 == ~T8_E~0); 43295#L1372-1 assume !(1 == ~T9_E~0); 43296#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43601#L1382-1 assume !(1 == ~T11_E~0); 43602#L1387-1 assume !(1 == ~T12_E~0); 44287#L1392-1 assume !(1 == ~E_M~0); 43629#L1397-1 assume !(1 == ~E_1~0); 43630#L1402-1 assume !(1 == ~E_2~0); 43306#L1407-1 assume !(1 == ~E_3~0); 43307#L1412-1 assume !(1 == ~E_4~0); 44458#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44459#L1422-1 assume !(1 == ~E_6~0); 44675#L1427-1 assume !(1 == ~E_7~0); 43489#L1432-1 assume !(1 == ~E_8~0); 43490#L1437-1 assume !(1 == ~E_9~0); 44408#L1442-1 assume !(1 == ~E_10~0); 44409#L1447-1 assume !(1 == ~E_11~0); 44277#L1452-1 assume !(1 == ~E_12~0); 43095#L1457-1 assume { :end_inline_reset_delta_events } true; 43096#L1803-2 [2021-12-15 17:21:03,205 INFO L793 eck$LassoCheckResult]: Loop: 43096#L1803-2 assume !false; 43432#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42968#L1169 assume !false; 43557#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43662#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43163#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43164#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 43939#L996 assume !(0 != eval_~tmp~0#1); 44051#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44052#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44022#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44023#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43267#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43268#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43516#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42960#L1214-3 assume !(0 == ~T5_E~0); 42961#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43708#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43709#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43740#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43133#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43134#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43565#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44142#L1254-3 assume !(0 == ~E_M~0); 44622#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44257#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43139#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43140#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44654#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43706#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43707#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43690#L1294-3 assume !(0 == ~E_8~0); 43691#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44073#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44074#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43603#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43604#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43612#L586-42 assume !(1 == ~m_pc~0); 43613#L586-44 is_master_triggered_~__retres1~0#1 := 0; 43208#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43209#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44633#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 43730#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43731#L605-42 assume 1 == ~t1_pc~0; 44328#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44036#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44037#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43732#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43733#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43744#L624-42 assume !(1 == ~t2_pc~0); 43745#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43888#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43048#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43049#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43562#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43563#L643-42 assume 1 == ~t3_pc~0; 43904#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43869#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43870#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43702#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43703#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44418#L662-42 assume !(1 == ~t4_pc~0); 44611#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43231#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43232#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43798#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44650#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44616#L681-42 assume !(1 == ~t5_pc~0); 43091#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 43092#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43451#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43452#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44466#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43588#L700-42 assume 1 == ~t6_pc~0; 43589#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43399#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44388#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44474#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44475#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44664#L719-42 assume !(1 == ~t7_pc~0); 43283#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43284#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43334#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43335#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 43665#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43666#L738-42 assume 1 == ~t8_pc~0; 43858#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43621#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43174#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43137#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43138#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43658#L757-42 assume 1 == ~t9_pc~0; 43994#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43318#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43319#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43462#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43436#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43437#L776-42 assume 1 == ~t10_pc~0; 44407#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44394#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44441#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44703#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44704#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44231#L795-42 assume !(1 == ~t11_pc~0); 44232#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43278#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43279#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43374#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43375#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43675#L814-42 assume !(1 == ~t12_pc~0); 43552#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43190#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43191#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42999#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43000#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43151#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43152#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43125#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43126#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43934#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44105#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44106#L1357-3 assume !(1 == ~T6_E~0); 44544#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44712#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44708#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42980#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42981#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43584#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43585#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44415#L1397-3 assume !(1 == ~E_1~0); 44673#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44056#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43236#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43237#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43953#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43954#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44543#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44312#L1437-3 assume !(1 == ~E_9~0); 44075#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44076#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43034#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43035#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43640#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43486#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44298#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 43227#L1822 assume !(0 == start_simulation_~tmp~3#1); 43228#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44177#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43482#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43483#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 44014#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44126#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44071#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 44072#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 43096#L1803-2 [2021-12-15 17:21:03,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,205 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2021-12-15 17:21:03,205 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109228247] [2021-12-15 17:21:03,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,206 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109228247] [2021-12-15 17:21:03,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109228247] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,262 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,262 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,263 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99570437] [2021-12-15 17:21:03,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,263 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:03,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1797209546, now seen corresponding path program 2 times [2021-12-15 17:21:03,263 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389976939] [2021-12-15 17:21:03,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,264 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,301 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389976939] [2021-12-15 17:21:03,301 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389976939] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,301 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,301 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,301 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970461125] [2021-12-15 17:21:03,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,301 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:03,301 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:03,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:03,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:03,302 INFO L87 Difference]: Start difference. First operand 1785 states and 2635 transitions. cyclomatic complexity: 851 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:03,383 INFO L93 Difference]: Finished difference Result 3314 states and 4876 transitions. [2021-12-15 17:21:03,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:03,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3314 states and 4876 transitions. [2021-12-15 17:21:03,394 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3125 [2021-12-15 17:21:03,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3314 states to 3314 states and 4876 transitions. [2021-12-15 17:21:03,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3314 [2021-12-15 17:21:03,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3314 [2021-12-15 17:21:03,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3314 states and 4876 transitions. [2021-12-15 17:21:03,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:03,406 INFO L681 BuchiCegarLoop]: Abstraction has 3314 states and 4876 transitions. [2021-12-15 17:21:03,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3314 states and 4876 transitions. [2021-12-15 17:21:03,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3314 to 3314. [2021-12-15 17:21:03,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3314 states, 3314 states have (on average 1.4713337356668679) internal successors, (4876), 3313 states have internal predecessors, (4876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3314 states to 3314 states and 4876 transitions. [2021-12-15 17:21:03,446 INFO L704 BuchiCegarLoop]: Abstraction has 3314 states and 4876 transitions. [2021-12-15 17:21:03,446 INFO L587 BuchiCegarLoop]: Abstraction has 3314 states and 4876 transitions. [2021-12-15 17:21:03,446 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:21:03,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3314 states and 4876 transitions. [2021-12-15 17:21:03,452 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3125 [2021-12-15 17:21:03,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:03,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:03,453 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,454 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,454 INFO L791 eck$LassoCheckResult]: Stem: 48849#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 48850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 49661#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49662#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48368#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 48369#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48271#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48272#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49574#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48893#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48894#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48796#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48797#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49312#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49313#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48557#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48558#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48986#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48987#L1194 assume !(0 == ~M_E~0); 49139#L1194-2 assume !(0 == ~T1_E~0); 49140#L1199-1 assume !(0 == ~T2_E~0); 49444#L1204-1 assume !(0 == ~T3_E~0); 49368#L1209-1 assume !(0 == ~T4_E~0); 49369#L1214-1 assume !(0 == ~T5_E~0); 49784#L1219-1 assume !(0 == ~T6_E~0); 49888#L1224-1 assume !(0 == ~T7_E~0); 48631#L1229-1 assume !(0 == ~T8_E~0); 48187#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48188#L1239-1 assume !(0 == ~T10_E~0); 48230#L1244-1 assume !(0 == ~T11_E~0); 48231#L1249-1 assume !(0 == ~T12_E~0); 48928#L1254-1 assume !(0 == ~E_M~0); 48134#L1259-1 assume !(0 == ~E_1~0); 48098#L1264-1 assume !(0 == ~E_2~0); 48099#L1269-1 assume !(0 == ~E_3~0); 49894#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 49821#L1279-1 assume !(0 == ~E_5~0); 48309#L1284-1 assume !(0 == ~E_6~0); 48310#L1289-1 assume !(0 == ~E_7~0); 48993#L1294-1 assume !(0 == ~E_8~0); 48994#L1299-1 assume !(0 == ~E_9~0); 49004#L1304-1 assume !(0 == ~E_10~0); 49880#L1309-1 assume !(0 == ~E_11~0); 49886#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 48262#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48184#L586 assume 1 == ~m_pc~0; 48185#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48256#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49338#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48465#L1485 assume !(0 != activate_threads_~tmp~1#1); 48466#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49577#L605 assume !(1 == ~t1_pc~0); 49076#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48821#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48822#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49740#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49415#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48738#L624 assume 1 == ~t2_pc~0; 48236#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48237#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48901#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49771#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 49615#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49484#L643 assume !(1 == ~t3_pc~0); 49331#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49017#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48927#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48567#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 48568#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48329#L662 assume 1 == ~t4_pc~0; 48330#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48288#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48289#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49049#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 48171#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48172#L681 assume !(1 == ~t5_pc~0); 48046#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48047#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49104#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49734#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 48579#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48580#L700 assume 1 == ~t6_pc~0; 49289#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48320#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48321#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48370#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 48371#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49665#L719 assume 1 == ~t7_pc~0; 49748#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48537#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49322#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49323#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 48060#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48061#L738 assume !(1 == ~t8_pc~0); 49450#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49360#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48430#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48431#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49136#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49507#L757 assume 1 == ~t9_pc~0; 49508#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48055#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48056#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49269#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 49096#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49097#L776 assume !(1 == ~t10_pc~0); 48080#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48079#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48469#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48311#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 48312#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48263#L795 assume 1 == ~t11_pc~0; 48264#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48598#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49566#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49567#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 49329#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49315#L814 assume !(1 == ~t12_pc~0); 49166#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49167#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49546#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49657#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 48522#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48523#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 49627#L1332-2 assume !(1 == ~T1_E~0); 49840#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49236#L1342-1 assume !(1 == ~T3_E~0); 49237#L1347-1 assume !(1 == ~T4_E~0); 49652#L1352-1 assume !(1 == ~T5_E~0); 49513#L1357-1 assume !(1 == ~T6_E~0); 48792#L1362-1 assume !(1 == ~T7_E~0); 48793#L1367-1 assume !(1 == ~T8_E~0); 48405#L1372-1 assume !(1 == ~T9_E~0); 48406#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48711#L1382-1 assume !(1 == ~T11_E~0); 48712#L1387-1 assume !(1 == ~T12_E~0); 49413#L1392-1 assume !(1 == ~E_M~0); 48739#L1397-1 assume !(1 == ~E_1~0); 48740#L1402-1 assume !(1 == ~E_2~0); 48416#L1407-1 assume !(1 == ~E_3~0); 48417#L1412-1 assume !(1 == ~E_4~0); 49592#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 49593#L1422-1 assume !(1 == ~E_6~0); 49841#L1427-1 assume !(1 == ~E_7~0); 48599#L1432-1 assume !(1 == ~E_8~0); 48600#L1437-1 assume !(1 == ~E_9~0); 49536#L1442-1 assume !(1 == ~E_10~0); 49537#L1447-1 assume !(1 == ~E_11~0); 50166#L1452-1 assume !(1 == ~E_12~0); 49922#L1457-1 assume { :end_inline_reset_delta_events } true; 49920#L1803-2 [2021-12-15 17:21:03,454 INFO L793 eck$LassoCheckResult]: Loop: 49920#L1803-2 assume !false; 49919#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49917#L1169 assume !false; 49916#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49913#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49902#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 49055#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49056#L996 assume !(0 != eval_~tmp~0#1); 49171#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49172#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49877#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49882#L1194-5 assume !(0 == ~T1_E~0); 48377#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48378#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48626#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48069#L1214-3 assume !(0 == ~T5_E~0); 48070#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48819#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48820#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48851#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48242#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48243#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48675#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49262#L1254-3 assume !(0 == ~E_M~0); 49778#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49383#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48248#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48249#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49817#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48817#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48818#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48801#L1294-3 assume !(0 == ~E_8~0); 48802#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49193#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49194#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48713#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48714#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48722#L586-42 assume !(1 == ~m_pc~0); 48723#L586-44 is_master_triggered_~__retres1~0#1 := 0; 48318#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48319#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49790#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 48841#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48842#L605-42 assume 1 == ~t1_pc~0; 49454#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49156#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49157#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48843#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48844#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48855#L624-42 assume !(1 == ~t2_pc~0); 48856#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 49003#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48157#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48158#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48672#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48673#L643-42 assume 1 == ~t3_pc~0; 49020#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48984#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48985#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48813#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48814#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49547#L662-42 assume !(1 == ~t4_pc~0); 49763#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 48341#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48342#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48911#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49812#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49770#L681-42 assume 1 == ~t5_pc~0; 49030#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48201#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48561#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48562#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49601#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48698#L700-42 assume 1 == ~t6_pc~0; 48699#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48509#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49514#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49609#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49610#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49828#L719-42 assume !(1 == ~t7_pc~0); 48393#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 48394#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48444#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48445#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 48776#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48777#L738-42 assume 1 == ~t8_pc~0; 48973#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48731#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48284#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48246#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48247#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48769#L757-42 assume 1 == ~t9_pc~0; 49113#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48428#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48429#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48572#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48546#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48547#L776-42 assume !(1 == ~t10_pc~0); 49521#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 49522#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49575#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49871#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49872#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49357#L795-42 assume !(1 == ~t11_pc~0); 49358#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 48388#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48389#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48484#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48485#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48786#L814-42 assume !(1 == ~t12_pc~0); 48662#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 48300#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48301#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48108#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48109#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48260#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48261#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48234#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48235#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49050#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49225#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49226#L1357-3 assume !(1 == ~T6_E~0); 49686#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49883#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49878#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48089#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48090#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48694#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48695#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49544#L1397-3 assume !(1 == ~E_1~0); 49839#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49176#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48346#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48347#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49070#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49071#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49685#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49438#L1437-3 assume !(1 == ~E_9~0); 49195#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49196#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48143#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48144#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48751#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 48596#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 49807#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 50246#L1822 assume !(0 == start_simulation_~tmp~3#1); 49300#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49301#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49927#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 49926#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 49925#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49924#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49923#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 49921#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 49920#L1803-2 [2021-12-15 17:21:03,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,454 INFO L85 PathProgramCache]: Analyzing trace with hash 282356976, now seen corresponding path program 1 times [2021-12-15 17:21:03,455 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916398623] [2021-12-15 17:21:03,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,455 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916398623] [2021-12-15 17:21:03,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916398623] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,476 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,476 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,476 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015226956] [2021-12-15 17:21:03,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,476 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:03,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,476 INFO L85 PathProgramCache]: Analyzing trace with hash 354852472, now seen corresponding path program 1 times [2021-12-15 17:21:03,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302311205] [2021-12-15 17:21:03,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,477 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,499 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302311205] [2021-12-15 17:21:03,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302311205] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,499 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,499 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94897011] [2021-12-15 17:21:03,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,500 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:03,500 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:03,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:03,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:03,500 INFO L87 Difference]: Start difference. First operand 3314 states and 4876 transitions. cyclomatic complexity: 1564 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:03,571 INFO L93 Difference]: Finished difference Result 6362 states and 9339 transitions. [2021-12-15 17:21:03,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:03,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6362 states and 9339 transitions. [2021-12-15 17:21:03,590 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6131 [2021-12-15 17:21:03,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6362 states to 6362 states and 9339 transitions. [2021-12-15 17:21:03,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6362 [2021-12-15 17:21:03,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6362 [2021-12-15 17:21:03,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6362 states and 9339 transitions. [2021-12-15 17:21:03,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:03,611 INFO L681 BuchiCegarLoop]: Abstraction has 6362 states and 9339 transitions. [2021-12-15 17:21:03,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6362 states and 9339 transitions. [2021-12-15 17:21:03,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6362 to 6362. [2021-12-15 17:21:03,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6362 states, 6362 states have (on average 1.467934611757309) internal successors, (9339), 6361 states have internal predecessors, (9339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6362 states to 6362 states and 9339 transitions. [2021-12-15 17:21:03,796 INFO L704 BuchiCegarLoop]: Abstraction has 6362 states and 9339 transitions. [2021-12-15 17:21:03,796 INFO L587 BuchiCegarLoop]: Abstraction has 6362 states and 9339 transitions. [2021-12-15 17:21:03,796 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:21:03,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6362 states and 9339 transitions. [2021-12-15 17:21:03,808 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6131 [2021-12-15 17:21:03,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:03,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:03,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:03,810 INFO L791 eck$LassoCheckResult]: Stem: 58551#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 58552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 59382#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59383#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58057#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 58058#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57959#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57960#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59288#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58594#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58595#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58498#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58499#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59020#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59021#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 58248#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 58249#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58686#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58687#L1194 assume !(0 == ~M_E~0); 58840#L1194-2 assume !(0 == ~T1_E~0); 58841#L1199-1 assume !(0 == ~T2_E~0); 59158#L1204-1 assume !(0 == ~T3_E~0); 59077#L1209-1 assume !(0 == ~T4_E~0); 59078#L1214-1 assume !(0 == ~T5_E~0); 59510#L1219-1 assume !(0 == ~T6_E~0); 59618#L1224-1 assume !(0 == ~T7_E~0); 58327#L1229-1 assume !(0 == ~T8_E~0); 57873#L1234-1 assume !(0 == ~T9_E~0); 57874#L1239-1 assume !(0 == ~T10_E~0); 57917#L1244-1 assume !(0 == ~T11_E~0); 57918#L1249-1 assume !(0 == ~T12_E~0); 58629#L1254-1 assume !(0 == ~E_M~0); 57820#L1259-1 assume !(0 == ~E_1~0); 57784#L1264-1 assume !(0 == ~E_2~0); 57785#L1269-1 assume !(0 == ~E_3~0); 59626#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 59545#L1279-1 assume !(0 == ~E_5~0); 57997#L1284-1 assume !(0 == ~E_6~0); 57998#L1289-1 assume !(0 == ~E_7~0); 58693#L1294-1 assume !(0 == ~E_8~0); 58694#L1299-1 assume !(0 == ~E_9~0); 58704#L1304-1 assume !(0 == ~E_10~0); 59609#L1309-1 assume !(0 == ~E_11~0); 59613#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 57950#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57870#L586 assume 1 == ~m_pc~0; 57871#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 57943#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59046#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58156#L1485 assume !(0 != activate_threads_~tmp~1#1); 58157#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59292#L605 assume !(1 == ~t1_pc~0); 58777#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58523#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58524#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59467#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59127#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58439#L624 assume 1 == ~t2_pc~0; 57923#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57924#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58602#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59495#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 59336#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59201#L643 assume !(1 == ~t3_pc~0); 59038#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58718#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58628#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58259#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 58260#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58018#L662 assume 1 == ~t4_pc~0; 58019#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 57976#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57977#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58751#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 57857#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57858#L681 assume !(1 == ~t5_pc~0); 57732#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 57733#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58804#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59460#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 58273#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58274#L700 assume 1 == ~t6_pc~0; 59000#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58008#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58009#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58059#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 58060#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59387#L719 assume 1 == ~t7_pc~0; 59475#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58228#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59029#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59030#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 57746#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57747#L738 assume !(1 == ~t8_pc~0); 59164#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59069#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58121#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58122#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58837#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59225#L757 assume 1 == ~t9_pc~0; 59226#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57741#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57742#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58979#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 58796#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58797#L776 assume !(1 == ~t10_pc~0); 57766#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 57765#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58160#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57999#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 58000#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 57951#L795 assume 1 == ~t11_pc~0; 57952#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58293#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59280#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59281#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 59036#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59023#L814 assume !(1 == ~t12_pc~0); 58866#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58867#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59265#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59379#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 58213#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58214#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 59347#L1332-2 assume !(1 == ~T1_E~0); 60348#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58943#L1342-1 assume !(1 == ~T3_E~0); 58944#L1347-1 assume !(1 == ~T4_E~0); 59373#L1352-1 assume !(1 == ~T5_E~0); 59232#L1357-1 assume !(1 == ~T6_E~0); 59233#L1362-1 assume !(1 == ~T7_E~0); 60168#L1367-1 assume !(1 == ~T8_E~0); 60166#L1372-1 assume !(1 == ~T9_E~0); 60134#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60090#L1382-1 assume !(1 == ~T11_E~0); 60040#L1387-1 assume !(1 == ~T12_E~0); 60000#L1392-1 assume !(1 == ~E_M~0); 59998#L1397-1 assume !(1 == ~E_1~0); 59962#L1402-1 assume !(1 == ~E_2~0); 59960#L1407-1 assume !(1 == ~E_3~0); 59957#L1412-1 assume !(1 == ~E_4~0); 59916#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 59914#L1422-1 assume !(1 == ~E_6~0); 59868#L1427-1 assume !(1 == ~E_7~0); 59747#L1432-1 assume !(1 == ~E_8~0); 59744#L1437-1 assume !(1 == ~E_9~0); 59727#L1442-1 assume !(1 == ~E_10~0); 59711#L1447-1 assume !(1 == ~E_11~0); 59697#L1452-1 assume !(1 == ~E_12~0); 59685#L1457-1 assume { :end_inline_reset_delta_events } true; 59677#L1803-2 [2021-12-15 17:21:03,811 INFO L793 eck$LassoCheckResult]: Loop: 59677#L1803-2 assume !false; 59671#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59666#L1169 assume !false; 59665#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59662#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59651#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59650#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 59648#L996 assume !(0 != eval_~tmp~0#1); 59647#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59646#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59644#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59645#L1194-5 assume !(0 == ~T1_E~0); 61040#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61037#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61036#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61004#L1214-3 assume !(0 == ~T5_E~0); 60978#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60976#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60974#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60973#L1234-3 assume !(0 == ~T9_E~0); 60971#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 60969#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60967#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60965#L1254-3 assume !(0 == ~E_M~0); 60963#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60961#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60959#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60957#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60936#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60933#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 60931#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60929#L1294-3 assume !(0 == ~E_8~0); 60885#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 60883#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 60881#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60878#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 60876#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60875#L586-42 assume !(1 == ~m_pc~0); 59167#L586-44 is_master_triggered_~__retres1~0#1 := 0; 58006#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58007#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59515#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 60698#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60659#L605-42 assume 1 == ~t1_pc~0; 60656#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60654#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60623#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60620#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60619#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60590#L624-42 assume !(1 == ~t2_pc~0); 60586#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 60584#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60582#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60581#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60580#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60579#L643-42 assume 1 == ~t3_pc~0; 60547#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60545#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60506#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60504#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60502#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60471#L662-42 assume !(1 == ~t4_pc~0); 60468#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 60466#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60431#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60397#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60395#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60394#L681-42 assume 1 == ~t5_pc~0; 60391#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60388#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60345#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60303#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60301#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60299#L700-42 assume !(1 == ~t6_pc~0); 60295#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 60260#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60259#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60256#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60254#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60252#L719-42 assume !(1 == ~t7_pc~0); 58083#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 58084#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58135#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58136#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 60188#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60186#L738-42 assume 1 == ~t8_pc~0; 60180#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60178#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60176#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60174#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60173#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60172#L757-42 assume 1 == ~t9_pc~0; 58813#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58119#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58120#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58264#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58237#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58238#L776-42 assume 1 == ~t10_pc~0; 59254#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59240#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59289#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59601#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59602#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59066#L795-42 assume !(1 == ~t11_pc~0); 59067#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 59953#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59950#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59948#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59946#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59944#L814-42 assume 1 == ~t12_pc~0; 59941#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 59939#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59938#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59937#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59935#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57948#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57949#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58966#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59860#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59856#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59853#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59850#L1357-3 assume !(1 == ~T6_E~0); 59847#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 59844#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 59841#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 59836#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59834#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59832#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59830#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59828#L1397-3 assume !(1 == ~E_1~0); 59826#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59823#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59821#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59819#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59817#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59815#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59813#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59810#L1437-3 assume !(1 == ~E_9~0); 59808#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 59806#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 59804#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59802#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59799#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59785#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59783#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 59781#L1822 assume !(0 == start_simulation_~tmp~3#1); 59229#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59773#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 59764#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 59742#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 59725#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59709#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59696#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 59684#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 59677#L1803-2 [2021-12-15 17:21:03,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,811 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2021-12-15 17:21:03,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009194516] [2021-12-15 17:21:03,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,812 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,834 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009194516] [2021-12-15 17:21:03,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009194516] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,835 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,835 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,835 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780736309] [2021-12-15 17:21:03,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,835 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:03,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:03,836 INFO L85 PathProgramCache]: Analyzing trace with hash -447956935, now seen corresponding path program 1 times [2021-12-15 17:21:03,836 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:03,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183817179] [2021-12-15 17:21:03,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:03,836 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:03,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:03,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:03,858 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:03,858 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183817179] [2021-12-15 17:21:03,858 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183817179] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:03,858 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:03,858 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:03,858 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117685364] [2021-12-15 17:21:03,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:03,859 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:03,859 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:03,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:03,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:03,859 INFO L87 Difference]: Start difference. First operand 6362 states and 9339 transitions. cyclomatic complexity: 2981 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:03,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:03,987 INFO L93 Difference]: Finished difference Result 12050 states and 17658 transitions. [2021-12-15 17:21:03,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:03,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12050 states and 17658 transitions. [2021-12-15 17:21:04,030 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11771 [2021-12-15 17:21:04,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12050 states to 12050 states and 17658 transitions. [2021-12-15 17:21:04,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12050 [2021-12-15 17:21:04,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12050 [2021-12-15 17:21:04,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12050 states and 17658 transitions. [2021-12-15 17:21:04,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:04,082 INFO L681 BuchiCegarLoop]: Abstraction has 12050 states and 17658 transitions. [2021-12-15 17:21:04,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12050 states and 17658 transitions. [2021-12-15 17:21:04,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12050 to 12046. [2021-12-15 17:21:04,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12046 states, 12046 states have (on average 1.465548729868836) internal successors, (17654), 12045 states have internal predecessors, (17654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:04,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12046 states to 12046 states and 17654 transitions. [2021-12-15 17:21:04,238 INFO L704 BuchiCegarLoop]: Abstraction has 12046 states and 17654 transitions. [2021-12-15 17:21:04,238 INFO L587 BuchiCegarLoop]: Abstraction has 12046 states and 17654 transitions. [2021-12-15 17:21:04,238 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:21:04,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12046 states and 17654 transitions. [2021-12-15 17:21:04,270 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11771 [2021-12-15 17:21:04,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:04,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:04,350 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,350 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:04,350 INFO L791 eck$LassoCheckResult]: Stem: 76974#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 76975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 77815#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77816#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76476#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 76477#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76379#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76380#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77723#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77014#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77015#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76912#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76913#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77442#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77443#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76667#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76668#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77110#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77111#L1194 assume !(0 == ~M_E~0); 77260#L1194-2 assume !(0 == ~T1_E~0); 77261#L1199-1 assume !(0 == ~T2_E~0); 77582#L1204-1 assume !(0 == ~T3_E~0); 77501#L1209-1 assume !(0 == ~T4_E~0); 77502#L1214-1 assume !(0 == ~T5_E~0); 77936#L1219-1 assume !(0 == ~T6_E~0); 78064#L1224-1 assume !(0 == ~T7_E~0); 76743#L1229-1 assume !(0 == ~T8_E~0); 76303#L1234-1 assume !(0 == ~T9_E~0); 76304#L1239-1 assume !(0 == ~T10_E~0); 76343#L1244-1 assume !(0 == ~T11_E~0); 76344#L1249-1 assume !(0 == ~T12_E~0); 77051#L1254-1 assume !(0 == ~E_M~0); 76242#L1259-1 assume !(0 == ~E_1~0); 76206#L1264-1 assume !(0 == ~E_2~0); 76207#L1269-1 assume !(0 == ~E_3~0); 78076#L1274-1 assume !(0 == ~E_4~0); 77981#L1279-1 assume !(0 == ~E_5~0); 76417#L1284-1 assume !(0 == ~E_6~0); 76418#L1289-1 assume !(0 == ~E_7~0); 77116#L1294-1 assume !(0 == ~E_8~0); 77117#L1299-1 assume !(0 == ~E_9~0); 77128#L1304-1 assume !(0 == ~E_10~0); 78057#L1309-1 assume !(0 == ~E_11~0); 78062#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 76372#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76292#L586 assume 1 == ~m_pc~0; 76293#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76365#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77473#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76573#L1485 assume !(0 != activate_threads_~tmp~1#1); 76574#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77728#L605 assume !(1 == ~t1_pc~0); 77196#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76938#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76939#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77896#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77551#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76853#L624 assume 1 == ~t2_pc~0; 76348#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76349#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77022#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77925#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 77768#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77622#L643 assume !(1 == ~t3_pc~0); 77464#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77144#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77048#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76678#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 76679#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76437#L662 assume 1 == ~t4_pc~0; 76438#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76398#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76399#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77170#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 76281#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76282#L681 assume !(1 == ~t5_pc~0); 76154#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76155#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77225#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77890#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 76690#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76691#L700 assume 1 == ~t6_pc~0; 77420#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76428#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76429#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76478#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 76479#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77819#L719 assume 1 == ~t7_pc~0; 77908#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76645#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77456#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77457#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 76168#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76169#L738 assume !(1 == ~t8_pc~0); 77588#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 77493#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76538#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76539#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77257#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77645#L757 assume 1 == ~t9_pc~0; 77646#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76163#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76164#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77401#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 77215#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77216#L776 assume !(1 == ~t10_pc~0); 76188#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76187#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76580#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76419#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 76420#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76373#L795 assume 1 == ~t11_pc~0; 76374#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76711#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77712#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77713#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 77462#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77445#L814 assume !(1 == ~t12_pc~0); 77286#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77287#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77694#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77812#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 76630#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76631#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 77779#L1332-2 assume !(1 == ~T1_E~0); 78006#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 79675#L1342-1 assume !(1 == ~T3_E~0); 79673#L1347-1 assume !(1 == ~T4_E~0); 79671#L1352-1 assume !(1 == ~T5_E~0); 79669#L1357-1 assume !(1 == ~T6_E~0); 79667#L1362-1 assume !(1 == ~T7_E~0); 77851#L1367-1 assume !(1 == ~T8_E~0); 76513#L1372-1 assume !(1 == ~T9_E~0); 76514#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76826#L1382-1 assume !(1 == ~T11_E~0); 76827#L1387-1 assume !(1 == ~T12_E~0); 77548#L1392-1 assume !(1 == ~E_M~0); 76854#L1397-1 assume !(1 == ~E_1~0); 76855#L1402-1 assume !(1 == ~E_2~0); 76526#L1407-1 assume !(1 == ~E_3~0); 76527#L1412-1 assume !(1 == ~E_4~0); 78055#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78215#L1422-1 assume !(1 == ~E_6~0); 78213#L1427-1 assume !(1 == ~E_7~0); 78192#L1432-1 assume !(1 == ~E_8~0); 78190#L1437-1 assume !(1 == ~E_9~0); 78174#L1442-1 assume !(1 == ~E_10~0); 78157#L1447-1 assume !(1 == ~E_11~0); 78145#L1452-1 assume !(1 == ~E_12~0); 78134#L1457-1 assume { :end_inline_reset_delta_events } true; 78126#L1803-2 [2021-12-15 17:21:04,351 INFO L793 eck$LassoCheckResult]: Loop: 78126#L1803-2 assume !false; 78120#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78115#L1169 assume !false; 78114#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78111#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78100#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78099#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 78097#L996 assume !(0 != eval_~tmp~0#1); 78096#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78095#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78093#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78094#L1194-5 assume !(0 == ~T1_E~0); 79704#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79702#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79700#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79698#L1214-3 assume !(0 == ~T5_E~0); 79696#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79694#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79692#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 79690#L1234-3 assume !(0 == ~T9_E~0); 79688#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 79686#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 79684#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 79682#L1254-3 assume !(0 == ~E_M~0); 79680#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79522#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79251#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79249#L1274-3 assume !(0 == ~E_4~0); 79247#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79245#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79243#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 79242#L1294-3 assume !(0 == ~E_8~0); 79241#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79227#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79225#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79223#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 79220#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79218#L586-42 assume !(1 == ~m_pc~0); 79173#L586-44 is_master_triggered_~__retres1~0#1 := 0; 79163#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79155#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78970#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 78968#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78966#L605-42 assume 1 == ~t1_pc~0; 78963#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 78961#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78959#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78957#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78955#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78953#L624-42 assume 1 == ~t2_pc~0; 78951#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78948#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78946#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78944#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78942#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77900#L643-42 assume !(1 == ~t3_pc~0); 77141#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 77106#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77107#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76930#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76931#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77693#L662-42 assume 1 == ~t4_pc~0; 77920#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76449#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76450#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77032#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77965#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77924#L681-42 assume !(1 == ~t5_pc~0); 76308#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 76309#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78732#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78724#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78715#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78708#L700-42 assume 1 == ~t6_pc~0; 78697#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78694#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78692#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78690#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78688#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78687#L719-42 assume 1 == ~t7_pc~0; 78665#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78658#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78654#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78648#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 78642#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78637#L738-42 assume !(1 == ~t8_pc~0); 78631#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 78627#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78542#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78539#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78537#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78535#L757-42 assume !(1 == ~t9_pc~0); 78533#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 78530#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78528#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78527#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78524#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78522#L776-42 assume 1 == ~t10_pc~0; 78519#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78517#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78515#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78513#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78510#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78439#L795-42 assume 1 == ~t11_pc~0; 78437#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 78434#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78432#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78430#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 78428#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78427#L814-42 assume !(1 == ~t12_pc~0); 78411#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 78401#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 78393#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78386#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78378#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76369#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76370#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77386#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78354#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78349#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78344#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78339#L1357-3 assume !(1 == ~T6_E~0); 78334#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78328#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78323#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78317#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78314#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78311#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78308#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78304#L1397-3 assume !(1 == ~E_1~0); 78301#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78298#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78295#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78291#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78289#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78286#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78284#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78282#L1437-3 assume !(1 == ~E_9~0); 78280#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78278#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78276#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78273#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78270#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78257#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78255#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 78253#L1822 assume !(0 == start_simulation_~tmp~3#1); 77649#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78239#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78210#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78189#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 78173#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78156#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78144#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 78133#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 78126#L1803-2 [2021-12-15 17:21:04,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:04,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2021-12-15 17:21:04,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:04,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404246367] [2021-12-15 17:21:04,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:04,352 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:04,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:04,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:04,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:04,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404246367] [2021-12-15 17:21:04,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404246367] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:04,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:04,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:04,375 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217723483] [2021-12-15 17:21:04,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:04,376 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:04,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:04,376 INFO L85 PathProgramCache]: Analyzing trace with hash -247119365, now seen corresponding path program 1 times [2021-12-15 17:21:04,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:04,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422890658] [2021-12-15 17:21:04,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:04,377 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:04,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:04,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:04,398 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:04,398 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422890658] [2021-12-15 17:21:04,399 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422890658] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:04,399 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:04,399 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:04,399 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025179442] [2021-12-15 17:21:04,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:04,399 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:04,400 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:04,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:04,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:04,400 INFO L87 Difference]: Start difference. First operand 12046 states and 17654 transitions. cyclomatic complexity: 5616 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:04,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:04,549 INFO L93 Difference]: Finished difference Result 22978 states and 33613 transitions. [2021-12-15 17:21:04,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:04,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22978 states and 33613 transitions. [2021-12-15 17:21:04,637 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22679 [2021-12-15 17:21:04,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22978 states to 22978 states and 33613 transitions. [2021-12-15 17:21:04,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22978 [2021-12-15 17:21:04,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22978 [2021-12-15 17:21:04,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22978 states and 33613 transitions. [2021-12-15 17:21:04,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:04,758 INFO L681 BuchiCegarLoop]: Abstraction has 22978 states and 33613 transitions. [2021-12-15 17:21:04,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22978 states and 33613 transitions. [2021-12-15 17:21:05,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22978 to 22970. [2021-12-15 17:21:05,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22970 states, 22970 states have (on average 1.4629952111449718) internal successors, (33605), 22969 states have internal predecessors, (33605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:05,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22970 states to 22970 states and 33605 transitions. [2021-12-15 17:21:05,184 INFO L704 BuchiCegarLoop]: Abstraction has 22970 states and 33605 transitions. [2021-12-15 17:21:05,184 INFO L587 BuchiCegarLoop]: Abstraction has 22970 states and 33605 transitions. [2021-12-15 17:21:05,184 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:21:05,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22970 states and 33605 transitions. [2021-12-15 17:21:05,245 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22679 [2021-12-15 17:21:05,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:05,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:05,246 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:05,247 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:05,247 INFO L791 eck$LassoCheckResult]: Stem: 111999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 112000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 112814#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112815#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111512#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 111513#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111413#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111414#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112724#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112042#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112043#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111945#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111946#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 112462#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112463#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 111702#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111703#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112136#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112137#L1194 assume !(0 == ~M_E~0); 112288#L1194-2 assume !(0 == ~T1_E~0); 112289#L1199-1 assume !(0 == ~T2_E~0); 112597#L1204-1 assume !(0 == ~T3_E~0); 112517#L1209-1 assume !(0 == ~T4_E~0); 112518#L1214-1 assume !(0 == ~T5_E~0); 112929#L1219-1 assume !(0 == ~T6_E~0); 113033#L1224-1 assume !(0 == ~T7_E~0); 111777#L1229-1 assume !(0 == ~T8_E~0); 111337#L1234-1 assume !(0 == ~T9_E~0); 111338#L1239-1 assume !(0 == ~T10_E~0); 111374#L1244-1 assume !(0 == ~T11_E~0); 111375#L1249-1 assume !(0 == ~T12_E~0); 112077#L1254-1 assume !(0 == ~E_M~0); 111276#L1259-1 assume !(0 == ~E_1~0); 111240#L1264-1 assume !(0 == ~E_2~0); 111241#L1269-1 assume !(0 == ~E_3~0); 113038#L1274-1 assume !(0 == ~E_4~0); 112963#L1279-1 assume !(0 == ~E_5~0); 111451#L1284-1 assume !(0 == ~E_6~0); 111452#L1289-1 assume !(0 == ~E_7~0); 112141#L1294-1 assume !(0 == ~E_8~0); 112142#L1299-1 assume !(0 == ~E_9~0); 112154#L1304-1 assume !(0 == ~E_10~0); 113026#L1309-1 assume !(0 == ~E_11~0); 113031#L1314-1 assume !(0 == ~E_12~0); 111406#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111326#L586 assume 1 == ~m_pc~0; 111327#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 111398#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112488#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 111610#L1485 assume !(0 != activate_threads_~tmp~1#1); 111611#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112728#L605 assume !(1 == ~t1_pc~0); 112225#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111971#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111972#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112892#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112567#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111886#L624 assume 1 == ~t2_pc~0; 111381#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 111382#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112050#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112917#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 112768#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112638#L643 assume !(1 == ~t3_pc~0); 112479#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112171#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112076#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111712#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 111713#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111471#L662 assume 1 == ~t4_pc~0; 111472#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111432#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111433#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112197#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 111315#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111316#L681 assume !(1 == ~t5_pc~0); 111188#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 111189#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112253#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112887#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 111724#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111725#L700 assume 1 == ~t6_pc~0; 112441#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111462#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111463#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111514#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 111515#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112818#L719 assume 1 == ~t7_pc~0; 112897#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 111682#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112472#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112473#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 111202#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111203#L738 assume !(1 == ~t8_pc~0); 112603#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 112509#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 111575#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111576#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 112285#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112661#L757 assume 1 == ~t9_pc~0; 112662#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111197#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111198#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112421#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 112245#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112246#L776 assume !(1 == ~t10_pc~0); 111222#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 111221#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111614#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111453#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 111454#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111407#L795 assume 1 == ~t11_pc~0; 111408#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111743#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112716#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112717#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 112477#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112465#L814 assume !(1 == ~t12_pc~0); 112315#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 112316#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112700#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 112811#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 111667#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111668#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 112779#L1332-2 assume !(1 == ~T1_E~0); 113418#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 113416#L1342-1 assume !(1 == ~T3_E~0); 113415#L1347-1 assume !(1 == ~T4_E~0); 113414#L1352-1 assume !(1 == ~T5_E~0); 112668#L1357-1 assume !(1 == ~T6_E~0); 111943#L1362-1 assume !(1 == ~T7_E~0); 111944#L1367-1 assume !(1 == ~T8_E~0); 113294#L1372-1 assume !(1 == ~T9_E~0); 113292#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 113288#L1382-1 assume !(1 == ~T11_E~0); 113286#L1387-1 assume !(1 == ~T12_E~0); 113284#L1392-1 assume !(1 == ~E_M~0); 113282#L1397-1 assume !(1 == ~E_1~0); 113280#L1402-1 assume !(1 == ~E_2~0); 113278#L1407-1 assume !(1 == ~E_3~0); 113248#L1412-1 assume !(1 == ~E_4~0); 113246#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 113191#L1422-1 assume !(1 == ~E_6~0); 113188#L1427-1 assume !(1 == ~E_7~0); 113171#L1432-1 assume !(1 == ~E_8~0); 113167#L1437-1 assume !(1 == ~E_9~0); 113140#L1442-1 assume !(1 == ~E_10~0); 113139#L1447-1 assume !(1 == ~E_11~0); 113104#L1452-1 assume !(1 == ~E_12~0); 113091#L1457-1 assume { :end_inline_reset_delta_events } true; 113083#L1803-2 [2021-12-15 17:21:05,247 INFO L793 eck$LassoCheckResult]: Loop: 113083#L1803-2 assume !false; 113077#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 113072#L1169 assume !false; 113071#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113068#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113057#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113056#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 113054#L996 assume !(0 != eval_~tmp~0#1); 113053#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113052#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 113050#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 113051#L1194-5 assume !(0 == ~T1_E~0); 125857#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 125856#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 125855#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 125854#L1214-3 assume !(0 == ~T5_E~0); 125853#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 125851#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 125848#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 125846#L1234-3 assume !(0 == ~T9_E~0); 125844#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 125842#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 125840#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 125838#L1254-3 assume !(0 == ~E_M~0); 125835#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 125833#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 125831#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 125829#L1274-3 assume !(0 == ~E_4~0); 125827#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 125825#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 125822#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 125820#L1294-3 assume !(0 == ~E_8~0); 125818#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 125815#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 125813#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 125811#L1314-3 assume !(0 == ~E_12~0); 125809#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 125807#L586-42 assume !(1 == ~m_pc~0); 125805#L586-44 is_master_triggered_~__retres1~0#1 := 0; 125801#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125799#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 125797#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 125795#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125793#L605-42 assume 1 == ~t1_pc~0; 125789#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 125787#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125784#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 125782#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 125766#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125755#L624-42 assume 1 == ~t2_pc~0; 125745#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125735#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125726#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125720#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 125713#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125708#L643-42 assume 1 == ~t3_pc~0; 125701#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125697#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125691#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 125684#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 125678#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125673#L662-42 assume !(1 == ~t4_pc~0); 125667#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 125662#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125656#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125649#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 125643#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125638#L681-42 assume 1 == ~t5_pc~0; 125633#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 125628#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125622#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 125615#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 125609#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125604#L700-42 assume 1 == ~t6_pc~0; 125599#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 125593#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125587#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125580#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 125574#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125569#L719-42 assume 1 == ~t7_pc~0; 125563#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125559#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125556#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125555#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 125554#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125553#L738-42 assume !(1 == ~t8_pc~0); 125287#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 125284#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 125282#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 125280#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 125278#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 125275#L757-42 assume !(1 == ~t9_pc~0); 125273#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 125270#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125268#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125266#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 125264#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125263#L776-42 assume !(1 == ~t10_pc~0); 125113#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 113673#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 113671#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 113669#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 113666#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 113664#L795-42 assume !(1 == ~t11_pc~0); 113661#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 113659#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 113657#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 113655#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 113654#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 113651#L814-42 assume !(1 == ~t12_pc~0); 113649#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 113646#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 113644#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 113642#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 113524#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113411#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 111403#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 113406#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 113404#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 113402#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 113400#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 113398#L1357-3 assume !(1 == ~T6_E~0); 113335#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 113333#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 113331#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 113327#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 113325#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 113323#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 113275#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 113272#L1397-3 assume !(1 == ~E_1~0); 113270#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 113268#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 113244#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 113240#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 113238#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 113236#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 113234#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 113233#L1437-3 assume !(1 == ~E_9~0); 113232#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 113230#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 113228#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 113224#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113186#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113170#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113166#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 113165#L1822 assume !(0 == start_simulation_~tmp~3#1); 112665#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 113133#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 113124#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 113122#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 113120#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 113118#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 113101#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 113090#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 113083#L1803-2 [2021-12-15 17:21:05,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:05,248 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2021-12-15 17:21:05,248 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:05,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909340] [2021-12-15 17:21:05,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:05,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:05,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:05,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:05,275 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:05,275 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909340] [2021-12-15 17:21:05,275 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909340] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:05,275 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:05,275 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:05,275 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677869083] [2021-12-15 17:21:05,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:05,276 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:05,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:05,276 INFO L85 PathProgramCache]: Analyzing trace with hash 1323126270, now seen corresponding path program 1 times [2021-12-15 17:21:05,276 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:05,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261491093] [2021-12-15 17:21:05,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:05,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:05,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:05,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:05,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:05,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [261491093] [2021-12-15 17:21:05,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [261491093] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:05,305 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:05,305 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:05,305 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414608688] [2021-12-15 17:21:05,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:05,305 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:05,305 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:05,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:05,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:05,306 INFO L87 Difference]: Start difference. First operand 22970 states and 33605 transitions. cyclomatic complexity: 10651 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:05,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:05,489 INFO L93 Difference]: Finished difference Result 45407 states and 66040 transitions. [2021-12-15 17:21:05,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:05,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45407 states and 66040 transitions. [2021-12-15 17:21:05,816 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45085 [2021-12-15 17:21:06,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45407 states to 45407 states and 66040 transitions. [2021-12-15 17:21:06,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45407 [2021-12-15 17:21:06,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45407 [2021-12-15 17:21:06,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45407 states and 66040 transitions. [2021-12-15 17:21:06,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:06,095 INFO L681 BuchiCegarLoop]: Abstraction has 45407 states and 66040 transitions. [2021-12-15 17:21:06,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45407 states and 66040 transitions. [2021-12-15 17:21:06,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45407 to 43967. [2021-12-15 17:21:06,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43967 states, 43967 states have (on average 1.4558191370800828) internal successors, (64008), 43966 states have internal predecessors, (64008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:06,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43967 states to 43967 states and 64008 transitions. [2021-12-15 17:21:06,620 INFO L704 BuchiCegarLoop]: Abstraction has 43967 states and 64008 transitions. [2021-12-15 17:21:06,620 INFO L587 BuchiCegarLoop]: Abstraction has 43967 states and 64008 transitions. [2021-12-15 17:21:06,620 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:21:06,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43967 states and 64008 transitions. [2021-12-15 17:21:06,821 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43645 [2021-12-15 17:21:06,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:06,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:06,823 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,823 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:06,823 INFO L791 eck$LassoCheckResult]: Stem: 180396#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 180397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 181344#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 181345#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 179897#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 179898#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 179796#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 179797#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 181219#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 180442#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180443#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 180341#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 180342#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 180895#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 180896#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 180092#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 180093#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 180541#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 180542#L1194 assume !(0 == ~M_E~0); 180706#L1194-2 assume !(0 == ~T1_E~0); 180707#L1199-1 assume !(0 == ~T2_E~0); 181059#L1204-1 assume !(0 == ~T3_E~0); 180964#L1209-1 assume !(0 == ~T4_E~0); 180965#L1214-1 assume !(0 == ~T5_E~0); 181516#L1219-1 assume !(0 == ~T6_E~0); 181711#L1224-1 assume !(0 == ~T7_E~0); 180168#L1229-1 assume !(0 == ~T8_E~0); 179712#L1234-1 assume !(0 == ~T9_E~0); 179713#L1239-1 assume !(0 == ~T10_E~0); 179754#L1244-1 assume !(0 == ~T11_E~0); 179755#L1249-1 assume !(0 == ~T12_E~0); 180479#L1254-1 assume !(0 == ~E_M~0); 179660#L1259-1 assume !(0 == ~E_1~0); 179624#L1264-1 assume !(0 == ~E_2~0); 179625#L1269-1 assume !(0 == ~E_3~0); 181725#L1274-1 assume !(0 == ~E_4~0); 181572#L1279-1 assume !(0 == ~E_5~0); 179835#L1284-1 assume !(0 == ~E_6~0); 179836#L1289-1 assume !(0 == ~E_7~0); 180550#L1294-1 assume !(0 == ~E_8~0); 180551#L1299-1 assume !(0 == ~E_9~0); 180562#L1304-1 assume !(0 == ~E_10~0); 181695#L1309-1 assume !(0 == ~E_11~0); 181705#L1314-1 assume !(0 == ~E_12~0); 179787#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 179710#L586 assume !(1 == ~m_pc~0); 179711#L586-2 is_master_triggered_~__retres1~0#1 := 0; 179780#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 180928#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 179998#L1485 assume !(0 != activate_threads_~tmp~1#1); 179999#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 181223#L605 assume !(1 == ~t1_pc~0); 180642#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 180367#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180368#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 181461#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 181024#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180280#L624 assume 1 == ~t2_pc~0; 179760#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 179761#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180452#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 181499#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 181282#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 181110#L643 assume !(1 == ~t3_pc~0); 180920#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 180578#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180478#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 180102#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 180103#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 179855#L662 assume 1 == ~t4_pc~0; 179856#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 179814#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179815#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 180613#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 179697#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 179698#L681 assume !(1 == ~t5_pc~0); 179572#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 179573#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180669#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 181448#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 180116#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 180117#L700 assume 1 == ~t6_pc~0; 180873#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 179845#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 179846#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 179899#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 179900#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 181348#L719 assume 1 == ~t7_pc~0; 181471#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 180070#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180906#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 180907#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 179586#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 179587#L738 assume !(1 == ~t8_pc~0); 181065#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 180956#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 179963#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 179964#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180703#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 181140#L757 assume 1 == ~t9_pc~0; 181141#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 179581#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 179582#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 180847#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 180661#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 180662#L776 assume !(1 == ~t10_pc~0); 179606#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 179605#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 180002#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 179837#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 179838#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 179788#L795 assume 1 == ~t11_pc~0; 179789#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 180135#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 181208#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 181209#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 180914#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 180898#L814 assume !(1 == ~t12_pc~0); 180733#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 180734#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 181186#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 181341#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 180055#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180056#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 181298#L1332-2 assume !(1 == ~T1_E~0); 184193#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 184191#L1342-1 assume !(1 == ~T3_E~0); 184190#L1347-1 assume !(1 == ~T4_E~0); 184189#L1352-1 assume !(1 == ~T5_E~0); 184188#L1357-1 assume !(1 == ~T6_E~0); 183642#L1362-1 assume !(1 == ~T7_E~0); 183640#L1367-1 assume !(1 == ~T8_E~0); 183638#L1372-1 assume !(1 == ~T9_E~0); 183636#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 183250#L1382-1 assume !(1 == ~T11_E~0); 183248#L1387-1 assume !(1 == ~T12_E~0); 183246#L1392-1 assume !(1 == ~E_M~0); 183244#L1397-1 assume !(1 == ~E_1~0); 182995#L1402-1 assume !(1 == ~E_2~0); 182993#L1407-1 assume !(1 == ~E_3~0); 182990#L1412-1 assume !(1 == ~E_4~0); 182988#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 182803#L1422-1 assume !(1 == ~E_6~0); 182801#L1427-1 assume !(1 == ~E_7~0); 182800#L1432-1 assume !(1 == ~E_8~0); 182765#L1437-1 assume !(1 == ~E_9~0); 182745#L1442-1 assume !(1 == ~E_10~0); 182743#L1447-1 assume !(1 == ~E_11~0); 182723#L1452-1 assume !(1 == ~E_12~0); 182710#L1457-1 assume { :end_inline_reset_delta_events } true; 182702#L1803-2 [2021-12-15 17:21:06,824 INFO L793 eck$LassoCheckResult]: Loop: 182702#L1803-2 assume !false; 182696#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 182691#L1169 assume !false; 182690#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 182687#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 182676#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 182675#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 182673#L996 assume !(0 != eval_~tmp~0#1); 182672#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 182671#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 182667#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 182668#L1194-5 assume !(0 == ~T1_E~0); 184691#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 184689#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 184687#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 184685#L1214-3 assume !(0 == ~T5_E~0); 184683#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 184681#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 184679#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 184677#L1234-3 assume !(0 == ~T9_E~0); 184675#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 184673#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 184671#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 184669#L1254-3 assume !(0 == ~E_M~0); 184667#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 184665#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 184663#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 184661#L1274-3 assume !(0 == ~E_4~0); 184659#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 184657#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 184655#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 184186#L1294-3 assume !(0 == ~E_8~0); 184185#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 184183#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 184181#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 184179#L1314-3 assume !(0 == ~E_12~0); 184176#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 184174#L586-42 assume !(1 == ~m_pc~0); 184172#L586-44 is_master_triggered_~__retres1~0#1 := 0; 184170#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 184168#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 184166#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 184164#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 184162#L605-42 assume !(1 == ~t1_pc~0); 184160#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 184157#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 184155#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 184153#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 184151#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184149#L624-42 assume !(1 == ~t2_pc~0); 184146#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 184144#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184142#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 184140#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 184138#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 184136#L643-42 assume !(1 == ~t3_pc~0); 184134#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 184131#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 184129#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 184127#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 184125#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184123#L662-42 assume !(1 == ~t4_pc~0); 184120#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 184118#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184116#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 184114#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 184112#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 184110#L681-42 assume 1 == ~t5_pc~0; 184107#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 184104#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 184102#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 184100#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 184098#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 184096#L700-42 assume 1 == ~t6_pc~0; 184094#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 184090#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184088#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 184086#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 184084#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 184082#L719-42 assume !(1 == ~t7_pc~0); 184080#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 184076#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 184074#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 184072#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 184070#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 184068#L738-42 assume !(1 == ~t8_pc~0); 184066#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 183625#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 183622#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 183620#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 183618#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 183616#L757-42 assume !(1 == ~t9_pc~0); 183614#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 183611#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 183608#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 183606#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 183604#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 183602#L776-42 assume !(1 == ~t10_pc~0); 183600#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 183597#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 183594#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 183592#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 183590#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 183588#L795-42 assume 1 == ~t11_pc~0; 183586#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 183583#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 183580#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 183578#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 183576#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 183574#L814-42 assume !(1 == ~t12_pc~0); 183558#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 183555#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 183553#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 183550#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 183548#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183193#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 182959#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 182955#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 182953#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 182951#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 182949#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 182947#L1357-3 assume !(1 == ~T6_E~0); 182945#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 182943#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 182939#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 182935#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 182933#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 182931#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 182929#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 182927#L1397-3 assume !(1 == ~E_1~0); 182925#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 182923#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 182919#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 182915#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 182913#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 182911#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 182909#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 182907#L1437-3 assume !(1 == ~E_9~0); 182905#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 182903#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 182902#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 182899#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 182896#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 182883#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 182881#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 182878#L1822 assume !(0 == start_simulation_~tmp~3#1); 181144#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 182793#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 182784#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 182763#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 182762#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 182741#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 182720#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 182709#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 182702#L1803-2 [2021-12-15 17:21:06,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2021-12-15 17:21:06,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299305558] [2021-12-15 17:21:06,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:06,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:06,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:06,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299305558] [2021-12-15 17:21:06,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299305558] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:06,856 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:06,856 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:06,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088404196] [2021-12-15 17:21:06,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:06,857 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:06,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:06,857 INFO L85 PathProgramCache]: Analyzing trace with hash -1827927615, now seen corresponding path program 1 times [2021-12-15 17:21:06,857 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:06,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944497406] [2021-12-15 17:21:06,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:06,857 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:06,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:06,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:06,880 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:06,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944497406] [2021-12-15 17:21:06,880 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944497406] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:06,880 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:06,880 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:06,880 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306190244] [2021-12-15 17:21:06,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:06,881 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:06,881 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:06,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:06,882 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:06,882 INFO L87 Difference]: Start difference. First operand 43967 states and 64008 transitions. cyclomatic complexity: 20073 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:07,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:07,506 INFO L93 Difference]: Finished difference Result 125535 states and 182372 transitions. [2021-12-15 17:21:07,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:07,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125535 states and 182372 transitions. [2021-12-15 17:21:08,209 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 124680 [2021-12-15 17:21:08,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125535 states to 125535 states and 182372 transitions. [2021-12-15 17:21:08,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125535 [2021-12-15 17:21:08,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125535 [2021-12-15 17:21:08,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125535 states and 182372 transitions. [2021-12-15 17:21:08,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:08,930 INFO L681 BuchiCegarLoop]: Abstraction has 125535 states and 182372 transitions. [2021-12-15 17:21:08,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125535 states and 182372 transitions. [2021-12-15 17:21:09,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125535 to 45176. [2021-12-15 17:21:09,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45176 states, 45176 states have (on average 1.443620506463609) internal successors, (65217), 45175 states have internal predecessors, (65217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:09,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45176 states to 45176 states and 65217 transitions. [2021-12-15 17:21:09,912 INFO L704 BuchiCegarLoop]: Abstraction has 45176 states and 65217 transitions. [2021-12-15 17:21:09,912 INFO L587 BuchiCegarLoop]: Abstraction has 45176 states and 65217 transitions. [2021-12-15 17:21:09,912 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:21:09,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45176 states and 65217 transitions. [2021-12-15 17:21:10,011 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44851 [2021-12-15 17:21:10,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:10,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:10,013 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:10,013 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:10,013 INFO L791 eck$LassoCheckResult]: Stem: 349921#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 349922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 350878#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 350879#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 349413#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 349414#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 349312#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 349313#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 350750#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 349959#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 349960#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 349859#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 349860#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 350407#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 350408#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 349607#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 349608#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 350061#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 350062#L1194 assume !(0 == ~M_E~0); 350217#L1194-2 assume !(0 == ~T1_E~0); 350218#L1199-1 assume !(0 == ~T2_E~0); 350571#L1204-1 assume !(0 == ~T3_E~0); 350476#L1209-1 assume !(0 == ~T4_E~0); 350477#L1214-1 assume !(0 == ~T5_E~0); 351045#L1219-1 assume !(0 == ~T6_E~0); 351247#L1224-1 assume !(0 == ~T7_E~0); 349687#L1229-1 assume !(0 == ~T8_E~0); 349236#L1234-1 assume !(0 == ~T9_E~0); 349237#L1239-1 assume !(0 == ~T10_E~0); 349274#L1244-1 assume !(0 == ~T11_E~0); 349275#L1249-1 assume !(0 == ~T12_E~0); 349995#L1254-1 assume !(0 == ~E_M~0); 349175#L1259-1 assume !(0 == ~E_1~0); 349139#L1264-1 assume !(0 == ~E_2~0); 349140#L1269-1 assume !(0 == ~E_3~0); 351265#L1274-1 assume !(0 == ~E_4~0); 351100#L1279-1 assume !(0 == ~E_5~0); 349350#L1284-1 assume !(0 == ~E_6~0); 349351#L1289-1 assume !(0 == ~E_7~0); 350069#L1294-1 assume !(0 == ~E_8~0); 350070#L1299-1 assume !(0 == ~E_9~0); 350081#L1304-1 assume !(0 == ~E_10~0); 351235#L1309-1 assume !(0 == ~E_11~0); 351243#L1314-1 assume !(0 == ~E_12~0); 349305#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349226#L586 assume !(1 == ~m_pc~0); 349227#L586-2 is_master_triggered_~__retres1~0#1 := 0; 349296#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 350444#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349513#L1485 assume !(0 != activate_threads_~tmp~1#1); 349514#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350755#L605 assume !(1 == ~t1_pc~0); 350152#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 349885#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 349886#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 351035#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 350537#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 349801#L624 assume 1 == ~t2_pc~0; 349279#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 349280#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 349968#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 351026#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 350814#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350625#L643 assume !(1 == ~t3_pc~0); 350437#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 350099#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 349994#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 349617#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 349618#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 349370#L662 assume 1 == ~t4_pc~0; 349371#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 349331#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 349332#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350125#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 349215#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 349216#L681 assume !(1 == ~t5_pc~0); 349087#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 349088#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350179#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 350975#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 349631#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 349632#L700 assume 1 == ~t6_pc~0; 350381#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 349360#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 349361#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 349415#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 349416#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 350883#L719 assume 1 == ~t7_pc~0; 350994#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 349586#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350420#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 350421#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 349101#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 349102#L738 assume !(1 == ~t8_pc~0); 350579#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 350468#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 349478#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 349479#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 350214#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 350653#L757 assume 1 == ~t9_pc~0; 350654#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 349096#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 349097#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 350359#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 350171#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 350172#L776 assume !(1 == ~t10_pc~0); 349121#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 349120#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 349517#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 349352#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 349353#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 349306#L795 assume 1 == ~t11_pc~0; 349307#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 349654#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 350741#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 350742#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 350428#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 350410#L814 assume !(1 == ~t12_pc~0); 350245#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 350246#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 350716#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 350875#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 349570#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 349571#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 350832#L1332-2 assume !(1 == ~T1_E~0); 351142#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 352528#L1342-1 assume !(1 == ~T3_E~0); 352526#L1347-1 assume !(1 == ~T4_E~0); 352492#L1352-1 assume !(1 == ~T5_E~0); 352490#L1357-1 assume !(1 == ~T6_E~0); 349857#L1362-1 assume !(1 == ~T7_E~0); 349858#L1367-1 assume !(1 == ~T8_E~0); 350928#L1372-1 assume !(1 == ~T9_E~0); 352461#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 352459#L1382-1 assume !(1 == ~T11_E~0); 352457#L1387-1 assume !(1 == ~T12_E~0); 352455#L1392-1 assume !(1 == ~E_M~0); 352453#L1397-1 assume !(1 == ~E_1~0); 352451#L1402-1 assume !(1 == ~E_2~0); 352449#L1407-1 assume !(1 == ~E_3~0); 352447#L1412-1 assume !(1 == ~E_4~0); 352419#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 352387#L1422-1 assume !(1 == ~E_6~0); 352385#L1427-1 assume !(1 == ~E_7~0); 352362#L1432-1 assume !(1 == ~E_8~0); 352360#L1437-1 assume !(1 == ~E_9~0); 352344#L1442-1 assume !(1 == ~E_10~0); 352342#L1447-1 assume !(1 == ~E_11~0); 352329#L1452-1 assume !(1 == ~E_12~0); 352316#L1457-1 assume { :end_inline_reset_delta_events } true; 352308#L1803-2 [2021-12-15 17:21:10,014 INFO L793 eck$LassoCheckResult]: Loop: 352308#L1803-2 assume !false; 352302#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 352297#L1169 assume !false; 352296#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352293#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352282#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352281#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 352279#L996 assume !(0 != eval_~tmp~0#1); 352278#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 352277#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 352274#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 352275#L1194-5 assume !(0 == ~T1_E~0); 365942#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 365940#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 365938#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 365935#L1214-3 assume !(0 == ~T5_E~0); 365933#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 365931#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 365929#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 365927#L1234-3 assume !(0 == ~T9_E~0); 365923#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 365921#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 365919#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 365918#L1254-3 assume !(0 == ~E_M~0); 365917#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 365916#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 365915#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 365914#L1274-3 assume !(0 == ~E_4~0); 365913#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 365912#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 365911#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 365910#L1294-3 assume !(0 == ~E_8~0); 365909#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 365908#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 365907#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 365906#L1314-3 assume !(0 == ~E_12~0); 365905#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 365904#L586-42 assume !(1 == ~m_pc~0); 365903#L586-44 is_master_triggered_~__retres1~0#1 := 0; 365902#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 365901#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 365900#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 365899#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365898#L605-42 assume !(1 == ~t1_pc~0); 365897#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 365895#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365893#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 365891#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 365888#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365886#L624-42 assume 1 == ~t2_pc~0; 365883#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 365880#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365878#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 365876#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 365874#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365872#L643-42 assume !(1 == ~t3_pc~0); 365869#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 365866#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365864#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 365862#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 365860#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365858#L662-42 assume 1 == ~t4_pc~0; 365855#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 365852#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 365850#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 365848#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 365846#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 365844#L681-42 assume !(1 == ~t5_pc~0); 365841#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 365838#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 365836#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 365834#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 365832#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 365830#L700-42 assume 1 == ~t6_pc~0; 365827#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 365824#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 365822#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 365820#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 365818#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 365817#L719-42 assume !(1 == ~t7_pc~0); 365813#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 365810#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 365808#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 365807#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 365806#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 365805#L738-42 assume !(1 == ~t8_pc~0); 365804#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 365802#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 365801#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 365800#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 365799#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 365798#L757-42 assume !(1 == ~t9_pc~0); 365797#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 365795#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 365794#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 365793#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 365792#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 365791#L776-42 assume 1 == ~t10_pc~0; 365789#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 365788#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 365787#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 365786#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 365785#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 365784#L795-42 assume 1 == ~t11_pc~0; 365783#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 365781#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 365780#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 365779#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 365778#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 365777#L814-42 assume !(1 == ~t12_pc~0); 363904#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 363900#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 363898#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 363834#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 363825#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363818#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349301#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 350345#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 363747#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 363736#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 363729#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 363721#L1357-3 assume !(1 == ~T6_E~0); 363713#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 363705#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 363698#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 363691#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 363644#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 352703#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 352701#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 352673#L1397-3 assume !(1 == ~E_1~0); 352671#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 352669#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 352645#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 352624#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 352597#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 352595#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 352594#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 352592#L1437-3 assume !(1 == ~E_9~0); 352555#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 352553#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 352550#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 352546#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352520#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352481#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352476#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 352442#L1822 assume !(0 == start_simulation_~tmp~3#1); 350657#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 352413#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 352386#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 352384#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 352358#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352340#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 352326#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 352315#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 352308#L1803-2 [2021-12-15 17:21:10,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:10,014 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2021-12-15 17:21:10,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:10,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920607022] [2021-12-15 17:21:10,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:10,015 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:10,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:10,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:10,037 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:10,037 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920607022] [2021-12-15 17:21:10,037 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920607022] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:10,038 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:10,038 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:10,038 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492498358] [2021-12-15 17:21:10,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:10,038 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:10,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:10,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1489994113, now seen corresponding path program 1 times [2021-12-15 17:21:10,039 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:10,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986256735] [2021-12-15 17:21:10,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:10,039 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:10,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:10,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:10,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:10,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986256735] [2021-12-15 17:21:10,061 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986256735] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:10,061 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:10,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:10,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820747061] [2021-12-15 17:21:10,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:10,062 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:10,062 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:10,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:10,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:10,063 INFO L87 Difference]: Start difference. First operand 45176 states and 65217 transitions. cyclomatic complexity: 20073 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:10,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:10,657 INFO L93 Difference]: Finished difference Result 126045 states and 180583 transitions. [2021-12-15 17:21:10,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:10,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126045 states and 180583 transitions. [2021-12-15 17:21:11,307 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125405 [2021-12-15 17:21:11,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126045 states to 126045 states and 180583 transitions. [2021-12-15 17:21:11,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126045 [2021-12-15 17:21:11,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126045 [2021-12-15 17:21:11,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126045 states and 180583 transitions. [2021-12-15 17:21:11,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:11,919 INFO L681 BuchiCegarLoop]: Abstraction has 126045 states and 180583 transitions. [2021-12-15 17:21:11,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126045 states and 180583 transitions. [2021-12-15 17:21:13,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126045 to 123357. [2021-12-15 17:21:13,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123357 states, 123357 states have (on average 1.4338140518981493) internal successors, (176871), 123356 states have internal predecessors, (176871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:13,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123357 states to 123357 states and 176871 transitions. [2021-12-15 17:21:13,398 INFO L704 BuchiCegarLoop]: Abstraction has 123357 states and 176871 transitions. [2021-12-15 17:21:13,398 INFO L587 BuchiCegarLoop]: Abstraction has 123357 states and 176871 transitions. [2021-12-15 17:21:13,398 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:21:13,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123357 states and 176871 transitions. [2021-12-15 17:21:14,042 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 122909 [2021-12-15 17:21:14,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:14,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:14,059 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:14,060 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:14,060 INFO L791 eck$LassoCheckResult]: Stem: 521132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 521133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 522045#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 522046#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 520640#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 520641#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 520542#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 520543#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 521927#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 521176#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 521177#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 521077#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 521078#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 521623#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 521624#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 520829#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 520830#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 521273#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 521274#L1194 assume !(0 == ~M_E~0); 521432#L1194-2 assume !(0 == ~T1_E~0); 521433#L1199-1 assume !(0 == ~T2_E~0); 521770#L1204-1 assume !(0 == ~T3_E~0); 521682#L1209-1 assume !(0 == ~T4_E~0); 521683#L1214-1 assume !(0 == ~T5_E~0); 522189#L1219-1 assume !(0 == ~T6_E~0); 522335#L1224-1 assume !(0 == ~T7_E~0); 520906#L1229-1 assume !(0 == ~T8_E~0); 520460#L1234-1 assume !(0 == ~T9_E~0); 520461#L1239-1 assume !(0 == ~T10_E~0); 520503#L1244-1 assume !(0 == ~T11_E~0); 520504#L1249-1 assume !(0 == ~T12_E~0); 521213#L1254-1 assume !(0 == ~E_M~0); 520405#L1259-1 assume !(0 == ~E_1~0); 520370#L1264-1 assume !(0 == ~E_2~0); 520371#L1269-1 assume !(0 == ~E_3~0); 522352#L1274-1 assume !(0 == ~E_4~0); 522234#L1279-1 assume !(0 == ~E_5~0); 520580#L1284-1 assume !(0 == ~E_6~0); 520581#L1289-1 assume !(0 == ~E_7~0); 521281#L1294-1 assume !(0 == ~E_8~0); 521282#L1299-1 assume !(0 == ~E_9~0); 521293#L1304-1 assume !(0 == ~E_10~0); 522321#L1309-1 assume !(0 == ~E_11~0); 522331#L1314-1 assume !(0 == ~E_12~0); 520533#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 520458#L586 assume !(1 == ~m_pc~0); 520459#L586-2 is_master_triggered_~__retres1~0#1 := 0; 520526#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 521649#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520737#L1485 assume !(0 != activate_threads_~tmp~1#1); 520738#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 521934#L605 assume !(1 == ~t1_pc~0); 522068#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 521104#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521105#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 522139#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 521736#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 521017#L624 assume !(1 == ~t2_pc~0); 521018#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 521185#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 521186#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 522175#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 521988#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 521822#L643 assume !(1 == ~t3_pc~0); 521643#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 521306#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 521212#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 520839#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 520840#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 520600#L662 assume 1 == ~t4_pc~0; 520601#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 520559#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 520560#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 521340#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 520445#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 520446#L681 assume !(1 == ~t5_pc~0); 520318#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 520319#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 521397#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 522131#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 520852#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 520853#L700 assume 1 == ~t6_pc~0; 521598#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 520591#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 520592#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 520642#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 520643#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 522049#L719 assume 1 == ~t7_pc~0; 522144#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 520807#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 521633#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 521634#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 520332#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 520333#L738 assume !(1 == ~t8_pc~0); 521778#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 521675#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 520702#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 520703#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 521429#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 521846#L757 assume 1 == ~t9_pc~0; 521847#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 520327#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 520328#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 521576#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 521387#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 521388#L776 assume !(1 == ~t10_pc~0); 520352#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 520351#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520741#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 520582#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 520583#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 520534#L795 assume 1 == ~t11_pc~0; 520535#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 520871#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 521916#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 521917#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 521639#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 521626#L814 assume !(1 == ~t12_pc~0); 521461#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 521462#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 521894#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 522038#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 520793#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 520794#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 522004#L1332-2 assume !(1 == ~T1_E~0); 522260#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 521540#L1342-1 assume !(1 == ~T3_E~0); 521541#L1347-1 assume !(1 == ~T4_E~0); 522032#L1352-1 assume !(1 == ~T5_E~0); 521853#L1357-1 assume !(1 == ~T6_E~0); 521073#L1362-1 assume !(1 == ~T7_E~0); 521074#L1367-1 assume !(1 == ~T8_E~0); 520676#L1372-1 assume !(1 == ~T9_E~0); 520677#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 520990#L1382-1 assume !(1 == ~T11_E~0); 520991#L1387-1 assume !(1 == ~T12_E~0); 521734#L1392-1 assume !(1 == ~E_M~0); 521019#L1397-1 assume !(1 == ~E_1~0); 521020#L1402-1 assume !(1 == ~E_2~0); 520688#L1407-1 assume !(1 == ~E_3~0); 520689#L1412-1 assume !(1 == ~E_4~0); 522318#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 557861#L1422-1 assume !(1 == ~E_6~0); 557859#L1427-1 assume !(1 == ~E_7~0); 557857#L1432-1 assume !(1 == ~E_8~0); 557854#L1437-1 assume !(1 == ~E_9~0); 557852#L1442-1 assume !(1 == ~E_10~0); 557850#L1447-1 assume !(1 == ~E_11~0); 557848#L1452-1 assume !(1 == ~E_12~0); 527169#L1457-1 assume { :end_inline_reset_delta_events } true; 531921#L1803-2 [2021-12-15 17:21:14,060 INFO L793 eck$LassoCheckResult]: Loop: 531921#L1803-2 assume !false; 530232#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 530225#L1169 assume !false; 528989#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 527787#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 527775#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 527773#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 527771#L996 assume !(0 != eval_~tmp~0#1); 527772#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 560965#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 560963#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 560961#L1194-5 assume !(0 == ~T1_E~0); 560959#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 560957#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 560955#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 560953#L1214-3 assume !(0 == ~T5_E~0); 560951#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 560949#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 560947#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 560945#L1234-3 assume !(0 == ~T9_E~0); 560943#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 560941#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 560939#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 560937#L1254-3 assume !(0 == ~E_M~0); 560935#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 560933#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 560931#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 560929#L1274-3 assume !(0 == ~E_4~0); 560927#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 560925#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 560923#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 560921#L1294-3 assume !(0 == ~E_8~0); 560919#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 560917#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 560915#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 560913#L1314-3 assume !(0 == ~E_12~0); 560911#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 560909#L586-42 assume !(1 == ~m_pc~0); 560907#L586-44 is_master_triggered_~__retres1~0#1 := 0; 560905#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 560902#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 560900#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 560898#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 560896#L605-42 assume !(1 == ~t1_pc~0); 560894#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 560892#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 560889#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 560887#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 560885#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560883#L624-42 assume !(1 == ~t2_pc~0); 560881#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 560879#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 560876#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 560874#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 560872#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 560870#L643-42 assume 1 == ~t3_pc~0; 560867#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 560865#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560862#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 560860#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 560858#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560856#L662-42 assume !(1 == ~t4_pc~0); 560853#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 560851#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 560848#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 560846#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 560844#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 560842#L681-42 assume !(1 == ~t5_pc~0); 560840#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 560836#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560832#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 560829#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 560826#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 560823#L700-42 assume !(1 == ~t6_pc~0); 560819#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 560816#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 560812#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 560809#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 560805#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560801#L719-42 assume 1 == ~t7_pc~0; 560796#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 560792#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560787#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 560783#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 560779#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 560776#L738-42 assume 1 == ~t8_pc~0; 560771#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 560767#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 560761#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 560757#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 560753#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 560749#L757-42 assume 1 == ~t9_pc~0; 560744#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 560741#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 560740#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 560739#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 560738#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 560737#L776-42 assume 1 == ~t10_pc~0; 560735#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 560734#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 560731#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 560728#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 560725#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 560722#L795-42 assume !(1 == ~t11_pc~0); 560718#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 560715#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 560711#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 560708#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 560705#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 560702#L814-42 assume 1 == ~t12_pc~0; 560697#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 560695#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 560692#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 560690#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 560675#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 560670#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 528494#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 560660#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 560656#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 560652#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 560646#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 560642#L1357-3 assume !(1 == ~T6_E~0); 560638#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 560634#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 560630#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 545460#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 560621#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 560617#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 560613#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 560610#L1397-3 assume !(1 == ~E_1~0); 560607#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 560587#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 560584#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 530376#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 560577#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 560572#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 560568#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 560563#L1437-3 assume !(1 == ~E_9~0); 560558#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 560553#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 560548#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 528335#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 560451#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 560435#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 560430#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 558586#L1822 assume !(0 == start_simulation_~tmp~3#1); 558583#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 531947#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 531938#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 531936#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 531934#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 531931#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 531929#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 531926#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 531921#L1803-2 [2021-12-15 17:21:14,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:14,062 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2021-12-15 17:21:14,062 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:14,062 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277694178] [2021-12-15 17:21:14,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:14,062 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:14,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:14,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:14,112 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:14,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277694178] [2021-12-15 17:21:14,112 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277694178] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:14,113 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:14,113 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:14,113 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542225608] [2021-12-15 17:21:14,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:14,113 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:14,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:14,114 INFO L85 PathProgramCache]: Analyzing trace with hash -912788288, now seen corresponding path program 1 times [2021-12-15 17:21:14,114 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:14,114 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202130192] [2021-12-15 17:21:14,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:14,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:14,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:14,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:14,135 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:14,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202130192] [2021-12-15 17:21:14,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1202130192] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:14,136 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:14,136 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:14,136 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268369780] [2021-12-15 17:21:14,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:14,136 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:14,136 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:14,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:14,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:14,137 INFO L87 Difference]: Start difference. First operand 123357 states and 176871 transitions. cyclomatic complexity: 53578 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:15,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:15,389 INFO L93 Difference]: Finished difference Result 346618 states and 493838 transitions. [2021-12-15 17:21:15,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:15,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 346618 states and 493838 transitions. [2021-12-15 17:21:17,118 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 345211 [2021-12-15 17:21:18,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 346618 states to 346618 states and 493838 transitions. [2021-12-15 17:21:18,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 346618 [2021-12-15 17:21:18,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 346618 [2021-12-15 17:21:18,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 346618 states and 493838 transitions. [2021-12-15 17:21:18,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:18,631 INFO L681 BuchiCegarLoop]: Abstraction has 346618 states and 493838 transitions. [2021-12-15 17:21:18,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346618 states and 493838 transitions. [2021-12-15 17:21:21,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346618 to 339834. [2021-12-15 17:21:21,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 339834 states, 339834 states have (on average 1.4256784194636205) internal successors, (484494), 339833 states have internal predecessors, (484494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:23,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339834 states to 339834 states and 484494 transitions. [2021-12-15 17:21:23,435 INFO L704 BuchiCegarLoop]: Abstraction has 339834 states and 484494 transitions. [2021-12-15 17:21:23,435 INFO L587 BuchiCegarLoop]: Abstraction has 339834 states and 484494 transitions. [2021-12-15 17:21:23,435 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:21:23,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 339834 states and 484494 transitions. [2021-12-15 17:21:24,167 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 339067 [2021-12-15 17:21:24,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:24,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:24,177 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:24,178 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:24,179 INFO L791 eck$LassoCheckResult]: Stem: 991112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 991113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 992010#L1766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 992011#L834 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 990619#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 990620#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 990524#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 990525#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 991904#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 991156#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 991157#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 991056#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 991057#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 991597#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 991598#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 990809#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 990810#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 991252#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 991253#L1194 assume !(0 == ~M_E~0); 991407#L1194-2 assume !(0 == ~T1_E~0); 991408#L1199-1 assume !(0 == ~T2_E~0); 991749#L1204-1 assume !(0 == ~T3_E~0); 991658#L1209-1 assume !(0 == ~T4_E~0); 991659#L1214-1 assume !(0 == ~T5_E~0); 992149#L1219-1 assume !(0 == ~T6_E~0); 992322#L1224-1 assume !(0 == ~T7_E~0); 990888#L1229-1 assume !(0 == ~T8_E~0); 990443#L1234-1 assume !(0 == ~T9_E~0); 990444#L1239-1 assume !(0 == ~T10_E~0); 990487#L1244-1 assume !(0 == ~T11_E~0); 990488#L1249-1 assume !(0 == ~T12_E~0); 991193#L1254-1 assume !(0 == ~E_M~0); 990390#L1259-1 assume !(0 == ~E_1~0); 990355#L1264-1 assume !(0 == ~E_2~0); 990356#L1269-1 assume !(0 == ~E_3~0); 992340#L1274-1 assume !(0 == ~E_4~0); 992200#L1279-1 assume !(0 == ~E_5~0); 990561#L1284-1 assume !(0 == ~E_6~0); 990562#L1289-1 assume !(0 == ~E_7~0); 991259#L1294-1 assume !(0 == ~E_8~0); 991260#L1299-1 assume !(0 == ~E_9~0); 991271#L1304-1 assume !(0 == ~E_10~0); 992308#L1309-1 assume !(0 == ~E_11~0); 992320#L1314-1 assume !(0 == ~E_12~0); 990516#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 990441#L586 assume !(1 == ~m_pc~0); 990442#L586-2 is_master_triggered_~__retres1~0#1 := 0; 990510#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 991623#L598 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 990717#L1485 assume !(0 != activate_threads_~tmp~1#1); 990718#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 991909#L605 assume !(1 == ~t1_pc~0); 992032#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 991084#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 991085#L617 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 992104#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 991716#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 990998#L624 assume !(1 == ~t2_pc~0); 990999#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 991165#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991166#L636 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 992134#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 991957#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 991796#L643 assume !(1 == ~t3_pc~0); 991616#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 991284#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 991192#L655 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 990819#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 990820#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 990581#L662 assume !(1 == ~t4_pc~0); 990582#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 990540#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 990541#L674 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 991318#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 990429#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 990430#L681 assume !(1 == ~t5_pc~0); 990303#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 990304#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 991372#L693 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 992093#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 990831#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 990832#L700 assume 1 == ~t6_pc~0; 991572#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 990572#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 990573#L712 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 990621#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 990622#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 992014#L719 assume 1 == ~t7_pc~0; 992111#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 990787#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 991607#L731 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 991608#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 990317#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 990318#L738 assume !(1 == ~t8_pc~0); 991757#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 991650#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 990682#L750 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 990683#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 991404#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 991820#L757 assume 1 == ~t9_pc~0; 991821#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 990312#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 990313#L769 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 991551#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 991363#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 991364#L776 assume !(1 == ~t10_pc~0); 990337#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 990336#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 990721#L788 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 990563#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 990564#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 990517#L795 assume 1 == ~t11_pc~0; 990518#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 990852#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 991896#L807 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 991897#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 991614#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 991600#L814 assume !(1 == ~t12_pc~0); 991435#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 991436#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 991871#L826 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 992005#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 990773#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 990774#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 991972#L1332-2 assume !(1 == ~T1_E~0); 992235#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 991513#L1342-1 assume !(1 == ~T3_E~0); 991514#L1347-1 assume !(1 == ~T4_E~0); 991999#L1352-1 assume !(1 == ~T5_E~0); 991827#L1357-1 assume !(1 == ~T6_E~0); 991052#L1362-1 assume !(1 == ~T7_E~0); 991053#L1367-1 assume !(1 == ~T8_E~0); 990657#L1372-1 assume !(1 == ~T9_E~0); 990658#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 990971#L1382-1 assume !(1 == ~T11_E~0); 990972#L1387-1 assume !(1 == ~T12_E~0); 992169#L1392-1 assume !(1 == ~E_M~0); 992170#L1397-1 assume !(1 == ~E_1~0); 992238#L1402-1 assume !(1 == ~E_2~0); 992239#L1407-1 assume !(1 == ~E_3~0); 992301#L1412-1 assume !(1 == ~E_4~0); 992302#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1018814#L1422-1 assume !(1 == ~E_6~0); 1018813#L1427-1 assume !(1 == ~E_7~0); 1018812#L1432-1 assume !(1 == ~E_8~0); 1018811#L1437-1 assume !(1 == ~E_9~0); 1018810#L1442-1 assume !(1 == ~E_10~0); 1018809#L1447-1 assume !(1 == ~E_11~0); 1018808#L1452-1 assume !(1 == ~E_12~0); 1009376#L1457-1 assume { :end_inline_reset_delta_events } true; 1010904#L1803-2 [2021-12-15 17:21:24,179 INFO L793 eck$LassoCheckResult]: Loop: 1010904#L1803-2 assume !false; 1010905#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1010894#L1169 assume !false; 1010895#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1010884#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1010871#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1010869#L982 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1010866#L996 assume !(0 != eval_~tmp~0#1); 1010867#L1184 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1020210#L834-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1020208#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1020206#L1194-5 assume !(0 == ~T1_E~0); 1020204#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1020202#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1020200#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1020197#L1214-3 assume !(0 == ~T5_E~0); 1020195#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1020193#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1020191#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1020189#L1234-3 assume !(0 == ~T9_E~0); 1020187#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1020185#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1020183#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1020181#L1254-3 assume !(0 == ~E_M~0); 1020179#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1020111#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1020103#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1020095#L1274-3 assume !(0 == ~E_4~0); 1020089#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1020083#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1020077#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1020071#L1294-3 assume !(0 == ~E_8~0); 1020062#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1020054#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1020048#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1020042#L1314-3 assume !(0 == ~E_12~0); 1020037#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1020032#L586-42 assume !(1 == ~m_pc~0); 1020028#L586-44 is_master_triggered_~__retres1~0#1 := 0; 1020027#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1020026#L598-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1020025#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 1020024#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1020023#L605-42 assume !(1 == ~t1_pc~0); 1020022#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1020021#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1020019#L617-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1020017#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 1020015#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1020013#L624-42 assume !(1 == ~t2_pc~0); 1020011#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1020009#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1020007#L636-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1020005#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1020003#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1020001#L643-42 assume !(1 == ~t3_pc~0); 1019999#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1019996#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1019994#L655-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1019992#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1019990#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1019988#L662-42 assume !(1 == ~t4_pc~0); 1019986#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1019984#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1019982#L674-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1019980#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1019978#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1019976#L681-42 assume !(1 == ~t5_pc~0); 1019974#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1019971#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1019969#L693-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1019967#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1019965#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1019963#L700-42 assume 1 == ~t6_pc~0; 1019961#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1019958#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1019956#L712-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1019954#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1019951#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1019952#L719-42 assume 1 == ~t7_pc~0; 1106683#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1106682#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1106681#L731-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1106680#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 1106679#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1106678#L738-42 assume 1 == ~t8_pc~0; 1106676#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1106675#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1106674#L750-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1106673#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1106672#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1106671#L757-42 assume 1 == ~t9_pc~0; 1106669#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1106668#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1106667#L769-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1106666#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1106665#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1106664#L776-42 assume 1 == ~t10_pc~0; 1106662#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1106661#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1106660#L788-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1106659#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1106658#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1106657#L795-42 assume 1 == ~t11_pc~0; 1106656#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1106654#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1106653#L807-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1106652#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1106651#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1106650#L814-42 assume 1 == ~t12_pc~0; 1106648#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1106647#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1106646#L826-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1106645#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1106644#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1106643#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1012223#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1016854#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1019491#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1019484#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1019476#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1019477#L1357-3 assume !(1 == ~T6_E~0); 1106632#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1106630#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1018990#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1018991#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1018982#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1018983#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1018976#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1018977#L1397-3 assume !(1 == ~E_1~0); 1018970#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1018971#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1018964#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1018965#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1018956#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1018957#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1018950#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1018951#L1437-3 assume !(1 == ~E_9~0); 1018942#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1018943#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1018923#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1012161#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1018846#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1018833#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1018831#L982-1 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1018829#L1822 assume !(0 == start_simulation_~tmp~3#1); 1018806#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1018807#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1103488#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1103487#L982-2 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 1103486#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1103485#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1103484#L1785 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1010907#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 1010904#L1803-2 [2021-12-15 17:21:24,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:24,180 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2021-12-15 17:21:24,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:24,181 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870601004] [2021-12-15 17:21:24,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:24,181 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:24,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:24,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:24,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:24,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870601004] [2021-12-15 17:21:24,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870601004] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:24,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:24,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:24,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539017359] [2021-12-15 17:21:24,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:24,246 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:24,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:24,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1912459647, now seen corresponding path program 1 times [2021-12-15 17:21:24,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:24,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954030921] [2021-12-15 17:21:24,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:24,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:24,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:24,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:24,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:24,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1954030921] [2021-12-15 17:21:24,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1954030921] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:24,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:24,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:24,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187706352] [2021-12-15 17:21:24,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:24,272 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:24,272 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:24,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:24,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:24,273 INFO L87 Difference]: Start difference. First operand 339834 states and 484494 transitions. cyclomatic complexity: 144788 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:28,445 INFO L93 Difference]: Finished difference Result 956651 states and 1356453 transitions. [2021-12-15 17:21:28,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:28,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 956651 states and 1356453 transitions. [2021-12-15 17:21:33,787 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 953261 [2021-12-15 17:21:36,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 956651 states to 956651 states and 1356453 transitions. [2021-12-15 17:21:36,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 956651 [2021-12-15 17:21:37,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 956651 [2021-12-15 17:21:37,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 956651 states and 1356453 transitions. [2021-12-15 17:21:38,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:38,478 INFO L681 BuchiCegarLoop]: Abstraction has 956651 states and 1356453 transitions. [2021-12-15 17:21:39,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 956651 states and 1356453 transitions.