./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:21:24,803 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:21:24,807 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:21:24,846 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:21:24,846 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:21:24,847 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:21:24,849 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:21:24,850 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:21:24,852 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:21:24,853 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:21:24,853 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:21:24,854 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:21:24,855 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:21:24,856 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:21:24,857 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:21:24,858 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:21:24,860 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:21:24,864 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:21:24,866 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:21:24,873 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:21:24,880 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:21:24,882 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:21:24,883 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:21:24,883 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:21:24,885 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:21:24,891 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:21:24,895 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:21:24,896 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:21:24,897 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:21:24,898 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:21:24,898 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:21:24,899 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:21:24,900 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:21:24,901 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:21:24,902 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:21:24,903 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:21:24,904 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:21:24,904 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:21:24,904 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:21:24,905 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:21:24,906 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:21:24,907 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:21:24,945 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:21:24,946 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:21:24,947 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:21:24,947 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:21:24,949 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:21:24,949 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:21:24,949 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:21:24,949 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:21:24,950 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:21:24,950 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:21:24,951 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:21:24,951 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:21:24,951 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:21:24,951 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:21:24,952 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:21:24,952 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:21:24,952 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:21:24,952 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:21:24,952 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:21:24,952 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:21:24,953 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:21:24,953 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:21:24,953 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:21:24,953 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:21:24,953 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:21:24,953 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:21:24,954 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:21:24,954 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:21:24,954 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:21:24,954 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:21:24,955 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:21:24,955 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:21:24,956 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:21:24,956 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2021-12-15 17:21:25,200 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:21:25,231 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:21:25,234 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:21:25,235 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:21:25,235 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:21:25,237 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.01.cil.c [2021-12-15 17:21:25,336 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5832e4997/67d5dcff4ffc4ef2bea1c4696bd6b621/FLAG158798705 [2021-12-15 17:21:25,776 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:21:25,777 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c [2021-12-15 17:21:25,786 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5832e4997/67d5dcff4ffc4ef2bea1c4696bd6b621/FLAG158798705 [2021-12-15 17:21:26,167 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5832e4997/67d5dcff4ffc4ef2bea1c4696bd6b621 [2021-12-15 17:21:26,170 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:21:26,172 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:21:26,174 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:26,174 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:21:26,177 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:21:26,178 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,179 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e8bacf0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26, skipping insertion in model container [2021-12-15 17:21:26,180 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,186 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:21:26,213 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:21:26,365 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2021-12-15 17:21:26,431 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:26,442 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:21:26,452 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2021-12-15 17:21:26,480 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:26,500 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:21:26,501 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26 WrapperNode [2021-12-15 17:21:26,501 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:26,502 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:26,503 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:21:26,503 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:21:26,509 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,525 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,562 INFO L137 Inliner]: procedures = 30, calls = 33, calls flagged for inlining = 28, calls inlined = 34, statements flattened = 357 [2021-12-15 17:21:26,563 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:26,564 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:21:26,564 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:21:26,564 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:21:26,571 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,572 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,582 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,583 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,591 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,603 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,607 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,613 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:21:26,615 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:21:26,615 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:21:26,616 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:21:26,617 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (1/1) ... [2021-12-15 17:21:26,623 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:21:26,637 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:21:26,653 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:21:26,678 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:21:26,691 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:21:26,692 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:21:26,692 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:21:26,692 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:21:26,771 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:21:26,772 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:21:27,097 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:21:27,119 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:21:27,119 INFO L301 CfgBuilder]: Removed 5 assume(true) statements. [2021-12-15 17:21:27,121 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:27 BoogieIcfgContainer [2021-12-15 17:21:27,121 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:21:27,122 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:21:27,122 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:21:27,125 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:21:27,125 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:27,125 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:21:26" (1/3) ... [2021-12-15 17:21:27,126 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49dd0352 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:27, skipping insertion in model container [2021-12-15 17:21:27,127 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:27,127 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:26" (2/3) ... [2021-12-15 17:21:27,127 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49dd0352 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:27, skipping insertion in model container [2021-12-15 17:21:27,127 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:27,127 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:27" (3/3) ... [2021-12-15 17:21:27,129 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2021-12-15 17:21:27,161 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:21:27,161 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:21:27,161 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:21:27,161 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:21:27,162 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:21:27,162 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:21:27,162 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:21:27,162 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:21:27,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:27,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2021-12-15 17:21:27,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:27,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:27,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:27,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:27,226 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:21:27,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:27,239 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2021-12-15 17:21:27,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:27,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:27,245 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:27,246 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:27,254 INFO L791 eck$LassoCheckResult]: Stem: 117#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 46#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 15#L367true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92#L154true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 7#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 78#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L250true assume !(0 == ~M_E~0); 105#L250-2true assume !(0 == ~T1_E~0); 38#L255-1true assume !(0 == ~E_1~0); 79#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52#L115true assume !(1 == ~m_pc~0); 56#L115-2true is_master_triggered_~__retres1~0#1 := 0; 67#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121#L127true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 63#L300true assume !(0 != activate_threads_~tmp~1#1); 104#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119#L134true assume 1 == ~t1_pc~0; 106#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85#L146true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11#L308true assume !(0 != activate_threads_~tmp___0~0#1); 59#L308-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57#L273true assume !(1 == ~M_E~0); 109#L273-2true assume !(1 == ~T1_E~0); 99#L278-1true assume !(1 == ~E_1~0); 69#L283-1true assume { :end_inline_reset_delta_events } true; 55#L404-2true [2021-12-15 17:21:27,255 INFO L793 eck$LassoCheckResult]: Loop: 55#L404-2true assume !false; 80#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43#L225true assume !true; 25#L240true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114#L154-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 118#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 96#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 101#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 8#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48#L115-6true assume 1 == ~m_pc~0; 113#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 133#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58#L127-2true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 72#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 115#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131#L134-6true assume !(1 == ~t1_pc~0); 33#L134-8true is_transmit1_triggered_~__retres1~1#1 := 0; 51#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112#L146-2true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 49#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9#L308-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 44#L273-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 35#L278-3true assume 1 == ~E_1~0;~E_1~0 := 2; 93#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 75#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 110#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 132#L192-1true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 19#L423true assume !(0 == start_simulation_~tmp~3#1); 18#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 70#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 94#L192-2true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 14#L378true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76#L386true start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 42#L436true assume !(0 != start_simulation_~tmp___0~1#1); 55#L404-2true [2021-12-15 17:21:27,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:27,260 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2021-12-15 17:21:27,268 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:27,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076124468] [2021-12-15 17:21:27,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:27,270 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:27,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:27,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:27,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:27,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076124468] [2021-12-15 17:21:27,444 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076124468] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:27,445 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:27,445 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:27,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489405086] [2021-12-15 17:21:27,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:27,463 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:27,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:27,466 INFO L85 PathProgramCache]: Analyzing trace with hash 478113713, now seen corresponding path program 1 times [2021-12-15 17:21:27,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:27,466 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075363550] [2021-12-15 17:21:27,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:27,467 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:27,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:27,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:27,534 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:27,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075363550] [2021-12-15 17:21:27,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075363550] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:27,535 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:27,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:27,536 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537181800] [2021-12-15 17:21:27,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:27,537 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:27,538 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:27,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:27,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:27,571 INFO L87 Difference]: Start difference. First operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:27,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:27,614 INFO L93 Difference]: Finished difference Result 132 states and 188 transitions. [2021-12-15 17:21:27,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:27,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132 states and 188 transitions. [2021-12-15 17:21:27,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2021-12-15 17:21:27,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132 states to 126 states and 182 transitions. [2021-12-15 17:21:27,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126 [2021-12-15 17:21:27,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126 [2021-12-15 17:21:27,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126 states and 182 transitions. [2021-12-15 17:21:27,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:27,640 INFO L681 BuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2021-12-15 17:21:27,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states and 182 transitions. [2021-12-15 17:21:27,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2021-12-15 17:21:27,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:27,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 182 transitions. [2021-12-15 17:21:27,675 INFO L704 BuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2021-12-15 17:21:27,676 INFO L587 BuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2021-12-15 17:21:27,676 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:21:27,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126 states and 182 transitions. [2021-12-15 17:21:27,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2021-12-15 17:21:27,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:27,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:27,682 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:27,683 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:27,683 INFO L791 eck$LassoCheckResult]: Stem: 398#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 341#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 293#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 294#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 287#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 278#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 375#L250 assume !(0 == ~M_E~0); 382#L250-2 assume !(0 == ~T1_E~0); 331#L255-1 assume !(0 == ~E_1~0); 332#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 347#L115 assume !(1 == ~m_pc~0); 318#L115-2 is_master_triggered_~__retres1~0#1 := 0; 319#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 359#L300 assume !(0 != activate_threads_~tmp~1#1); 360#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 391#L134 assume 1 == ~t1_pc~0; 392#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 349#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 285#L308 assume !(0 != activate_threads_~tmp___0~0#1); 286#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352#L273 assume !(1 == ~M_E~0); 353#L273-2 assume !(1 == ~T1_E~0); 389#L278-1 assume !(1 == ~E_1~0); 365#L283-1 assume { :end_inline_reset_delta_events } true; 337#L404-2 [2021-12-15 17:21:27,684 INFO L793 eck$LassoCheckResult]: Loop: 337#L404-2 assume !false; 351#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 301#L225 assume !false; 338#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 379#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 321#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 374#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 329#L206 assume !(0 != eval_~tmp~0#1); 310#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 311#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 396#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 387#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 388#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 280#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281#L115-6 assume 1 == ~m_pc~0; 342#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 395#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 354#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 355#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 368#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 397#L134-6 assume !(1 == ~t1_pc~0); 322#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 323#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 346#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 344#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 283#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 339#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 325#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 326#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 371#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 372#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 393#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 298#L423 assume !(0 == start_simulation_~tmp~3#1); 296#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 297#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 304#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 366#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 291#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 292#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 295#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 336#L436 assume !(0 != start_simulation_~tmp___0~1#1); 337#L404-2 [2021-12-15 17:21:27,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:27,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2021-12-15 17:21:27,686 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:27,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735356832] [2021-12-15 17:21:27,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:27,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:27,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:27,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:27,769 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:27,771 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735356832] [2021-12-15 17:21:27,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735356832] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:27,772 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:27,772 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:27,772 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107441843] [2021-12-15 17:21:27,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:27,773 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:27,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:27,775 INFO L85 PathProgramCache]: Analyzing trace with hash -445215682, now seen corresponding path program 1 times [2021-12-15 17:21:27,780 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:27,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117421314] [2021-12-15 17:21:27,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:27,781 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:27,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:27,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:27,854 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:27,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117421314] [2021-12-15 17:21:27,854 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117421314] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:27,855 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:27,855 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:27,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037395362] [2021-12-15 17:21:27,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:27,856 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:27,856 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:27,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:27,857 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:27,858 INFO L87 Difference]: Start difference. First operand 126 states and 182 transitions. cyclomatic complexity: 57 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:27,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:27,998 INFO L93 Difference]: Finished difference Result 304 states and 423 transitions. [2021-12-15 17:21:27,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:28,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304 states and 423 transitions. [2021-12-15 17:21:28,003 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 254 [2021-12-15 17:21:28,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304 states to 304 states and 423 transitions. [2021-12-15 17:21:28,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304 [2021-12-15 17:21:28,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304 [2021-12-15 17:21:28,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304 states and 423 transitions. [2021-12-15 17:21:28,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:28,008 INFO L681 BuchiCegarLoop]: Abstraction has 304 states and 423 transitions. [2021-12-15 17:21:28,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states and 423 transitions. [2021-12-15 17:21:28,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 284. [2021-12-15 17:21:28,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 399 transitions. [2021-12-15 17:21:28,020 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 399 transitions. [2021-12-15 17:21:28,020 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 399 transitions. [2021-12-15 17:21:28,020 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:21:28,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 399 transitions. [2021-12-15 17:21:28,022 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 252 [2021-12-15 17:21:28,022 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:28,022 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:28,023 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,023 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,023 INFO L791 eck$LassoCheckResult]: Stem: 853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 735#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 736#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 729#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 720#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 721#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 824#L250 assume !(0 == ~M_E~0); 834#L250-2 assume !(0 == ~T1_E~0); 773#L255-1 assume !(0 == ~E_1~0); 774#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 789#L115 assume !(1 == ~m_pc~0); 790#L115-2 is_master_triggered_~__retres1~0#1 := 0; 794#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 808#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 804#L300 assume !(0 != activate_threads_~tmp~1#1); 805#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 844#L134 assume !(1 == ~t1_pc~0); 802#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 791#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 792#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 727#L308 assume !(0 != activate_threads_~tmp___0~0#1); 728#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 795#L273 assume !(1 == ~M_E~0); 796#L273-2 assume !(1 == ~T1_E~0); 840#L278-1 assume !(1 == ~E_1~0); 812#L283-1 assume { :end_inline_reset_delta_events } true; 813#L404-2 [2021-12-15 17:21:28,023 INFO L793 eck$LassoCheckResult]: Loop: 813#L404-2 assume !false; 969#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 966#L225 assume !false; 964#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 857#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 761#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 823#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 959#L206 assume !(0 != eval_~tmp~0#1); 753#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 754#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 851#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 854#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 842#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 722#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 723#L115-6 assume !(1 == ~m_pc~0); 784#L115-8 is_master_triggered_~__retres1~0#1 := 0; 856#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 797#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 798#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 815#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 852#L134-6 assume !(1 == ~t1_pc~0); 861#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 985#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 982#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 980#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 978#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 977#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 976#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 974#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 973#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 818#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 819#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 846#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 740#L423 assume !(0 == start_simulation_~tmp~3#1); 742#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 983#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 981#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 979#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 975#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 972#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 821#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 822#L436 assume !(0 != start_simulation_~tmp___0~1#1); 813#L404-2 [2021-12-15 17:21:28,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,024 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2021-12-15 17:21:28,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466846231] [2021-12-15 17:21:28,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,033 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:28,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,061 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:28,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,062 INFO L85 PathProgramCache]: Analyzing trace with hash -753654691, now seen corresponding path program 1 times [2021-12-15 17:21:28,062 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,062 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976925487] [2021-12-15 17:21:28,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,062 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:28,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:28,101 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:28,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976925487] [2021-12-15 17:21:28,102 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976925487] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:28,102 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:28,102 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:28,102 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405045615] [2021-12-15 17:21:28,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:28,103 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:28,103 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:28,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:28,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:28,104 INFO L87 Difference]: Start difference. First operand 284 states and 399 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:28,184 INFO L93 Difference]: Finished difference Result 478 states and 654 transitions. [2021-12-15 17:21:28,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:21:28,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 654 transitions. [2021-12-15 17:21:28,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 441 [2021-12-15 17:21:28,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 654 transitions. [2021-12-15 17:21:28,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2021-12-15 17:21:28,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2021-12-15 17:21:28,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 654 transitions. [2021-12-15 17:21:28,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:28,196 INFO L681 BuchiCegarLoop]: Abstraction has 478 states and 654 transitions. [2021-12-15 17:21:28,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 654 transitions. [2021-12-15 17:21:28,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 293. [2021-12-15 17:21:28,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293 states to 293 states and 408 transitions. [2021-12-15 17:21:28,210 INFO L704 BuchiCegarLoop]: Abstraction has 293 states and 408 transitions. [2021-12-15 17:21:28,210 INFO L587 BuchiCegarLoop]: Abstraction has 293 states and 408 transitions. [2021-12-15 17:21:28,210 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:21:28,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 293 states and 408 transitions. [2021-12-15 17:21:28,212 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 261 [2021-12-15 17:21:28,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:28,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:28,213 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,213 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,213 INFO L791 eck$LassoCheckResult]: Stem: 1643#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1513#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1514#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1507#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1498#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1499#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1608#L250 assume !(0 == ~M_E~0); 1620#L250-2 assume !(0 == ~T1_E~0); 1552#L255-1 assume !(0 == ~E_1~0); 1553#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1572#L115 assume !(1 == ~m_pc~0); 1573#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1577#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1591#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1587#L300 assume !(0 != activate_threads_~tmp~1#1); 1588#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1631#L134 assume !(1 == ~t1_pc~0); 1582#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1574#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1575#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1505#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1506#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1578#L273 assume !(1 == ~M_E~0); 1579#L273-2 assume !(1 == ~T1_E~0); 1627#L278-1 assume !(1 == ~E_1~0); 1594#L283-1 assume { :end_inline_reset_delta_events } true; 1595#L404-2 [2021-12-15 17:21:28,213 INFO L793 eck$LassoCheckResult]: Loop: 1595#L404-2 assume !false; 1751#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1744#L225 assume !false; 1694#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1690#L179 assume !(0 == ~m_st~0); 1685#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 1682#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1679#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1676#L206 assume !(0 != eval_~tmp~0#1); 1674#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1672#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1670#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1668#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1665#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1666#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1565#L115-6 assume !(1 == ~m_pc~0); 1566#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1645#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1728#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1599#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1600#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1649#L134-6 assume !(1 == ~t1_pc~0); 1543#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1544#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1569#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1636#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1725#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1724#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1560#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1546#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1547#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1604#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1605#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1634#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1518#L423 assume !(0 == start_simulation_~tmp~3#1); 1520#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1763#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1762#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1760#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1758#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1756#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1754#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1752#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1595#L404-2 [2021-12-15 17:21:28,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,214 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2021-12-15 17:21:28,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520442296] [2021-12-15 17:21:28,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,223 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:28,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,233 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:28,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,234 INFO L85 PathProgramCache]: Analyzing trace with hash -682345966, now seen corresponding path program 1 times [2021-12-15 17:21:28,234 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026249652] [2021-12-15 17:21:28,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,235 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:28,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:28,291 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:28,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026249652] [2021-12-15 17:21:28,291 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026249652] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:28,291 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:28,291 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:28,292 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114537566] [2021-12-15 17:21:28,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:28,292 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:28,292 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:28,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:28,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:28,293 INFO L87 Difference]: Start difference. First operand 293 states and 408 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:28,387 INFO L93 Difference]: Finished difference Result 623 states and 857 transitions. [2021-12-15 17:21:28,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:28,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 623 states and 857 transitions. [2021-12-15 17:21:28,392 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 591 [2021-12-15 17:21:28,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 623 states to 623 states and 857 transitions. [2021-12-15 17:21:28,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 623 [2021-12-15 17:21:28,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 623 [2021-12-15 17:21:28,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 623 states and 857 transitions. [2021-12-15 17:21:28,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:28,397 INFO L681 BuchiCegarLoop]: Abstraction has 623 states and 857 transitions. [2021-12-15 17:21:28,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states and 857 transitions. [2021-12-15 17:21:28,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 311. [2021-12-15 17:21:28,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 423 transitions. [2021-12-15 17:21:28,419 INFO L704 BuchiCegarLoop]: Abstraction has 311 states and 423 transitions. [2021-12-15 17:21:28,419 INFO L587 BuchiCegarLoop]: Abstraction has 311 states and 423 transitions. [2021-12-15 17:21:28,419 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:21:28,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311 states and 423 transitions. [2021-12-15 17:21:28,421 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 279 [2021-12-15 17:21:28,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:28,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:28,424 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,424 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,424 INFO L791 eck$LassoCheckResult]: Stem: 2561#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2442#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2443#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2436#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2427#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2428#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2533#L250 assume !(0 == ~M_E~0); 2544#L250-2 assume !(0 == ~T1_E~0); 2480#L255-1 assume !(0 == ~E_1~0); 2481#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2500#L115 assume !(1 == ~m_pc~0); 2501#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2505#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2518#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2515#L300 assume !(0 != activate_threads_~tmp~1#1); 2516#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2552#L134 assume !(1 == ~t1_pc~0); 2513#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2502#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2503#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2434#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2435#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2506#L273 assume !(1 == ~M_E~0); 2507#L273-2 assume !(1 == ~T1_E~0); 2548#L278-1 assume !(1 == ~E_1~0); 2522#L283-1 assume { :end_inline_reset_delta_events } true; 2523#L404-2 [2021-12-15 17:21:28,425 INFO L793 eck$LassoCheckResult]: Loop: 2523#L404-2 assume !false; 2604#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2602#L225 assume !false; 2601#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2599#L179 assume !(0 == ~m_st~0); 2600#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2598#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2596#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2594#L206 assume !(0 != eval_~tmp~0#1); 2592#L240 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2590#L154-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2587#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2584#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2582#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2579#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2493#L115-6 assume !(1 == ~m_pc~0); 2494#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2647#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2646#L127-2 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2645#L300-6 assume !(0 != activate_threads_~tmp~1#1); 2644#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2643#L134-6 assume !(1 == ~t1_pc~0); 2641#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2639#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2637#L146-2 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2635#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2633#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2631#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2629#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2627#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2625#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2622#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2620#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2618#L192-1 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2615#L423 assume !(0 == start_simulation_~tmp~3#1); 2613#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2611#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2610#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2609#L192-2 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2608#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2607#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2606#L386 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2605#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2523#L404-2 [2021-12-15 17:21:28,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,426 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2021-12-15 17:21:28,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079568666] [2021-12-15 17:21:28,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,430 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,444 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:28,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,452 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:28,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,453 INFO L85 PathProgramCache]: Analyzing trace with hash -816359472, now seen corresponding path program 1 times [2021-12-15 17:21:28,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045963684] [2021-12-15 17:21:28,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,454 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:28,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:28,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:28,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2045963684] [2021-12-15 17:21:28,478 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2045963684] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:28,478 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:28,478 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:28,478 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1091720326] [2021-12-15 17:21:28,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:28,478 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:28,479 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:28,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:28,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:28,479 INFO L87 Difference]: Start difference. First operand 311 states and 423 transitions. cyclomatic complexity: 114 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:28,506 INFO L93 Difference]: Finished difference Result 460 states and 611 transitions. [2021-12-15 17:21:28,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:28,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 460 states and 611 transitions. [2021-12-15 17:21:28,510 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 426 [2021-12-15 17:21:28,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 460 states to 460 states and 611 transitions. [2021-12-15 17:21:28,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460 [2021-12-15 17:21:28,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 460 [2021-12-15 17:21:28,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 460 states and 611 transitions. [2021-12-15 17:21:28,513 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:28,514 INFO L681 BuchiCegarLoop]: Abstraction has 460 states and 611 transitions. [2021-12-15 17:21:28,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states and 611 transitions. [2021-12-15 17:21:28,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 439. [2021-12-15 17:21:28,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:28,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 586 transitions. [2021-12-15 17:21:28,529 INFO L704 BuchiCegarLoop]: Abstraction has 439 states and 586 transitions. [2021-12-15 17:21:28,529 INFO L587 BuchiCegarLoop]: Abstraction has 439 states and 586 transitions. [2021-12-15 17:21:28,529 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:21:28,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 439 states and 586 transitions. [2021-12-15 17:21:28,531 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 405 [2021-12-15 17:21:28,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:28,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:28,533 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,533 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:28,533 INFO L791 eck$LassoCheckResult]: Stem: 3337#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3268#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3219#L367 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3220#L154 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3213#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3204#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3205#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3304#L250 assume !(0 == ~M_E~0); 3314#L250-2 assume !(0 == ~T1_E~0); 3256#L255-1 assume !(0 == ~E_1~0); 3257#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3273#L115 assume !(1 == ~m_pc~0); 3274#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3278#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3290#L127 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3286#L300 assume !(0 != activate_threads_~tmp~1#1); 3287#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3327#L134 assume !(1 == ~t1_pc~0); 3285#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3275#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3276#L146 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3211#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3212#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3279#L273 assume !(1 == ~M_E~0); 3280#L273-2 assume !(1 == ~T1_E~0); 3322#L278-1 assume !(1 == ~E_1~0); 3294#L283-1 assume { :end_inline_reset_delta_events } true; 3295#L404-2 assume !false; 3541#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3539#L225 [2021-12-15 17:21:28,534 INFO L793 eck$LassoCheckResult]: Loop: 3539#L225 assume !false; 3538#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3536#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3534#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3532#L192 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3530#L206 assume 0 != eval_~tmp~0#1; 3528#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3525#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 3526#L211 assume !(0 == ~t1_st~0); 3539#L225 [2021-12-15 17:21:28,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,534 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 1 times [2021-12-15 17:21:28,534 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,535 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348538687] [2021-12-15 17:21:28,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,535 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,546 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:28,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,571 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:28,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,572 INFO L85 PathProgramCache]: Analyzing trace with hash 438949112, now seen corresponding path program 1 times [2021-12-15 17:21:28,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936562657] [2021-12-15 17:21:28,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,576 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:28,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:28,579 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:28,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:28,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1724815409, now seen corresponding path program 1 times [2021-12-15 17:21:28,579 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:28,579 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973913330] [2021-12-15 17:21:28,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:28,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:28,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:28,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:28,600 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:28,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973913330] [2021-12-15 17:21:28,600 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973913330] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:28,600 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:28,600 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:28,600 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922551591] [2021-12-15 17:21:28,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:28,666 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:21:28,672 INFO L158 Benchmark]: Toolchain (without parser) took 2499.27ms. Allocated memory was 94.4MB in the beginning and 113.2MB in the end (delta: 18.9MB). Free memory was 58.6MB in the beginning and 73.8MB in the end (delta: -15.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-15 17:21:28,672 INFO L158 Benchmark]: CDTParser took 0.19ms. Allocated memory is still 75.5MB. Free memory was 40.9MB in the beginning and 40.8MB in the end (delta: 44.2kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:21:28,672 INFO L158 Benchmark]: CACSL2BoogieTranslator took 327.28ms. Allocated memory is still 94.4MB. Free memory was 58.4MB in the beginning and 71.5MB in the end (delta: -13.1MB). Peak memory consumption was 14.6MB. Max. memory is 16.1GB. [2021-12-15 17:21:28,673 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.60ms. Allocated memory is still 94.4MB. Free memory was 71.5MB in the beginning and 69.1MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:21:28,673 INFO L158 Benchmark]: Boogie Preprocessor took 50.22ms. Allocated memory is still 94.4MB. Free memory was 69.1MB in the beginning and 67.4MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:21:28,674 INFO L158 Benchmark]: RCFGBuilder took 506.09ms. Allocated memory is still 94.4MB. Free memory was 67.4MB in the beginning and 50.6MB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2021-12-15 17:21:28,674 INFO L158 Benchmark]: BuchiAutomizer took 1548.61ms. Allocated memory was 94.4MB in the beginning and 113.2MB in the end (delta: 18.9MB). Free memory was 50.6MB in the beginning and 73.8MB in the end (delta: -23.2MB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:21:28,676 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19ms. Allocated memory is still 75.5MB. Free memory was 40.9MB in the beginning and 40.8MB in the end (delta: 44.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 327.28ms. Allocated memory is still 94.4MB. Free memory was 58.4MB in the beginning and 71.5MB in the end (delta: -13.1MB). Peak memory consumption was 14.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.60ms. Allocated memory is still 94.4MB. Free memory was 71.5MB in the beginning and 69.1MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 50.22ms. Allocated memory is still 94.4MB. Free memory was 69.1MB in the beginning and 67.4MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 506.09ms. Allocated memory is still 94.4MB. Free memory was 67.4MB in the beginning and 50.6MB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 1548.61ms. Allocated memory was 94.4MB in the beginning and 113.2MB in the end (delta: 18.9MB). Free memory was 50.6MB in the beginning and 73.8MB in the end (delta: -23.2MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:21:28,720 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable